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Rev | Author | Line No. | Line |
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1179 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #include |
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29 | #include "drmP.h" |
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30 | #include "radeon_reg.h" |
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31 | #include "radeon.h" |
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32 | #include "atom.h" |
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33 | #include "r420d.h" |
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34 | |||
35 | int r420_mc_init(struct radeon_device *rdev) |
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36 | { |
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37 | int r; |
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38 | |||
39 | /* Setup GPU memory space */ |
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40 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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41 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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1221 | serge | 42 | if (rdev->flags & RADEON_IS_AGP) { |
43 | r = radeon_agp_init(rdev); |
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44 | if (r) { |
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45 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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46 | rdev->flags &= ~RADEON_IS_AGP; |
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47 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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48 | } else { |
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49 | rdev->mc.gtt_location = rdev->mc.agp_base; |
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50 | } |
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51 | } |
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1179 | serge | 52 | r = radeon_mc_setup(rdev); |
53 | if (r) { |
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54 | return r; |
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55 | } |
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56 | return 0; |
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57 | } |
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58 | |||
59 | void r420_pipes_init(struct radeon_device *rdev) |
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60 | { |
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61 | unsigned tmp; |
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62 | unsigned gb_pipe_select; |
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63 | unsigned num_pipes; |
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64 | |||
65 | /* GA_ENHANCE workaround TCL deadlock issue */ |
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66 | WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); |
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67 | /* add idle wait as per freedesktop.org bug 24041 */ |
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68 | if (r100_gui_wait_for_idle(rdev)) { |
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69 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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70 | "programming pipes. Bad things might happen.\n"); |
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71 | } |
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72 | /* get max number of pipes */ |
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73 | gb_pipe_select = RREG32(0x402C); |
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74 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
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75 | rdev->num_gb_pipes = num_pipes; |
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76 | tmp = 0; |
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77 | switch (num_pipes) { |
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78 | default: |
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79 | /* force to 1 pipe */ |
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80 | num_pipes = 1; |
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81 | case 1: |
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82 | tmp = (0 << 1); |
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83 | break; |
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84 | case 2: |
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85 | tmp = (3 << 1); |
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86 | break; |
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87 | case 3: |
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88 | tmp = (6 << 1); |
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89 | break; |
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90 | case 4: |
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91 | tmp = (7 << 1); |
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92 | break; |
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93 | } |
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94 | WREG32(0x42C8, (1 << num_pipes) - 1); |
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95 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
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96 | tmp |= (1 << 4) | (1 << 0); |
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97 | WREG32(0x4018, tmp); |
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98 | if (r100_gui_wait_for_idle(rdev)) { |
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99 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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100 | "programming pipes. Bad things might happen.\n"); |
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101 | } |
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102 | |||
103 | tmp = RREG32(0x170C); |
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104 | WREG32(0x170C, tmp | (1 << 31)); |
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105 | |||
106 | WREG32(R300_RB2D_DSTCACHE_MODE, |
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107 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
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108 | R300_DC_AUTOFLUSH_ENABLE | |
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109 | R300_DC_DC_DISABLE_IGNORE_PE); |
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110 | |||
111 | if (r100_gui_wait_for_idle(rdev)) { |
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112 | printk(KERN_WARNING "Failed to wait GUI idle while " |
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113 | "programming pipes. Bad things might happen.\n"); |
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114 | } |
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115 | |||
116 | if (rdev->family == CHIP_RV530) { |
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117 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
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118 | if ((tmp & 3) == 3) |
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119 | rdev->num_z_pipes = 2; |
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120 | else |
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121 | rdev->num_z_pipes = 1; |
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122 | } else |
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123 | rdev->num_z_pipes = 1; |
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124 | |||
125 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
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126 | rdev->num_gb_pipes, rdev->num_z_pipes); |
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127 | } |
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128 | |||
129 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
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130 | { |
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131 | u32 r; |
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132 | |||
133 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
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134 | r = RREG32(R_0001FC_MC_IND_DATA); |
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135 | return r; |
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136 | } |
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137 | |||
138 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
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139 | { |
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140 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
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141 | S_0001F8_MC_IND_WR_EN(1)); |
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142 | WREG32(R_0001FC_MC_IND_DATA, v); |
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143 | } |
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144 | |||
145 | static void r420_debugfs(struct radeon_device *rdev) |
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146 | { |
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147 | if (r100_debugfs_rbbm_init(rdev)) { |
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148 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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149 | } |
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150 | if (r420_debugfs_pipes_info_init(rdev)) { |
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151 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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152 | } |
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153 | } |
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154 | |||
155 | static void r420_clock_resume(struct radeon_device *rdev) |
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156 | { |
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157 | u32 sclk_cntl; |
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1221 | serge | 158 | |
159 | if (radeon_dynclks != -1 && radeon_dynclks) |
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160 | radeon_atom_set_clock_gating(rdev, 1); |
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1179 | serge | 161 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
162 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
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163 | if (rdev->family == CHIP_R420) |
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164 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
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165 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
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166 | } |
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167 | |||
168 | static int r420_startup(struct radeon_device *rdev) |
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169 | { |
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170 | int r; |
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171 | |||
172 | r300_mc_program(rdev); |
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1221 | serge | 173 | /* Resume clock */ |
174 | r420_clock_resume(rdev); |
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1179 | serge | 175 | /* Initialize GART (initialize after TTM so we can allocate |
176 | * memory through TTM but finalize after TTM) */ |
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177 | if (rdev->flags & RADEON_IS_PCIE) { |
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178 | r = rv370_pcie_gart_enable(rdev); |
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179 | if (r) |
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180 | return r; |
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181 | } |
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182 | if (rdev->flags & RADEON_IS_PCI) { |
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183 | r = r100_pci_gart_enable(rdev); |
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184 | if (r) |
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185 | return r; |
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186 | } |
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187 | r420_pipes_init(rdev); |
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188 | /* Enable IRQ */ |
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189 | // rdev->irq.sw_int = true; |
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190 | // r100_irq_set(rdev); |
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191 | /* 1M ring buffer */ |
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1221 | serge | 192 | // r = r100_cp_init(rdev, 1024 * 1024); |
193 | // if (r) { |
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194 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
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195 | // return r; |
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196 | // } |
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1179 | serge | 197 | // r = r100_wb_init(rdev); |
198 | // if (r) { |
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199 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
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200 | // } |
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201 | // r = r100_ib_init(rdev); |
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202 | // if (r) { |
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203 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
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204 | // return r; |
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205 | // } |
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206 | return 0; |
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207 | } |
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208 | |||
209 | int r420_resume(struct radeon_device *rdev) |
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210 | { |
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211 | /* Make sur GART are not working */ |
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212 | if (rdev->flags & RADEON_IS_PCIE) |
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213 | rv370_pcie_gart_disable(rdev); |
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214 | if (rdev->flags & RADEON_IS_PCI) |
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215 | r100_pci_gart_disable(rdev); |
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216 | /* Resume clock before doing reset */ |
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217 | r420_clock_resume(rdev); |
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218 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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219 | if (radeon_gpu_reset(rdev)) { |
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220 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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221 | RREG32(R_000E40_RBBM_STATUS), |
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222 | RREG32(R_0007C0_CP_STAT)); |
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223 | } |
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224 | /* check if cards are posted or not */ |
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225 | if (rdev->is_atom_bios) { |
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226 | atom_asic_init(rdev->mode_info.atom_context); |
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227 | } else { |
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228 | radeon_combios_asic_init(rdev->ddev); |
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229 | } |
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230 | /* Resume clock after posting */ |
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231 | r420_clock_resume(rdev); |
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232 | |||
233 | return r420_startup(rdev); |
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234 | } |
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235 | |||
236 | |||
237 | |||
238 | int r420_init(struct radeon_device *rdev) |
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239 | { |
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240 | int r; |
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241 | |||
242 | /* Initialize scratch registers */ |
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243 | radeon_scratch_init(rdev); |
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244 | /* Initialize surface registers */ |
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245 | radeon_surface_init(rdev); |
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246 | /* TODO: disable VGA need to use VGA request */ |
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247 | /* BIOS*/ |
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248 | if (!radeon_get_bios(rdev)) { |
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249 | if (ASIC_IS_AVIVO(rdev)) |
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250 | return -EINVAL; |
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251 | } |
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252 | if (rdev->is_atom_bios) { |
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253 | r = radeon_atombios_init(rdev); |
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254 | if (r) { |
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255 | return r; |
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256 | } |
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257 | } else { |
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258 | r = radeon_combios_init(rdev); |
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259 | if (r) { |
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260 | return r; |
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261 | } |
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262 | } |
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263 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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264 | if (radeon_gpu_reset(rdev)) { |
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265 | dev_warn(rdev->dev, |
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266 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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267 | RREG32(R_000E40_RBBM_STATUS), |
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268 | RREG32(R_0007C0_CP_STAT)); |
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269 | } |
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270 | /* check if cards are posted or not */ |
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271 | if (!radeon_card_posted(rdev) && rdev->bios) { |
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272 | DRM_INFO("GPU not posted. posting now...\n"); |
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273 | if (rdev->is_atom_bios) { |
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274 | atom_asic_init(rdev->mode_info.atom_context); |
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275 | } else { |
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276 | radeon_combios_asic_init(rdev->ddev); |
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277 | } |
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278 | } |
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279 | /* Initialize clocks */ |
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280 | radeon_get_clock_info(rdev->ddev); |
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1268 | serge | 281 | /* Initialize power management */ |
282 | radeon_pm_init(rdev); |
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1179 | serge | 283 | /* Get vram informations */ |
284 | r300_vram_info(rdev); |
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285 | /* Initialize memory controller (also test AGP) */ |
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286 | r = r420_mc_init(rdev); |
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287 | if (r) { |
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288 | return r; |
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289 | } |
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290 | r420_debugfs(rdev); |
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291 | /* Fence driver */ |
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292 | // r = radeon_fence_driver_init(rdev); |
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293 | // if (r) { |
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294 | // return r; |
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295 | // } |
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296 | // r = radeon_irq_kms_init(rdev); |
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297 | // if (r) { |
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298 | // return r; |
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299 | // } |
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300 | /* Memory manager */ |
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301 | r = radeon_object_init(rdev); |
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302 | if (r) { |
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303 | return r; |
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304 | } |
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305 | if (rdev->flags & RADEON_IS_PCIE) { |
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306 | r = rv370_pcie_gart_init(rdev); |
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307 | if (r) |
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308 | return r; |
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309 | } |
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310 | if (rdev->flags & RADEON_IS_PCI) { |
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311 | r = r100_pci_gart_init(rdev); |
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312 | if (r) |
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313 | return r; |
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314 | } |
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315 | r300_set_reg_safe(rdev); |
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316 | rdev->accel_working = true; |
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317 | r = r420_startup(rdev); |
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318 | if (r) { |
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319 | /* Somethings want wront with the accel init stop accel */ |
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320 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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1221 | serge | 321 | // r420_suspend(rdev); |
1179 | serge | 322 | // r100_cp_fini(rdev); |
323 | // r100_wb_fini(rdev); |
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324 | // r100_ib_fini(rdev); |
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325 | if (rdev->flags & RADEON_IS_PCIE) |
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326 | rv370_pcie_gart_fini(rdev); |
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327 | if (rdev->flags & RADEON_IS_PCI) |
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328 | r100_pci_gart_fini(rdev); |
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329 | // radeon_agp_fini(rdev); |
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330 | // radeon_irq_kms_fini(rdev); |
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331 | rdev->accel_working = false; |
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332 | } |
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333 | return 0; |
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334 | } |
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335 | |||
336 | /* |
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337 | * Debugfs info |
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338 | */ |
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339 | #if defined(CONFIG_DEBUG_FS) |
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340 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
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341 | { |
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342 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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343 | struct drm_device *dev = node->minor->dev; |
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344 | struct radeon_device *rdev = dev->dev_private; |
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345 | uint32_t tmp; |
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346 | |||
347 | tmp = RREG32(R400_GB_PIPE_SELECT); |
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348 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
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349 | tmp = RREG32(R300_GB_TILE_CONFIG); |
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350 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
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351 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
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352 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
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353 | return 0; |
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354 | } |
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355 | |||
356 | static struct drm_info_list r420_pipes_info_list[] = { |
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357 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
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358 | }; |
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359 | #endif |
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360 | |||
361 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
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362 | { |
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363 | #if defined(CONFIG_DEBUG_FS) |
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364 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
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365 | #else |
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366 | return 0; |
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367 | #endif |
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368 | }><>><>><>><>><>><>><>><>><>><>><>><> |