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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 3764 | Serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | #ifndef __R300D_H__ |
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| 29 | #define __R300D_H__ |
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| 30 | |||
| 31 | #define CP_PACKET0 0x00000000 |
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| 32 | #define PACKET0_BASE_INDEX_SHIFT 0 |
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| 33 | #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
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| 34 | #define PACKET0_COUNT_SHIFT 16 |
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| 35 | #define PACKET0_COUNT_MASK (0x3fff << 16) |
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| 36 | #define CP_PACKET1 0x40000000 |
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| 37 | #define CP_PACKET2 0x80000000 |
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| 38 | #define PACKET2_PAD_SHIFT 0 |
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| 39 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
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| 40 | #define CP_PACKET3 0xC0000000 |
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| 41 | #define PACKET3_IT_OPCODE_SHIFT 8 |
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| 42 | #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
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| 43 | #define PACKET3_COUNT_SHIFT 16 |
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| 44 | #define PACKET3_COUNT_MASK (0x3fff << 16) |
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| 45 | /* PACKET3 op code */ |
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| 46 | #define PACKET3_NOP 0x10 |
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| 47 | #define PACKET3_3D_DRAW_VBUF 0x28 |
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| 48 | #define PACKET3_3D_DRAW_IMMD 0x29 |
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| 49 | #define PACKET3_3D_DRAW_INDX 0x2A |
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| 50 | #define PACKET3_3D_LOAD_VBPNTR 0x2F |
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| 51 | #define PACKET3_3D_CLEAR_ZMASK 0x32 |
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| 52 | #define PACKET3_INDX_BUFFER 0x33 |
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| 53 | #define PACKET3_3D_DRAW_VBUF_2 0x34 |
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| 54 | #define PACKET3_3D_DRAW_IMMD_2 0x35 |
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| 55 | #define PACKET3_3D_DRAW_INDX_2 0x36 |
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| 56 | #define PACKET3_3D_CLEAR_HIZ 0x37 |
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| 57 | #define PACKET3_3D_CLEAR_CMASK 0x38 |
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| 58 | #define PACKET3_BITBLT_MULTI 0x9B |
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| 59 | |||
| 60 | #define PACKET0(reg, n) (CP_PACKET0 | \ |
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| 61 | REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
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| 62 | REG_SET(PACKET0_COUNT, (n))) |
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| 63 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
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| 64 | #define PACKET3(op, n) (CP_PACKET3 | \ |
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| 65 | REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
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| 66 | REG_SET(PACKET3_COUNT, (n))) |
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| 67 | |||
| 68 | /* Registers */ |
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| 69 | #define R_000148_MC_FB_LOCATION 0x000148 |
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| 70 | #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
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| 71 | #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
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| 72 | #define C_000148_MC_FB_START 0xFFFF0000 |
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| 73 | #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
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| 74 | #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
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| 75 | #define C_000148_MC_FB_TOP 0x0000FFFF |
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| 76 | #define R_00014C_MC_AGP_LOCATION 0x00014C |
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| 77 | #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
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| 78 | #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
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| 79 | #define C_00014C_MC_AGP_START 0xFFFF0000 |
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| 80 | #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
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| 81 | #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
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| 82 | #define C_00014C_MC_AGP_TOP 0x0000FFFF |
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| 83 | #define R_00015C_AGP_BASE_2 0x00015C |
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| 84 | #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) |
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| 85 | #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) |
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| 86 | #define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0 |
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| 87 | #define R_000170_AGP_BASE 0x000170 |
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| 88 | #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
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| 89 | #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
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| 90 | #define C_000170_AGP_BASE_ADDR 0x00000000 |
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| 91 | #define R_0007C0_CP_STAT 0x0007C0 |
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| 92 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
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| 93 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
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| 94 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
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| 95 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
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| 96 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
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| 97 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
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| 98 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
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| 99 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
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| 100 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
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| 101 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
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| 102 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
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| 103 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
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| 104 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
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| 105 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
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| 106 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
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| 107 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
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| 108 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
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| 109 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
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| 110 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
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| 111 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
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| 112 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
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| 113 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
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| 114 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
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| 115 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
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| 116 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
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| 117 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
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| 118 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
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| 119 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) |
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| 120 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) |
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| 121 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF |
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| 122 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) |
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| 123 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) |
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| 124 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF |
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| 125 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
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| 126 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
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| 127 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
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| 128 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
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| 129 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
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| 130 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
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| 131 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
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| 132 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
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| 133 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
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| 134 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
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| 135 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
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| 136 | #define C_0007C0_CP_BUSY 0x7FFFFFFF |
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| 137 | #define R_000E40_RBBM_STATUS 0x000E40 |
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| 138 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
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| 139 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
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| 140 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
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| 141 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
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| 142 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) |
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| 143 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF |
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| 144 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) |
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| 145 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) |
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| 146 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF |
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| 147 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) |
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| 148 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) |
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| 149 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF |
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| 150 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) |
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| 151 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) |
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| 152 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF |
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| 153 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) |
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| 154 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) |
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| 155 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF |
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| 156 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) |
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| 157 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) |
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| 158 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF |
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| 159 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) |
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| 160 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) |
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| 161 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF |
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| 162 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) |
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| 163 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) |
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| 164 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF |
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| 165 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) |
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| 166 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) |
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| 167 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF |
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| 168 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) |
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| 169 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) |
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| 170 | #define C_000E40_E2_BUSY 0xFFFDFFFF |
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| 171 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) |
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| 172 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) |
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| 173 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF |
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| 174 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) |
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| 175 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) |
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| 176 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF |
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| 177 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) |
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| 178 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) |
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| 179 | #define C_000E40_VAP_BUSY 0xFFEFFFFF |
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| 180 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) |
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| 181 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) |
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| 182 | #define C_000E40_RE_BUSY 0xFFDFFFFF |
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| 183 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) |
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| 184 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) |
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| 185 | #define C_000E40_TAM_BUSY 0xFFBFFFFF |
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| 186 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) |
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| 187 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) |
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| 188 | #define C_000E40_TDM_BUSY 0xFF7FFFFF |
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| 189 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) |
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| 190 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) |
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| 191 | #define C_000E40_PB_BUSY 0xFEFFFFFF |
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| 192 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) |
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| 193 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) |
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| 194 | #define C_000E40_TIM_BUSY 0xFDFFFFFF |
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| 195 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) |
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| 196 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) |
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| 197 | #define C_000E40_GA_BUSY 0xFBFFFFFF |
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| 198 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) |
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| 199 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) |
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| 200 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF |
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| 201 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
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| 202 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
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| 203 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
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| 204 | #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 |
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| 205 | #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) |
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| 206 | #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) |
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| 207 | #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE |
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| 208 | #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) |
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| 209 | #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) |
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| 210 | #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD |
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| 211 | #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) |
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| 212 | #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) |
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| 213 | #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB |
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| 214 | #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) |
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| 215 | #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) |
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| 216 | #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 |
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| 217 | #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) |
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| 218 | #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) |
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| 219 | #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF |
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| 220 | #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) |
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| 221 | #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) |
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| 222 | #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF |
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| 223 | #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) |
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| 224 | #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) |
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| 225 | #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF |
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| 226 | #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) |
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| 227 | #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) |
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| 228 | #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F |
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| 229 | #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) |
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| 230 | #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) |
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| 231 | #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF |
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| 232 | #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) |
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| 233 | #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) |
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| 234 | #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF |
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| 235 | #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) |
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| 236 | #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) |
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| 237 | #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF |
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| 238 | #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) |
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| 239 | #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) |
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| 240 | #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF |
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| 241 | #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) |
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| 242 | #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) |
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| 243 | #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF |
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| 244 | #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) |
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| 245 | #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) |
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| 246 | #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF |
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| 247 | #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) |
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| 248 | #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) |
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| 249 | #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF |
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| 250 | |||
| 251 | #define R_00000D_SCLK_CNTL 0x00000D |
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| 252 | #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) |
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| 253 | #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) |
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| 254 | #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 |
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| 255 | #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) |
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| 256 | #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) |
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| 257 | #define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7 |
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| 258 | #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) |
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| 259 | #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) |
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| 260 | #define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF |
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| 261 | #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) |
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| 262 | #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) |
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| 263 | #define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF |
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| 264 | #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) |
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| 265 | #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) |
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| 266 | #define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF |
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| 267 | #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) |
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| 268 | #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) |
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| 269 | #define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F |
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| 270 | #define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8) |
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| 271 | #define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1) |
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| 272 | #define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF |
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| 273 | #define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9) |
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| 274 | #define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1) |
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| 275 | #define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF |
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| 276 | #define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10) |
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| 277 | #define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1) |
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| 278 | #define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF |
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| 279 | #define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11) |
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| 280 | #define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1) |
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| 281 | #define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF |
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| 282 | #define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12) |
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| 283 | #define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1) |
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| 284 | #define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF |
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| 285 | #define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13) |
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| 286 | #define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1) |
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| 287 | #define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF |
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| 288 | #define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14) |
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| 289 | #define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1) |
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| 290 | #define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF |
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| 291 | #define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15) |
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| 292 | #define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1) |
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| 293 | #define C_00000D_FORCE_DISP2 0xFFFF7FFF |
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| 294 | #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) |
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| 295 | #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) |
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| 296 | #define C_00000D_FORCE_CP 0xFFFEFFFF |
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| 297 | #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) |
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| 298 | #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) |
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| 299 | #define C_00000D_FORCE_HDP 0xFFFDFFFF |
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| 300 | #define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18) |
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| 301 | #define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1) |
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| 302 | #define C_00000D_FORCE_DISP1 0xFFFBFFFF |
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| 303 | #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) |
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| 304 | #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) |
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| 305 | #define C_00000D_FORCE_TOP 0xFFF7FFFF |
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| 306 | #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) |
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| 307 | #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) |
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| 308 | #define C_00000D_FORCE_E2 0xFFEFFFFF |
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| 309 | #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) |
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| 310 | #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) |
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| 311 | #define C_00000D_FORCE_SE 0xFFDFFFFF |
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| 312 | #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) |
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| 313 | #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) |
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| 314 | #define C_00000D_FORCE_IDCT 0xFFBFFFFF |
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| 315 | #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) |
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| 316 | #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) |
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| 317 | #define C_00000D_FORCE_VIP 0xFF7FFFFF |
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| 318 | #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) |
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| 319 | #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) |
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| 320 | #define C_00000D_FORCE_RE 0xFEFFFFFF |
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| 321 | #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) |
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| 322 | #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) |
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| 323 | #define C_00000D_FORCE_PB 0xFDFFFFFF |
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| 324 | #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) |
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| 325 | #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) |
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| 326 | #define C_00000D_FORCE_TAM 0xFBFFFFFF |
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| 327 | #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) |
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| 328 | #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) |
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| 329 | #define C_00000D_FORCE_TDM 0xF7FFFFFF |
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| 330 | #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) |
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| 331 | #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) |
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| 332 | #define C_00000D_FORCE_RB 0xEFFFFFFF |
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| 333 | #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) |
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| 334 | #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) |
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| 335 | #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF |
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| 336 | #define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) |
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| 337 | #define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) |
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| 338 | #define C_00000D_FORCE_SUBPIC 0xBFFFFFFF |
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| 339 | #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) |
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| 340 | #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) |
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| 341 | #define C_00000D_FORCE_OV0 0x7FFFFFFF |
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| 342 | |||
| 343 | #endif |