WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1120	serge	31	#include "radeon_reg.h"
		32	#include "radeon.h"
1179	serge	33	#include "radeon_drm.h"
1120	serge	34
1179	serge	35	#include "r300d.h"
1221	serge	36	#include "rv350d.h"
1179	serge	37	#include "r300_reg_safe.h"
		38
1403	serge	39	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
		40	*
		41	* GPU Errata:
		42	* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
		43	* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
		44	* However, scheduling such write to the ring seems harmless, i suspect
		45	* the CP read collide with the flush somehow, or maybe the MC, hard to
		46	* tell. (Jerome Glisse)
		47	*/
1120	serge	48
		49	/*
		50	* rv370,rv380 PCIE GART
		51	*/
1221	serge	52	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		53
1120	serge	54	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		55	{
		56	uint32_t tmp;
		57	int i;
		58
		59	/* Workaround HW bug do flush 2 times */
		60	for (i = 0; i < 2; i++) {
		61	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		62	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		63	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		64	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	65	}
1120	serge	66	mb();
1179	serge	67	}
		68
		69	int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		70	{
		71	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		72
		73	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		74	return -EINVAL;
1120	serge	75	}
1179	serge	76	addr = (lower_32_bits(addr) >> 8) \|
		77	((upper_32_bits(addr) & 0xff) << 24) \|
		78	0xc;
		79	/* on x86 we want this to be CPU endian, on powerpc
		80	* on powerpc without HW swappers, it'll get swapped on way
		81	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
		82	writel(addr, ((void __iomem )ptr) + (i 4));
		83	return 0;
1120	serge	84	}
		85
1179	serge	86	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	87	{
		88	int r;
		89
1179	serge	90	if (rdev->gart.table.vram.robj) {
		91	WARN(1, "RV370 PCIE GART already initialized.\n");
		92	return 0;
		93	}
1120	serge	94	/* Initialize common gart structure */
		95	r = radeon_gart_init(rdev);
1179	serge	96	if (r)
1120	serge	97	return r;
1129	serge	98	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	99	if (r)
1129	serge	100	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	101	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		102	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		103	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		104	return radeon_gart_table_vram_alloc(rdev);
		105	}
		106
		107	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		108	{
		109	uint32_t table_addr;
		110	uint32_t tmp;
		111	int r;
		112
		113	if (rdev->gart.table.vram.robj == NULL) {
		114	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		115	return -EINVAL;
1129	serge	116	}
1179	serge	117	r = radeon_gart_table_vram_pin(rdev);
		118	if (r)
1120	serge	119	return r;
1430	serge	120	radeon_gart_restore(rdev);
1120	serge	121	/* discard memory request outside of configured range */
		122	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		123	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1430	serge	124	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
		125	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
1120	serge	126	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		127	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		128	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		129	table_addr = rdev->gart.table_addr;
		130	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		131	/* FIXME: setup default page */
1430	serge	132	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
1120	serge	133	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		134	/* Clear error */
		135	WREG32_PCIE(0x18, 0);
		136	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		137	tmp \|= RADEON_PCIE_TX_GART_EN;
		138	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		139	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		140	rv370_pcie_gart_tlb_flush(rdev);
		141	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
1179	serge	142	(unsigned)(rdev->mc.gtt_size >> 20), table_addr);
1120	serge	143	rdev->gart.ready = true;
		144	return 0;
		145	}
		146
		147	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		148	{
1321	serge	149	u32 tmp;
		150	int r;
1120	serge	151
		152	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		153	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		154	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
		155	if (rdev->gart.table.vram.robj) {
1404	serge	156	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
		157	if (likely(r == 0)) {
		158	radeon_bo_kunmap(rdev->gart.table.vram.robj);
		159	radeon_bo_unpin(rdev->gart.table.vram.robj);
		160	radeon_bo_unreserve(rdev->gart.table.vram.robj);
		161	}
1120	serge	162	}
		163	}
		164
1179	serge	165	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	166	{
		167	rv370_pcie_gart_disable(rdev);
1179	serge	168	radeon_gart_table_vram_free(rdev);
		169	radeon_gart_fini(rdev);
1120	serge	170	}
		171
		172	void r300_fence_ring_emit(struct radeon_device *rdev,
		173	struct radeon_fence *fence)
		174	{
		175	/* Who ever call radeon_fence_emit should call ring_lock and ask
		176	* for enough space (today caller are ib schedule and buffer move) */
		177	/* Write SC register so SC & US assert idle */
1430	serge	178	radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
1120	serge	179	radeon_ring_write(rdev, 0);
1430	serge	180	radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
1120	serge	181	radeon_ring_write(rdev, 0);
		182	/* Flush 3D cache */
1430	serge	183	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		184	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
		185	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		186	radeon_ring_write(rdev, R300_ZC_FLUSH);
1120	serge	187	/* Wait until IDLE & CLEAN */
1430	serge	188	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		189	radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN \|
		190	RADEON_WAIT_2D_IDLECLEAN \|
		191	RADEON_WAIT_DMA_GUI_IDLE));
1403	serge	192	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		193	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl \|
		194	RADEON_HDP_READ_BUFFER_INVALIDATE);
		195	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		196	radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
1120	serge	197	/* Emit fence sequence & fire IRQ */
		198	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		199	radeon_ring_write(rdev, fence->seq);
		200	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		201	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		202	}
		203
		204	void r300_ring_start(struct radeon_device *rdev)
		205	{
		206	unsigned gb_tile_config;
		207	int r;
		208
		209	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		210	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		211	switch(rdev->num_gb_pipes) {
		212	case 2:
		213	gb_tile_config \|= R300_PIPE_COUNT_R300;
		214	break;
		215	case 3:
		216	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		217	break;
		218	case 4:
		219	gb_tile_config \|= R300_PIPE_COUNT_R420;
		220	break;
		221	case 1:
		222	default:
		223	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		224	break;
		225	}
		226
		227	r = radeon_ring_lock(rdev, 64);
		228	if (r) {
		229	return;
		230	}
		231	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		232	radeon_ring_write(rdev,
		233	RADEON_ISYNC_ANY2D_IDLE3D \|
		234	RADEON_ISYNC_ANY3D_IDLE2D \|
		235	RADEON_ISYNC_WAIT_IDLEGUI \|
		236	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		237	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
		238	radeon_ring_write(rdev, gb_tile_config);
		239	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		240	radeon_ring_write(rdev,
		241	RADEON_WAIT_2D_IDLECLEAN \|
		242	RADEON_WAIT_3D_IDLECLEAN);
1430	serge	243	radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
		244	radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
1120	serge	245	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
		246	radeon_ring_write(rdev, 0);
		247	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
		248	radeon_ring_write(rdev, 0);
		249	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		250	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		251	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		252	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		253	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		254	radeon_ring_write(rdev,
		255	RADEON_WAIT_2D_IDLECLEAN \|
		256	RADEON_WAIT_3D_IDLECLEAN);
		257	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
		258	radeon_ring_write(rdev, 0);
		259	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		260	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		261	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		262	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		263	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
		264	radeon_ring_write(rdev,
		265	((6 << R300_MS_X0_SHIFT) \|
		266	(6 << R300_MS_Y0_SHIFT) \|
		267	(6 << R300_MS_X1_SHIFT) \|
		268	(6 << R300_MS_Y1_SHIFT) \|
		269	(6 << R300_MS_X2_SHIFT) \|
		270	(6 << R300_MS_Y2_SHIFT) \|
		271	(6 << R300_MSBD0_Y_SHIFT) \|
		272	(6 << R300_MSBD0_X_SHIFT)));
		273	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
		274	radeon_ring_write(rdev,
		275	((6 << R300_MS_X3_SHIFT) \|
		276	(6 << R300_MS_Y3_SHIFT) \|
		277	(6 << R300_MS_X4_SHIFT) \|
		278	(6 << R300_MS_Y4_SHIFT) \|
		279	(6 << R300_MS_X5_SHIFT) \|
		280	(6 << R300_MS_Y5_SHIFT) \|
		281	(6 << R300_MSBD1_SHIFT)));
		282	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
		283	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		284	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
		285	radeon_ring_write(rdev,
		286	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
		287	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
		288	radeon_ring_write(rdev,
		289	R300_GEOMETRY_ROUND_NEAREST \|
		290	R300_COLOR_ROUND_NEAREST);
		291	radeon_ring_unlock_commit(rdev);
		292	}
		293
		294	void r300_errata(struct radeon_device *rdev)
		295	{
		296	rdev->pll_errata = 0;
		297
		298	if (rdev->family == CHIP_R300 &&
		299	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		300	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		301	}
		302	}
		303
		304	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		305	{
		306	unsigned i;
		307	uint32_t tmp;
		308
		309	for (i = 0; i < rdev->usec_timeout; i++) {
		310	/* read MC_STATUS */
1430	serge	311	tmp = RREG32(RADEON_MC_STATUS);
		312	if (tmp & R300_MC_IDLE) {
1120	serge	313	return 0;
		314	}
		315	DRM_UDELAY(1);
		316	}
		317	return -1;
		318	}
		319
		320	void r300_gpu_init(struct radeon_device *rdev)
		321	{
		322	uint32_t gb_tile_config, tmp;
		323
		324	r100_hdp_reset(rdev);
		325	/* FIXME: rv380 one pipes ? */
		326	if ((rdev->family == CHIP_R300) \|\| (rdev->family == CHIP_R350)) {
		327	/* r300,r350 */
		328	rdev->num_gb_pipes = 2;
		329	} else {
		330	/* rv350,rv370,rv380 */
		331	rdev->num_gb_pipes = 1;
		332	}
1179	serge	333	rdev->num_z_pipes = 1;
1120	serge	334	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		335	switch (rdev->num_gb_pipes) {
		336	case 2:
		337	gb_tile_config \|= R300_PIPE_COUNT_R300;
		338	break;
		339	case 3:
		340	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		341	break;
		342	case 4:
		343	gb_tile_config \|= R300_PIPE_COUNT_R420;
		344	break;
		345	default:
		346	case 1:
		347	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		348	break;
		349	}
		350	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		351
		352	if (r100_gui_wait_for_idle(rdev)) {
		353	printk(KERN_WARNING "Failed to wait GUI idle while "
		354	"programming pipes. Bad things might happen.\n");
		355	}
		356
1430	serge	357	tmp = RREG32(R300_DST_PIPE_CONFIG);
		358	WREG32(R300_DST_PIPE_CONFIG, tmp \| R300_PIPE_AUTO_CONFIG);
1120	serge	359
		360	WREG32(R300_RB2D_DSTCACHE_MODE,
		361	R300_DC_AUTOFLUSH_ENABLE \|
		362	R300_DC_DC_DISABLE_IGNORE_PE);
		363
		364	if (r100_gui_wait_for_idle(rdev)) {
		365	printk(KERN_WARNING "Failed to wait GUI idle while "
		366	"programming pipes. Bad things might happen.\n");
		367	}
		368	if (r300_mc_wait_for_idle(rdev)) {
		369	printk(KERN_WARNING "Failed to wait MC idle while "
		370	"programming pipes. Bad things might happen.\n");
		371	}
1179	serge	372	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		373	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	374	}
		375
		376	int r300_ga_reset(struct radeon_device *rdev)
		377	{
		378	uint32_t tmp;
		379	bool reinit_cp;
		380	int i;
		381
		382	reinit_cp = rdev->cp.ready;
		383	rdev->cp.ready = false;
		384	for (i = 0; i < rdev->usec_timeout; i++) {
		385	WREG32(RADEON_CP_CSQ_MODE, 0);
		386	WREG32(RADEON_CP_CSQ_CNTL, 0);
		387	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		388	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		389	udelay(200);
		390	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		391	/* Wait to prevent race in RBBM_STATUS */
		392	mdelay(1);
		393	tmp = RREG32(RADEON_RBBM_STATUS);
		394	if (tmp & ((1 << 20) \| (1 << 26))) {
		395	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
		396	/* GA still busy soft reset it */
		397	WREG32(0x429C, 0x200);
		398	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
1430	serge	399	WREG32(R300_RE_SCISSORS_TL, 0);
		400	WREG32(R300_RE_SCISSORS_BR, 0);
1120	serge	401	WREG32(0x24AC, 0);
		402	}
		403	/* Wait to prevent race in RBBM_STATUS */
		404	mdelay(1);
		405	tmp = RREG32(RADEON_RBBM_STATUS);
		406	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		407	break;
		408	}
		409	}
		410	for (i = 0; i < rdev->usec_timeout; i++) {
		411	tmp = RREG32(RADEON_RBBM_STATUS);
		412	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		413	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
		414	tmp);
		415	if (reinit_cp) {
		416	return r100_cp_init(rdev, rdev->cp.ring_size);
		417	}
		418	return 0;
		419	}
		420	DRM_UDELAY(1);
		421	}
		422	tmp = RREG32(RADEON_RBBM_STATUS);
		423	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
		424	return -1;
		425	}
		426
		427	int r300_gpu_reset(struct radeon_device *rdev)
		428	{
		429	uint32_t status;
		430
		431	/* reset order likely matter */
		432	status = RREG32(RADEON_RBBM_STATUS);
		433	/* reset HDP */
		434	r100_hdp_reset(rdev);
		435	/* reset rb2d */
		436	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		437	r100_rb2d_reset(rdev);
		438	}
		439	/* reset GA */
		440	if (status & ((1 << 20) \| (1 << 26))) {
		441	r300_ga_reset(rdev);
		442	}
		443	/* reset CP */
		444	status = RREG32(RADEON_RBBM_STATUS);
		445	if (status & (1 << 16)) {
		446	r100_cp_reset(rdev);
		447	}
		448	/* Check if GPU is idle */
		449	status = RREG32(RADEON_RBBM_STATUS);
1430	serge	450	if (status & RADEON_RBBM_ACTIVE) {
1120	serge	451	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		452	return -1;
		453	}
		454	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		455	return 0;
		456	}
		457
		458
		459	/*
		460	* r300,r350,rv350,rv380 VRAM info
		461	*/
1430	serge	462	void r300_mc_init(struct radeon_device *rdev)
1120	serge	463	{
1430	serge	464	u64 base;
		465	u32 tmp;
1120	serge	466
		467	/* DDR for all card after R300 & IGP */
		468	rdev->mc.vram_is_ddr = true;
		469	tmp = RREG32(RADEON_MEM_CNTL);
1404	serge	470	tmp &= R300_MEM_NUM_CHANNELS_MASK;
		471	switch (tmp) {
		472	case 0: rdev->mc.vram_width = 64; break;
		473	case 1: rdev->mc.vram_width = 128; break;
		474	case 2: rdev->mc.vram_width = 256; break;
		475	default: rdev->mc.vram_width = 128; break;
1120	serge	476	}
1179	serge	477	r100_vram_init_sizes(rdev);
1430	serge	478	base = rdev->mc.aper_base;
		479	if (rdev->flags & RADEON_IS_IGP)
		480	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		481	radeon_vram_location(rdev, &rdev->mc, base);
		482	if (!(rdev->flags & RADEON_IS_AGP))
		483	radeon_gtt_location(rdev, &rdev->mc);
1120	serge	484	}
		485
		486	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		487	{
		488	uint32_t link_width_cntl, mask;
		489
		490	if (rdev->flags & RADEON_IS_IGP)
		491	return;
		492
		493	if (!(rdev->flags & RADEON_IS_PCIE))
		494	return;
		495
		496	/* FIXME wait for idle */
		497
		498	switch (lanes) {
		499	case 0:
		500	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		501	break;
		502	case 1:
		503	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		504	break;
		505	case 2:
		506	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		507	break;
		508	case 4:
		509	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		510	break;
		511	case 8:
		512	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		513	break;
		514	case 12:
		515	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		516	break;
		517	case 16:
		518	default:
		519	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		520	break;
		521	}
		522
		523	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		524
		525	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		526	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		527	return;
		528
		529	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		530	RADEON_PCIE_LC_RECONFIG_NOW \|
		531	RADEON_PCIE_LC_RECONFIG_LATER \|
		532	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		533	link_width_cntl \|= mask;
		534	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		535	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		536	RADEON_PCIE_LC_RECONFIG_NOW));
		537
		538	/* wait for lane set to complete */
		539	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		540	while (link_width_cntl == 0xffffffff)
		541	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		542
		543	}
		544
1430	serge	545	int rv370_get_pcie_lanes(struct radeon_device *rdev)
		546	{
		547	u32 link_width_cntl;
		548
		549	if (rdev->flags & RADEON_IS_IGP)
		550	return 0;
		551
		552	if (!(rdev->flags & RADEON_IS_PCIE))
		553	return 0;
		554
		555	/* FIXME wait for idle */
		556
		557	if (rdev->family < CHIP_R600)
		558	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		559	else
		560	link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		561
		562	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
		563	case RADEON_PCIE_LC_LINK_WIDTH_X0:
		564	return 0;
		565	case RADEON_PCIE_LC_LINK_WIDTH_X1:
		566	return 1;
		567	case RADEON_PCIE_LC_LINK_WIDTH_X2:
		568	return 2;
		569	case RADEON_PCIE_LC_LINK_WIDTH_X4:
		570	return 4;
		571	case RADEON_PCIE_LC_LINK_WIDTH_X8:
		572	return 8;
		573	case RADEON_PCIE_LC_LINK_WIDTH_X16:
		574	default:
		575	return 16;
		576	}
		577	}
		578
1120	serge	579	#if defined(CONFIG_DEBUG_FS)
		580	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		581	{
		582	struct drm_info_node node = (struct drm_info_node ) m->private;
		583	struct drm_device *dev = node->minor->dev;
		584	struct radeon_device *rdev = dev->dev_private;
		585	uint32_t tmp;
		586
		587	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		588	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		589	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		590	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		591	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		592	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		593	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		594	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		595	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		596	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		597	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		598	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		599	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		600	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		601	return 0;
		602	}
		603
		604	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		605	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		606	};
		607	#endif
		608
1221	serge	609	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	610	{
		611	#if defined(CONFIG_DEBUG_FS)
		612	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		613	#else
		614	return 0;
		615	#endif
		616	}
		617
		618
1128	serge	619	#if 0
1221	serge	620
1120	serge	621	static int r300_packet0_check(struct radeon_cs_parser *p,
		622	struct radeon_cs_packet *pkt,
		623	unsigned idx, unsigned reg)
		624	{
		625	struct radeon_cs_reloc *reloc;
1179	serge	626	struct r100_cs_track *track;
1120	serge	627	volatile uint32_t *ib;
1179	serge	628	uint32_t tmp, tile_flags = 0;
1120	serge	629	unsigned i;
		630	int r;
1221	serge	631	u32 idx_value;
1120	serge	632
		633	ib = p->ib->ptr;
1179	serge	634	track = (struct r100_cs_track *)p->track;
1221	serge	635	idx_value = radeon_get_ib_value(p, idx);
		636
1120	serge	637	switch(reg) {
1179	serge	638	case AVIVO_D1MODE_VLINE_START_END:
		639	case RADEON_CRTC_GUI_TRIG_VLINE:
		640	r = r100_cs_packet_parse_vline(p);
1120	serge	641	if (r) {
		642	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		643	idx, reg);
		644	r100_cs_dump_packet(p, pkt);
		645	return r;
		646	}
		647	break;
1179	serge	648	case RADEON_DST_PITCH_OFFSET:
		649	case RADEON_SRC_PITCH_OFFSET:
		650	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		651	if (r)
		652	return r;
		653	break;
1120	serge	654	case R300_RB3D_COLOROFFSET0:
		655	case R300_RB3D_COLOROFFSET1:
		656	case R300_RB3D_COLOROFFSET2:
		657	case R300_RB3D_COLOROFFSET3:
		658	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		659	r = r100_cs_packet_next_reloc(p, &reloc);
		660	if (r) {
		661	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		662	idx, reg);
		663	r100_cs_dump_packet(p, pkt);
		664	return r;
		665	}
		666	track->cb[i].robj = reloc->robj;
1221	serge	667	track->cb[i].offset = idx_value;
		668	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	669	break;
		670	case R300_ZB_DEPTHOFFSET:
		671	r = r100_cs_packet_next_reloc(p, &reloc);
		672	if (r) {
		673	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		674	idx, reg);
		675	r100_cs_dump_packet(p, pkt);
		676	return r;
		677	}
		678	track->zb.robj = reloc->robj;
1221	serge	679	track->zb.offset = idx_value;
		680	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	681	break;
		682	case R300_TX_OFFSET_0:
		683	case R300_TX_OFFSET_0+4:
		684	case R300_TX_OFFSET_0+8:
		685	case R300_TX_OFFSET_0+12:
		686	case R300_TX_OFFSET_0+16:
		687	case R300_TX_OFFSET_0+20:
		688	case R300_TX_OFFSET_0+24:
		689	case R300_TX_OFFSET_0+28:
		690	case R300_TX_OFFSET_0+32:
		691	case R300_TX_OFFSET_0+36:
		692	case R300_TX_OFFSET_0+40:
		693	case R300_TX_OFFSET_0+44:
		694	case R300_TX_OFFSET_0+48:
		695	case R300_TX_OFFSET_0+52:
		696	case R300_TX_OFFSET_0+56:
		697	case R300_TX_OFFSET_0+60:
		698	i = (reg - R300_TX_OFFSET_0) >> 2;
		699	r = r100_cs_packet_next_reloc(p, &reloc);
		700	if (r) {
		701	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		702	idx, reg);
		703	r100_cs_dump_packet(p, pkt);
		704	return r;
		705	}
1403	serge	706
		707	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		708	tile_flags \|= R300_TXO_MACRO_TILE;
		709	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		710	tile_flags \|= R300_TXO_MICRO_TILE;
1430	serge	711	else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
		712	tile_flags \|= R300_TXO_MICRO_TILE_SQUARE;
1403	serge	713
		714	tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
		715	tmp \|= tile_flags;
		716	ib[idx] = tmp;
1120	serge	717	track->textures[i].robj = reloc->robj;
		718	break;
		719	/* Tracked registers */
		720	case 0x2084:
		721	/* VAP_VF_CNTL */
1221	serge	722	track->vap_vf_cntl = idx_value;
1120	serge	723	break;
		724	case 0x20B4:
		725	/* VAP_VTX_SIZE */
1221	serge	726	track->vtx_size = idx_value & 0x7F;
1120	serge	727	break;
		728	case 0x2134:
		729	/* VAP_VF_MAX_VTX_INDX */
1221	serge	730	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	731	break;
		732	case 0x43E4:
		733	/* SC_SCISSOR1 */
1221	serge	734	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	735	if (p->rdev->family < CHIP_RV515) {
		736	track->maxy -= 1440;
		737	}
		738	break;
		739	case 0x4E00:
		740	/* RB3D_CCTL */
1221	serge	741	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1120	serge	742	break;
		743	case 0x4E38:
		744	case 0x4E3C:
		745	case 0x4E40:
		746	case 0x4E44:
		747	/* RB3D_COLORPITCH0 */
		748	/* RB3D_COLORPITCH1 */
		749	/* RB3D_COLORPITCH2 */
		750	/* RB3D_COLORPITCH3 */
1179	serge	751	r = r100_cs_packet_next_reloc(p, &reloc);
		752	if (r) {
		753	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		754	idx, reg);
		755	r100_cs_dump_packet(p, pkt);
		756	return r;
		757	}
		758
		759	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		760	tile_flags \|= R300_COLOR_TILE_ENABLE;
		761	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		762	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
1430	serge	763	else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
		764	tile_flags \|= R300_COLOR_MICROTILE_SQUARE_ENABLE;
1179	serge	765
1221	serge	766	tmp = idx_value & ~(0x7 << 16);
1179	serge	767	tmp \|= tile_flags;
		768	ib[idx] = tmp;
		769
1120	serge	770	i = (reg - 0x4E38) >> 2;
1221	serge	771	track->cb[i].pitch = idx_value & 0x3FFE;
		772	switch (((idx_value >> 21) & 0xF)) {
1120	serge	773	case 9:
		774	case 11:
		775	case 12:
		776	track->cb[i].cpp = 1;
		777	break;
		778	case 3:
		779	case 4:
		780	case 13:
		781	case 15:
		782	track->cb[i].cpp = 2;
		783	break;
		784	case 6:
		785	track->cb[i].cpp = 4;
		786	break;
		787	case 10:
		788	track->cb[i].cpp = 8;
		789	break;
		790	case 7:
		791	track->cb[i].cpp = 16;
		792	break;
		793	default:
		794	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	795	((idx_value >> 21) & 0xF));
1120	serge	796	return -EINVAL;
		797	}
		798	break;
		799	case 0x4F00:
		800	/* ZB_CNTL */
1221	serge	801	if (idx_value & 2) {
1120	serge	802	track->z_enabled = true;
		803	} else {
		804	track->z_enabled = false;
		805	}
		806	break;
		807	case 0x4F10:
		808	/* ZB_FORMAT */
1221	serge	809	switch ((idx_value & 0xF)) {
1120	serge	810	case 0:
		811	case 1:
		812	track->zb.cpp = 2;
		813	break;
		814	case 2:
		815	track->zb.cpp = 4;
		816	break;
		817	default:
		818	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	819	(idx_value & 0xF));
1120	serge	820	return -EINVAL;
		821	}
		822	break;
		823	case 0x4F24:
		824	/* ZB_DEPTHPITCH */
1179	serge	825	r = r100_cs_packet_next_reloc(p, &reloc);
		826	if (r) {
		827	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		828	idx, reg);
		829	r100_cs_dump_packet(p, pkt);
		830	return r;
		831	}
		832
		833	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		834	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
		835	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1430	serge	836	tile_flags \|= R300_DEPTHMICROTILE_TILED;
		837	else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
		838	tile_flags \|= R300_DEPTHMICROTILE_TILED_SQUARE;
1179	serge	839
1221	serge	840	tmp = idx_value & ~(0x7 << 16);
1179	serge	841	tmp \|= tile_flags;
		842	ib[idx] = tmp;
		843
1221	serge	844	track->zb.pitch = idx_value & 0x3FFC;
1120	serge	845	break;
		846	case 0x4104:
		847	for (i = 0; i < 16; i++) {
		848	bool enabled;
		849
1221	serge	850	enabled = !!(idx_value & (1 << i));
1120	serge	851	track->textures[i].enabled = enabled;
		852	}
		853	break;
		854	case 0x44C0:
		855	case 0x44C4:
		856	case 0x44C8:
		857	case 0x44CC:
		858	case 0x44D0:
		859	case 0x44D4:
		860	case 0x44D8:
		861	case 0x44DC:
		862	case 0x44E0:
		863	case 0x44E4:
		864	case 0x44E8:
		865	case 0x44EC:
		866	case 0x44F0:
		867	case 0x44F4:
		868	case 0x44F8:
		869	case 0x44FC:
		870	/* TX_FORMAT1_[0-15] */
		871	i = (reg - 0x44C0) >> 2;
1221	serge	872	tmp = (idx_value >> 25) & 0x3;
1120	serge	873	track->textures[i].tex_coord_type = tmp;
1221	serge	874	switch ((idx_value & 0x1F)) {
1179	serge	875	case R300_TX_FORMAT_X8:
		876	case R300_TX_FORMAT_Y4X4:
		877	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	878	track->textures[i].cpp = 1;
		879	break;
1179	serge	880	case R300_TX_FORMAT_X16:
		881	case R300_TX_FORMAT_Y8X8:
		882	case R300_TX_FORMAT_Z5Y6X5:
		883	case R300_TX_FORMAT_Z6Y5X5:
		884	case R300_TX_FORMAT_W4Z4Y4X4:
		885	case R300_TX_FORMAT_W1Z5Y5X5:
		886	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		887	case R300_TX_FORMAT_B8G8_B8G8:
		888	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	889	track->textures[i].cpp = 2;
		890	break;
1179	serge	891	case R300_TX_FORMAT_Y16X16:
		892	case R300_TX_FORMAT_Z11Y11X10:
		893	case R300_TX_FORMAT_Z10Y11X11:
		894	case R300_TX_FORMAT_W8Z8Y8X8:
		895	case R300_TX_FORMAT_W2Z10Y10X10:
		896	case 0x17:
		897	case R300_TX_FORMAT_FL_I32:
		898	case 0x1e:
1120	serge	899	track->textures[i].cpp = 4;
		900	break;
1179	serge	901	case R300_TX_FORMAT_W16Z16Y16X16:
		902	case R300_TX_FORMAT_FL_R16G16B16A16:
		903	case R300_TX_FORMAT_FL_I32A32:
1120	serge	904	track->textures[i].cpp = 8;
		905	break;
1179	serge	906	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	907	track->textures[i].cpp = 16;
		908	break;
1403	serge	909	case R300_TX_FORMAT_DXT1:
		910	track->textures[i].cpp = 1;
		911	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		912	break;
		913	case R300_TX_FORMAT_ATI2N:
		914	if (p->rdev->family < CHIP_R420) {
		915	DRM_ERROR("Invalid texture format %u\n",
		916	(idx_value & 0x1F));
		917	return -EINVAL;
		918	}
		919	/* The same rules apply as for DXT3/5. */
		920	/* Pass through. */
		921	case R300_TX_FORMAT_DXT3:
		922	case R300_TX_FORMAT_DXT5:
		923	track->textures[i].cpp = 1;
		924	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		925	break;
1120	serge	926	default:
		927	DRM_ERROR("Invalid texture format %u\n",
1221	serge	928	(idx_value & 0x1F));
1120	serge	929	return -EINVAL;
		930	break;
		931	}
		932	break;
		933	case 0x4400:
		934	case 0x4404:
		935	case 0x4408:
		936	case 0x440C:
		937	case 0x4410:
		938	case 0x4414:
		939	case 0x4418:
		940	case 0x441C:
		941	case 0x4420:
		942	case 0x4424:
		943	case 0x4428:
		944	case 0x442C:
		945	case 0x4430:
		946	case 0x4434:
		947	case 0x4438:
		948	case 0x443C:
		949	/* TX_FILTER0_[0-15] */
		950	i = (reg - 0x4400) >> 2;
1221	serge	951	tmp = idx_value & 0x7;
1120	serge	952	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		953	track->textures[i].roundup_w = false;
		954	}
1221	serge	955	tmp = (idx_value >> 3) & 0x7;
1120	serge	956	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		957	track->textures[i].roundup_h = false;
		958	}
		959	break;
		960	case 0x4500:
		961	case 0x4504:
		962	case 0x4508:
		963	case 0x450C:
		964	case 0x4510:
		965	case 0x4514:
		966	case 0x4518:
		967	case 0x451C:
		968	case 0x4520:
		969	case 0x4524:
		970	case 0x4528:
		971	case 0x452C:
		972	case 0x4530:
		973	case 0x4534:
		974	case 0x4538:
		975	case 0x453C:
		976	/* TX_FORMAT2_[0-15] */
		977	i = (reg - 0x4500) >> 2;
1221	serge	978	tmp = idx_value & 0x3FFF;
1120	serge	979	track->textures[i].pitch = tmp + 1;
		980	if (p->rdev->family >= CHIP_RV515) {
1221	serge	981	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	982	track->textures[i].width_11 = tmp;
1221	serge	983	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	984	track->textures[i].height_11 = tmp;
1403	serge	985
		986	/* ATI1N */
		987	if (idx_value & (1 << 14)) {
		988	/* The same rules apply as for DXT1. */
		989	track->textures[i].compress_format =
		990	R100_TRACK_COMP_DXT1;
		991	}
		992	} else if (idx_value & (1 << 14)) {
		993	DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
		994	return -EINVAL;
1120	serge	995	}
		996	break;
		997	case 0x4480:
		998	case 0x4484:
		999	case 0x4488:
		1000	case 0x448C:
		1001	case 0x4490:
		1002	case 0x4494:
		1003	case 0x4498:
		1004	case 0x449C:
		1005	case 0x44A0:
		1006	case 0x44A4:
		1007	case 0x44A8:
		1008	case 0x44AC:
		1009	case 0x44B0:
		1010	case 0x44B4:
		1011	case 0x44B8:
		1012	case 0x44BC:
		1013	/* TX_FORMAT0_[0-15] */
		1014	i = (reg - 0x4480) >> 2;
1221	serge	1015	tmp = idx_value & 0x7FF;
1120	serge	1016	track->textures[i].width = tmp + 1;
1221	serge	1017	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	1018	track->textures[i].height = tmp + 1;
1221	serge	1019	tmp = (idx_value >> 26) & 0xF;
1120	serge	1020	track->textures[i].num_levels = tmp;
1221	serge	1021	tmp = idx_value & (1 << 31);
1120	serge	1022	track->textures[i].use_pitch = !!tmp;
1221	serge	1023	tmp = (idx_value >> 22) & 0xF;
1120	serge	1024	track->textures[i].txdepth = tmp;
		1025	break;
1179	serge	1026	case R300_ZB_ZPASS_ADDR:
		1027	r = r100_cs_packet_next_reloc(p, &reloc);
		1028	if (r) {
		1029	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1030	idx, reg);
		1031	r100_cs_dump_packet(p, pkt);
		1032	return r;
		1033	}
1221	serge	1034	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1035	break;
1403	serge	1036	case 0x4e0c:
		1037	/* RB3D_COLOR_CHANNEL_MASK */
		1038	track->color_channel_mask = idx_value;
		1039	break;
		1040	case 0x4d1c:
		1041	/* ZB_BW_CNTL */
		1042	track->fastfill = !!(idx_value & (1 << 2));
		1043	break;
		1044	case 0x4e04:
		1045	/* RB3D_BLENDCNTL */
		1046	track->blend_read_enable = !!(idx_value & (1 << 2));
		1047	break;
1179	serge	1048	case 0x4be8:
		1049	/* valid register only on RV530 */
		1050	if (p->rdev->family == CHIP_RV530)
		1051	break;
		1052	/* fallthrough do not move */
1120	serge	1053	default:
		1054	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1055	reg, idx);
		1056	return -EINVAL;
		1057	}
		1058	return 0;
		1059	}
		1060
		1061	static int r300_packet3_check(struct radeon_cs_parser *p,
		1062	struct radeon_cs_packet *pkt)
		1063	{
		1064	struct radeon_cs_reloc *reloc;
1179	serge	1065	struct r100_cs_track *track;
1120	serge	1066	volatile uint32_t *ib;
		1067	unsigned idx;
		1068	int r;
		1069
		1070	ib = p->ib->ptr;
		1071	idx = pkt->idx + 1;
1179	serge	1072	track = (struct r100_cs_track *)p->track;
1120	serge	1073	switch(pkt->opcode) {
		1074	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1075	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1076	if (r)
1120	serge	1077	return r;
		1078	break;
		1079	case PACKET3_INDX_BUFFER:
		1080	r = r100_cs_packet_next_reloc(p, &reloc);
		1081	if (r) {
		1082	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1083	r100_cs_dump_packet(p, pkt);
		1084	return r;
		1085	}
1221	serge	1086	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1120	serge	1087	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1088	if (r) {
		1089	return r;
		1090	}
		1091	break;
		1092	/* Draw packet */
		1093	case PACKET3_3D_DRAW_IMMD:
		1094	/* Number of dwords is vtx_size * (num_vertices - 1)
		1095	* PRIM_WALK must be equal to 3 vertex data in embedded
		1096	* in cmd stream */
1221	serge	1097	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1098	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1099	return -EINVAL;
		1100	}
1221	serge	1101	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1102	track->immd_dwords = pkt->count - 1;
1179	serge	1103	r = r100_cs_track_check(p->rdev, track);
1120	serge	1104	if (r) {
		1105	return r;
		1106	}
		1107	break;
		1108	case PACKET3_3D_DRAW_IMMD_2:
		1109	/* Number of dwords is vtx_size * (num_vertices - 1)
		1110	* PRIM_WALK must be equal to 3 vertex data in embedded
		1111	* in cmd stream */
1221	serge	1112	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1113	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1114	return -EINVAL;
		1115	}
1221	serge	1116	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1117	track->immd_dwords = pkt->count;
1179	serge	1118	r = r100_cs_track_check(p->rdev, track);
1120	serge	1119	if (r) {
		1120	return r;
		1121	}
		1122	break;
		1123	case PACKET3_3D_DRAW_VBUF:
1221	serge	1124	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1125	r = r100_cs_track_check(p->rdev, track);
1120	serge	1126	if (r) {
		1127	return r;
		1128	}
		1129	break;
		1130	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1131	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1132	r = r100_cs_track_check(p->rdev, track);
1120	serge	1133	if (r) {
		1134	return r;
		1135	}
		1136	break;
		1137	case PACKET3_3D_DRAW_INDX:
1221	serge	1138	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1139	r = r100_cs_track_check(p->rdev, track);
1120	serge	1140	if (r) {
		1141	return r;
		1142	}
		1143	break;
		1144	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1145	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1146	r = r100_cs_track_check(p->rdev, track);
1120	serge	1147	if (r) {
		1148	return r;
		1149	}
		1150	break;
		1151	case PACKET3_NOP:
		1152	break;
		1153	default:
		1154	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1155	return -EINVAL;
		1156	}
		1157	return 0;
		1158	}
		1159
		1160	int r300_cs_parse(struct radeon_cs_parser *p)
		1161	{
		1162	struct radeon_cs_packet pkt;
1179	serge	1163	struct r100_cs_track *track;
1120	serge	1164	int r;
		1165
1179	serge	1166	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1167	r100_cs_track_clear(p->rdev, track);
		1168	p->track = track;
1120	serge	1169	do {
		1170	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1171	if (r) {
		1172	return r;
		1173	}
		1174	p->idx += pkt.count + 2;
		1175	switch (pkt.type) {
		1176	case PACKET_TYPE0:
		1177	r = r100_cs_parse_packet0(p, &pkt,
		1178	p->rdev->config.r300.reg_safe_bm,
		1179	p->rdev->config.r300.reg_safe_bm_size,
		1180	&r300_packet0_check);
		1181	break;
		1182	case PACKET_TYPE2:
		1183	break;
		1184	case PACKET_TYPE3:
		1185	r = r300_packet3_check(p, &pkt);
		1186	break;
		1187	default:
		1188	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1189	return -EINVAL;
		1190	}
		1191	if (r) {
		1192	return r;
		1193	}
		1194	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1195	return 0;
		1196	}
1128	serge	1197	#endif
		1198
1179	serge	1199
		1200	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1201	{
		1202	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1203	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1204	}
		1205
		1206	void r300_mc_program(struct radeon_device *rdev)
		1207	{
		1208	struct r100_mc_save save;
		1209	int r;
1120	serge	1210
1179	serge	1211	r = r100_debugfs_mc_info_init(rdev);
		1212	if (r) {
		1213	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1214	}
		1215
		1216	/* Stops all mc clients */
		1217	r100_mc_stop(rdev, &save);
		1218	if (rdev->flags & RADEON_IS_AGP) {
		1219	WREG32(R_00014C_MC_AGP_LOCATION,
		1220	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1221	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1222	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1223	WREG32(R_00015C_AGP_BASE_2,
		1224	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1225	} else {
		1226	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1227	WREG32(R_000170_AGP_BASE, 0);
		1228	WREG32(R_00015C_AGP_BASE_2, 0);
		1229	}
		1230	/* Wait for mc idle */
		1231	if (r300_mc_wait_for_idle(rdev))
		1232	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1233	/* Program MC, should be a 32bits limited address space */
		1234	WREG32(R_000148_MC_FB_LOCATION,
		1235	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1236	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1237	r100_mc_resume(rdev, &save);
		1238	}
1221	serge	1239
		1240	void r300_clock_startup(struct radeon_device *rdev)
		1241	{
		1242	u32 tmp;
		1243
		1244	if (radeon_dynclks != -1 && radeon_dynclks)
		1245	radeon_legacy_set_clock_gating(rdev, 1);
		1246	/* We need to force on some of the block */
		1247	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1248	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1249	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1250	tmp \|= S_00000D_FORCE_VAP(1);
		1251	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1252	}
		1253
		1254	static int r300_startup(struct radeon_device *rdev)
		1255	{
		1256	int r;
		1257
1321	serge	1258	/* set common regs */
		1259	r100_set_common_regs(rdev);
		1260	/* program mc */
1221	serge	1261	r300_mc_program(rdev);
		1262	/* Resume clock */
		1263	r300_clock_startup(rdev);
		1264	/* Initialize GPU configuration (# pipes, ...) */
		1265	r300_gpu_init(rdev);
		1266	/* Initialize GART (initialize after TTM so we can allocate
		1267	* memory through TTM but finalize after TTM) */
		1268	if (rdev->flags & RADEON_IS_PCIE) {
		1269	r = rv370_pcie_gart_enable(rdev);
		1270	if (r)
		1271	return r;
		1272	}
1321	serge	1273
		1274	if (rdev->family == CHIP_R300 \|\|
		1275	rdev->family == CHIP_R350 \|\|
		1276	rdev->family == CHIP_RV350)
		1277	r100_enable_bm(rdev);
		1278
1221	serge	1279	if (rdev->flags & RADEON_IS_PCI) {
		1280	r = r100_pci_gart_enable(rdev);
		1281	if (r)
		1282	return r;
		1283	}
		1284	/* Enable IRQ */
		1285	// r100_irq_set(rdev);
1403	serge	1286	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	1287	/* 1M ring buffer */
1412	serge	1288	r = r100_cp_init(rdev, 1024 * 1024);
		1289	if (r) {
		1290	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		1291	return r;
		1292	}
1221	serge	1293	// r = r100_wb_init(rdev);
		1294	// if (r)
		1295	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		1296	// r = r100_ib_init(rdev);
		1297	// if (r) {
		1298	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		1299	// return r;
		1300	// }
		1301	return 0;
		1302	}
		1303
		1304
		1305
		1306
		1307
		1308	int r300_init(struct radeon_device *rdev)
		1309	{
		1310	int r;
		1311
		1312	/* Disable VGA */
		1313	r100_vga_render_disable(rdev);
		1314	/* Initialize scratch registers */
		1315	radeon_scratch_init(rdev);
		1316	/* Initialize surface registers */
		1317	radeon_surface_init(rdev);
		1318	/* TODO: disable VGA need to use VGA request */
		1319	/* BIOS*/
		1320	if (!radeon_get_bios(rdev)) {
		1321	if (ASIC_IS_AVIVO(rdev))
		1322	return -EINVAL;
		1323	}
		1324	if (rdev->is_atom_bios) {
		1325	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1326	return -EINVAL;
		1327	} else {
		1328	r = radeon_combios_init(rdev);
		1329	if (r)
		1330	return r;
		1331	}
		1332	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		1333	if (radeon_gpu_reset(rdev)) {
		1334	dev_warn(rdev->dev,
		1335	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1336	RREG32(R_000E40_RBBM_STATUS),
		1337	RREG32(R_0007C0_CP_STAT));
		1338	}
		1339	/* check if cards are posted or not */
1321	serge	1340	if (radeon_boot_test_post_card(rdev) == false)
		1341	return -EINVAL;
1221	serge	1342	/* Set asic errata */
		1343	r300_errata(rdev);
		1344	/* Initialize clocks */
		1345	radeon_get_clock_info(rdev->ddev);
1403	serge	1346	/* Initialize power management */
		1347	radeon_pm_init(rdev);
1430	serge	1348	/* initialize AGP */
		1349	if (rdev->flags & RADEON_IS_AGP) {
		1350	r = radeon_agp_init(rdev);
		1351	if (r) {
		1352	radeon_agp_disable(rdev);
		1353	}
		1354	}
		1355	/* initialize memory controller */
		1356	r300_mc_init(rdev);
1221	serge	1357	/* Fence driver */
		1358	// r = radeon_fence_driver_init(rdev);
		1359	// if (r)
		1360	// return r;
		1361	// r = radeon_irq_kms_init(rdev);
		1362	// if (r)
		1363	// return r;
		1364	/* Memory manager */
1404	serge	1365	r = radeon_bo_init(rdev);
1221	serge	1366	if (r)
		1367	return r;
		1368	if (rdev->flags & RADEON_IS_PCIE) {
		1369	r = rv370_pcie_gart_init(rdev);
		1370	if (r)
		1371	return r;
		1372	}
		1373	if (rdev->flags & RADEON_IS_PCI) {
		1374	r = r100_pci_gart_init(rdev);
		1375	if (r)
		1376	return r;
		1377	}
		1378	r300_set_reg_safe(rdev);
		1379	rdev->accel_working = true;
		1380	r = r300_startup(rdev);
		1381	if (r) {
		1382	/* Somethings want wront with the accel init stop accel */
		1383	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		1384	// r100_cp_fini(rdev);
		1385	// r100_wb_fini(rdev);
		1386	// r100_ib_fini(rdev);
		1387	if (rdev->flags & RADEON_IS_PCIE)
		1388	rv370_pcie_gart_fini(rdev);
		1389	if (rdev->flags & RADEON_IS_PCI)
		1390	r100_pci_gart_fini(rdev);
1404	serge	1391	// radeon_agp_fini(rdev);
1221	serge	1392	rdev->accel_working = false;
		1393	}
		1394	return 0;
		1395	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r300.c – Rev 1430