WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r300.c

Rev	Author	Line No.	Line
1120	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1120	serge	31	#include "radeon_reg.h"
		32	#include "radeon.h"
1179	serge	33	#include "radeon_drm.h"
1120	serge	34
1179	serge	35	#include "r300d.h"
1221	serge	36	#include "rv350d.h"
1179	serge	37	#include "r300_reg_safe.h"
		38
1221	serge	39	/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
1120	serge	40
		41	/*
		42	* rv370,rv380 PCIE GART
		43	*/
1221	serge	44	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
		45
1120	serge	46	void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
		47	{
		48	uint32_t tmp;
		49	int i;
		50
		51	/* Workaround HW bug do flush 2 times */
		52	for (i = 0; i < 2; i++) {
		53	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		54	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp \| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
		55	(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		56	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1179	serge	57	}
1120	serge	58	mb();
1179	serge	59	}
		60
		61	int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		62	{
		63	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
		64
		65	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		66	return -EINVAL;
1120	serge	67	}
1179	serge	68	addr = (lower_32_bits(addr) >> 8) \|
		69	((upper_32_bits(addr) & 0xff) << 24) \|
		70	0xc;
		71	/* on x86 we want this to be CPU endian, on powerpc
		72	* on powerpc without HW swappers, it'll get swapped on way
		73	* into VRAM - so no need for cpu_to_le32 on VRAM tables */
		74	writel(addr, ((void __iomem )ptr) + (i 4));
		75	return 0;
1120	serge	76	}
		77
1179	serge	78	int rv370_pcie_gart_init(struct radeon_device *rdev)
1120	serge	79	{
		80	int r;
		81
1179	serge	82	if (rdev->gart.table.vram.robj) {
		83	WARN(1, "RV370 PCIE GART already initialized.\n");
		84	return 0;
		85	}
1120	serge	86	/* Initialize common gart structure */
		87	r = radeon_gart_init(rdev);
1179	serge	88	if (r)
1120	serge	89	return r;
1129	serge	90	r = rv370_debugfs_pcie_gart_info_init(rdev);
1179	serge	91	if (r)
1129	serge	92	DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
1179	serge	93	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		94	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		95	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		96	return radeon_gart_table_vram_alloc(rdev);
		97	}
		98
		99	int rv370_pcie_gart_enable(struct radeon_device *rdev)
		100	{
		101	uint32_t table_addr;
		102	uint32_t tmp;
		103	int r;
		104
		105	if (rdev->gart.table.vram.robj == NULL) {
		106	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		107	return -EINVAL;
1129	serge	108	}
1179	serge	109	r = radeon_gart_table_vram_pin(rdev);
		110	if (r)
1120	serge	111	return r;
		112	/* discard memory request outside of configured range */
		113	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		114	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		115	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
		116	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
		117	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
		118	WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
		119	WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
		120	table_addr = rdev->gart.table_addr;
		121	WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
		122	/* FIXME: setup default page */
		123	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
		124	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
		125	/* Clear error */
		126	WREG32_PCIE(0x18, 0);
		127	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		128	tmp \|= RADEON_PCIE_TX_GART_EN;
		129	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		130	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
		131	rv370_pcie_gart_tlb_flush(rdev);
		132	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
1179	serge	133	(unsigned)(rdev->mc.gtt_size >> 20), table_addr);
1120	serge	134	rdev->gart.ready = true;
		135	return 0;
		136	}
		137
		138	void rv370_pcie_gart_disable(struct radeon_device *rdev)
		139	{
		140	uint32_t tmp;
		141
		142	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		143	tmp \|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
		144	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
		145	if (rdev->gart.table.vram.robj) {
		146	// radeon_object_kunmap(rdev->gart.table.vram.robj);
		147	// radeon_object_unpin(rdev->gart.table.vram.robj);
		148	}
		149	}
		150
1179	serge	151	void rv370_pcie_gart_fini(struct radeon_device *rdev)
1120	serge	152	{
		153	rv370_pcie_gart_disable(rdev);
1179	serge	154	radeon_gart_table_vram_free(rdev);
		155	radeon_gart_fini(rdev);
1120	serge	156	}
		157
		158	void r300_fence_ring_emit(struct radeon_device *rdev,
		159	struct radeon_fence *fence)
		160	{
		161	/* Who ever call radeon_fence_emit should call ring_lock and ask
		162	* for enough space (today caller are ib schedule and buffer move) */
		163	/* Write SC register so SC & US assert idle */
		164	radeon_ring_write(rdev, PACKET0(0x43E0, 0));
		165	radeon_ring_write(rdev, 0);
		166	radeon_ring_write(rdev, PACKET0(0x43E4, 0));
		167	radeon_ring_write(rdev, 0);
		168	/* Flush 3D cache */
		169	radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
		170	radeon_ring_write(rdev, (2 << 0));
		171	radeon_ring_write(rdev, PACKET0(0x4F18, 0));
		172	radeon_ring_write(rdev, (1 << 0));
		173	/* Wait until IDLE & CLEAN */
		174	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		175	radeon_ring_write(rdev, (1 << 17) \| (1 << 16) \| (1 << 9));
		176	/* Emit fence sequence & fire IRQ */
		177	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		178	radeon_ring_write(rdev, fence->seq);
		179	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		180	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		181	}
		182
		183
1128	serge	184	#if 0
		185
1221	serge	186
1120	serge	187	int r300_copy_dma(struct radeon_device *rdev,
		188	uint64_t src_offset,
		189	uint64_t dst_offset,
		190	unsigned num_pages,
		191	struct radeon_fence *fence)
		192	{
		193	uint32_t size;
		194	uint32_t cur_size;
		195	int i, num_loops;
		196	int r = 0;
		197
		198	/* radeon pitch is /64 */
		199	size = num_pages << PAGE_SHIFT;
		200	num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
		201	r = radeon_ring_lock(rdev, num_loops * 4 + 64);
		202	if (r) {
		203	DRM_ERROR("radeon: moving bo (%d).\n", r);
		204	return r;
		205	}
		206	/* Must wait for 2D idle & clean before DMA or hangs might happen */
		207	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
		208	radeon_ring_write(rdev, (1 << 16));
		209	for (i = 0; i < num_loops; i++) {
		210	cur_size = size;
		211	if (cur_size > 0x1FFFFF) {
		212	cur_size = 0x1FFFFF;
		213	}
		214	size -= cur_size;
		215	radeon_ring_write(rdev, PACKET0(0x720, 2));
		216	radeon_ring_write(rdev, src_offset);
		217	radeon_ring_write(rdev, dst_offset);
		218	radeon_ring_write(rdev, cur_size \| (1 << 31) \| (1 << 30));
		219	src_offset += cur_size;
		220	dst_offset += cur_size;
		221	}
		222	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		223	radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
		224	if (fence) {
		225	r = radeon_fence_emit(rdev, fence);
		226	}
		227	radeon_ring_unlock_commit(rdev);
		228	return r;
		229	}
		230
1128	serge	231	#endif
		232
1120	serge	233	void r300_ring_start(struct radeon_device *rdev)
		234	{
		235	unsigned gb_tile_config;
		236	int r;
		237
		238	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
		239	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		240	switch(rdev->num_gb_pipes) {
		241	case 2:
		242	gb_tile_config \|= R300_PIPE_COUNT_R300;
		243	break;
		244	case 3:
		245	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		246	break;
		247	case 4:
		248	gb_tile_config \|= R300_PIPE_COUNT_R420;
		249	break;
		250	case 1:
		251	default:
		252	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		253	break;
		254	}
		255
		256	r = radeon_ring_lock(rdev, 64);
		257	if (r) {
		258	return;
		259	}
		260	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		261	radeon_ring_write(rdev,
		262	RADEON_ISYNC_ANY2D_IDLE3D \|
		263	RADEON_ISYNC_ANY3D_IDLE2D \|
		264	RADEON_ISYNC_WAIT_IDLEGUI \|
		265	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		266	radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
		267	radeon_ring_write(rdev, gb_tile_config);
		268	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		269	radeon_ring_write(rdev,
		270	RADEON_WAIT_2D_IDLECLEAN \|
		271	RADEON_WAIT_3D_IDLECLEAN);
		272	radeon_ring_write(rdev, PACKET0(0x170C, 0));
		273	radeon_ring_write(rdev, 1 << 31);
		274	radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
		275	radeon_ring_write(rdev, 0);
		276	radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
		277	radeon_ring_write(rdev, 0);
		278	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		279	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		280	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		281	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		282	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		283	radeon_ring_write(rdev,
		284	RADEON_WAIT_2D_IDLECLEAN \|
		285	RADEON_WAIT_3D_IDLECLEAN);
		286	radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
		287	radeon_ring_write(rdev, 0);
		288	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
		289	radeon_ring_write(rdev, R300_RB3D_DC_FLUSH \| R300_RB3D_DC_FREE);
		290	radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
		291	radeon_ring_write(rdev, R300_ZC_FLUSH \| R300_ZC_FREE);
		292	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
		293	radeon_ring_write(rdev,
		294	((6 << R300_MS_X0_SHIFT) \|
		295	(6 << R300_MS_Y0_SHIFT) \|
		296	(6 << R300_MS_X1_SHIFT) \|
		297	(6 << R300_MS_Y1_SHIFT) \|
		298	(6 << R300_MS_X2_SHIFT) \|
		299	(6 << R300_MS_Y2_SHIFT) \|
		300	(6 << R300_MSBD0_Y_SHIFT) \|
		301	(6 << R300_MSBD0_X_SHIFT)));
		302	radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
		303	radeon_ring_write(rdev,
		304	((6 << R300_MS_X3_SHIFT) \|
		305	(6 << R300_MS_Y3_SHIFT) \|
		306	(6 << R300_MS_X4_SHIFT) \|
		307	(6 << R300_MS_Y4_SHIFT) \|
		308	(6 << R300_MS_X5_SHIFT) \|
		309	(6 << R300_MS_Y5_SHIFT) \|
		310	(6 << R300_MSBD1_SHIFT)));
		311	radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
		312	radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL);
		313	radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
		314	radeon_ring_write(rdev,
		315	R300_FRONT_PTYPE_TRIANGE \| R300_BACK_PTYPE_TRIANGE);
		316	radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
		317	radeon_ring_write(rdev,
		318	R300_GEOMETRY_ROUND_NEAREST \|
		319	R300_COLOR_ROUND_NEAREST);
		320	radeon_ring_unlock_commit(rdev);
		321	}
		322
		323	void r300_errata(struct radeon_device *rdev)
		324	{
		325	rdev->pll_errata = 0;
		326
		327	if (rdev->family == CHIP_R300 &&
		328	(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
		329	rdev->pll_errata \|= CHIP_ERRATA_R300_CG;
		330	}
		331	}
		332
		333	int r300_mc_wait_for_idle(struct radeon_device *rdev)
		334	{
		335	unsigned i;
		336	uint32_t tmp;
		337
		338	for (i = 0; i < rdev->usec_timeout; i++) {
		339	/* read MC_STATUS */
		340	tmp = RREG32(0x0150);
		341	if (tmp & (1 << 4)) {
		342	return 0;
		343	}
		344	DRM_UDELAY(1);
		345	}
		346	return -1;
		347	}
		348
		349	void r300_gpu_init(struct radeon_device *rdev)
		350	{
		351	uint32_t gb_tile_config, tmp;
		352
		353	r100_hdp_reset(rdev);
		354	/* FIXME: rv380 one pipes ? */
		355	if ((rdev->family == CHIP_R300) \|\| (rdev->family == CHIP_R350)) {
		356	/* r300,r350 */
		357	rdev->num_gb_pipes = 2;
		358	} else {
		359	/* rv350,rv370,rv380 */
		360	rdev->num_gb_pipes = 1;
		361	}
1179	serge	362	rdev->num_z_pipes = 1;
1120	serge	363	gb_tile_config = (R300_ENABLE_TILING \| R300_TILE_SIZE_16);
		364	switch (rdev->num_gb_pipes) {
		365	case 2:
		366	gb_tile_config \|= R300_PIPE_COUNT_R300;
		367	break;
		368	case 3:
		369	gb_tile_config \|= R300_PIPE_COUNT_R420_3P;
		370	break;
		371	case 4:
		372	gb_tile_config \|= R300_PIPE_COUNT_R420;
		373	break;
		374	default:
		375	case 1:
		376	gb_tile_config \|= R300_PIPE_COUNT_RV350;
		377	break;
		378	}
		379	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
		380
		381	if (r100_gui_wait_for_idle(rdev)) {
		382	printk(KERN_WARNING "Failed to wait GUI idle while "
		383	"programming pipes. Bad things might happen.\n");
		384	}
		385
		386	tmp = RREG32(0x170C);
		387	WREG32(0x170C, tmp \| (1 << 31));
		388
		389	WREG32(R300_RB2D_DSTCACHE_MODE,
		390	R300_DC_AUTOFLUSH_ENABLE \|
		391	R300_DC_DC_DISABLE_IGNORE_PE);
		392
		393	if (r100_gui_wait_for_idle(rdev)) {
		394	printk(KERN_WARNING "Failed to wait GUI idle while "
		395	"programming pipes. Bad things might happen.\n");
		396	}
		397	if (r300_mc_wait_for_idle(rdev)) {
		398	printk(KERN_WARNING "Failed to wait MC idle while "
		399	"programming pipes. Bad things might happen.\n");
		400	}
1179	serge	401	DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
		402	rdev->num_gb_pipes, rdev->num_z_pipes);
1120	serge	403	}
		404
		405	int r300_ga_reset(struct radeon_device *rdev)
		406	{
		407	uint32_t tmp;
		408	bool reinit_cp;
		409	int i;
		410
		411	reinit_cp = rdev->cp.ready;
		412	rdev->cp.ready = false;
		413	for (i = 0; i < rdev->usec_timeout; i++) {
		414	WREG32(RADEON_CP_CSQ_MODE, 0);
		415	WREG32(RADEON_CP_CSQ_CNTL, 0);
		416	WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
		417	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		418	udelay(200);
		419	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		420	/* Wait to prevent race in RBBM_STATUS */
		421	mdelay(1);
		422	tmp = RREG32(RADEON_RBBM_STATUS);
		423	if (tmp & ((1 << 20) \| (1 << 26))) {
		424	DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
		425	/* GA still busy soft reset it */
		426	WREG32(0x429C, 0x200);
		427	WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
		428	WREG32(0x43E0, 0);
		429	WREG32(0x43E4, 0);
		430	WREG32(0x24AC, 0);
		431	}
		432	/* Wait to prevent race in RBBM_STATUS */
		433	mdelay(1);
		434	tmp = RREG32(RADEON_RBBM_STATUS);
		435	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		436	break;
		437	}
		438	}
		439	for (i = 0; i < rdev->usec_timeout; i++) {
		440	tmp = RREG32(RADEON_RBBM_STATUS);
		441	if (!(tmp & ((1 << 20) \| (1 << 26)))) {
		442	DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
		443	tmp);
		444	if (reinit_cp) {
		445	return r100_cp_init(rdev, rdev->cp.ring_size);
		446	}
		447	return 0;
		448	}
		449	DRM_UDELAY(1);
		450	}
		451	tmp = RREG32(RADEON_RBBM_STATUS);
		452	DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
		453	return -1;
		454	}
		455
		456	int r300_gpu_reset(struct radeon_device *rdev)
		457	{
		458	uint32_t status;
		459
		460	/* reset order likely matter */
		461	status = RREG32(RADEON_RBBM_STATUS);
		462	/* reset HDP */
		463	r100_hdp_reset(rdev);
		464	/* reset rb2d */
		465	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		466	r100_rb2d_reset(rdev);
		467	}
		468	/* reset GA */
		469	if (status & ((1 << 20) \| (1 << 26))) {
		470	r300_ga_reset(rdev);
		471	}
		472	/* reset CP */
		473	status = RREG32(RADEON_RBBM_STATUS);
		474	if (status & (1 << 16)) {
		475	r100_cp_reset(rdev);
		476	}
		477	/* Check if GPU is idle */
		478	status = RREG32(RADEON_RBBM_STATUS);
		479	if (status & (1 << 31)) {
		480	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		481	return -1;
		482	}
		483	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		484	return 0;
		485	}
		486
		487
		488	/*
		489	* r300,r350,rv350,rv380 VRAM info
		490	*/
		491	void r300_vram_info(struct radeon_device *rdev)
		492	{
		493	uint32_t tmp;
		494
		495	/* DDR for all card after R300 & IGP */
		496	rdev->mc.vram_is_ddr = true;
		497	tmp = RREG32(RADEON_MEM_CNTL);
		498	if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
		499	rdev->mc.vram_width = 128;
		500	} else {
		501	rdev->mc.vram_width = 64;
		502	}
		503
1179	serge	504	r100_vram_init_sizes(rdev);
1120	serge	505	}
		506
		507	void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
		508	{
		509	uint32_t link_width_cntl, mask;
		510
		511	if (rdev->flags & RADEON_IS_IGP)
		512	return;
		513
		514	if (!(rdev->flags & RADEON_IS_PCIE))
		515	return;
		516
		517	/* FIXME wait for idle */
		518
		519	switch (lanes) {
		520	case 0:
		521	mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
		522	break;
		523	case 1:
		524	mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
		525	break;
		526	case 2:
		527	mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
		528	break;
		529	case 4:
		530	mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
		531	break;
		532	case 8:
		533	mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
		534	break;
		535	case 12:
		536	mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
		537	break;
		538	case 16:
		539	default:
		540	mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
		541	break;
		542	}
		543
		544	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		545
		546	if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
		547	(mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
		548	return;
		549
		550	link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK \|
		551	RADEON_PCIE_LC_RECONFIG_NOW \|
		552	RADEON_PCIE_LC_RECONFIG_LATER \|
		553	RADEON_PCIE_LC_SHORT_RECONFIG_EN);
		554	link_width_cntl \|= mask;
		555	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
		556	WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl \|
		557	RADEON_PCIE_LC_RECONFIG_NOW));
		558
		559	/* wait for lane set to complete */
		560	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		561	while (link_width_cntl == 0xffffffff)
		562	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
		563
		564	}
		565
		566	#if defined(CONFIG_DEBUG_FS)
		567	static int rv370_debugfs_pcie_gart_info(struct seq_file m, void data)
		568	{
		569	struct drm_info_node node = (struct drm_info_node ) m->private;
		570	struct drm_device *dev = node->minor->dev;
		571	struct radeon_device *rdev = dev->dev_private;
		572	uint32_t tmp;
		573
		574	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
		575	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
		576	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
		577	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
		578	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
		579	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
		580	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
		581	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
		582	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
		583	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
		584	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
		585	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
		586	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
		587	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
		588	return 0;
		589	}
		590
		591	static struct drm_info_list rv370_pcie_gart_info_list[] = {
		592	{"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
		593	};
		594	#endif
		595
1221	serge	596	static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
1120	serge	597	{
		598	#if defined(CONFIG_DEBUG_FS)
		599	return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
		600	#else
		601	return 0;
		602	#endif
		603	}
		604
		605
1128	serge	606	#if 0
1221	serge	607
1120	serge	608	static int r300_packet0_check(struct radeon_cs_parser *p,
		609	struct radeon_cs_packet *pkt,
		610	unsigned idx, unsigned reg)
		611	{
		612	struct radeon_cs_reloc *reloc;
1179	serge	613	struct r100_cs_track *track;
1120	serge	614	volatile uint32_t *ib;
1179	serge	615	uint32_t tmp, tile_flags = 0;
1120	serge	616	unsigned i;
		617	int r;
1221	serge	618	u32 idx_value;
1120	serge	619
		620	ib = p->ib->ptr;
1179	serge	621	track = (struct r100_cs_track *)p->track;
1221	serge	622	idx_value = radeon_get_ib_value(p, idx);
		623
1120	serge	624	switch(reg) {
1179	serge	625	case AVIVO_D1MODE_VLINE_START_END:
		626	case RADEON_CRTC_GUI_TRIG_VLINE:
		627	r = r100_cs_packet_parse_vline(p);
1120	serge	628	if (r) {
		629	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		630	idx, reg);
		631	r100_cs_dump_packet(p, pkt);
		632	return r;
		633	}
		634	break;
1179	serge	635	case RADEON_DST_PITCH_OFFSET:
		636	case RADEON_SRC_PITCH_OFFSET:
		637	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		638	if (r)
		639	return r;
		640	break;
1120	serge	641	case R300_RB3D_COLOROFFSET0:
		642	case R300_RB3D_COLOROFFSET1:
		643	case R300_RB3D_COLOROFFSET2:
		644	case R300_RB3D_COLOROFFSET3:
		645	i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
		646	r = r100_cs_packet_next_reloc(p, &reloc);
		647	if (r) {
		648	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		649	idx, reg);
		650	r100_cs_dump_packet(p, pkt);
		651	return r;
		652	}
		653	track->cb[i].robj = reloc->robj;
1221	serge	654	track->cb[i].offset = idx_value;
		655	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	656	break;
		657	case R300_ZB_DEPTHOFFSET:
		658	r = r100_cs_packet_next_reloc(p, &reloc);
		659	if (r) {
		660	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		661	idx, reg);
		662	r100_cs_dump_packet(p, pkt);
		663	return r;
		664	}
		665	track->zb.robj = reloc->robj;
1221	serge	666	track->zb.offset = idx_value;
		667	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	668	break;
		669	case R300_TX_OFFSET_0:
		670	case R300_TX_OFFSET_0+4:
		671	case R300_TX_OFFSET_0+8:
		672	case R300_TX_OFFSET_0+12:
		673	case R300_TX_OFFSET_0+16:
		674	case R300_TX_OFFSET_0+20:
		675	case R300_TX_OFFSET_0+24:
		676	case R300_TX_OFFSET_0+28:
		677	case R300_TX_OFFSET_0+32:
		678	case R300_TX_OFFSET_0+36:
		679	case R300_TX_OFFSET_0+40:
		680	case R300_TX_OFFSET_0+44:
		681	case R300_TX_OFFSET_0+48:
		682	case R300_TX_OFFSET_0+52:
		683	case R300_TX_OFFSET_0+56:
		684	case R300_TX_OFFSET_0+60:
		685	i = (reg - R300_TX_OFFSET_0) >> 2;
		686	r = r100_cs_packet_next_reloc(p, &reloc);
		687	if (r) {
		688	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		689	idx, reg);
		690	r100_cs_dump_packet(p, pkt);
		691	return r;
		692	}
1221	serge	693	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1120	serge	694	track->textures[i].robj = reloc->robj;
		695	break;
		696	/* Tracked registers */
		697	case 0x2084:
		698	/* VAP_VF_CNTL */
1221	serge	699	track->vap_vf_cntl = idx_value;
1120	serge	700	break;
		701	case 0x20B4:
		702	/* VAP_VTX_SIZE */
1221	serge	703	track->vtx_size = idx_value & 0x7F;
1120	serge	704	break;
		705	case 0x2134:
		706	/* VAP_VF_MAX_VTX_INDX */
1221	serge	707	track->max_indx = idx_value & 0x00FFFFFFUL;
1120	serge	708	break;
		709	case 0x43E4:
		710	/* SC_SCISSOR1 */
1221	serge	711	track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
1120	serge	712	if (p->rdev->family < CHIP_RV515) {
		713	track->maxy -= 1440;
		714	}
		715	break;
		716	case 0x4E00:
		717	/* RB3D_CCTL */
1221	serge	718	track->num_cb = ((idx_value >> 5) & 0x3) + 1;
1120	serge	719	break;
		720	case 0x4E38:
		721	case 0x4E3C:
		722	case 0x4E40:
		723	case 0x4E44:
		724	/* RB3D_COLORPITCH0 */
		725	/* RB3D_COLORPITCH1 */
		726	/* RB3D_COLORPITCH2 */
		727	/* RB3D_COLORPITCH3 */
1179	serge	728	r = r100_cs_packet_next_reloc(p, &reloc);
		729	if (r) {
		730	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		731	idx, reg);
		732	r100_cs_dump_packet(p, pkt);
		733	return r;
		734	}
		735
		736	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		737	tile_flags \|= R300_COLOR_TILE_ENABLE;
		738	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		739	tile_flags \|= R300_COLOR_MICROTILE_ENABLE;
		740
1221	serge	741	tmp = idx_value & ~(0x7 << 16);
1179	serge	742	tmp \|= tile_flags;
		743	ib[idx] = tmp;
		744
1120	serge	745	i = (reg - 0x4E38) >> 2;
1221	serge	746	track->cb[i].pitch = idx_value & 0x3FFE;
		747	switch (((idx_value >> 21) & 0xF)) {
1120	serge	748	case 9:
		749	case 11:
		750	case 12:
		751	track->cb[i].cpp = 1;
		752	break;
		753	case 3:
		754	case 4:
		755	case 13:
		756	case 15:
		757	track->cb[i].cpp = 2;
		758	break;
		759	case 6:
		760	track->cb[i].cpp = 4;
		761	break;
		762	case 10:
		763	track->cb[i].cpp = 8;
		764	break;
		765	case 7:
		766	track->cb[i].cpp = 16;
		767	break;
		768	default:
		769	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	770	((idx_value >> 21) & 0xF));
1120	serge	771	return -EINVAL;
		772	}
		773	break;
		774	case 0x4F00:
		775	/* ZB_CNTL */
1221	serge	776	if (idx_value & 2) {
1120	serge	777	track->z_enabled = true;
		778	} else {
		779	track->z_enabled = false;
		780	}
		781	break;
		782	case 0x4F10:
		783	/* ZB_FORMAT */
1221	serge	784	switch ((idx_value & 0xF)) {
1120	serge	785	case 0:
		786	case 1:
		787	track->zb.cpp = 2;
		788	break;
		789	case 2:
		790	track->zb.cpp = 4;
		791	break;
		792	default:
		793	DRM_ERROR("Invalid z buffer format (%d) !\n",
1221	serge	794	(idx_value & 0xF));
1120	serge	795	return -EINVAL;
		796	}
		797	break;
		798	case 0x4F24:
		799	/* ZB_DEPTHPITCH */
1179	serge	800	r = r100_cs_packet_next_reloc(p, &reloc);
		801	if (r) {
		802	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		803	idx, reg);
		804	r100_cs_dump_packet(p, pkt);
		805	return r;
		806	}
		807
		808	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		809	tile_flags \|= R300_DEPTHMACROTILE_ENABLE;
		810	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		811	tile_flags \|= R300_DEPTHMICROTILE_TILED;;
		812
1221	serge	813	tmp = idx_value & ~(0x7 << 16);
1179	serge	814	tmp \|= tile_flags;
		815	ib[idx] = tmp;
		816
1221	serge	817	track->zb.pitch = idx_value & 0x3FFC;
1120	serge	818	break;
		819	case 0x4104:
		820	for (i = 0; i < 16; i++) {
		821	bool enabled;
		822
1221	serge	823	enabled = !!(idx_value & (1 << i));
1120	serge	824	track->textures[i].enabled = enabled;
		825	}
		826	break;
		827	case 0x44C0:
		828	case 0x44C4:
		829	case 0x44C8:
		830	case 0x44CC:
		831	case 0x44D0:
		832	case 0x44D4:
		833	case 0x44D8:
		834	case 0x44DC:
		835	case 0x44E0:
		836	case 0x44E4:
		837	case 0x44E8:
		838	case 0x44EC:
		839	case 0x44F0:
		840	case 0x44F4:
		841	case 0x44F8:
		842	case 0x44FC:
		843	/* TX_FORMAT1_[0-15] */
		844	i = (reg - 0x44C0) >> 2;
1221	serge	845	tmp = (idx_value >> 25) & 0x3;
1120	serge	846	track->textures[i].tex_coord_type = tmp;
1221	serge	847	switch ((idx_value & 0x1F)) {
1179	serge	848	case R300_TX_FORMAT_X8:
		849	case R300_TX_FORMAT_Y4X4:
		850	case R300_TX_FORMAT_Z3Y3X2:
1120	serge	851	track->textures[i].cpp = 1;
		852	break;
1179	serge	853	case R300_TX_FORMAT_X16:
		854	case R300_TX_FORMAT_Y8X8:
		855	case R300_TX_FORMAT_Z5Y6X5:
		856	case R300_TX_FORMAT_Z6Y5X5:
		857	case R300_TX_FORMAT_W4Z4Y4X4:
		858	case R300_TX_FORMAT_W1Z5Y5X5:
		859	case R300_TX_FORMAT_DXT1:
		860	case R300_TX_FORMAT_D3DMFT_CxV8U8:
		861	case R300_TX_FORMAT_B8G8_B8G8:
		862	case R300_TX_FORMAT_G8R8_G8B8:
1120	serge	863	track->textures[i].cpp = 2;
		864	break;
1179	serge	865	case R300_TX_FORMAT_Y16X16:
		866	case R300_TX_FORMAT_Z11Y11X10:
		867	case R300_TX_FORMAT_Z10Y11X11:
		868	case R300_TX_FORMAT_W8Z8Y8X8:
		869	case R300_TX_FORMAT_W2Z10Y10X10:
		870	case 0x17:
		871	case R300_TX_FORMAT_FL_I32:
		872	case 0x1e:
		873	case R300_TX_FORMAT_DXT3:
		874	case R300_TX_FORMAT_DXT5:
1120	serge	875	track->textures[i].cpp = 4;
		876	break;
1179	serge	877	case R300_TX_FORMAT_W16Z16Y16X16:
		878	case R300_TX_FORMAT_FL_R16G16B16A16:
		879	case R300_TX_FORMAT_FL_I32A32:
1120	serge	880	track->textures[i].cpp = 8;
		881	break;
1179	serge	882	case R300_TX_FORMAT_FL_R32G32B32A32:
1120	serge	883	track->textures[i].cpp = 16;
		884	break;
		885	default:
		886	DRM_ERROR("Invalid texture format %u\n",
1221	serge	887	(idx_value & 0x1F));
1120	serge	888	return -EINVAL;
		889	break;
		890	}
		891	break;
		892	case 0x4400:
		893	case 0x4404:
		894	case 0x4408:
		895	case 0x440C:
		896	case 0x4410:
		897	case 0x4414:
		898	case 0x4418:
		899	case 0x441C:
		900	case 0x4420:
		901	case 0x4424:
		902	case 0x4428:
		903	case 0x442C:
		904	case 0x4430:
		905	case 0x4434:
		906	case 0x4438:
		907	case 0x443C:
		908	/* TX_FILTER0_[0-15] */
		909	i = (reg - 0x4400) >> 2;
1221	serge	910	tmp = idx_value & 0x7;
1120	serge	911	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		912	track->textures[i].roundup_w = false;
		913	}
1221	serge	914	tmp = (idx_value >> 3) & 0x7;
1120	serge	915	if (tmp == 2 \|\| tmp == 4 \|\| tmp == 6) {
		916	track->textures[i].roundup_h = false;
		917	}
		918	break;
		919	case 0x4500:
		920	case 0x4504:
		921	case 0x4508:
		922	case 0x450C:
		923	case 0x4510:
		924	case 0x4514:
		925	case 0x4518:
		926	case 0x451C:
		927	case 0x4520:
		928	case 0x4524:
		929	case 0x4528:
		930	case 0x452C:
		931	case 0x4530:
		932	case 0x4534:
		933	case 0x4538:
		934	case 0x453C:
		935	/* TX_FORMAT2_[0-15] */
		936	i = (reg - 0x4500) >> 2;
1221	serge	937	tmp = idx_value & 0x3FFF;
1120	serge	938	track->textures[i].pitch = tmp + 1;
		939	if (p->rdev->family >= CHIP_RV515) {
1221	serge	940	tmp = ((idx_value >> 15) & 1) << 11;
1120	serge	941	track->textures[i].width_11 = tmp;
1221	serge	942	tmp = ((idx_value >> 16) & 1) << 11;
1120	serge	943	track->textures[i].height_11 = tmp;
		944	}
		945	break;
		946	case 0x4480:
		947	case 0x4484:
		948	case 0x4488:
		949	case 0x448C:
		950	case 0x4490:
		951	case 0x4494:
		952	case 0x4498:
		953	case 0x449C:
		954	case 0x44A0:
		955	case 0x44A4:
		956	case 0x44A8:
		957	case 0x44AC:
		958	case 0x44B0:
		959	case 0x44B4:
		960	case 0x44B8:
		961	case 0x44BC:
		962	/* TX_FORMAT0_[0-15] */
		963	i = (reg - 0x4480) >> 2;
1221	serge	964	tmp = idx_value & 0x7FF;
1120	serge	965	track->textures[i].width = tmp + 1;
1221	serge	966	tmp = (idx_value >> 11) & 0x7FF;
1120	serge	967	track->textures[i].height = tmp + 1;
1221	serge	968	tmp = (idx_value >> 26) & 0xF;
1120	serge	969	track->textures[i].num_levels = tmp;
1221	serge	970	tmp = idx_value & (1 << 31);
1120	serge	971	track->textures[i].use_pitch = !!tmp;
1221	serge	972	tmp = (idx_value >> 22) & 0xF;
1120	serge	973	track->textures[i].txdepth = tmp;
		974	break;
1179	serge	975	case R300_ZB_ZPASS_ADDR:
		976	r = r100_cs_packet_next_reloc(p, &reloc);
		977	if (r) {
		978	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		979	idx, reg);
		980	r100_cs_dump_packet(p, pkt);
		981	return r;
		982	}
1221	serge	983	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	984	break;
		985	case 0x4be8:
		986	/* valid register only on RV530 */
		987	if (p->rdev->family == CHIP_RV530)
		988	break;
		989	/* fallthrough do not move */
1120	serge	990	default:
		991	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		992	reg, idx);
		993	return -EINVAL;
		994	}
		995	return 0;
		996	}
		997
		998	static int r300_packet3_check(struct radeon_cs_parser *p,
		999	struct radeon_cs_packet *pkt)
		1000	{
		1001	struct radeon_cs_reloc *reloc;
1179	serge	1002	struct r100_cs_track *track;
1120	serge	1003	volatile uint32_t *ib;
		1004	unsigned idx;
		1005	int r;
		1006
		1007	ib = p->ib->ptr;
		1008	idx = pkt->idx + 1;
1179	serge	1009	track = (struct r100_cs_track *)p->track;
1120	serge	1010	switch(pkt->opcode) {
		1011	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1012	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1013	if (r)
1120	serge	1014	return r;
		1015	break;
		1016	case PACKET3_INDX_BUFFER:
		1017	r = r100_cs_packet_next_reloc(p, &reloc);
		1018	if (r) {
		1019	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1020	r100_cs_dump_packet(p, pkt);
		1021	return r;
		1022	}
1221	serge	1023	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1120	serge	1024	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1025	if (r) {
		1026	return r;
		1027	}
		1028	break;
		1029	/* Draw packet */
		1030	case PACKET3_3D_DRAW_IMMD:
		1031	/* Number of dwords is vtx_size * (num_vertices - 1)
		1032	* PRIM_WALK must be equal to 3 vertex data in embedded
		1033	* in cmd stream */
1221	serge	1034	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1120	serge	1035	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1036	return -EINVAL;
		1037	}
1221	serge	1038	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1120	serge	1039	track->immd_dwords = pkt->count - 1;
1179	serge	1040	r = r100_cs_track_check(p->rdev, track);
1120	serge	1041	if (r) {
		1042	return r;
		1043	}
		1044	break;
		1045	case PACKET3_3D_DRAW_IMMD_2:
		1046	/* Number of dwords is vtx_size * (num_vertices - 1)
		1047	* PRIM_WALK must be equal to 3 vertex data in embedded
		1048	* in cmd stream */
1221	serge	1049	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1120	serge	1050	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1051	return -EINVAL;
		1052	}
1221	serge	1053	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1120	serge	1054	track->immd_dwords = pkt->count;
1179	serge	1055	r = r100_cs_track_check(p->rdev, track);
1120	serge	1056	if (r) {
		1057	return r;
		1058	}
		1059	break;
		1060	case PACKET3_3D_DRAW_VBUF:
1221	serge	1061	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1062	r = r100_cs_track_check(p->rdev, track);
1120	serge	1063	if (r) {
		1064	return r;
		1065	}
		1066	break;
		1067	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1068	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1069	r = r100_cs_track_check(p->rdev, track);
1120	serge	1070	if (r) {
		1071	return r;
		1072	}
		1073	break;
		1074	case PACKET3_3D_DRAW_INDX:
1221	serge	1075	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1076	r = r100_cs_track_check(p->rdev, track);
1120	serge	1077	if (r) {
		1078	return r;
		1079	}
		1080	break;
		1081	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1082	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1083	r = r100_cs_track_check(p->rdev, track);
1120	serge	1084	if (r) {
		1085	return r;
		1086	}
		1087	break;
		1088	case PACKET3_NOP:
		1089	break;
		1090	default:
		1091	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1092	return -EINVAL;
		1093	}
		1094	return 0;
		1095	}
		1096
		1097	int r300_cs_parse(struct radeon_cs_parser *p)
		1098	{
		1099	struct radeon_cs_packet pkt;
1179	serge	1100	struct r100_cs_track *track;
1120	serge	1101	int r;
		1102
1179	serge	1103	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1104	r100_cs_track_clear(p->rdev, track);
		1105	p->track = track;
1120	serge	1106	do {
		1107	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1108	if (r) {
		1109	return r;
		1110	}
		1111	p->idx += pkt.count + 2;
		1112	switch (pkt.type) {
		1113	case PACKET_TYPE0:
		1114	r = r100_cs_parse_packet0(p, &pkt,
		1115	p->rdev->config.r300.reg_safe_bm,
		1116	p->rdev->config.r300.reg_safe_bm_size,
		1117	&r300_packet0_check);
		1118	break;
		1119	case PACKET_TYPE2:
		1120	break;
		1121	case PACKET_TYPE3:
		1122	r = r300_packet3_check(p, &pkt);
		1123	break;
		1124	default:
		1125	DRM_ERROR("Unknown packet type %d !\n", pkt.type);
		1126	return -EINVAL;
		1127	}
		1128	if (r) {
		1129	return r;
		1130	}
		1131	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1132	return 0;
		1133	}
1128	serge	1134	#endif
		1135
1179	serge	1136
		1137	void r300_set_reg_safe(struct radeon_device *rdev)
1120	serge	1138	{
		1139	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
		1140	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1179	serge	1141	}
		1142
		1143	void r300_mc_program(struct radeon_device *rdev)
		1144	{
		1145	struct r100_mc_save save;
		1146	int r;
1120	serge	1147
1179	serge	1148	r = r100_debugfs_mc_info_init(rdev);
		1149	if (r) {
		1150	dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		1151	}
		1152
		1153	/* Stops all mc clients */
		1154	r100_mc_stop(rdev, &save);
		1155	if (rdev->flags & RADEON_IS_AGP) {
		1156	WREG32(R_00014C_MC_AGP_LOCATION,
		1157	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		1158	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		1159	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		1160	WREG32(R_00015C_AGP_BASE_2,
		1161	upper_32_bits(rdev->mc.agp_base) & 0xff);
		1162	} else {
		1163	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		1164	WREG32(R_000170_AGP_BASE, 0);
		1165	WREG32(R_00015C_AGP_BASE_2, 0);
		1166	}
		1167	/* Wait for mc idle */
		1168	if (r300_mc_wait_for_idle(rdev))
		1169	DRM_INFO("Failed to wait MC idle before programming MC.\n");
		1170	/* Program MC, should be a 32bits limited address space */
		1171	WREG32(R_000148_MC_FB_LOCATION,
		1172	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		1173	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		1174	r100_mc_resume(rdev, &save);
		1175	}
1221	serge	1176
		1177	void r300_clock_startup(struct radeon_device *rdev)
		1178	{
		1179	u32 tmp;
		1180
		1181	if (radeon_dynclks != -1 && radeon_dynclks)
		1182	radeon_legacy_set_clock_gating(rdev, 1);
		1183	/* We need to force on some of the block */
		1184	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		1185	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		1186	if ((rdev->family == CHIP_RV350) \|\| (rdev->family == CHIP_RV380))
		1187	tmp \|= S_00000D_FORCE_VAP(1);
		1188	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		1189	}
		1190
		1191	static int r300_startup(struct radeon_device *rdev)
		1192	{
		1193	int r;
		1194
		1195	r300_mc_program(rdev);
		1196	/* Resume clock */
		1197	r300_clock_startup(rdev);
		1198	/* Initialize GPU configuration (# pipes, ...) */
		1199	r300_gpu_init(rdev);
		1200	/* Initialize GART (initialize after TTM so we can allocate
		1201	* memory through TTM but finalize after TTM) */
		1202	if (rdev->flags & RADEON_IS_PCIE) {
		1203	r = rv370_pcie_gart_enable(rdev);
		1204	if (r)
		1205	return r;
		1206	}
		1207	if (rdev->flags & RADEON_IS_PCI) {
		1208	r = r100_pci_gart_enable(rdev);
		1209	if (r)
		1210	return r;
		1211	}
		1212	/* Enable IRQ */
		1213	// rdev->irq.sw_int = true;
		1214	// r100_irq_set(rdev);
		1215	/* 1M ring buffer */
		1216	// r = r100_cp_init(rdev, 1024 * 1024);
		1217	// if (r) {
		1218	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		1219	// return r;
		1220	// }
		1221	// r = r100_wb_init(rdev);
		1222	// if (r)
		1223	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		1224	// r = r100_ib_init(rdev);
		1225	// if (r) {
		1226	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		1227	// return r;
		1228	// }
		1229	return 0;
		1230	}
		1231
		1232
		1233
		1234
		1235
		1236	int r300_init(struct radeon_device *rdev)
		1237	{
		1238	int r;
		1239
		1240	/* Disable VGA */
		1241	r100_vga_render_disable(rdev);
		1242	/* Initialize scratch registers */
		1243	radeon_scratch_init(rdev);
		1244	/* Initialize surface registers */
		1245	radeon_surface_init(rdev);
		1246	/* TODO: disable VGA need to use VGA request */
		1247	/* BIOS*/
		1248	if (!radeon_get_bios(rdev)) {
		1249	if (ASIC_IS_AVIVO(rdev))
		1250	return -EINVAL;
		1251	}
		1252	if (rdev->is_atom_bios) {
		1253	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		1254	return -EINVAL;
		1255	} else {
		1256	r = radeon_combios_init(rdev);
		1257	if (r)
		1258	return r;
		1259	}
		1260	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		1261	if (radeon_gpu_reset(rdev)) {
		1262	dev_warn(rdev->dev,
		1263	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		1264	RREG32(R_000E40_RBBM_STATUS),
		1265	RREG32(R_0007C0_CP_STAT));
		1266	}
		1267	/* check if cards are posted or not */
		1268	if (!radeon_card_posted(rdev) && rdev->bios) {
		1269	DRM_INFO("GPU not posted. posting now...\n");
		1270	radeon_combios_asic_init(rdev->ddev);
		1271	}
		1272	/* Set asic errata */
		1273	r300_errata(rdev);
		1274	/* Initialize clocks */
		1275	radeon_get_clock_info(rdev->ddev);
		1276	/* Get vram informations */
		1277	r300_vram_info(rdev);
		1278	/* Initialize memory controller (also test AGP) */
		1279	r = r420_mc_init(rdev);
1246	serge	1280	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	1281	if (r)
		1282	return r;
		1283	/* Fence driver */
		1284	// r = radeon_fence_driver_init(rdev);
		1285	// if (r)
		1286	// return r;
		1287	// r = radeon_irq_kms_init(rdev);
		1288	// if (r)
		1289	// return r;
		1290	/* Memory manager */
		1291	r = radeon_object_init(rdev);
		1292	if (r)
		1293	return r;
		1294	if (rdev->flags & RADEON_IS_PCIE) {
		1295	r = rv370_pcie_gart_init(rdev);
		1296	if (r)
		1297	return r;
		1298	}
		1299	if (rdev->flags & RADEON_IS_PCI) {
		1300	r = r100_pci_gart_init(rdev);
		1301	if (r)
		1302	return r;
		1303	}
		1304	r300_set_reg_safe(rdev);
		1305	rdev->accel_working = true;
		1306	r = r300_startup(rdev);
		1307	if (r) {
		1308	/* Somethings want wront with the accel init stop accel */
		1309	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		1310	// r300_suspend(rdev);
		1311	// r100_cp_fini(rdev);
		1312	// r100_wb_fini(rdev);
		1313	// r100_ib_fini(rdev);
		1314	if (rdev->flags & RADEON_IS_PCIE)
		1315	rv370_pcie_gart_fini(rdev);
		1316	if (rdev->flags & RADEON_IS_PCI)
		1317	r100_pci_gart_fini(rdev);
		1318	// radeon_irq_kms_fini(rdev);
		1319	rdev->accel_working = false;
		1320	}
		1321	return 0;
		1322	}

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(root)/drivers/video/drm/radeon/r300.c – Rev 1246