Rev 1221 | Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1179 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 28 | #include "drmP.h" |
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| 29 | #include "drm.h" |
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| 30 | #include "radeon_drm.h" |
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| 31 | #include "radeon_reg.h" |
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| 32 | #include "radeon.h" |
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| 33 | |||
| 34 | #include "r200_reg_safe.h" |
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| 35 | |||
| 36 | //#include "r100_track.h" |
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| 37 | |||
| 38 | #if 0 |
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| 39 | static int r200_get_vtx_size_0(uint32_t vtx_fmt_0) |
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| 40 | { |
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| 41 | int vtx_size, i; |
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| 42 | vtx_size = 2; |
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| 43 | |||
| 44 | if (vtx_fmt_0 & R200_VTX_Z0) |
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| 45 | vtx_size++; |
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| 46 | if (vtx_fmt_0 & R200_VTX_W0) |
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| 47 | vtx_size++; |
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| 48 | /* blend weight */ |
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| 49 | if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT)) |
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| 50 | vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7; |
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| 51 | if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL) |
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| 52 | vtx_size++; |
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| 53 | if (vtx_fmt_0 & R200_VTX_N0) |
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| 54 | vtx_size += 3; |
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| 55 | if (vtx_fmt_0 & R200_VTX_POINT_SIZE) |
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| 56 | vtx_size++; |
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| 57 | if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG) |
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| 58 | vtx_size++; |
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| 59 | if (vtx_fmt_0 & R200_VTX_SHININESS_0) |
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| 60 | vtx_size++; |
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| 61 | if (vtx_fmt_0 & R200_VTX_SHININESS_1) |
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| 62 | vtx_size++; |
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| 63 | for (i = 0; i < 8; i++) { |
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| 64 | int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3; |
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| 65 | switch (color_size) { |
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| 66 | case 0: break; |
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| 67 | case 1: vtx_size++; break; |
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| 68 | case 2: vtx_size += 3; break; |
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| 69 | case 3: vtx_size += 4; break; |
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| 70 | } |
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| 71 | } |
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| 72 | if (vtx_fmt_0 & R200_VTX_XY1) |
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| 73 | vtx_size += 2; |
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| 74 | if (vtx_fmt_0 & R200_VTX_Z1) |
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| 75 | vtx_size++; |
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| 76 | if (vtx_fmt_0 & R200_VTX_W1) |
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| 77 | vtx_size++; |
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| 78 | if (vtx_fmt_0 & R200_VTX_N1) |
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| 79 | vtx_size += 3; |
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| 80 | return vtx_size; |
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| 81 | } |
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| 82 | |||
| 83 | static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
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| 84 | { |
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| 85 | int vtx_size, i, tex_size; |
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| 86 | vtx_size = 0; |
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| 87 | for (i = 0; i < 6; i++) { |
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| 88 | tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7; |
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| 89 | if (tex_size > 4) |
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| 90 | continue; |
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| 91 | vtx_size += tex_size; |
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| 92 | } |
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| 93 | return vtx_size; |
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| 94 | } |
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| 95 | |||
| 96 | int r200_packet0_check(struct radeon_cs_parser *p, |
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| 97 | struct radeon_cs_packet *pkt, |
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| 98 | unsigned idx, unsigned reg) |
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| 99 | { |
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| 100 | struct radeon_cs_chunk *ib_chunk; |
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| 101 | struct radeon_cs_reloc *reloc; |
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| 102 | struct r100_cs_track *track; |
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| 103 | volatile uint32_t *ib; |
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| 104 | uint32_t tmp; |
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| 105 | int r; |
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| 106 | int i; |
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| 107 | int face; |
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| 108 | u32 tile_flags = 0; |
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| 109 | |||
| 110 | ib = p->ib->ptr; |
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| 111 | ib_chunk = &p->chunks[p->chunk_ib_idx]; |
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| 112 | track = (struct r100_cs_track *)p->track; |
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| 113 | |||
| 114 | switch (reg) { |
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| 115 | case RADEON_CRTC_GUI_TRIG_VLINE: |
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| 116 | r = r100_cs_packet_parse_vline(p); |
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| 117 | if (r) { |
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| 118 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 119 | idx, reg); |
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| 120 | r100_cs_dump_packet(p, pkt); |
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| 121 | return r; |
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| 122 | } |
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| 123 | break; |
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| 124 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
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| 125 | * range access */ |
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| 126 | case RADEON_DST_PITCH_OFFSET: |
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| 127 | case RADEON_SRC_PITCH_OFFSET: |
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| 128 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
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| 129 | if (r) |
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| 130 | return r; |
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| 131 | break; |
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| 132 | case RADEON_RB3D_DEPTHOFFSET: |
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| 133 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 134 | if (r) { |
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| 135 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 136 | idx, reg); |
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| 137 | r100_cs_dump_packet(p, pkt); |
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| 138 | return r; |
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| 139 | } |
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| 140 | track->zb.robj = reloc->robj; |
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| 141 | track->zb.offset = ib_chunk->kdata[idx]; |
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| 142 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
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| 143 | break; |
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| 144 | case RADEON_RB3D_COLOROFFSET: |
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| 145 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 146 | if (r) { |
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| 147 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 148 | idx, reg); |
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| 149 | r100_cs_dump_packet(p, pkt); |
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| 150 | return r; |
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| 151 | } |
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| 152 | track->cb[0].robj = reloc->robj; |
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| 153 | track->cb[0].offset = ib_chunk->kdata[idx]; |
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| 154 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
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| 155 | break; |
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| 156 | case R200_PP_TXOFFSET_0: |
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| 157 | case R200_PP_TXOFFSET_1: |
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| 158 | case R200_PP_TXOFFSET_2: |
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| 159 | case R200_PP_TXOFFSET_3: |
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| 160 | case R200_PP_TXOFFSET_4: |
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| 161 | case R200_PP_TXOFFSET_5: |
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| 162 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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| 163 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 164 | if (r) { |
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| 165 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 166 | idx, reg); |
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| 167 | r100_cs_dump_packet(p, pkt); |
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| 168 | return r; |
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| 169 | } |
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| 170 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
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| 171 | track->textures[i].robj = reloc->robj; |
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| 172 | break; |
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| 173 | case R200_PP_CUBIC_OFFSET_F1_0: |
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| 174 | case R200_PP_CUBIC_OFFSET_F2_0: |
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| 175 | case R200_PP_CUBIC_OFFSET_F3_0: |
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| 176 | case R200_PP_CUBIC_OFFSET_F4_0: |
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| 177 | case R200_PP_CUBIC_OFFSET_F5_0: |
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| 178 | case R200_PP_CUBIC_OFFSET_F1_1: |
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| 179 | case R200_PP_CUBIC_OFFSET_F2_1: |
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| 180 | case R200_PP_CUBIC_OFFSET_F3_1: |
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| 181 | case R200_PP_CUBIC_OFFSET_F4_1: |
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| 182 | case R200_PP_CUBIC_OFFSET_F5_1: |
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| 183 | case R200_PP_CUBIC_OFFSET_F1_2: |
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| 184 | case R200_PP_CUBIC_OFFSET_F2_2: |
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| 185 | case R200_PP_CUBIC_OFFSET_F3_2: |
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| 186 | case R200_PP_CUBIC_OFFSET_F4_2: |
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| 187 | case R200_PP_CUBIC_OFFSET_F5_2: |
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| 188 | case R200_PP_CUBIC_OFFSET_F1_3: |
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| 189 | case R200_PP_CUBIC_OFFSET_F2_3: |
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| 190 | case R200_PP_CUBIC_OFFSET_F3_3: |
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| 191 | case R200_PP_CUBIC_OFFSET_F4_3: |
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| 192 | case R200_PP_CUBIC_OFFSET_F5_3: |
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| 193 | case R200_PP_CUBIC_OFFSET_F1_4: |
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| 194 | case R200_PP_CUBIC_OFFSET_F2_4: |
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| 195 | case R200_PP_CUBIC_OFFSET_F3_4: |
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| 196 | case R200_PP_CUBIC_OFFSET_F4_4: |
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| 197 | case R200_PP_CUBIC_OFFSET_F5_4: |
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| 198 | case R200_PP_CUBIC_OFFSET_F1_5: |
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| 199 | case R200_PP_CUBIC_OFFSET_F2_5: |
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| 200 | case R200_PP_CUBIC_OFFSET_F3_5: |
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| 201 | case R200_PP_CUBIC_OFFSET_F4_5: |
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| 202 | case R200_PP_CUBIC_OFFSET_F5_5: |
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| 203 | i = (reg - R200_PP_TXOFFSET_0) / 24; |
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| 204 | face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; |
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| 205 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 206 | if (r) { |
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| 207 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 208 | idx, reg); |
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| 209 | r100_cs_dump_packet(p, pkt); |
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| 210 | return r; |
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| 211 | } |
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| 212 | track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; |
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| 213 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
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| 214 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
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| 215 | break; |
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| 216 | case RADEON_RE_WIDTH_HEIGHT: |
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| 217 | track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); |
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| 218 | break; |
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| 219 | case RADEON_RB3D_COLORPITCH: |
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| 220 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 221 | if (r) { |
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| 222 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 223 | idx, reg); |
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| 224 | r100_cs_dump_packet(p, pkt); |
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| 225 | return r; |
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| 226 | } |
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| 227 | |||
| 228 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
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| 229 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
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| 230 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
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| 231 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
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| 232 | |||
| 233 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
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| 234 | tmp |= tile_flags; |
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| 235 | ib[idx] = tmp; |
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| 236 | |||
| 237 | track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; |
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| 238 | break; |
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| 239 | case RADEON_RB3D_DEPTHPITCH: |
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| 240 | track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; |
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| 241 | break; |
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| 242 | case RADEON_RB3D_CNTL: |
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| 243 | switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
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| 244 | case 7: |
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| 245 | case 8: |
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| 246 | case 9: |
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| 247 | case 11: |
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| 248 | case 12: |
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| 249 | track->cb[0].cpp = 1; |
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| 250 | break; |
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| 251 | case 3: |
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| 252 | case 4: |
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| 253 | case 15: |
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| 254 | track->cb[0].cpp = 2; |
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| 255 | break; |
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| 256 | case 6: |
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| 257 | track->cb[0].cpp = 4; |
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| 258 | break; |
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| 259 | default: |
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| 260 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
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| 261 | ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
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| 262 | return -EINVAL; |
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| 263 | } |
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| 264 | if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { |
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| 265 | DRM_ERROR("No support for depth xy offset in kms\n"); |
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| 266 | return -EINVAL; |
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| 267 | } |
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| 268 | |||
| 269 | track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); |
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| 270 | break; |
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| 271 | case RADEON_RB3D_ZSTENCILCNTL: |
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| 272 | switch (ib_chunk->kdata[idx] & 0xf) { |
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| 273 | case 0: |
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| 274 | track->zb.cpp = 2; |
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| 275 | break; |
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| 276 | case 2: |
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| 277 | case 3: |
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| 278 | case 4: |
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| 279 | case 5: |
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| 280 | case 9: |
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| 281 | case 11: |
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| 282 | track->zb.cpp = 4; |
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| 283 | break; |
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| 284 | default: |
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| 285 | break; |
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| 286 | } |
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| 287 | break; |
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| 288 | case RADEON_RB3D_ZPASS_ADDR: |
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| 289 | r = r100_cs_packet_next_reloc(p, &reloc); |
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| 290 | if (r) { |
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| 291 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
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| 292 | idx, reg); |
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| 293 | r100_cs_dump_packet(p, pkt); |
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| 294 | return r; |
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| 295 | } |
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| 296 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
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| 297 | break; |
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| 298 | case RADEON_PP_CNTL: |
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| 299 | { |
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| 300 | uint32_t temp = ib_chunk->kdata[idx] >> 4; |
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| 301 | for (i = 0; i < track->num_texture; i++) |
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| 302 | track->textures[i].enabled = !!(temp & (1 << i)); |
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| 303 | } |
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| 304 | break; |
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| 305 | case RADEON_SE_VF_CNTL: |
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| 306 | track->vap_vf_cntl = ib_chunk->kdata[idx]; |
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| 307 | break; |
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| 308 | case 0x210c: |
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| 309 | /* VAP_VF_MAX_VTX_INDX */ |
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| 310 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
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| 311 | break; |
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| 312 | case R200_SE_VTX_FMT_0: |
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| 313 | track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); |
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| 314 | break; |
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| 315 | case R200_SE_VTX_FMT_1: |
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| 316 | track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); |
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| 317 | break; |
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| 318 | case R200_PP_TXSIZE_0: |
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| 319 | case R200_PP_TXSIZE_1: |
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| 320 | case R200_PP_TXSIZE_2: |
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| 321 | case R200_PP_TXSIZE_3: |
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| 322 | case R200_PP_TXSIZE_4: |
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| 323 | case R200_PP_TXSIZE_5: |
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| 324 | i = (reg - R200_PP_TXSIZE_0) / 32; |
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| 325 | track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; |
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| 326 | track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
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| 327 | break; |
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| 328 | case R200_PP_TXPITCH_0: |
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| 329 | case R200_PP_TXPITCH_1: |
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| 330 | case R200_PP_TXPITCH_2: |
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| 331 | case R200_PP_TXPITCH_3: |
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| 332 | case R200_PP_TXPITCH_4: |
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| 333 | case R200_PP_TXPITCH_5: |
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| 334 | i = (reg - R200_PP_TXPITCH_0) / 32; |
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| 335 | track->textures[i].pitch = ib_chunk->kdata[idx] + 32; |
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| 336 | break; |
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| 337 | case R200_PP_TXFILTER_0: |
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| 338 | case R200_PP_TXFILTER_1: |
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| 339 | case R200_PP_TXFILTER_2: |
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| 340 | case R200_PP_TXFILTER_3: |
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| 341 | case R200_PP_TXFILTER_4: |
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| 342 | case R200_PP_TXFILTER_5: |
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| 343 | i = (reg - R200_PP_TXFILTER_0) / 32; |
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| 344 | track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) |
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| 345 | >> R200_MAX_MIP_LEVEL_SHIFT); |
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| 346 | tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; |
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| 347 | if (tmp == 2 || tmp == 6) |
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| 348 | track->textures[i].roundup_w = false; |
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| 349 | tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; |
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| 350 | if (tmp == 2 || tmp == 6) |
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| 351 | track->textures[i].roundup_h = false; |
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| 352 | break; |
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| 353 | case R200_PP_TXMULTI_CTL_0: |
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| 354 | case R200_PP_TXMULTI_CTL_1: |
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| 355 | case R200_PP_TXMULTI_CTL_2: |
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| 356 | case R200_PP_TXMULTI_CTL_3: |
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| 357 | case R200_PP_TXMULTI_CTL_4: |
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| 358 | case R200_PP_TXMULTI_CTL_5: |
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| 359 | i = (reg - R200_PP_TXMULTI_CTL_0) / 32; |
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| 360 | break; |
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| 361 | case R200_PP_TXFORMAT_X_0: |
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| 362 | case R200_PP_TXFORMAT_X_1: |
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| 363 | case R200_PP_TXFORMAT_X_2: |
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| 364 | case R200_PP_TXFORMAT_X_3: |
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| 365 | case R200_PP_TXFORMAT_X_4: |
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| 366 | case R200_PP_TXFORMAT_X_5: |
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| 367 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
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| 368 | track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; |
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| 369 | tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; |
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| 370 | /* 2D, 3D, CUBE */ |
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| 371 | switch (tmp) { |
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| 372 | case 0: |
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| 373 | case 5: |
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| 374 | case 6: |
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| 375 | case 7: |
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| 376 | track->textures[i].tex_coord_type = 0; |
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| 377 | break; |
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| 378 | case 1: |
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| 379 | track->textures[i].tex_coord_type = 1; |
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| 380 | break; |
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| 381 | case 2: |
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| 382 | track->textures[i].tex_coord_type = 2; |
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| 383 | break; |
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| 384 | } |
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| 385 | break; |
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| 386 | case R200_PP_TXFORMAT_0: |
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| 387 | case R200_PP_TXFORMAT_1: |
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| 388 | case R200_PP_TXFORMAT_2: |
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| 389 | case R200_PP_TXFORMAT_3: |
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| 390 | case R200_PP_TXFORMAT_4: |
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| 391 | case R200_PP_TXFORMAT_5: |
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| 392 | i = (reg - R200_PP_TXFORMAT_0) / 32; |
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| 393 | if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { |
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| 394 | track->textures[i].use_pitch = 1; |
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| 395 | } else { |
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| 396 | track->textures[i].use_pitch = 0; |
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| 397 | track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
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| 398 | track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
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| 399 | } |
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| 400 | switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { |
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| 401 | case R200_TXFORMAT_I8: |
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| 402 | case R200_TXFORMAT_RGB332: |
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| 403 | case R200_TXFORMAT_Y8: |
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| 404 | track->textures[i].cpp = 1; |
||
| 405 | break; |
||
| 406 | case R200_TXFORMAT_DXT1: |
||
| 407 | case R200_TXFORMAT_AI88: |
||
| 408 | case R200_TXFORMAT_ARGB1555: |
||
| 409 | case R200_TXFORMAT_RGB565: |
||
| 410 | case R200_TXFORMAT_ARGB4444: |
||
| 411 | case R200_TXFORMAT_VYUY422: |
||
| 412 | case R200_TXFORMAT_YVYU422: |
||
| 413 | case R200_TXFORMAT_LDVDU655: |
||
| 414 | case R200_TXFORMAT_DVDU88: |
||
| 415 | case R200_TXFORMAT_AVYU4444: |
||
| 416 | track->textures[i].cpp = 2; |
||
| 417 | break; |
||
| 418 | case R200_TXFORMAT_ARGB8888: |
||
| 419 | case R200_TXFORMAT_RGBA8888: |
||
| 420 | case R200_TXFORMAT_ABGR8888: |
||
| 421 | case R200_TXFORMAT_BGR111110: |
||
| 422 | case R200_TXFORMAT_LDVDU8888: |
||
| 423 | case R200_TXFORMAT_DXT23: |
||
| 424 | case R200_TXFORMAT_DXT45: |
||
| 425 | track->textures[i].cpp = 4; |
||
| 426 | break; |
||
| 427 | } |
||
| 428 | track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); |
||
| 429 | track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); |
||
| 430 | break; |
||
| 431 | case R200_PP_CUBIC_FACES_0: |
||
| 432 | case R200_PP_CUBIC_FACES_1: |
||
| 433 | case R200_PP_CUBIC_FACES_2: |
||
| 434 | case R200_PP_CUBIC_FACES_3: |
||
| 435 | case R200_PP_CUBIC_FACES_4: |
||
| 436 | case R200_PP_CUBIC_FACES_5: |
||
| 437 | tmp = ib_chunk->kdata[idx]; |
||
| 438 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
||
| 439 | for (face = 0; face < 4; face++) { |
||
| 440 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
| 441 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
| 442 | } |
||
| 443 | break; |
||
| 444 | default: |
||
| 445 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
| 446 | reg, idx); |
||
| 447 | return -EINVAL; |
||
| 448 | } |
||
| 449 | return 0; |
||
| 450 | } |
||
| 451 | #endif |
||
| 452 | |||
| 453 | int r200_init(struct radeon_device *rdev) |
||
| 454 | { |
||
| 455 | rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; |
||
| 456 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); |
||
| 457 | return 0; |
||
| 458 | } |