WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
2997	Serge	30	#include
		31	#include
1117	serge	32	#include "radeon_reg.h"
		33	#include "radeon.h"
1963	serge	34	#include "radeon_asic.h"
1179	serge	35	#include "r100d.h"
1221	serge	36	#include "rs100d.h"
		37	#include "rv200d.h"
		38	#include "rv250d.h"
1963	serge	39	#include "atom.h"
1117	serge	40
1221	serge	41	#include
2997	Serge	42	#include
1221	serge	43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
5078	serge	64	#include "r100_track.h"
1221	serge	65
1117	serge	66	/* This files gather functions specifics to:
		67	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
2997	Serge	68	* and others in some cases.
1117	serge	69	*/
		70
3764	Serge	71	static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
		72	{
		73	if (crtc == 0) {
		74	if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
		75	return true;
		76	else
		77	return false;
		78	} else {
		79	if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
		80	return true;
		81	else
		82	return false;
		83	}
		84	}
		85
		86	static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
		87	{
		88	u32 vline1, vline2;
		89
		90	if (crtc == 0) {
		91	vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		92	vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		93	} else {
		94	vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		95	vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		96	}
		97	if (vline1 != vline2)
		98	return true;
		99	else
		100	return false;
		101	}
		102
2997	Serge	103	/**
		104	* r100_wait_for_vblank - vblank wait asic callback.
		105	*
		106	* @rdev: radeon_device pointer
		107	* @crtc: crtc to wait for vblank on
		108	*
		109	* Wait for vblank on the requested crtc (r1xx-r4xx).
		110	*/
		111	void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		112	{
3764	Serge	113	unsigned i = 0;
2997	Serge	114
		115	if (crtc >= rdev->num_crtc)
		116	return;
		117
		118	if (crtc == 0) {
3764	Serge	119	if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
		120	return;
		121	} else {
		122	if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
		123	return;
		124	}
		125
		126	/* depending on when we hit vblank, we may be close to active; if so,
		127	* wait for another frame.
		128	*/
		129	while (r100_is_in_vblank(rdev, crtc)) {
		130	if (i++ % 100 == 0) {
		131	if (!r100_is_counter_moving(rdev, crtc))
6104	serge	132	break;
2997	Serge	133	}
6104	serge	134	}
3764	Serge	135
		136	while (!r100_is_in_vblank(rdev, crtc)) {
		137	if (i++ % 100 == 0) {
		138	if (!r100_is_counter_moving(rdev, crtc))
6104	serge	139	break;
2997	Serge	140	}
		141	}
		142	}
5078	serge	143
		144	/**
		145	* r100_page_flip - pageflip callback.
		146	*
		147	* @rdev: radeon_device pointer
		148	* @crtc_id: crtc to cleanup pageflip on
		149	* @crtc_base: new address of the crtc (GPU MC address)
		150	*
		151	* Does the actual pageflip (r1xx-r4xx).
		152	* During vblank we take the crtc lock and wait for the update_pending
		153	* bit to go high, when it does, we release the lock, and allow the
		154	* double buffered update to take place.
		155	*/
		156	void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
1963	serge	157	{
		158	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		159	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
2997	Serge	160	int i;
1963	serge	161
		162	/* Lock the graphics update lock */
		163	/* update the scanout addresses */
		164	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		165
		166	/* Wait for update_pending to go high. */
2997	Serge	167	for (i = 0; i < rdev->usec_timeout; i++) {
		168	if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
		169	break;
		170	udelay(1);
		171	}
1963	serge	172	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		173
		174	/* Unlock the lock, so double-buffering can take place inside vblank */
		175	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		176	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		177
5078	serge	178	}
		179
		180	/**
		181	* r100_page_flip_pending - check if page flip is still pending
		182	*
		183	* @rdev: radeon_device pointer
		184	* @crtc_id: crtc to check
		185	*
		186	* Check if the last pagefilp is still pending (r1xx-r4xx).
		187	* Returns the current update pending status.
		188	*/
		189	bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
		190	{
		191	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		192
1963	serge	193	/* Return current update_pending status: */
5078	serge	194	return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
		195	RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
1963	serge	196	}
5078	serge	197
		198	/**
		199	* r100_pm_get_dynpm_state - look up dynpm power state callback.
		200	*
		201	* @rdev: radeon_device pointer
		202	*
		203	* Look up the optimal power state based on the
		204	* current state of the GPU (r1xx-r5xx).
		205	* Used for dynpm only.
		206	*/
		207	void r100_pm_get_dynpm_state(struct radeon_device *rdev)
		208	{
		209	int i;
		210	rdev->pm.dynpm_can_upclock = true;
		211	rdev->pm.dynpm_can_downclock = true;
		212
		213	switch (rdev->pm.dynpm_planned_action) {
		214	case DYNPM_ACTION_MINIMUM:
		215	rdev->pm.requested_power_state_index = 0;
		216	rdev->pm.dynpm_can_downclock = false;
		217	break;
		218	case DYNPM_ACTION_DOWNCLOCK:
		219	if (rdev->pm.current_power_state_index == 0) {
		220	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		221	rdev->pm.dynpm_can_downclock = false;
		222	} else {
		223	if (rdev->pm.active_crtc_count > 1) {
		224	for (i = 0; i < rdev->pm.num_power_states; i++) {
		225	if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
		226	continue;
		227	else if (i >= rdev->pm.current_power_state_index) {
		228	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		229	break;
		230	} else {
		231	rdev->pm.requested_power_state_index = i;
		232	break;
		233	}
		234	}
		235	} else
		236	rdev->pm.requested_power_state_index =
		237	rdev->pm.current_power_state_index - 1;
		238	}
		239	/* don't use the power state if crtcs are active and no display flag is set */
		240	if ((rdev->pm.active_crtc_count > 0) &&
		241	(rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
		242	RADEON_PM_MODE_NO_DISPLAY)) {
		243	rdev->pm.requested_power_state_index++;
		244	}
		245	break;
		246	case DYNPM_ACTION_UPCLOCK:
		247	if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
		248	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		249	rdev->pm.dynpm_can_upclock = false;
		250	} else {
		251	if (rdev->pm.active_crtc_count > 1) {
		252	for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
		253	if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
		254	continue;
		255	else if (i <= rdev->pm.current_power_state_index) {
		256	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
		257	break;
		258	} else {
		259	rdev->pm.requested_power_state_index = i;
		260	break;
		261	}
		262	}
		263	} else
		264	rdev->pm.requested_power_state_index =
		265	rdev->pm.current_power_state_index + 1;
		266	}
		267	break;
		268	case DYNPM_ACTION_DEFAULT:
		269	rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
		270	rdev->pm.dynpm_can_upclock = false;
		271	break;
		272	case DYNPM_ACTION_NONE:
		273	default:
		274	DRM_ERROR("Requested mode for not defined action\n");
		275	return;
		276	}
		277	/* only one clock mode per power state */
		278	rdev->pm.requested_clock_mode_index = 0;
		279
		280	DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
		281	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		282	clock_info[rdev->pm.requested_clock_mode_index].sclk,
		283	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		284	clock_info[rdev->pm.requested_clock_mode_index].mclk,
		285	rdev->pm.power_state[rdev->pm.requested_power_state_index].
		286	pcie_lanes);
		287	}
		288
		289	/**
		290	* r100_pm_init_profile - Initialize power profiles callback.
		291	*
		292	* @rdev: radeon_device pointer
		293	*
		294	* Initialize the power states used in profile mode
		295	* (r1xx-r3xx).
		296	* Used for profile mode only.
		297	*/
		298	void r100_pm_init_profile(struct radeon_device *rdev)
		299	{
		300	/* default */
		301	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
		302	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		303	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
		304	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
		305	/* low sh */
		306	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
		307	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
		308	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
		309	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
		310	/* mid sh */
		311	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
		312	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
		313	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
		314	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
		315	/* high sh */
		316	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
		317	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		318	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
		319	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
		320	/* low mh */
		321	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
		322	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		323	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
		324	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
		325	/* mid mh */
		326	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
		327	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		328	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
		329	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
		330	/* high mh */
		331	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
		332	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
		333	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
		334	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
		335	}
		336
		337	/**
		338	* r100_pm_misc - set additional pm hw parameters callback.
		339	*
		340	* @rdev: radeon_device pointer
		341	*
		342	* Set non-clock parameters associated with a power state
		343	* (voltage, pcie lanes, etc.) (r1xx-r4xx).
		344	*/
		345	void r100_pm_misc(struct radeon_device *rdev)
		346	{
		347	int requested_index = rdev->pm.requested_power_state_index;
		348	struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
		349	struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
		350	u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
		351
		352	if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
		353	if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
		354	tmp = RREG32(voltage->gpio.reg);
		355	if (voltage->active_high)
		356	tmp \|= voltage->gpio.mask;
		357	else
		358	tmp &= ~(voltage->gpio.mask);
		359	WREG32(voltage->gpio.reg, tmp);
		360	if (voltage->delay)
		361	udelay(voltage->delay);
		362	} else {
		363	tmp = RREG32(voltage->gpio.reg);
		364	if (voltage->active_high)
		365	tmp &= ~voltage->gpio.mask;
		366	else
		367	tmp \|= voltage->gpio.mask;
		368	WREG32(voltage->gpio.reg, tmp);
		369	if (voltage->delay)
		370	udelay(voltage->delay);
		371	}
		372	}
		373
		374	sclk_cntl = RREG32_PLL(SCLK_CNTL);
		375	sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
		376	sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
		377	sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
		378	sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
		379	if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
		380	sclk_more_cntl \|= REDUCED_SPEED_SCLK_EN;
		381	if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
		382	sclk_cntl2 \|= REDUCED_SPEED_SCLK_MODE;
		383	else
		384	sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
		385	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
		386	sclk_cntl2 \|= REDUCED_SPEED_SCLK_SEL(0);
		387	else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
		388	sclk_cntl2 \|= REDUCED_SPEED_SCLK_SEL(2);
		389	} else
		390	sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
		391
		392	if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
		393	sclk_more_cntl \|= IO_CG_VOLTAGE_DROP;
		394	if (voltage->delay) {
		395	sclk_more_cntl \|= VOLTAGE_DROP_SYNC;
		396	switch (voltage->delay) {
		397	case 33:
		398	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(0);
		399	break;
		400	case 66:
		401	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(1);
		402	break;
		403	case 99:
		404	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(2);
		405	break;
		406	case 132:
		407	sclk_more_cntl \|= VOLTAGE_DELAY_SEL(3);
		408	break;
		409	}
		410	} else
		411	sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
		412	} else
		413	sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
		414
		415	if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
		416	sclk_cntl &= ~FORCE_HDP;
		417	else
		418	sclk_cntl \|= FORCE_HDP;
		419
		420	WREG32_PLL(SCLK_CNTL, sclk_cntl);
		421	WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
		422	WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
		423
		424	/* set pcie lanes */
		425	if ((rdev->flags & RADEON_IS_PCIE) &&
		426	!(rdev->flags & RADEON_IS_IGP) &&
		427	rdev->asic->pm.set_pcie_lanes &&
		428	(ps->pcie_lanes !=
		429	rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
		430	radeon_set_pcie_lanes(rdev,
		431	ps->pcie_lanes);
		432	DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
		433	}
		434	}
		435
		436	/**
		437	* r100_pm_prepare - pre-power state change callback.
		438	*
		439	* @rdev: radeon_device pointer
		440	*
		441	* Prepare for a power state change (r1xx-r4xx).
		442	*/
		443	void r100_pm_prepare(struct radeon_device *rdev)
		444	{
		445	struct drm_device *ddev = rdev->ddev;
		446	struct drm_crtc *crtc;
		447	struct radeon_crtc *radeon_crtc;
		448	u32 tmp;
		449
		450	/* disable any active CRTCs */
		451	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		452	radeon_crtc = to_radeon_crtc(crtc);
		453	if (radeon_crtc->enabled) {
		454	if (radeon_crtc->crtc_id) {
		455	tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
		456	tmp \|= RADEON_CRTC2_DISP_REQ_EN_B;
		457	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		458	} else {
		459	tmp = RREG32(RADEON_CRTC_GEN_CNTL);
		460	tmp \|= RADEON_CRTC_DISP_REQ_EN_B;
		461	WREG32(RADEON_CRTC_GEN_CNTL, tmp);
		462	}
		463	}
		464	}
		465	}
		466
		467	/**
		468	* r100_pm_finish - post-power state change callback.
		469	*
		470	* @rdev: radeon_device pointer
		471	*
		472	* Clean up after a power state change (r1xx-r4xx).
		473	*/
		474	void r100_pm_finish(struct radeon_device *rdev)
		475	{
		476	struct drm_device *ddev = rdev->ddev;
		477	struct drm_crtc *crtc;
		478	struct radeon_crtc *radeon_crtc;
		479	u32 tmp;
		480
		481	/* enable any active CRTCs */
		482	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
		483	radeon_crtc = to_radeon_crtc(crtc);
		484	if (radeon_crtc->enabled) {
		485	if (radeon_crtc->crtc_id) {
		486	tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
		487	tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
		488	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		489	} else {
		490	tmp = RREG32(RADEON_CRTC_GEN_CNTL);
		491	tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
		492	WREG32(RADEON_CRTC_GEN_CNTL, tmp);
		493	}
		494	}
		495	}
		496	}
		497
		498	/**
		499	* r100_gui_idle - gui idle callback.
		500	*
		501	* @rdev: radeon_device pointer
		502	*
		503	* Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
		504	* Returns true if idle, false if not.
		505	*/
1963	serge	506	bool r100_gui_idle(struct radeon_device *rdev)
		507	{
		508	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		509	return false;
		510	else
		511	return true;
		512	}
		513
1321	serge	514	/* hpd for digital panel detect/disconnect */
2997	Serge	515	/**
		516	* r100_hpd_sense - hpd sense callback.
		517	*
		518	* @rdev: radeon_device pointer
		519	* @hpd: hpd (hotplug detect) pin
		520	*
		521	* Checks if a digital monitor is connected (r1xx-r4xx).
		522	* Returns true if connected, false if not connected.
		523	*/
1321	serge	524	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		525	{
		526	bool connected = false;
		527
		528	switch (hpd) {
		529	case RADEON_HPD_1:
		530	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		531	connected = true;
		532	break;
		533	case RADEON_HPD_2:
		534	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		535	connected = true;
		536	break;
		537	default:
		538	break;
		539	}
		540	return connected;
		541	}
		542
2997	Serge	543	/**
		544	* r100_hpd_set_polarity - hpd set polarity callback.
		545	*
		546	* @rdev: radeon_device pointer
		547	* @hpd: hpd (hotplug detect) pin
		548	*
		549	* Set the polarity of the hpd pin (r1xx-r4xx).
		550	*/
1321	serge	551	void r100_hpd_set_polarity(struct radeon_device *rdev,
		552	enum radeon_hpd_id hpd)
		553	{
		554	u32 tmp;
		555	bool connected = r100_hpd_sense(rdev, hpd);
		556
		557	switch (hpd) {
		558	case RADEON_HPD_1:
		559	tmp = RREG32(RADEON_FP_GEN_CNTL);
		560	if (connected)
		561	tmp &= ~RADEON_FP_DETECT_INT_POL;
		562	else
		563	tmp \|= RADEON_FP_DETECT_INT_POL;
		564	WREG32(RADEON_FP_GEN_CNTL, tmp);
		565	break;
		566	case RADEON_HPD_2:
		567	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		568	if (connected)
		569	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		570	else
		571	tmp \|= RADEON_FP2_DETECT_INT_POL;
		572	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		573	break;
		574	default:
		575	break;
		576	}
		577	}
		578
2997	Serge	579	/**
		580	* r100_hpd_init - hpd setup callback.
		581	*
		582	* @rdev: radeon_device pointer
		583	*
		584	* Setup the hpd pins used by the card (r1xx-r4xx).
		585	* Set the polarity, and enable the hpd interrupts.
		586	*/
1321	serge	587	void r100_hpd_init(struct radeon_device *rdev)
		588	{
		589	struct drm_device *dev = rdev->ddev;
		590	struct drm_connector *connector;
2997	Serge	591	unsigned enable = 0;
1321	serge	592
		593	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		594	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	595	enable \|= 1 << radeon_connector->hpd.hpd;
		596	radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
1321	serge	597	}
2997	Serge	598	// radeon_irq_kms_enable_hpd(rdev, enable);
1321	serge	599	}
		600
2997	Serge	601	/**
		602	* r100_hpd_fini - hpd tear down callback.
		603	*
		604	* @rdev: radeon_device pointer
		605	*
		606	* Tear down the hpd pins used by the card (r1xx-r4xx).
		607	* Disable the hpd interrupts.
		608	*/
1321	serge	609	void r100_hpd_fini(struct radeon_device *rdev)
		610	{
		611	struct drm_device *dev = rdev->ddev;
		612	struct drm_connector *connector;
2997	Serge	613	unsigned disable = 0;
1321	serge	614
		615	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		616	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2997	Serge	617	disable \|= 1 << radeon_connector->hpd.hpd;
1321	serge	618	}
2997	Serge	619	// radeon_irq_kms_disable_hpd(rdev, disable);
1321	serge	620	}
		621
1117	serge	622	/*
		623	* PCI GART
		624	*/
		625	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		626	{
		627	/* TODO: can we do somethings here ? */
		628	/* It seems hw only cache one entry so we should discard this
		629	* entry otherwise if first GPU GART read hit this entry it
		630	* could end up in wrong address. */
		631	}
		632
1179	serge	633	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	634	{
		635	int r;
		636
2997	Serge	637	if (rdev->gart.ptr) {
1963	serge	638	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	639	return 0;
		640	}
1117	serge	641	/* Initialize common gart structure */
		642	r = radeon_gart_init(rdev);
1179	serge	643	if (r)
1117	serge	644	return r;
6104	serge	645	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
2997	Serge	646	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
6104	serge	647	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
2997	Serge	648	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1179	serge	649	return radeon_gart_table_ram_alloc(rdev);
		650	}
		651
		652	int r100_pci_gart_enable(struct radeon_device *rdev)
		653	{
		654	uint32_t tmp;
		655
1117	serge	656	/* discard memory request outside of configured range */
		657	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		658	WREG32(RADEON_AIC_CNTL, tmp);
		659	/* set address range for PCI address translate */
1430	serge	660	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		661	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	662	/* set PCI GART page-table base address */
		663	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		664	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		665	WREG32(RADEON_AIC_CNTL, tmp);
		666	r100_pci_gart_tlb_flush(rdev);
2997	Serge	667	DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
		668	(unsigned)(rdev->mc.gtt_size >> 20),
		669	(unsigned long long)rdev->gart.table_addr);
1117	serge	670	rdev->gart.ready = true;
		671	return 0;
		672	}
		673
		674	void r100_pci_gart_disable(struct radeon_device *rdev)
		675	{
		676	uint32_t tmp;
		677
		678	/* discard memory request outside of configured range */
		679	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		680	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		681	WREG32(RADEON_AIC_LO_ADDR, 0);
		682	WREG32(RADEON_AIC_HI_ADDR, 0);
		683	}
		684
6104	serge	685	uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
		686	{
		687	return addr;
		688	}
		689
5078	serge	690	void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
6104	serge	691	uint64_t entry)
1117	serge	692	{
2997	Serge	693	u32 *gtt = rdev->gart.ptr;
6104	serge	694	gtt[i] = cpu_to_le32(lower_32_bits(entry));
1117	serge	695	}
		696
1179	serge	697	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	698	{
1963	serge	699	radeon_gart_fini(rdev);
6104	serge	700	r100_pci_gart_disable(rdev);
1179	serge	701	radeon_gart_table_ram_free(rdev);
1117	serge	702	}
		703
2005	serge	704	int r100_irq_set(struct radeon_device *rdev)
		705	{
		706	uint32_t tmp = 0;
1117	serge	707
2005	serge	708	if (!rdev->irq.installed) {
		709	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		710	WREG32(R_000040_GEN_INT_CNTL, 0);
		711	return -EINVAL;
		712	}
2997	Serge	713	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2005	serge	714	tmp \|= RADEON_SW_INT_ENABLE;
		715	}
		716	if (rdev->irq.crtc_vblank_int[0] \|\|
2997	Serge	717	atomic_read(&rdev->irq.pflip[0])) {
2005	serge	718	tmp \|= RADEON_CRTC_VBLANK_MASK;
		719	}
		720	if (rdev->irq.crtc_vblank_int[1] \|\|
2997	Serge	721	atomic_read(&rdev->irq.pflip[1])) {
2005	serge	722	tmp \|= RADEON_CRTC2_VBLANK_MASK;
		723	}
		724	if (rdev->irq.hpd[0]) {
		725	tmp \|= RADEON_FP_DETECT_MASK;
		726	}
		727	if (rdev->irq.hpd[1]) {
		728	tmp \|= RADEON_FP2_DETECT_MASK;
		729	}
		730	WREG32(RADEON_GEN_INT_CNTL, tmp);
6104	serge	731
		732	/* read back to post the write */
		733	RREG32(RADEON_GEN_INT_CNTL);
		734
2005	serge	735	return 0;
		736	}
		737
1221	serge	738	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	739	{
1221	serge	740	u32 tmp;
1117	serge	741
1221	serge	742	WREG32(R_000040_GEN_INT_CNTL, 0);
		743	/* Wait and acknowledge irq */
		744	mdelay(1);
		745	tmp = RREG32(R_000044_GEN_INT_STATUS);
		746	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	747	}
		748
2997	Serge	749	static uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	750	{
1221	serge	751	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	752	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		753	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		754	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	755
1221	serge	756	if (irqs) {
		757	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	758	}
1221	serge	759	return irqs & irq_mask;
1117	serge	760	}
		761
2005	serge	762	int r100_irq_process(struct radeon_device *rdev)
		763	{
		764	uint32_t status, msi_rearm;
		765	bool queue_hotplug = false;
1117	serge	766
2005	serge	767	status = r100_irq_ack(rdev);
		768	if (!status) {
		769	return IRQ_NONE;
		770	}
		771	if (rdev->shutdown) {
		772	return IRQ_NONE;
		773	}
		774	while (status) {
		775	/* SW interrupt */
		776	if (status & RADEON_SW_INT_TEST) {
2997	Serge	777	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2005	serge	778	}
		779	/* Vertical blank interrupts */
		780	if (status & RADEON_CRTC_VBLANK_STAT) {
		781	if (rdev->irq.crtc_vblank_int[0]) {
6104	serge	782	drm_handle_vblank(rdev->ddev, 0);
2005	serge	783	rdev->pm.vblank_sync = true;
6104	serge	784	wake_up(&rdev->irq.vblank_queue);
2005	serge	785	}
6104	serge	786	if (atomic_read(&rdev->irq.pflip[0]))
		787	radeon_crtc_handle_vblank(rdev, 0);
2005	serge	788	}
		789	if (status & RADEON_CRTC2_VBLANK_STAT) {
		790	if (rdev->irq.crtc_vblank_int[1]) {
6104	serge	791	drm_handle_vblank(rdev->ddev, 1);
2005	serge	792	rdev->pm.vblank_sync = true;
6104	serge	793	wake_up(&rdev->irq.vblank_queue);
2005	serge	794	}
6104	serge	795	if (atomic_read(&rdev->irq.pflip[1]))
		796	radeon_crtc_handle_vblank(rdev, 1);
2005	serge	797	}
		798	if (status & RADEON_FP_DETECT_STAT) {
		799	queue_hotplug = true;
		800	DRM_DEBUG("HPD1\n");
		801	}
		802	if (status & RADEON_FP2_DETECT_STAT) {
		803	queue_hotplug = true;
		804	DRM_DEBUG("HPD2\n");
		805	}
		806	status = r100_irq_ack(rdev);
		807	}
		808	// if (queue_hotplug)
		809	// schedule_work(&rdev->hotplug_work);
		810	if (rdev->msi_enabled) {
		811	switch (rdev->family) {
		812	case CHIP_RS400:
		813	case CHIP_RS480:
		814	msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
		815	WREG32(RADEON_AIC_CNTL, msi_rearm);
		816	WREG32(RADEON_AIC_CNTL, msi_rearm \| RS400_MSI_REARM);
		817	break;
		818	default:
2997	Serge	819	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
2005	serge	820	break;
		821	}
		822	}
		823	return IRQ_HANDLED;
		824	}
		825
1403	serge	826	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		827	{
		828	if (crtc == 0)
		829	return RREG32(RADEON_CRTC_CRNT_FRAME);
		830	else
		831	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		832	}
1117	serge	833
5139	serge	834	/**
		835	* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
		836	* rdev: radeon device structure
		837	* ring: ring buffer struct for emitting packets
		838	*/
		839	static void r100_ring_hdp_flush(struct radeon_device rdev, struct radeon_ring ring)
		840	{
		841	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		842	radeon_ring_write(ring, rdev->config.r100.hdp_cntl \|
		843	RADEON_HDP_READ_BUFFER_INVALIDATE);
		844	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		845	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
		846	}
		847
1404	serge	848	/* Who ever call radeon_fence_emit should call ring_lock and ask
		849	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	850	void r100_fence_ring_emit(struct radeon_device *rdev,
		851	struct radeon_fence *fence)
		852	{
2997	Serge	853	struct radeon_ring *ring = &rdev->ring[fence->ring];
		854
1404	serge	855	/* We have to make sure that caches are flushed before
		856	* CPU might read something from VRAM. */
2997	Serge	857	radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		858	radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
		859	radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		860	radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	861	/* Wait until IDLE & CLEAN */
2997	Serge	862	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		863	radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
5078	serge	864	r100_ring_hdp_flush(rdev, ring);
1117	serge	865	/* Emit fence sequence & fire IRQ */
2997	Serge	866	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
		867	radeon_ring_write(ring, fence->seq);
		868	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
		869	radeon_ring_write(ring, RADEON_SW_INT_FIRE);
1117	serge	870	}
		871
5078	serge	872	bool r100_semaphore_ring_emit(struct radeon_device *rdev,
2997	Serge	873	struct radeon_ring *ring,
		874	struct radeon_semaphore *semaphore,
		875	bool emit_wait)
		876	{
		877	/* Unused on older asics, since we don't have semaphores or multiple rings */
		878	BUG();
5078	serge	879	return false;
2997	Serge	880	}
		881
5271	serge	882	struct radeon_fence r100_copy_blit(struct radeon_device rdev,
6104	serge	883	uint64_t src_offset,
		884	uint64_t dst_offset,
		885	unsigned num_gpu_pages,
5271	serge	886	struct reservation_object *resv)
1117	serge	887	{
2997	Serge	888	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
5271	serge	889	struct radeon_fence *fence;
1117	serge	890	uint32_t cur_pages;
2997	Serge	891	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
1117	serge	892	uint32_t pitch;
		893	uint32_t stride_pixels;
		894	unsigned ndw;
		895	int num_loops;
		896	int r = 0;
		897
		898	/* radeon limited to 16k stride */
		899	stride_bytes &= 0x3fff;
		900	/* radeon pitch is /64 */
		901	pitch = stride_bytes / 64;
		902	stride_pixels = stride_bytes / 4;
2997	Serge	903	num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
1117	serge	904
		905	/* Ask for enough room for blit + flush + fence */
		906	ndw = 64 + (10 * num_loops);
2997	Serge	907	r = radeon_ring_lock(rdev, ring, ndw);
1117	serge	908	if (r) {
		909	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
5271	serge	910	return ERR_PTR(-EINVAL);
1117	serge	911	}
2997	Serge	912	while (num_gpu_pages > 0) {
		913	cur_pages = num_gpu_pages;
1117	serge	914	if (cur_pages > 8191) {
		915	cur_pages = 8191;
		916	}
2997	Serge	917	num_gpu_pages -= cur_pages;
1117	serge	918
		919	/* pages are in Y direction - height
		920	page width in X direction - width */
2997	Serge	921	radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
		922	radeon_ring_write(ring,
1117	serge	923	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		924	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		925	RADEON_GMC_SRC_CLIPPING \|
		926	RADEON_GMC_DST_CLIPPING \|
		927	RADEON_GMC_BRUSH_NONE \|
		928	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		929	RADEON_GMC_SRC_DATATYPE_COLOR \|
		930	RADEON_ROP3_S \|
		931	RADEON_DP_SRC_SOURCE_MEMORY \|
		932	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		933	RADEON_GMC_WR_MSK_DIS);
2997	Serge	934	radeon_ring_write(ring, (pitch << 22) \| (src_offset >> 10));
		935	radeon_ring_write(ring, (pitch << 22) \| (dst_offset >> 10));
		936	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		937	radeon_ring_write(ring, 0);
		938	radeon_ring_write(ring, (0x1fff) \| (0x1fff << 16));
		939	radeon_ring_write(ring, num_gpu_pages);
		940	radeon_ring_write(ring, num_gpu_pages);
		941	radeon_ring_write(ring, cur_pages \| (stride_pixels << 16));
1117	serge	942	}
2997	Serge	943	radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		944	radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
		945	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
		946	radeon_ring_write(ring,
1117	serge	947	RADEON_WAIT_2D_IDLECLEAN \|
		948	RADEON_WAIT_HOST_IDLECLEAN \|
		949	RADEON_WAIT_DMA_GUI_IDLE);
5271	serge	950	r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
		951	if (r) {
		952	radeon_ring_unlock_undo(rdev, ring);
		953	return ERR_PTR(r);
1117	serge	954	}
5078	serge	955	radeon_ring_unlock_commit(rdev, ring, false);
5271	serge	956	return fence;
1117	serge	957	}
		958
1179	serge	959	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		960	{
		961	unsigned i;
		962	u32 tmp;
		963
		964	for (i = 0; i < rdev->usec_timeout; i++) {
		965	tmp = RREG32(R_000E40_RBBM_STATUS);
		966	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		967	return 0;
		968	}
		969	udelay(1);
		970	}
		971	return -1;
		972	}
		973
2997	Serge	974	void r100_ring_start(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	975	{
		976	int r;
		977
2997	Serge	978	r = radeon_ring_lock(rdev, ring, 2);
1117	serge	979	if (r) {
		980	return;
		981	}
2997	Serge	982	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
		983	radeon_ring_write(ring,
1117	serge	984	RADEON_ISYNC_ANY2D_IDLE3D \|
		985	RADEON_ISYNC_ANY3D_IDLE2D \|
		986	RADEON_ISYNC_WAIT_IDLEGUI \|
		987	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
5078	serge	988	radeon_ring_unlock_commit(rdev, ring, false);
1117	serge	989	}
		990
1221	serge	991
		992	/* Load the microcode for the CP */
		993	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	994	{
1221	serge	995	const char *fw_name = NULL;
		996	int err;
1117	serge	997
1963	serge	998	DRM_DEBUG_KMS("\n");
1117	serge	999
		1000	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		1001	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		1002	(rdev->family == CHIP_RS200)) {
		1003	DRM_INFO("Loading R100 Microcode\n");
1221	serge	1004	fw_name = FIRMWARE_R100;
1117	serge	1005	} else if ((rdev->family == CHIP_R200) \|\|
		1006	(rdev->family == CHIP_RV250) \|\|
		1007	(rdev->family == CHIP_RV280) \|\|
		1008	(rdev->family == CHIP_RS300)) {
		1009	DRM_INFO("Loading R200 Microcode\n");
1221	serge	1010	fw_name = FIRMWARE_R200;
1117	serge	1011	} else if ((rdev->family == CHIP_R300) \|\|
		1012	(rdev->family == CHIP_R350) \|\|
		1013	(rdev->family == CHIP_RV350) \|\|
		1014	(rdev->family == CHIP_RV380) \|\|
		1015	(rdev->family == CHIP_RS400) \|\|
		1016	(rdev->family == CHIP_RS480)) {
		1017	DRM_INFO("Loading R300 Microcode\n");
1221	serge	1018	fw_name = FIRMWARE_R300;
1117	serge	1019	} else if ((rdev->family == CHIP_R420) \|\|
		1020	(rdev->family == CHIP_R423) \|\|
		1021	(rdev->family == CHIP_RV410)) {
		1022	DRM_INFO("Loading R400 Microcode\n");
1221	serge	1023	fw_name = FIRMWARE_R420;
1117	serge	1024	} else if ((rdev->family == CHIP_RS690) \|\|
		1025	(rdev->family == CHIP_RS740)) {
		1026	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	1027	fw_name = FIRMWARE_RS690;
1117	serge	1028	} else if (rdev->family == CHIP_RS600) {
		1029	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	1030	fw_name = FIRMWARE_RS600;
1117	serge	1031	} else if ((rdev->family == CHIP_RV515) \|\|
		1032	(rdev->family == CHIP_R520) \|\|
		1033	(rdev->family == CHIP_RV530) \|\|
		1034	(rdev->family == CHIP_R580) \|\|
		1035	(rdev->family == CHIP_RV560) \|\|
		1036	(rdev->family == CHIP_RV570)) {
		1037	DRM_INFO("Loading R500 Microcode\n");
1221	serge	1038	fw_name = FIRMWARE_R520;
6104	serge	1039	}
1221	serge	1040
5078	serge	1041	err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
6104	serge	1042	if (err) {
		1043	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		1044	fw_name);
1221	serge	1045	} else if (rdev->me_fw->size % 8) {
		1046	printk(KERN_ERR
		1047	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		1048	rdev->me_fw->size, fw_name);
		1049	err = -EINVAL;
		1050	release_firmware(rdev->me_fw);
		1051	rdev->me_fw = NULL;
1117	serge	1052	}
1221	serge	1053	return err;
1117	serge	1054	}
		1055
5078	serge	1056	u32 r100_gfx_get_rptr(struct radeon_device *rdev,
		1057	struct radeon_ring *ring)
		1058	{
		1059	u32 rptr;
		1060
		1061	if (rdev->wb.enabled)
		1062	rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
		1063	else
		1064	rptr = RREG32(RADEON_CP_RB_RPTR);
		1065
		1066	return rptr;
		1067	}
		1068
		1069	u32 r100_gfx_get_wptr(struct radeon_device *rdev,
		1070	struct radeon_ring *ring)
		1071	{
		1072	u32 wptr;
		1073
		1074	wptr = RREG32(RADEON_CP_RB_WPTR);
		1075
		1076	return wptr;
		1077	}
		1078
		1079	void r100_gfx_set_wptr(struct radeon_device *rdev,
		1080	struct radeon_ring *ring)
		1081	{
		1082	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
		1083	(void)RREG32(RADEON_CP_RB_WPTR);
		1084	}
		1085
1221	serge	1086	static void r100_cp_load_microcode(struct radeon_device *rdev)
		1087	{
		1088	const __be32 *fw_data;
		1089	int i, size;
		1090
		1091	if (r100_gui_wait_for_idle(rdev)) {
		1092	printk(KERN_WARNING "Failed to wait GUI idle while "
		1093	"programming pipes. Bad things might happen.\n");
		1094	}
		1095
		1096	if (rdev->me_fw) {
		1097	size = rdev->me_fw->size / 4;
		1098	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		1099	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		1100	for (i = 0; i < size; i += 2) {
		1101	WREG32(RADEON_CP_ME_RAM_DATAH,
		1102	be32_to_cpup(&fw_data[i]));
		1103	WREG32(RADEON_CP_ME_RAM_DATAL,
		1104	be32_to_cpup(&fw_data[i + 1]));
		1105	}
		1106	}
		1107	}
		1108
1117	serge	1109	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		1110	{
2997	Serge	1111	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1117	serge	1112	unsigned rb_bufsz;
		1113	unsigned rb_blksz;
		1114	unsigned max_fetch;
		1115	unsigned pre_write_timer;
		1116	unsigned pre_write_limit;
		1117	unsigned indirect2_start;
		1118	unsigned indirect1_start;
		1119	uint32_t tmp;
		1120	int r;
		1121
1129	serge	1122	if (r100_debugfs_cp_init(rdev)) {
		1123	DRM_ERROR("Failed to register debugfs file for CP !\n");
		1124	}
1179	serge	1125	if (!rdev->me_fw) {
		1126	r = r100_cp_init_microcode(rdev);
		1127	if (r) {
		1128	DRM_ERROR("Failed to load firmware!\n");
		1129	return r;
		1130	}
		1131	}
		1132
1117	serge	1133	/* Align ring size */
5078	serge	1134	rb_bufsz = order_base_2(ring_size / 8);
1117	serge	1135	ring_size = (1 << (rb_bufsz + 1)) * 4;
		1136	r100_cp_load_microcode(rdev);
2997	Serge	1137	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
5078	serge	1138	RADEON_CP_PACKET2);
1117	serge	1139	if (r) {
		1140	return r;
		1141	}
		1142	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		1143	* the rptr copy in system ram */
		1144	rb_blksz = 9;
		1145	/* cp will read 128bytes at a time (4 dwords) */
		1146	max_fetch = 1;
2997	Serge	1147	ring->align_mask = 16 - 1;
1117	serge	1148	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		1149	pre_write_timer = 64;
		1150	/* Force CP_RB_WPTR write if written more than one time before the
		1151	* delay expire
		1152	*/
		1153	pre_write_limit = 0;
		1154	/* Setup the cp cache like this (cache size is 96 dwords) :
		1155	* RING 0 to 15
		1156	* INDIRECT1 16 to 79
		1157	* INDIRECT2 80 to 95
		1158	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		1159	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		1160	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		1161	* Idea being that most of the gpu cmd will be through indirect1 buffer
		1162	* so it gets the bigger cache.
		1163	*/
		1164	indirect2_start = 80;
		1165	indirect1_start = 16;
		1166	/* cp setup */
		1167	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	1168	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	1169	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	1170	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	1171	#ifdef __BIG_ENDIAN
		1172	tmp \|= RADEON_BUF_SWAP_32BIT;
		1173	#endif
1963	serge	1174	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	1175
1117	serge	1176	/* Set ring address */
2997	Serge	1177	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
		1178	WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1117	serge	1179	/* Force read & write ptr to 0 */
1963	serge	1180	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	1181	WREG32(RADEON_CP_RB_RPTR_WR, 0);
2997	Serge	1182	ring->wptr = 0;
		1183	WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1963	serge	1184
		1185	/* set the wb address whether it's enabled or not */
		1186	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		1187	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		1188	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		1189
		1190	if (rdev->wb.enabled)
		1191	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		1192	else {
		1193	tmp \|= RADEON_RB_NO_UPDATE;
		1194	WREG32(R_000770_SCRATCH_UMSK, 0);
		1195	}
		1196
1117	serge	1197	WREG32(RADEON_CP_RB_CNTL, tmp);
		1198	udelay(10);
		1199	/* Set cp mode to bus mastering & enable cp*/
		1200	WREG32(RADEON_CP_CSQ_MODE,
		1201	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		1202	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	1203	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		1204	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	1205	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2997	Serge	1206	radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
		1207	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1117	serge	1208	if (r) {
		1209	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		1210	return r;
		1211	}
2997	Serge	1212	ring->ready = true;
3192	Serge	1213	radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
		1214
		1215	if (!ring->rptr_save_reg /* not resuming from suspend */
		1216	&& radeon_ring_supports_scratch_reg(rdev, ring)) {
		1217	r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
		1218	if (r) {
		1219	DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
		1220	ring->rptr_save_reg = 0;
		1221	}
		1222	}
1117	serge	1223	return 0;
		1224	}
		1225
		1226	void r100_cp_fini(struct radeon_device *rdev)
		1227	{
1179	serge	1228	if (r100_cp_wait_for_idle(rdev)) {
		1229	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		1230	}
1117	serge	1231	/* Disable ring */
1179	serge	1232	r100_cp_disable(rdev);
3192	Serge	1233	radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
2997	Serge	1234	radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1117	serge	1235	DRM_INFO("radeon: cp finalized\n");
		1236	}
		1237
		1238	void r100_cp_disable(struct radeon_device *rdev)
		1239	{
		1240	/* Disable ring */
3192	Serge	1241	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2997	Serge	1242	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1117	serge	1243	WREG32(RADEON_CP_CSQ_MODE, 0);
		1244	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	1245	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	1246	if (r100_gui_wait_for_idle(rdev)) {
		1247	printk(KERN_WARNING "Failed to wait GUI idle while "
		1248	"programming pipes. Bad things might happen.\n");
		1249	}
		1250	}
		1251
2997	Serge	1252	/*
		1253	* CS functions
		1254	*/
		1255	int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
		1256	struct radeon_cs_packet *pkt,
		1257	unsigned idx,
		1258	unsigned reg)
1179	serge	1259	{
2997	Serge	1260	int r;
		1261	u32 tile_flags = 0;
		1262	u32 tmp;
5271	serge	1263	struct radeon_bo_list *reloc;
2997	Serge	1264	u32 value;
		1265
3764	Serge	1266	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1267	if (r) {
		1268	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1269	idx, reg);
3764	Serge	1270	radeon_cs_dump_packet(p, pkt);
2997	Serge	1271	return r;
		1272	}
		1273
		1274	value = radeon_get_ib_value(p, idx);
		1275	tmp = value & 0x003fffff;
5078	serge	1276	tmp += (((u32)reloc->gpu_offset) >> 10);
2997	Serge	1277
		1278	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1279	if (reloc->tiling_flags & RADEON_TILING_MACRO)
2997	Serge	1280	tile_flags \|= RADEON_DST_TILE_MACRO;
5078	serge	1281	if (reloc->tiling_flags & RADEON_TILING_MICRO) {
2997	Serge	1282	if (reg == RADEON_SRC_PITCH_OFFSET) {
		1283	DRM_ERROR("Cannot src blit from microtiled surface\n");
3764	Serge	1284	radeon_cs_dump_packet(p, pkt);
2997	Serge	1285	return -EINVAL;
		1286	}
		1287	tile_flags \|= RADEON_DST_TILE_MICRO;
		1288	}
		1289
		1290	tmp \|= tile_flags;
		1291	p->ib.ptr[idx] = (value & 0x3fc00000) \| tmp;
		1292	} else
		1293	p->ib.ptr[idx] = (value & 0xffc00000) \| tmp;
		1294	return 0;
1179	serge	1295	}
		1296
2997	Serge	1297	int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
		1298	struct radeon_cs_packet *pkt,
		1299	int idx)
		1300	{
		1301	unsigned c, i;
5271	serge	1302	struct radeon_bo_list *reloc;
2997	Serge	1303	struct r100_cs_track *track;
		1304	int r = 0;
		1305	volatile uint32_t *ib;
		1306	u32 idx_value;
1179	serge	1307
2997	Serge	1308	ib = p->ib.ptr;
		1309	track = (struct r100_cs_track *)p->track;
		1310	c = radeon_get_ib_value(p, idx++) & 0x1F;
		1311	if (c > 16) {
		1312	DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
		1313	pkt->opcode);
3764	Serge	1314	radeon_cs_dump_packet(p, pkt);
2997	Serge	1315	return -EINVAL;
		1316	}
		1317	track->num_arrays = c;
		1318	for (i = 0; i < (c - 1); i+=2, idx+=3) {
3764	Serge	1319	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1320	if (r) {
		1321	DRM_ERROR("No reloc for packet3 %d\n",
		1322	pkt->opcode);
3764	Serge	1323	radeon_cs_dump_packet(p, pkt);
2997	Serge	1324	return r;
		1325	}
		1326	idx_value = radeon_get_ib_value(p, idx);
5078	serge	1327	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
2997	Serge	1328
		1329	track->arrays[i + 0].esize = idx_value >> 8;
		1330	track->arrays[i + 0].robj = reloc->robj;
		1331	track->arrays[i + 0].esize &= 0x7F;
3764	Serge	1332	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1333	if (r) {
		1334	DRM_ERROR("No reloc for packet3 %d\n",
		1335	pkt->opcode);
3764	Serge	1336	radeon_cs_dump_packet(p, pkt);
2997	Serge	1337	return r;
		1338	}
5078	serge	1339	ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
2997	Serge	1340	track->arrays[i + 1].robj = reloc->robj;
		1341	track->arrays[i + 1].esize = idx_value >> 24;
		1342	track->arrays[i + 1].esize &= 0x7F;
		1343	}
		1344	if (c & 1) {
3764	Serge	1345	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2997	Serge	1346	if (r) {
		1347	DRM_ERROR("No reloc for packet3 %d\n",
		1348	pkt->opcode);
3764	Serge	1349	radeon_cs_dump_packet(p, pkt);
2997	Serge	1350	return r;
		1351	}
		1352	idx_value = radeon_get_ib_value(p, idx);
5078	serge	1353	ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
2997	Serge	1354	track->arrays[i + 0].robj = reloc->robj;
		1355	track->arrays[i + 0].esize = idx_value >> 8;
		1356	track->arrays[i + 0].esize &= 0x7F;
		1357	}
		1358	return r;
		1359	}
		1360
1117	serge	1361	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		1362	struct radeon_cs_packet *pkt,
		1363	const unsigned *auth, unsigned n,
		1364	radeon_packet0_check_t check)
		1365	{
		1366	unsigned reg;
		1367	unsigned i, j, m;
		1368	unsigned idx;
		1369	int r;
		1370
		1371	idx = pkt->idx + 1;
		1372	reg = pkt->reg;
		1373	/* Check that register fall into register range
		1374	* determined by the number of entry (n) in the
		1375	* safe register bitmap.
		1376	*/
		1377	if (pkt->one_reg_wr) {
		1378	if ((reg >> 7) > n) {
		1379	return -EINVAL;
		1380	}
		1381	} else {
		1382	if (((reg + (pkt->count << 2)) >> 7) > n) {
		1383	return -EINVAL;
		1384	}
		1385	}
		1386	for (i = 0; i <= pkt->count; i++, idx++) {
		1387	j = (reg >> 7);
		1388	m = 1 << ((reg >> 2) & 31);
		1389	if (auth[j] & m) {
		1390	r = check(p, pkt, idx, reg);
		1391	if (r) {
		1392	return r;
		1393	}
		1394	}
		1395	if (pkt->one_reg_wr) {
		1396	if (!(auth[j] & m)) {
		1397	break;
		1398	}
		1399	} else {
		1400	reg += 4;
		1401	}
		1402	}
		1403	return 0;
		1404	}
		1405
		1406	/**
1179	serge	1407	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		1408	* @parser: parser structure holding parsing context.
		1409	*
		1410	* Userspace sends a special sequence for VLINE waits.
		1411	* PACKET0 - VLINE_START_END + value
		1412	* PACKET0 - WAIT_UNTIL +_value
		1413	* RELOC (P3) - crtc_id in reloc.
		1414	*
		1415	* This function parses this and relocates the VLINE START END
		1416	* and WAIT UNTIL packets to the correct crtc.
		1417	* It also detects a switched off crtc and nulls out the
		1418	* wait in that case.
		1419	*/
		1420	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		1421	{
		1422	struct drm_crtc *crtc;
		1423	struct radeon_crtc *radeon_crtc;
		1424	struct radeon_cs_packet p3reloc, waitreloc;
		1425	int crtc_id;
		1426	int r;
		1427	uint32_t header, h_idx, reg;
1221	serge	1428	volatile uint32_t *ib;
1179	serge	1429
2997	Serge	1430	ib = p->ib.ptr;
1179	serge	1431
		1432	/* parse the wait until */
3764	Serge	1433	r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1179	serge	1434	if (r)
		1435	return r;
		1436
		1437	/* check its a wait until and only 1 count */
		1438	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		1439	waitreloc.count != 0) {
		1440	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	1441	return -EINVAL;
1179	serge	1442	}
		1443
1221	serge	1444	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	1445	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	1446	return -EINVAL;
1179	serge	1447	}
		1448
		1449	/* jump over the NOP */
3764	Serge	1450	r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	1451	if (r)
		1452	return r;
		1453
		1454	h_idx = p->idx - 2;
1221	serge	1455	p->idx += waitreloc.count + 2;
		1456	p->idx += p3reloc.count + 2;
1179	serge	1457
1221	serge	1458	header = radeon_get_ib_value(p, h_idx);
		1459	crtc_id = radeon_get_ib_value(p, h_idx + 5);
3764	Serge	1460	reg = R100_CP_PACKET0_GET_REG(header);
5078	serge	1461	crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
		1462	if (!crtc) {
1179	serge	1463	DRM_ERROR("cannot find crtc %d\n", crtc_id);
5078	serge	1464	return -ENOENT;
1179	serge	1465	}
		1466	radeon_crtc = to_radeon_crtc(crtc);
		1467	crtc_id = radeon_crtc->crtc_id;
		1468
		1469	if (!crtc->enabled) {
		1470	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	1471	ib[h_idx + 2] = PACKET2(0);
		1472	ib[h_idx + 3] = PACKET2(0);
1179	serge	1473	} else if (crtc_id == 1) {
		1474	switch (reg) {
		1475	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	1476	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1477	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		1478	break;
		1479	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	1480	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	1481	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		1482	break;
		1483	default:
		1484	DRM_ERROR("unknown crtc reloc\n");
1963	serge	1485	return -EINVAL;
1179	serge	1486	}
1221	serge	1487	ib[h_idx] = header;
		1488	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	1489	}
1963	serge	1490
		1491	return 0;
1179	serge	1492	}
		1493
		1494	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1495	{
		1496	int vtx_size;
		1497	vtx_size = 2;
		1498	/* ordered according to bits in spec */
		1499	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1500	vtx_size++;
		1501	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1502	vtx_size += 3;
		1503	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1504	vtx_size++;
		1505	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1506	vtx_size++;
		1507	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1508	vtx_size += 3;
		1509	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1510	vtx_size++;
		1511	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1512	vtx_size++;
		1513	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1514	vtx_size += 2;
		1515	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1516	vtx_size += 2;
		1517	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1518	vtx_size++;
		1519	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1520	vtx_size += 2;
		1521	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1522	vtx_size++;
		1523	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1524	vtx_size += 2;
		1525	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1526	vtx_size++;
		1527	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1528	vtx_size++;
		1529	/* blend weight */
		1530	if (vtx_fmt & (0x7 << 15))
		1531	vtx_size += (vtx_fmt >> 15) & 0x7;
		1532	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1533	vtx_size += 3;
		1534	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1535	vtx_size += 2;
		1536	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1537	vtx_size++;
		1538	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1539	vtx_size++;
		1540	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1541	vtx_size++;
		1542	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1543	vtx_size++;
		1544	return vtx_size;
		1545	}
		1546
1117	serge	1547	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1548	struct radeon_cs_packet *pkt,
		1549	unsigned idx, unsigned reg)
1117	serge	1550	{
5271	serge	1551	struct radeon_bo_list *reloc;
1179	serge	1552	struct r100_cs_track *track;
1117	serge	1553	volatile uint32_t *ib;
		1554	uint32_t tmp;
		1555	int r;
1179	serge	1556	int i, face;
		1557	u32 tile_flags = 0;
1221	serge	1558	u32 idx_value;
1117	serge	1559
2997	Serge	1560	ib = p->ib.ptr;
1179	serge	1561	track = (struct r100_cs_track *)p->track;
		1562
1221	serge	1563	idx_value = radeon_get_ib_value(p, idx);
		1564
6104	serge	1565	switch (reg) {
		1566	case RADEON_CRTC_GUI_TRIG_VLINE:
		1567	r = r100_cs_packet_parse_vline(p);
		1568	if (r) {
		1569	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1570	idx, reg);
3764	Serge	1571	radeon_cs_dump_packet(p, pkt);
6104	serge	1572	return r;
		1573	}
		1574	break;
1117	serge	1575	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1576	* range access */
6104	serge	1577	case RADEON_DST_PITCH_OFFSET:
		1578	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1579	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1580	if (r)
		1581	return r;
		1582	break;
		1583	case RADEON_RB3D_DEPTHOFFSET:
3764	Serge	1584	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	1585	if (r) {
		1586	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1587	idx, reg);
3764	Serge	1588	radeon_cs_dump_packet(p, pkt);
6104	serge	1589	return r;
		1590	}
1179	serge	1591	track->zb.robj = reloc->robj;
1221	serge	1592	track->zb.offset = idx_value;
1963	serge	1593	track->zb_dirty = true;
5078	serge	1594	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
6104	serge	1595	break;
		1596	case RADEON_RB3D_COLOROFFSET:
3764	Serge	1597	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1598	if (r) {
		1599	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1600	idx, reg);
3764	Serge	1601	radeon_cs_dump_packet(p, pkt);
1179	serge	1602	return r;
		1603	}
		1604	track->cb[0].robj = reloc->robj;
1221	serge	1605	track->cb[0].offset = idx_value;
1963	serge	1606	track->cb_dirty = true;
5078	serge	1607	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1608	break;
6104	serge	1609	case RADEON_PP_TXOFFSET_0:
		1610	case RADEON_PP_TXOFFSET_1:
		1611	case RADEON_PP_TXOFFSET_2:
1179	serge	1612	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
3764	Serge	1613	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1614	if (r) {
		1615	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1616	idx, reg);
3764	Serge	1617	radeon_cs_dump_packet(p, pkt);
1179	serge	1618	return r;
		1619	}
2997	Serge	1620	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1621	if (reloc->tiling_flags & RADEON_TILING_MACRO)
2997	Serge	1622	tile_flags \|= RADEON_TXO_MACRO_TILE;
5078	serge	1623	if (reloc->tiling_flags & RADEON_TILING_MICRO)
2997	Serge	1624	tile_flags \|= RADEON_TXO_MICRO_TILE_X2;
		1625
		1626	tmp = idx_value & ~(0x7 << 2);
		1627	tmp \|= tile_flags;
5078	serge	1628	ib[idx] = tmp + ((u32)reloc->gpu_offset);
2997	Serge	1629	} else
5078	serge	1630	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1631	track->textures[i].robj = reloc->robj;
1963	serge	1632	track->tex_dirty = true;
1179	serge	1633	break;
		1634	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1635	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1636	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1637	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1638	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1639	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
3764	Serge	1640	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1641	if (r) {
		1642	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1643	idx, reg);
3764	Serge	1644	radeon_cs_dump_packet(p, pkt);
1179	serge	1645	return r;
		1646	}
1221	serge	1647	track->textures[0].cube_info[i].offset = idx_value;
5078	serge	1648	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1649	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1650	track->tex_dirty = true;
1179	serge	1651	break;
		1652	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1653	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1654	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1655	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1656	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1657	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
3764	Serge	1658	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1179	serge	1659	if (r) {
		1660	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1661	idx, reg);
3764	Serge	1662	radeon_cs_dump_packet(p, pkt);
1179	serge	1663	return r;
6104	serge	1664	}
1221	serge	1665	track->textures[1].cube_info[i].offset = idx_value;
5078	serge	1666	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1667	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1668	track->tex_dirty = true;
1179	serge	1669	break;
		1670	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1671	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1672	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1673	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1674	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1675	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
3764	Serge	1676	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	1677	if (r) {
		1678	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1679	idx, reg);
3764	Serge	1680	radeon_cs_dump_packet(p, pkt);
6104	serge	1681	return r;
		1682	}
1221	serge	1683	track->textures[2].cube_info[i].offset = idx_value;
5078	serge	1684	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1179	serge	1685	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1686	track->tex_dirty = true;
1179	serge	1687	break;
		1688	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1689	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1690	track->cb_dirty = true;
		1691	track->zb_dirty = true;
6104	serge	1692	break;
		1693	case RADEON_RB3D_COLORPITCH:
3764	Serge	1694	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	1695	if (r) {
		1696	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1697	idx, reg);
3764	Serge	1698	radeon_cs_dump_packet(p, pkt);
6104	serge	1699	return r;
		1700	}
2997	Serge	1701	if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
5078	serge	1702	if (reloc->tiling_flags & RADEON_TILING_MACRO)
1179	serge	1703	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
5078	serge	1704	if (reloc->tiling_flags & RADEON_TILING_MICRO)
1179	serge	1705	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1706
6104	serge	1707	tmp = idx_value & ~(0x7 << 16);
1179	serge	1708	tmp \|= tile_flags;
		1709	ib[idx] = tmp;
2997	Serge	1710	} else
		1711	ib[idx] = idx_value;
1179	serge	1712
1221	serge	1713	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1714	track->cb_dirty = true;
1179	serge	1715	break;
		1716	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1717	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1718	track->zb_dirty = true;
1179	serge	1719	break;
		1720	case RADEON_RB3D_CNTL:
1221	serge	1721	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1722	case 7:
		1723	case 8:
		1724	case 9:
		1725	case 11:
		1726	case 12:
		1727	track->cb[0].cpp = 1;
		1728	break;
		1729	case 3:
		1730	case 4:
		1731	case 15:
		1732	track->cb[0].cpp = 2;
		1733	break;
		1734	case 6:
		1735	track->cb[0].cpp = 4;
		1736	break;
1117	serge	1737	default:
1179	serge	1738	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1739	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1740	return -EINVAL;
		1741	}
1221	serge	1742	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1743	track->cb_dirty = true;
		1744	track->zb_dirty = true;
1179	serge	1745	break;
		1746	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1747	switch (idx_value & 0xf) {
1179	serge	1748	case 0:
		1749	track->zb.cpp = 2;
1117	serge	1750	break;
1179	serge	1751	case 2:
		1752	case 3:
		1753	case 4:
		1754	case 5:
		1755	case 9:
		1756	case 11:
		1757	track->zb.cpp = 4;
		1758	break;
		1759	default:
		1760	break;
1117	serge	1761	}
1963	serge	1762	track->zb_dirty = true;
6104	serge	1763	break;
		1764	case RADEON_RB3D_ZPASS_ADDR:
3764	Serge	1765	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
6104	serge	1766	if (r) {
		1767	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1768	idx, reg);
3764	Serge	1769	radeon_cs_dump_packet(p, pkt);
6104	serge	1770	return r;
		1771	}
5078	serge	1772	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
6104	serge	1773	break;
1179	serge	1774	case RADEON_PP_CNTL:
		1775	{
1221	serge	1776	uint32_t temp = idx_value >> 4;
1179	serge	1777	for (i = 0; i < track->num_texture; i++)
		1778	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1779	track->tex_dirty = true;
1117	serge	1780	}
6104	serge	1781	break;
1179	serge	1782	case RADEON_SE_VF_CNTL:
1221	serge	1783	track->vap_vf_cntl = idx_value;
1179	serge	1784	break;
		1785	case RADEON_SE_VTX_FMT:
1221	serge	1786	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1787	break;
		1788	case RADEON_PP_TEX_SIZE_0:
		1789	case RADEON_PP_TEX_SIZE_1:
		1790	case RADEON_PP_TEX_SIZE_2:
		1791	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1792	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1793	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1794	track->tex_dirty = true;
1179	serge	1795	break;
		1796	case RADEON_PP_TEX_PITCH_0:
		1797	case RADEON_PP_TEX_PITCH_1:
		1798	case RADEON_PP_TEX_PITCH_2:
		1799	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1800	track->textures[i].pitch = idx_value + 32;
1963	serge	1801	track->tex_dirty = true;
1179	serge	1802	break;
		1803	case RADEON_PP_TXFILTER_0:
		1804	case RADEON_PP_TXFILTER_1:
		1805	case RADEON_PP_TXFILTER_2:
		1806	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1807	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1808	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1809	tmp = (idx_value >> 23) & 0x7;
1179	serge	1810	if (tmp == 2 \|\| tmp == 6)
		1811	track->textures[i].roundup_w = false;
1221	serge	1812	tmp = (idx_value >> 27) & 0x7;
1179	serge	1813	if (tmp == 2 \|\| tmp == 6)
		1814	track->textures[i].roundup_h = false;
1963	serge	1815	track->tex_dirty = true;
1179	serge	1816	break;
		1817	case RADEON_PP_TXFORMAT_0:
		1818	case RADEON_PP_TXFORMAT_1:
		1819	case RADEON_PP_TXFORMAT_2:
		1820	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1821	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1822	track->textures[i].use_pitch = 1;
		1823	} else {
		1824	track->textures[i].use_pitch = 0;
1221	serge	1825	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1826	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1827	}
1221	serge	1828	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1829	track->textures[i].tex_coord_type = 2;
1221	serge	1830	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1831	case RADEON_TXFORMAT_I8:
		1832	case RADEON_TXFORMAT_RGB332:
		1833	case RADEON_TXFORMAT_Y8:
		1834	track->textures[i].cpp = 1;
1963	serge	1835	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1836	break;
		1837	case RADEON_TXFORMAT_AI88:
		1838	case RADEON_TXFORMAT_ARGB1555:
		1839	case RADEON_TXFORMAT_RGB565:
		1840	case RADEON_TXFORMAT_ARGB4444:
		1841	case RADEON_TXFORMAT_VYUY422:
		1842	case RADEON_TXFORMAT_YVYU422:
		1843	case RADEON_TXFORMAT_SHADOW16:
		1844	case RADEON_TXFORMAT_LDUDV655:
		1845	case RADEON_TXFORMAT_DUDV88:
		1846	track->textures[i].cpp = 2;
1963	serge	1847	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1848	break;
		1849	case RADEON_TXFORMAT_ARGB8888:
		1850	case RADEON_TXFORMAT_RGBA8888:
		1851	case RADEON_TXFORMAT_SHADOW32:
		1852	case RADEON_TXFORMAT_LDUDUV8888:
		1853	track->textures[i].cpp = 4;
1963	serge	1854	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1855	break;
1403	serge	1856	case RADEON_TXFORMAT_DXT1:
		1857	track->textures[i].cpp = 1;
		1858	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1859	break;
		1860	case RADEON_TXFORMAT_DXT23:
		1861	case RADEON_TXFORMAT_DXT45:
		1862	track->textures[i].cpp = 1;
		1863	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1864	break;
1179	serge	1865	}
1221	serge	1866	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1867	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1868	track->tex_dirty = true;
1179	serge	1869	break;
		1870	case RADEON_PP_CUBIC_FACES_0:
		1871	case RADEON_PP_CUBIC_FACES_1:
		1872	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1873	tmp = idx_value;
1179	serge	1874	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1875	for (face = 0; face < 4; face++) {
		1876	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1877	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1878	}
1963	serge	1879	track->tex_dirty = true;
1179	serge	1880	break;
		1881	default:
		1882	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1883	reg, idx);
		1884	return -EINVAL;
1117	serge	1885	}
		1886	return 0;
		1887	}
		1888
		1889	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1890	struct radeon_cs_packet *pkt,
1321	serge	1891	struct radeon_bo *robj)
1117	serge	1892	{
		1893	unsigned idx;
1221	serge	1894	u32 value;
1117	serge	1895	idx = pkt->idx + 1;
1221	serge	1896	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1897	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1898	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1899	"(need %u have %lu) !\n",
1221	serge	1900	value + 1,
1321	serge	1901	radeon_bo_size(robj));
1117	serge	1902	return -EINVAL;
		1903	}
		1904	return 0;
		1905	}
		1906
		1907	static int r100_packet3_check(struct radeon_cs_parser *p,
		1908	struct radeon_cs_packet *pkt)
		1909	{
5271	serge	1910	struct radeon_bo_list *reloc;
1179	serge	1911	struct r100_cs_track *track;
1117	serge	1912	unsigned idx;
		1913	volatile uint32_t *ib;
		1914	int r;
		1915
2997	Serge	1916	ib = p->ib.ptr;
1117	serge	1917	idx = pkt->idx + 1;
1179	serge	1918	track = (struct r100_cs_track *)p->track;
1117	serge	1919	switch (pkt->opcode) {
		1920	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1921	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1922	if (r)
6104	serge	1923	return r;
1117	serge	1924	break;
		1925	case PACKET3_INDX_BUFFER:
3764	Serge	1926	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1927	if (r) {
		1928	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
3764	Serge	1929	radeon_cs_dump_packet(p, pkt);
1117	serge	1930	return r;
		1931	}
5078	serge	1932	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1117	serge	1933	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1934	if (r) {
		1935	return r;
		1936	}
		1937	break;
		1938	case 0x23:
		1939	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
3764	Serge	1940	r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1117	serge	1941	if (r) {
		1942	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
3764	Serge	1943	radeon_cs_dump_packet(p, pkt);
1117	serge	1944	return r;
		1945	}
5078	serge	1946	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1179	serge	1947	track->num_arrays = 1;
1221	serge	1948	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1949
		1950	track->arrays[0].robj = reloc->robj;
		1951	track->arrays[0].esize = track->vtx_size;
		1952
1221	serge	1953	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1954
1221	serge	1955	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1956	track->immd_dwords = pkt->count - 1;
		1957	r = r100_cs_track_check(p->rdev, track);
		1958	if (r)
		1959	return r;
1117	serge	1960	break;
		1961	case PACKET3_3D_DRAW_IMMD:
1221	serge	1962	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1963	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1964	return -EINVAL;
		1965	}
1403	serge	1966	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1967	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1968	track->immd_dwords = pkt->count - 1;
		1969	r = r100_cs_track_check(p->rdev, track);
		1970	if (r)
		1971	return r;
		1972	break;
1117	serge	1973	/* triggers drawing using in-packet vertex data */
		1974	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1975	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1976	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1977	return -EINVAL;
		1978	}
1221	serge	1979	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1980	track->immd_dwords = pkt->count;
		1981	r = r100_cs_track_check(p->rdev, track);
		1982	if (r)
		1983	return r;
		1984	break;
1117	serge	1985	/* triggers drawing using in-packet vertex data */
		1986	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1987	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1988	r = r100_cs_track_check(p->rdev, track);
		1989	if (r)
		1990	return r;
		1991	break;
1117	serge	1992	/* triggers drawing of vertex buffers setup elsewhere */
		1993	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1994	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1995	r = r100_cs_track_check(p->rdev, track);
		1996	if (r)
		1997	return r;
		1998	break;
1117	serge	1999	/* triggers drawing using indices to vertex buffer */
		2000	case PACKET3_3D_DRAW_VBUF:
1221	serge	2001	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	2002	r = r100_cs_track_check(p->rdev, track);
		2003	if (r)
		2004	return r;
		2005	break;
1117	serge	2006	/* triggers drawing of vertex buffers setup elsewhere */
		2007	case PACKET3_3D_DRAW_INDX:
1221	serge	2008	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	2009	r = r100_cs_track_check(p->rdev, track);
		2010	if (r)
		2011	return r;
		2012	break;
1117	serge	2013	/* triggers drawing using indices to vertex buffer */
1963	serge	2014	case PACKET3_3D_CLEAR_HIZ:
		2015	case PACKET3_3D_CLEAR_ZMASK:
		2016	if (p->rdev->hyperz_filp != p->filp)
		2017	return -EINVAL;
		2018	break;
1117	serge	2019	case PACKET3_NOP:
		2020	break;
		2021	default:
		2022	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		2023	return -EINVAL;
		2024	}
		2025	return 0;
		2026	}
		2027
		2028	int r100_cs_parse(struct radeon_cs_parser *p)
		2029	{
		2030	struct radeon_cs_packet pkt;
1179	serge	2031	struct r100_cs_track *track;
1117	serge	2032	int r;
		2033
1179	serge	2034	track = kzalloc(sizeof(*track), GFP_KERNEL);
2997	Serge	2035	if (!track)
		2036	return -ENOMEM;
1179	serge	2037	r100_cs_track_clear(p->rdev, track);
		2038	p->track = track;
1117	serge	2039	do {
3764	Serge	2040	r = radeon_cs_packet_parse(p, &pkt, p->idx);
1117	serge	2041	if (r) {
		2042	return r;
		2043	}
		2044	p->idx += pkt.count + 2;
		2045	switch (pkt.type) {
3764	Serge	2046	case RADEON_PACKET_TYPE0:
6104	serge	2047	if (p->rdev->family >= CHIP_R200)
		2048	r = r100_cs_parse_packet0(p, &pkt,
		2049	p->rdev->config.r100.reg_safe_bm,
		2050	p->rdev->config.r100.reg_safe_bm_size,
		2051	&r200_packet0_check);
		2052	else
		2053	r = r100_cs_parse_packet0(p, &pkt,
		2054	p->rdev->config.r100.reg_safe_bm,
		2055	p->rdev->config.r100.reg_safe_bm_size,
		2056	&r100_packet0_check);
		2057	break;
3764	Serge	2058	case RADEON_PACKET_TYPE2:
6104	serge	2059	break;
3764	Serge	2060	case RADEON_PACKET_TYPE3:
6104	serge	2061	r = r100_packet3_check(p, &pkt);
		2062	break;
		2063	default:
		2064	DRM_ERROR("Unknown packet type %d !\n",
		2065	pkt.type);
		2066	return -EINVAL;
1117	serge	2067	}
3764	Serge	2068	if (r)
1117	serge	2069	return r;
5271	serge	2070	} while (p->idx < p->chunk_ib->length_dw);
1117	serge	2071	return 0;
		2072	}
		2073
2997	Serge	2074	static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		2075	{
		2076	DRM_ERROR("pitch %d\n", t->pitch);
		2077	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		2078	DRM_ERROR("width %d\n", t->width);
		2079	DRM_ERROR("width_11 %d\n", t->width_11);
		2080	DRM_ERROR("height %d\n", t->height);
		2081	DRM_ERROR("height_11 %d\n", t->height_11);
		2082	DRM_ERROR("num levels %d\n", t->num_levels);
		2083	DRM_ERROR("depth %d\n", t->txdepth);
		2084	DRM_ERROR("bpp %d\n", t->cpp);
		2085	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		2086	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		2087	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		2088	DRM_ERROR("compress format %d\n", t->compress_format);
		2089	}
1117	serge	2090
2997	Serge	2091	static int r100_track_compress_size(int compress_format, int w, int h)
1117	serge	2092	{
2997	Serge	2093	int block_width, block_height, block_bytes;
		2094	int wblocks, hblocks;
		2095	int min_wblocks;
		2096	int sz;
1117	serge	2097
2997	Serge	2098	block_width = 4;
		2099	block_height = 4;
		2100
		2101	switch (compress_format) {
		2102	case R100_TRACK_COMP_DXT1:
		2103	block_bytes = 8;
		2104	min_wblocks = 4;
		2105	break;
		2106	default:
		2107	case R100_TRACK_COMP_DXT35:
		2108	block_bytes = 16;
		2109	min_wblocks = 2;
		2110	break;
1117	serge	2111	}
		2112
2997	Serge	2113	hblocks = (h + block_height - 1) / block_height;
		2114	wblocks = (w + block_width - 1) / block_width;
		2115	if (wblocks < min_wblocks)
		2116	wblocks = min_wblocks;
		2117	sz = wblocks * hblocks * block_bytes;
		2118	return sz;
		2119	}
		2120
		2121	static int r100_cs_track_cube(struct radeon_device *rdev,
		2122	struct r100_cs_track *track, unsigned idx)
		2123	{
		2124	unsigned face, w, h;
		2125	struct radeon_bo *cube_robj;
		2126	unsigned long size;
		2127	unsigned compress_format = track->textures[idx].compress_format;
		2128
		2129	for (face = 0; face < 5; face++) {
		2130	cube_robj = track->textures[idx].cube_info[face].robj;
		2131	w = track->textures[idx].cube_info[face].width;
		2132	h = track->textures[idx].cube_info[face].height;
		2133
		2134	if (compress_format) {
		2135	size = r100_track_compress_size(compress_format, w, h);
		2136	} else
		2137	size = w * h;
		2138	size *= track->textures[idx].cpp;
		2139
		2140	size += track->textures[idx].cube_info[face].offset;
		2141
		2142	if (size > radeon_bo_size(cube_robj)) {
		2143	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		2144	size, radeon_bo_size(cube_robj));
		2145	r100_cs_track_texture_print(&track->textures[idx]);
		2146	return -1;
		2147	}
1117	serge	2148	}
2997	Serge	2149	return 0;
1117	serge	2150	}
		2151
2997	Serge	2152	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		2153	struct r100_cs_track *track)
1117	serge	2154	{
2997	Serge	2155	struct radeon_bo *robj;
		2156	unsigned long size;
		2157	unsigned u, i, w, h, d;
		2158	int ret;
1117	serge	2159
2997	Serge	2160	for (u = 0; u < track->num_texture; u++) {
		2161	if (!track->textures[u].enabled)
		2162	continue;
		2163	if (track->textures[u].lookup_disable)
		2164	continue;
		2165	robj = track->textures[u].robj;
		2166	if (robj == NULL) {
		2167	DRM_ERROR("No texture bound to unit %u\n", u);
		2168	return -EINVAL;
		2169	}
		2170	size = 0;
		2171	for (i = 0; i <= track->textures[u].num_levels; i++) {
		2172	if (track->textures[u].use_pitch) {
		2173	if (rdev->family < CHIP_R300)
		2174	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		2175	else
		2176	w = track->textures[u].pitch / (1 << i);
		2177	} else {
		2178	w = track->textures[u].width;
		2179	if (rdev->family >= CHIP_RV515)
		2180	w \|= track->textures[u].width_11;
		2181	w = w / (1 << i);
		2182	if (track->textures[u].roundup_w)
		2183	w = roundup_pow_of_two(w);
		2184	}
		2185	h = track->textures[u].height;
		2186	if (rdev->family >= CHIP_RV515)
		2187	h \|= track->textures[u].height_11;
		2188	h = h / (1 << i);
		2189	if (track->textures[u].roundup_h)
		2190	h = roundup_pow_of_two(h);
		2191	if (track->textures[u].tex_coord_type == 1) {
		2192	d = (1 << track->textures[u].txdepth) / (1 << i);
		2193	if (!d)
		2194	d = 1;
		2195	} else {
		2196	d = 1;
		2197	}
		2198	if (track->textures[u].compress_format) {
		2199
		2200	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		2201	/* compressed textures are block based */
		2202	} else
		2203	size += w * h * d;
		2204	}
		2205	size *= track->textures[u].cpp;
		2206
		2207	switch (track->textures[u].tex_coord_type) {
		2208	case 0:
		2209	case 1:
		2210	break;
		2211	case 2:
		2212	if (track->separate_cube) {
		2213	ret = r100_cs_track_cube(rdev, track, u);
		2214	if (ret)
		2215	return ret;
		2216	} else
		2217	size *= 6;
		2218	break;
		2219	default:
		2220	DRM_ERROR("Invalid texture coordinate type %u for unit "
		2221	"%u\n", track->textures[u].tex_coord_type, u);
		2222	return -EINVAL;
		2223	}
		2224	if (size > radeon_bo_size(robj)) {
		2225	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		2226	"%lu\n", u, size, radeon_bo_size(robj));
		2227	r100_cs_track_texture_print(&track->textures[u]);
		2228	return -EINVAL;
		2229	}
1117	serge	2230	}
2997	Serge	2231	return 0;
		2232	}
		2233
		2234	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		2235	{
		2236	unsigned i;
		2237	unsigned long size;
		2238	unsigned prim_walk;
		2239	unsigned nverts;
		2240	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		2241
		2242	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		2243	!track->blend_read_enable)
		2244	num_cb = 0;
		2245
		2246	for (i = 0; i < num_cb; i++) {
		2247	if (track->cb[i].robj == NULL) {
		2248	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		2249	return -EINVAL;
1117	serge	2250	}
2997	Serge	2251	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		2252	size += track->cb[i].offset;
		2253	if (size > radeon_bo_size(track->cb[i].robj)) {
		2254	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		2255	"(need %lu have %lu) !\n", i, size,
		2256	radeon_bo_size(track->cb[i].robj));
		2257	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		2258	i, track->cb[i].pitch, track->cb[i].cpp,
		2259	track->cb[i].offset, track->maxy);
		2260	return -EINVAL;
		2261	}
1117	serge	2262	}
2997	Serge	2263	track->cb_dirty = false;
		2264
		2265	if (track->zb_dirty && track->z_enabled) {
		2266	if (track->zb.robj == NULL) {
		2267	DRM_ERROR("[drm] No buffer for z buffer !\n");
		2268	return -EINVAL;
		2269	}
		2270	size = track->zb.pitch * track->zb.cpp * track->maxy;
		2271	size += track->zb.offset;
		2272	if (size > radeon_bo_size(track->zb.robj)) {
		2273	DRM_ERROR("[drm] Buffer too small for z buffer "
		2274	"(need %lu have %lu) !\n", size,
		2275	radeon_bo_size(track->zb.robj));
		2276	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		2277	track->zb.pitch, track->zb.cpp,
		2278	track->zb.offset, track->maxy);
		2279	return -EINVAL;
		2280	}
		2281	}
		2282	track->zb_dirty = false;
		2283
		2284	if (track->aa_dirty && track->aaresolve) {
		2285	if (track->aa.robj == NULL) {
		2286	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		2287	return -EINVAL;
		2288	}
		2289	/* I believe the format comes from colorbuffer0. */
		2290	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		2291	size += track->aa.offset;
		2292	if (size > radeon_bo_size(track->aa.robj)) {
		2293	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		2294	"(need %lu have %lu) !\n", i, size,
		2295	radeon_bo_size(track->aa.robj));
		2296	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		2297	i, track->aa.pitch, track->cb[0].cpp,
		2298	track->aa.offset, track->maxy);
		2299	return -EINVAL;
		2300	}
		2301	}
		2302	track->aa_dirty = false;
		2303
		2304	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		2305	if (track->vap_vf_cntl & (1 << 14)) {
		2306	nverts = track->vap_alt_nverts;
		2307	} else {
		2308	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		2309	}
		2310	switch (prim_walk) {
		2311	case 1:
		2312	for (i = 0; i < track->num_arrays; i++) {
		2313	size = track->arrays[i].esize * track->max_indx * 4;
		2314	if (track->arrays[i].robj == NULL) {
		2315	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2316	"bound\n", prim_walk, i);
		2317	return -EINVAL;
		2318	}
		2319	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2320	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2321	"need %lu dwords have %lu dwords\n",
		2322	prim_walk, i, size >> 2,
		2323	radeon_bo_size(track->arrays[i].robj)
		2324	>> 2);
		2325	DRM_ERROR("Max indices %u\n", track->max_indx);
		2326	return -EINVAL;
		2327	}
		2328	}
		2329	break;
		2330	case 2:
		2331	for (i = 0; i < track->num_arrays; i++) {
		2332	size = track->arrays[i].esize * (nverts - 1) * 4;
		2333	if (track->arrays[i].robj == NULL) {
		2334	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		2335	"bound\n", prim_walk, i);
		2336	return -EINVAL;
		2337	}
		2338	if (size > radeon_bo_size(track->arrays[i].robj)) {
		2339	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		2340	"need %lu dwords have %lu dwords\n",
		2341	prim_walk, i, size >> 2,
		2342	radeon_bo_size(track->arrays[i].robj)
		2343	>> 2);
		2344	return -EINVAL;
		2345	}
		2346	}
		2347	break;
		2348	case 3:
		2349	size = track->vtx_size * nverts;
		2350	if (size != track->immd_dwords) {
		2351	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		2352	track->immd_dwords, size);
		2353	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		2354	nverts, track->vtx_size);
		2355	return -EINVAL;
		2356	}
		2357	break;
		2358	default:
		2359	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		2360	prim_walk);
		2361	return -EINVAL;
		2362	}
		2363
		2364	if (track->tex_dirty) {
		2365	track->tex_dirty = false;
		2366	return r100_cs_track_texture_check(rdev, track);
		2367	}
		2368	return 0;
1117	serge	2369	}
		2370
2997	Serge	2371	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
1117	serge	2372	{
2997	Serge	2373	unsigned i, face;
1117	serge	2374
2997	Serge	2375	track->cb_dirty = true;
		2376	track->zb_dirty = true;
		2377	track->tex_dirty = true;
		2378	track->aa_dirty = true;
1117	serge	2379
2997	Serge	2380	if (rdev->family < CHIP_R300) {
		2381	track->num_cb = 1;
		2382	if (rdev->family <= CHIP_RS200)
		2383	track->num_texture = 3;
		2384	else
		2385	track->num_texture = 6;
		2386	track->maxy = 2048;
		2387	track->separate_cube = 1;
		2388	} else {
		2389	track->num_cb = 4;
		2390	track->num_texture = 16;
		2391	track->maxy = 4096;
		2392	track->separate_cube = 0;
		2393	track->aaresolve = false;
		2394	track->aa.robj = NULL;
		2395	}
		2396
		2397	for (i = 0; i < track->num_cb; i++) {
		2398	track->cb[i].robj = NULL;
		2399	track->cb[i].pitch = 8192;
		2400	track->cb[i].cpp = 16;
		2401	track->cb[i].offset = 0;
		2402	}
		2403	track->z_enabled = true;
		2404	track->zb.robj = NULL;
		2405	track->zb.pitch = 8192;
		2406	track->zb.cpp = 4;
		2407	track->zb.offset = 0;
		2408	track->vtx_size = 0x7F;
		2409	track->immd_dwords = 0xFFFFFFFFUL;
		2410	track->num_arrays = 11;
		2411	track->max_indx = 0x00FFFFFFUL;
		2412	for (i = 0; i < track->num_arrays; i++) {
		2413	track->arrays[i].robj = NULL;
		2414	track->arrays[i].esize = 0x7F;
		2415	}
		2416	for (i = 0; i < track->num_texture; i++) {
		2417	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		2418	track->textures[i].pitch = 16536;
		2419	track->textures[i].width = 16536;
		2420	track->textures[i].height = 16536;
		2421	track->textures[i].width_11 = 1 << 11;
		2422	track->textures[i].height_11 = 1 << 11;
		2423	track->textures[i].num_levels = 12;
		2424	if (rdev->family <= CHIP_RS200) {
		2425	track->textures[i].tex_coord_type = 0;
		2426	track->textures[i].txdepth = 0;
		2427	} else {
		2428	track->textures[i].txdepth = 16;
		2429	track->textures[i].tex_coord_type = 1;
1117	serge	2430	}
2997	Serge	2431	track->textures[i].cpp = 64;
		2432	track->textures[i].robj = NULL;
		2433	/* CS IB emission code makes sure texture unit are disabled */
		2434	track->textures[i].enabled = false;
		2435	track->textures[i].lookup_disable = false;
		2436	track->textures[i].roundup_w = true;
		2437	track->textures[i].roundup_h = true;
		2438	if (track->separate_cube)
		2439	for (face = 0; face < 5; face++) {
		2440	track->textures[i].cube_info[face].robj = NULL;
		2441	track->textures[i].cube_info[face].width = 16536;
		2442	track->textures[i].cube_info[face].height = 16536;
		2443	track->textures[i].cube_info[face].offset = 0;
		2444	}
1117	serge	2445	}
		2446	}
		2447
2997	Serge	2448	/*
		2449	* Global GPU functions
		2450	*/
		2451	static void r100_errata(struct radeon_device *rdev)
1117	serge	2452	{
2997	Serge	2453	rdev->pll_errata = 0;
		2454
		2455	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		2456	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		2457	}
		2458
		2459	if (rdev->family == CHIP_RV100 \|\|
		2460	rdev->family == CHIP_RS100 \|\|
		2461	rdev->family == CHIP_RS200) {
		2462	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		2463	}
		2464	}
		2465
		2466	static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		2467	{
1117	serge	2468	unsigned i;
		2469	uint32_t tmp;
		2470
		2471	for (i = 0; i < rdev->usec_timeout; i++) {
		2472	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		2473	if (tmp >= n) {
		2474	return 0;
		2475	}
		2476	DRM_UDELAY(1);
		2477	}
		2478	return -1;
		2479	}
		2480
		2481	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		2482	{
		2483	unsigned i;
		2484	uint32_t tmp;
		2485
		2486	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		2487	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		2488	" Bad things might happen.\n");
		2489	}
		2490	for (i = 0; i < rdev->usec_timeout; i++) {
		2491	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	2492	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	2493	return 0;
		2494	}
		2495	DRM_UDELAY(1);
		2496	}
		2497	return -1;
		2498	}
		2499
		2500	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		2501	{
		2502	unsigned i;
		2503	uint32_t tmp;
		2504
		2505	for (i = 0; i < rdev->usec_timeout; i++) {
		2506	/* read MC_STATUS */
1430	serge	2507	tmp = RREG32(RADEON_MC_STATUS);
		2508	if (tmp & RADEON_MC_IDLE) {
1117	serge	2509	return 0;
		2510	}
		2511	DRM_UDELAY(1);
		2512	}
		2513	return -1;
		2514	}
		2515
2997	Serge	2516	bool r100_gpu_is_lockup(struct radeon_device rdev, struct radeon_ring ring)
1117	serge	2517	{
1963	serge	2518	u32 rbbm_status;
1117	serge	2519
1963	serge	2520	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		2521	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
5078	serge	2522	radeon_ring_lockup_update(rdev, ring);
1963	serge	2523	return false;
6104	serge	2524	}
2997	Serge	2525	return radeon_ring_test_lockup(rdev, ring);
1117	serge	2526	}
		2527
2997	Serge	2528	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		2529	void r100_enable_bm(struct radeon_device *rdev)
		2530	{
		2531	uint32_t tmp;
		2532	/* Enable bus mastering */
		2533	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		2534	WREG32(RADEON_BUS_CNTL, tmp);
		2535	}
		2536
1963	serge	2537	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	2538	{
1963	serge	2539	u32 tmp;
1117	serge	2540
1963	serge	2541	/* disable bus mastering */
		2542	tmp = RREG32(R_000030_BUS_CNTL);
		2543	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		2544	mdelay(1);
		2545	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		2546	mdelay(1);
		2547	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		2548	tmp = RREG32(RADEON_BUS_CNTL);
		2549	mdelay(1);
2997	Serge	2550	pci_clear_master(rdev->pdev);
1963	serge	2551	mdelay(1);
		2552	}
		2553
		2554	int r100_asic_reset(struct radeon_device *rdev)
		2555	{
		2556	struct r100_mc_save save;
		2557	u32 status, tmp;
		2558	int ret = 0;
		2559
		2560	status = RREG32(R_000E40_RBBM_STATUS);
		2561	if (!G_000E40_GUI_ACTIVE(status)) {
		2562	return 0;
1117	serge	2563	}
1963	serge	2564	r100_mc_stop(rdev, &save);
		2565	status = RREG32(R_000E40_RBBM_STATUS);
		2566	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2567	/* stop CP */
		2568	WREG32(RADEON_CP_CSQ_CNTL, 0);
		2569	tmp = RREG32(RADEON_CP_RB_CNTL);
		2570	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		2571	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		2572	WREG32(RADEON_CP_RB_WPTR, 0);
		2573	WREG32(RADEON_CP_RB_CNTL, tmp);
		2574	/* save PCI state */
		2575	// pci_save_state(rdev->pdev);
		2576	/* disable bus mastering */
		2577	r100_bm_disable(rdev);
		2578	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		2579	S_0000F0_SOFT_RESET_RE(1) \|
		2580	S_0000F0_SOFT_RESET_PP(1) \|
		2581	S_0000F0_SOFT_RESET_RB(1));
		2582	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2583	mdelay(500);
		2584	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2585	mdelay(1);
		2586	status = RREG32(R_000E40_RBBM_STATUS);
		2587	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	2588	/* reset CP */
1963	serge	2589	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		2590	RREG32(R_0000F0_RBBM_SOFT_RESET);
		2591	mdelay(500);
		2592	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		2593	mdelay(1);
		2594	status = RREG32(R_000E40_RBBM_STATUS);
		2595	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		2596	/* restore PCI & busmastering */
		2597	// pci_restore_state(rdev->pdev);
		2598	r100_enable_bm(rdev);
1117	serge	2599	/* Check if GPU is idle */
1963	serge	2600	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		2601	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		2602	dev_err(rdev->dev, "failed to reset GPU\n");
		2603	ret = -1;
		2604	} else
		2605	dev_info(rdev->dev, "GPU reset succeed\n");
		2606	r100_mc_resume(rdev, &save);
		2607	return ret;
1117	serge	2608	}
		2609
1321	serge	2610	void r100_set_common_regs(struct radeon_device *rdev)
		2611	{
1430	serge	2612	struct drm_device *dev = rdev->ddev;
		2613	bool force_dac2 = false;
1963	serge	2614	u32 tmp;
1430	serge	2615
1321	serge	2616	/* set these so they don't interfere with anything */
		2617	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		2618	WREG32(RADEON_SUBPIC_CNTL, 0);
		2619	WREG32(RADEON_VIPH_CONTROL, 0);
		2620	WREG32(RADEON_I2C_CNTL_1, 0);
		2621	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		2622	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		2623	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	2624
		2625	/* always set up dac2 on rn50 and some rv100 as lots
		2626	* of servers seem to wire it up to a VGA port but
		2627	* don't report it in the bios connector
		2628	* table.
		2629	*/
		2630	switch (dev->pdev->device) {
		2631	/* RN50 */
		2632	case 0x515e:
		2633	case 0x5969:
		2634	force_dac2 = true;
		2635	break;
		2636	/* RV100*/
		2637	case 0x5159:
		2638	case 0x515a:
		2639	/* DELL triple head servers */
		2640	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		2641	((dev->pdev->subsystem_device == 0x016c) \|\|
		2642	(dev->pdev->subsystem_device == 0x016d) \|\|
		2643	(dev->pdev->subsystem_device == 0x016e) \|\|
		2644	(dev->pdev->subsystem_device == 0x016f) \|\|
		2645	(dev->pdev->subsystem_device == 0x0170) \|\|
		2646	(dev->pdev->subsystem_device == 0x017d) \|\|
		2647	(dev->pdev->subsystem_device == 0x017e) \|\|
		2648	(dev->pdev->subsystem_device == 0x0183) \|\|
		2649	(dev->pdev->subsystem_device == 0x018a) \|\|
		2650	(dev->pdev->subsystem_device == 0x019a)))
		2651	force_dac2 = true;
		2652	break;
		2653	}
		2654
		2655	if (force_dac2) {
		2656	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		2657	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		2658	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		2659
		2660	/* For CRT on DAC2, don't turn it on if BIOS didn't
		2661	enable it, even it's detected.
		2662	*/
		2663
		2664	/* force it to crtc0 */
		2665	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		2666	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		2667	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		2668
		2669	/* set up the TV DAC */
		2670	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		2671	RADEON_TV_DAC_STD_MASK \|
		2672	RADEON_TV_DAC_RDACPD \|
		2673	RADEON_TV_DAC_GDACPD \|
		2674	RADEON_TV_DAC_BDACPD \|
		2675	RADEON_TV_DAC_BGADJ_MASK \|
		2676	RADEON_TV_DAC_DACADJ_MASK);
		2677	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		2678	RADEON_TV_DAC_NHOLD \|
		2679	RADEON_TV_DAC_STD_PS2 \|
		2680	(0x58 << 16));
		2681
		2682	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		2683	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		2684	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		2685	}
1963	serge	2686
		2687	/* switch PM block to ACPI mode */
		2688	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		2689	tmp &= ~RADEON_PM_MODE_SEL;
		2690	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		2691
1321	serge	2692	}
1117	serge	2693
		2694	/*
		2695	* VRAM info
		2696	*/
		2697	static void r100_vram_get_type(struct radeon_device *rdev)
		2698	{
		2699	uint32_t tmp;
		2700
		2701	rdev->mc.vram_is_ddr = false;
		2702	if (rdev->flags & RADEON_IS_IGP)
		2703	rdev->mc.vram_is_ddr = true;
		2704	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		2705	rdev->mc.vram_is_ddr = true;
		2706	if ((rdev->family == CHIP_RV100) \|\|
		2707	(rdev->family == CHIP_RS100) \|\|
		2708	(rdev->family == CHIP_RS200)) {
		2709	tmp = RREG32(RADEON_MEM_CNTL);
		2710	if (tmp & RV100_HALF_MODE) {
		2711	rdev->mc.vram_width = 32;
		2712	} else {
		2713	rdev->mc.vram_width = 64;
		2714	}
		2715	if (rdev->flags & RADEON_SINGLE_CRTC) {
		2716	rdev->mc.vram_width /= 4;
		2717	rdev->mc.vram_is_ddr = true;
		2718	}
		2719	} else if (rdev->family <= CHIP_RV280) {
		2720	tmp = RREG32(RADEON_MEM_CNTL);
		2721	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		2722	rdev->mc.vram_width = 128;
		2723	} else {
		2724	rdev->mc.vram_width = 64;
		2725	}
		2726	} else {
		2727	/* newer IGPs */
		2728	rdev->mc.vram_width = 128;
		2729	}
		2730	}
		2731
1179	serge	2732	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	2733	{
1179	serge	2734	u32 aper_size;
		2735	u8 byte;
1117	serge	2736
1179	serge	2737	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		2738
		2739	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		2740	* that is has the 2nd generation multifunction PCI interface
		2741	*/
		2742	if (rdev->family == CHIP_RV280 \|\|
		2743	rdev->family >= CHIP_RV350) {
		2744	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		2745	~RADEON_HDP_APER_CNTL);
		2746	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		2747	return aper_size * 2;
		2748	}
		2749
		2750	/* Older cards have all sorts of funny issues to deal with. First
		2751	* check if it's a multifunction card by reading the PCI config
		2752	* header type... Limit those to one aperture size
		2753	*/
		2754	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		2755	// if (byte & 0x80) {
		2756	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		2757	// DRM_INFO("Limiting VRAM to one aperture\n");
		2758	// return aper_size;
		2759	// }
		2760
		2761	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		2762	* have set it up. We don't write this as it's broken on some ASICs but
		2763	* we expect the BIOS to have done the right thing (might be too optimistic...)
		2764	*/
		2765	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		2766	return aper_size * 2;
		2767	return aper_size;
		2768	}
		2769
		2770	void r100_vram_init_sizes(struct radeon_device *rdev)
		2771	{
		2772	u64 config_aper_size;
		2773
1430	serge	2774	/* work out accessible VRAM */
1963	serge	2775	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		2776	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	2777	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		2778	/* FIXME we don't use the second aperture yet when we could use it */
		2779	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		2780	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	2781	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	2782	if (rdev->flags & RADEON_IS_IGP) {
		2783	uint32_t tom;
		2784	/* read NB_TOM to get the amount of ram stolen for the GPU */
		2785	tom = RREG32(RADEON_NB_TOM);
1179	serge	2786	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		2787	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		2788	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2789	} else {
1179	serge	2790	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	2791	/* Some production boards of m6 will report 0
		2792	* if it's 8 MB
		2793	*/
1179	serge	2794	if (rdev->mc.real_vram_size == 0) {
		2795	rdev->mc.real_vram_size = 8192 * 1024;
		2796	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	2797	}
6104	serge	2798	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	2799	* Novell bug 204882 + along with lots of ubuntu ones
		2800	*/
1963	serge	2801	if (rdev->mc.aper_size > config_aper_size)
		2802	config_aper_size = rdev->mc.aper_size;
		2803
1179	serge	2804	if (config_aper_size > rdev->mc.real_vram_size)
		2805	rdev->mc.mc_vram_size = config_aper_size;
		2806	else
		2807	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2808	}
		2809	}
		2810
1179	serge	2811	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		2812	{
		2813	uint32_t temp;
		2814
		2815	temp = RREG32(RADEON_CONFIG_CNTL);
		2816	if (state == false) {
1963	serge	2817	temp &= ~RADEON_CFG_VGA_RAM_EN;
		2818	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	2819	} else {
1963	serge	2820	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	2821	}
		2822	WREG32(RADEON_CONFIG_CNTL, temp);
		2823	}
		2824
2997	Serge	2825	static void r100_mc_init(struct radeon_device *rdev)
1179	serge	2826	{
1430	serge	2827	u64 base;
		2828
1179	serge	2829	r100_vram_get_type(rdev);
		2830	r100_vram_init_sizes(rdev);
1430	serge	2831	base = rdev->mc.aper_base;
		2832	if (rdev->flags & RADEON_IS_IGP)
		2833	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		2834	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	2835	rdev->mc.gtt_base_align = 0;
1430	serge	2836	if (!(rdev->flags & RADEON_IS_AGP))
		2837	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	2838	radeon_update_bandwidth_info(rdev);
1179	serge	2839	}
		2840
		2841
1117	serge	2842	/*
		2843	* Indirect registers accessor
		2844	*/
		2845	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2846	{
1963	serge	2847	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
6104	serge	2848	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2849	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2850	}
1117	serge	2851	}
		2852
		2853	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2854	{
		2855	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2856	* or the chip could hang on a subsequent access
		2857	*/
		2858	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2997	Serge	2859	mdelay(5);
1117	serge	2860	}
		2861
		2862	/* This function is required to workaround a hardware bug in some (all?)
		2863	* revisions of the R300. This workaround should be called after every
		2864	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2865	* may not be correct.
		2866	*/
		2867	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2868	uint32_t save, tmp;
		2869
		2870	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2871	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2872	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2873	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2874	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2875	}
		2876	}
		2877
		2878	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2879	{
5078	serge	2880	unsigned long flags;
1117	serge	2881	uint32_t data;
		2882
5078	serge	2883	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
1117	serge	2884	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2885	r100_pll_errata_after_index(rdev);
		2886	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2887	r100_pll_errata_after_data(rdev);
5078	serge	2888	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
1117	serge	2889	return data;
		2890	}
		2891
		2892	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2893	{
5078	serge	2894	unsigned long flags;
		2895
		2896	spin_lock_irqsave(&rdev->pll_idx_lock, flags);
1117	serge	2897	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2898	r100_pll_errata_after_index(rdev);
		2899	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2900	r100_pll_errata_after_data(rdev);
5078	serge	2901	spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
1117	serge	2902	}
		2903
2997	Serge	2904	static void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2905	{
1179	serge	2906	if (ASIC_IS_RN50(rdev)) {
		2907	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2908	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2909	} else if (rdev->family < CHIP_R200) {
		2910	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2911	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2912	} else {
1221	serge	2913	r200_set_safe_registers(rdev);
1117	serge	2914	}
		2915	}
		2916
1129	serge	2917	/*
		2918	* Debugfs info
		2919	*/
		2920	#if defined(CONFIG_DEBUG_FS)
		2921	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2922	{
		2923	struct drm_info_node node = (struct drm_info_node ) m->private;
		2924	struct drm_device *dev = node->minor->dev;
		2925	struct radeon_device *rdev = dev->dev_private;
		2926	uint32_t reg, value;
		2927	unsigned i;
		2928
		2929	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2930	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2931	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2932	for (i = 0; i < 64; i++) {
		2933	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2934	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2935	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2936	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2937	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2938	}
		2939	return 0;
		2940	}
		2941
		2942	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2943	{
		2944	struct drm_info_node node = (struct drm_info_node ) m->private;
		2945	struct drm_device *dev = node->minor->dev;
		2946	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2947	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1129	serge	2948	uint32_t rdp, wdp;
		2949	unsigned count, i, j;
		2950
2997	Serge	2951	radeon_ring_free_size(rdev, ring);
1129	serge	2952	rdp = RREG32(RADEON_CP_RB_RPTR);
		2953	wdp = RREG32(RADEON_CP_RB_WPTR);
2997	Serge	2954	count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
1129	serge	2955	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2956	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2957	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2997	Serge	2958	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
1129	serge	2959	seq_printf(m, "%u dwords in ring\n", count);
5078	serge	2960	if (ring->ready) {
6104	serge	2961	for (j = 0; j <= count; j++) {
		2962	i = (rdp + j) & ring->ptr_mask;
		2963	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
		2964	}
1129	serge	2965	}
		2966	return 0;
		2967	}
		2968
		2969
		2970	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2971	{
		2972	struct drm_info_node node = (struct drm_info_node ) m->private;
		2973	struct drm_device *dev = node->minor->dev;
		2974	struct radeon_device *rdev = dev->dev_private;
		2975	uint32_t csq_stat, csq2_stat, tmp;
		2976	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2977	unsigned i;
		2978
		2979	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2980	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2981	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2982	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2983	r_rptr = (csq_stat >> 0) & 0x3ff;
		2984	r_wptr = (csq_stat >> 10) & 0x3ff;
		2985	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2986	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2987	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2988	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2989	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2990	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2991	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2992	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2993	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2994	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2995	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2996	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2997	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2998	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2999	seq_printf(m, "Ring fifo:\n");
		3000	for (i = 0; i < 256; i++) {
		3001	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		3002	tmp = RREG32(RADEON_CP_CSQ_DATA);
		3003	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		3004	}
		3005	seq_printf(m, "Indirect1 fifo:\n");
		3006	for (i = 256; i <= 512; i++) {
		3007	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		3008	tmp = RREG32(RADEON_CP_CSQ_DATA);
		3009	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		3010	}
		3011	seq_printf(m, "Indirect2 fifo:\n");
		3012	for (i = 640; i < ib1_wptr; i++) {
		3013	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		3014	tmp = RREG32(RADEON_CP_CSQ_DATA);
		3015	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		3016	}
		3017	return 0;
		3018	}
		3019
		3020	static int r100_debugfs_mc_info(struct seq_file m, void data)
		3021	{
		3022	struct drm_info_node node = (struct drm_info_node ) m->private;
		3023	struct drm_device *dev = node->minor->dev;
		3024	struct radeon_device *rdev = dev->dev_private;
		3025	uint32_t tmp;
		3026
		3027	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		3028	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		3029	tmp = RREG32(RADEON_MC_FB_LOCATION);
		3030	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		3031	tmp = RREG32(RADEON_BUS_CNTL);
		3032	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		3033	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		3034	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		3035	tmp = RREG32(RADEON_AGP_BASE);
		3036	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		3037	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		3038	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		3039	tmp = RREG32(0x01D0);
		3040	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		3041	tmp = RREG32(RADEON_AIC_LO_ADDR);
		3042	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		3043	tmp = RREG32(RADEON_AIC_HI_ADDR);
		3044	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		3045	tmp = RREG32(0x01E4);
		3046	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		3047	return 0;
		3048	}
		3049
		3050	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		3051	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		3052	};
		3053
		3054	static struct drm_info_list r100_debugfs_cp_list[] = {
		3055	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		3056	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		3057	};
		3058
		3059	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		3060	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		3061	};
		3062	#endif
		3063
		3064	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		3065	{
		3066	#if defined(CONFIG_DEBUG_FS)
		3067	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		3068	#else
		3069	return 0;
		3070	#endif
		3071	}
		3072
		3073	int r100_debugfs_cp_init(struct radeon_device *rdev)
		3074	{
		3075	#if defined(CONFIG_DEBUG_FS)
		3076	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		3077	#else
		3078	return 0;
		3079	#endif
		3080	}
		3081
		3082	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		3083	{
		3084	#if defined(CONFIG_DEBUG_FS)
		3085	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		3086	#else
		3087	return 0;
		3088	#endif
		3089	}
1179	serge	3090
		3091	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		3092	uint32_t tiling_flags, uint32_t pitch,
		3093	uint32_t offset, uint32_t obj_size)
		3094	{
		3095	int surf_index = reg * 16;
		3096	int flags = 0;
		3097
		3098	if (rdev->family <= CHIP_RS200) {
		3099	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3100	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3101	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		3102	if (tiling_flags & RADEON_TILING_MACRO)
		3103	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
5078	serge	3104	/* setting pitch to 0 disables tiling */
		3105	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		3106	== 0)
		3107	pitch = 0;
1179	serge	3108	} else if (rdev->family <= CHIP_RV280) {
		3109	if (tiling_flags & (RADEON_TILING_MACRO))
		3110	flags \|= R200_SURF_TILE_COLOR_MACRO;
		3111	if (tiling_flags & RADEON_TILING_MICRO)
		3112	flags \|= R200_SURF_TILE_COLOR_MICRO;
		3113	} else {
		3114	if (tiling_flags & RADEON_TILING_MACRO)
		3115	flags \|= R300_SURF_TILE_MACRO;
		3116	if (tiling_flags & RADEON_TILING_MICRO)
		3117	flags \|= R300_SURF_TILE_MICRO;
		3118	}
		3119
		3120	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		3121	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		3122	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		3123	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		3124
1963	serge	3125	/* r100/r200 divide by 16 */
		3126	if (rdev->family < CHIP_R300)
		3127	flags \|= pitch / 16;
		3128	else
		3129	flags \|= pitch / 8;
		3130
		3131
		3132	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	3133	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		3134	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		3135	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		3136	return 0;
		3137	}
		3138
		3139	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		3140	{
		3141	int surf_index = reg * 16;
		3142	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		3143	}
		3144
		3145	void r100_bandwidth_update(struct radeon_device *rdev)
		3146	{
		3147	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		3148	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
6938	serge	3149	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
		3150	fixed20_12 crit_point_ff = {0};
1179	serge	3151	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		3152	fixed20_12 memtcas_ff[8] = {
1963	serge	3153	dfixed_init(1),
		3154	dfixed_init(2),
		3155	dfixed_init(3),
		3156	dfixed_init(0),
		3157	dfixed_init_half(1),
		3158	dfixed_init_half(2),
		3159	dfixed_init(0),
1179	serge	3160	};
		3161	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	3162	dfixed_init(0),
		3163	dfixed_init(1),
		3164	dfixed_init(2),
		3165	dfixed_init(3),
		3166	dfixed_init(0),
		3167	dfixed_init_half(1),
		3168	dfixed_init_half(2),
		3169	dfixed_init_half(3),
1179	serge	3170	};
		3171	fixed20_12 memtcas2_ff[8] = {
1963	serge	3172	dfixed_init(0),
		3173	dfixed_init(1),
		3174	dfixed_init(2),
		3175	dfixed_init(3),
		3176	dfixed_init(4),
		3177	dfixed_init(5),
		3178	dfixed_init(6),
		3179	dfixed_init(7),
1179	serge	3180	};
		3181	fixed20_12 memtrbs[8] = {
1963	serge	3182	dfixed_init(1),
		3183	dfixed_init_half(1),
		3184	dfixed_init(2),
		3185	dfixed_init_half(2),
		3186	dfixed_init(3),
		3187	dfixed_init_half(3),
		3188	dfixed_init(4),
		3189	dfixed_init_half(4)
1179	serge	3190	};
		3191	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	3192	dfixed_init(4),
		3193	dfixed_init(5),
		3194	dfixed_init(6),
		3195	dfixed_init(7),
		3196	dfixed_init(8),
		3197	dfixed_init(9),
		3198	dfixed_init(10),
		3199	dfixed_init(11)
1179	serge	3200	};
		3201	fixed20_12 min_mem_eff;
		3202	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		3203	fixed20_12 cur_latency_mclk, cur_latency_sclk;
6938	serge	3204	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
1179	serge	3205	disp_drain_rate2, read_return_rate;
		3206	fixed20_12 time_disp1_drop_priority;
		3207	int c;
		3208	int cur_size = 16; /* in octawords */
		3209	int critical_point = 0, critical_point2;
		3210	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		3211	int stop_req, max_stop_req;
		3212	struct drm_display_mode *mode1 = NULL;
		3213	struct drm_display_mode *mode2 = NULL;
		3214	uint32_t pixel_bytes1 = 0;
		3215	uint32_t pixel_bytes2 = 0;
		3216
6104	serge	3217	/* Guess line buffer size to be 8192 pixels */
		3218	u32 lb_size = 8192;
		3219
5271	serge	3220	if (!rdev->mode_info.mode_config_initialized)
		3221	return;
		3222
1963	serge	3223	radeon_update_display_priority(rdev);
		3224
1179	serge	3225	if (rdev->mode_info.crtcs[0]->base.enabled) {
		3226	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
5078	serge	3227	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
1179	serge	3228	}
1221	serge	3229	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
6104	serge	3230	if (rdev->mode_info.crtcs[1]->base.enabled) {
		3231	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
5078	serge	3232	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
6104	serge	3233	}
1179	serge	3234	}
		3235
1963	serge	3236	min_mem_eff.full = dfixed_const_8(0);
1179	serge	3237	/* get modes */
		3238	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		3239	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		3240	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		3241	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		3242	/* check crtc enables */
		3243	if (mode2)
		3244	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		3245	if (mode1)
		3246	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		3247	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		3248	}
		3249
		3250	/*
		3251	* determine is there is enough bw for current mode
		3252	*/
1963	serge	3253	sclk_ff = rdev->pm.sclk;
		3254	mclk_ff = rdev->pm.mclk;
1179	serge	3255
		3256	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	3257	temp_ff.full = dfixed_const(temp);
		3258	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3259
		3260	pix_clk.full = 0;
		3261	pix_clk2.full = 0;
		3262	peak_disp_bw.full = 0;
		3263	if (mode1) {
1963	serge	3264	temp_ff.full = dfixed_const(1000);
		3265	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		3266	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		3267	temp_ff.full = dfixed_const(pixel_bytes1);
		3268	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	3269	}
		3270	if (mode2) {
1963	serge	3271	temp_ff.full = dfixed_const(1000);
		3272	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		3273	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		3274	temp_ff.full = dfixed_const(pixel_bytes2);
		3275	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	3276	}
		3277
1963	serge	3278	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	3279	if (peak_disp_bw.full >= mem_bw.full) {
		3280	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		3281	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		3282	}
		3283
		3284	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		3285	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		3286	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		3287	mem_trcd = ((temp >> 2) & 0x3) + 1;
		3288	mem_trp = ((temp & 0x3)) + 1;
		3289	mem_tras = ((temp & 0x70) >> 4) + 1;
		3290	} else if (rdev->family == CHIP_R300 \|\|
		3291	rdev->family == CHIP_R350) { /* r300, r350 */
		3292	mem_trcd = (temp & 0x7) + 1;
		3293	mem_trp = ((temp >> 8) & 0x7) + 1;
		3294	mem_tras = ((temp >> 11) & 0xf) + 4;
		3295	} else if (rdev->family == CHIP_RV350 \|\|
		3296	rdev->family <= CHIP_RV380) {
		3297	/* rv3x0 */
		3298	mem_trcd = (temp & 0x7) + 3;
		3299	mem_trp = ((temp >> 8) & 0x7) + 3;
		3300	mem_tras = ((temp >> 11) & 0xf) + 6;
		3301	} else if (rdev->family == CHIP_R420 \|\|
		3302	rdev->family == CHIP_R423 \|\|
		3303	rdev->family == CHIP_RV410) {
		3304	/* r4xx */
		3305	mem_trcd = (temp & 0xf) + 3;
		3306	if (mem_trcd > 15)
		3307	mem_trcd = 15;
		3308	mem_trp = ((temp >> 8) & 0xf) + 3;
		3309	if (mem_trp > 15)
		3310	mem_trp = 15;
		3311	mem_tras = ((temp >> 12) & 0x1f) + 6;
		3312	if (mem_tras > 31)
		3313	mem_tras = 31;
		3314	} else { /* RV200, R200 */
		3315	mem_trcd = (temp & 0x7) + 1;
		3316	mem_trp = ((temp >> 8) & 0x7) + 1;
		3317	mem_tras = ((temp >> 12) & 0xf) + 4;
		3318	}
		3319	/* convert to FF */
1963	serge	3320	trcd_ff.full = dfixed_const(mem_trcd);
		3321	trp_ff.full = dfixed_const(mem_trp);
		3322	tras_ff.full = dfixed_const(mem_tras);
1179	serge	3323
		3324	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		3325	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3326	data = (temp & (7 << 20)) >> 20;
		3327	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		3328	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		3329	tcas_ff = memtcas_rs480_ff[data];
		3330	else
		3331	tcas_ff = memtcas_ff[data];
		3332	} else
		3333	tcas_ff = memtcas2_ff[data];
		3334
		3335	if (rdev->family == CHIP_RS400 \|\|
		3336	rdev->family == CHIP_RS480) {
		3337	/* extra cas latency stored in bits 23-25 0-4 clocks */
		3338	data = (temp >> 23) & 0x7;
		3339	if (data < 5)
1963	serge	3340	tcas_ff.full += dfixed_const(data);
1179	serge	3341	}
		3342
		3343	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		3344	/* on the R300, Tcas is included in Trbs.
		3345	*/
		3346	temp = RREG32(RADEON_MEM_CNTL);
		3347	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		3348	if (data == 1) {
		3349	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		3350	temp = RREG32(R300_MC_IND_INDEX);
		3351	temp &= ~R300_MC_IND_ADDR_MASK;
		3352	temp \|= R300_MC_READ_CNTL_CD_mcind;
		3353	WREG32(R300_MC_IND_INDEX, temp);
		3354	temp = RREG32(R300_MC_IND_DATA);
		3355	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		3356	} else {
		3357	temp = RREG32(R300_MC_READ_CNTL_AB);
		3358	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3359	}
		3360	} else {
		3361	temp = RREG32(R300_MC_READ_CNTL_AB);
		3362	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		3363	}
		3364	if (rdev->family == CHIP_RV410 \|\|
		3365	rdev->family == CHIP_R420 \|\|
		3366	rdev->family == CHIP_R423)
		3367	trbs_ff = memtrbs_r4xx[data];
		3368	else
		3369	trbs_ff = memtrbs[data];
		3370	tcas_ff.full += trbs_ff.full;
		3371	}
		3372
		3373	sclk_eff_ff.full = sclk_ff.full;
		3374
		3375	if (rdev->flags & RADEON_IS_AGP) {
		3376	fixed20_12 agpmode_ff;
1963	serge	3377	agpmode_ff.full = dfixed_const(radeon_agpmode);
		3378	temp_ff.full = dfixed_const_666(16);
		3379	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	3380	}
		3381	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		3382
		3383	if (ASIC_IS_R300(rdev)) {
1963	serge	3384	sclk_delay_ff.full = dfixed_const(250);
1179	serge	3385	} else {
		3386	if ((rdev->family == CHIP_RV100) \|\|
		3387	rdev->flags & RADEON_IS_IGP) {
		3388	if (rdev->mc.vram_is_ddr)
1963	serge	3389	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3390	else
1963	serge	3391	sclk_delay_ff.full = dfixed_const(33);
1179	serge	3392	} else {
		3393	if (rdev->mc.vram_width == 128)
1963	serge	3394	sclk_delay_ff.full = dfixed_const(57);
1179	serge	3395	else
1963	serge	3396	sclk_delay_ff.full = dfixed_const(41);
1179	serge	3397	}
		3398	}
		3399
1963	serge	3400	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	3401
		3402	if (rdev->mc.vram_is_ddr) {
		3403	if (rdev->mc.vram_width == 32) {
1963	serge	3404	k1.full = dfixed_const(40);
1179	serge	3405	c = 3;
		3406	} else {
1963	serge	3407	k1.full = dfixed_const(20);
1179	serge	3408	c = 1;
		3409	}
		3410	} else {
1963	serge	3411	k1.full = dfixed_const(40);
1179	serge	3412	c = 3;
		3413	}
		3414
1963	serge	3415	temp_ff.full = dfixed_const(2);
		3416	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		3417	temp_ff.full = dfixed_const(c);
		3418	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		3419	temp_ff.full = dfixed_const(4);
		3420	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		3421	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	3422	mc_latency_mclk.full += k1.full;
		3423
1963	serge	3424	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		3425	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3426
		3427	/*
		3428	HW cursor time assuming worst case of full size colour cursor.
		3429	*/
1963	serge	3430	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	3431	temp_ff.full += trcd_ff.full;
		3432	if (temp_ff.full < tras_ff.full)
		3433	temp_ff.full = tras_ff.full;
1963	serge	3434	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	3435
1963	serge	3436	temp_ff.full = dfixed_const(cur_size);
		3437	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	3438	/*
		3439	Find the total latency for the display data.
		3440	*/
1963	serge	3441	disp_latency_overhead.full = dfixed_const(8);
		3442	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	3443	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		3444	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		3445
		3446	if (mc_latency_mclk.full > mc_latency_sclk.full)
		3447	disp_latency.full = mc_latency_mclk.full;
		3448	else
		3449	disp_latency.full = mc_latency_sclk.full;
		3450
		3451	/* setup Max GRPH_STOP_REQ default value */
		3452	if (ASIC_IS_RV100(rdev))
		3453	max_stop_req = 0x5c;
		3454	else
		3455	max_stop_req = 0x7c;
		3456
		3457	if (mode1) {
		3458	/* CRTC1
		3459	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		3460	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		3461	*/
		3462	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		3463
		3464	if (stop_req > max_stop_req)
		3465	stop_req = max_stop_req;
		3466
		3467	/*
		3468	Find the drain rate of the display buffer.
		3469	*/
1963	serge	3470	temp_ff.full = dfixed_const((16/pixel_bytes1));
		3471	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	3472
		3473	/*
		3474	Find the critical point of the display buffer.
		3475	*/
1963	serge	3476	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		3477	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3478
1963	serge	3479	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	3480
		3481	if (rdev->disp_priority == 2) {
		3482	critical_point = 0;
		3483	}
		3484
		3485	/*
		3486	The critical point should never be above max_stop_req-4. Setting
		3487	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		3488	*/
		3489	if (max_stop_req - critical_point < 4)
		3490	critical_point = 0;
		3491
		3492	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		3493	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		3494	critical_point = 0x10;
		3495	}
		3496
		3497	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		3498	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3499	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3500	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		3501	if ((rdev->family == CHIP_R350) &&
		3502	(stop_req > 0x15)) {
		3503	stop_req -= 0x10;
		3504	}
		3505	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3506	temp \|= RADEON_GRPH_BUFFER_SIZE;
		3507	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3508	RADEON_GRPH_CRITICAL_AT_SOF \|
		3509	RADEON_GRPH_STOP_CNTL);
		3510	/*
		3511	Write the result into the register.
		3512	*/
		3513	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3514	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3515
		3516	#if 0
		3517	if ((rdev->family == CHIP_RS400) \|\|
		3518	(rdev->family == CHIP_RS480)) {
		3519	/* attempt to program RS400 disp regs correctly ??? */
		3520	temp = RREG32(RS400_DISP1_REG_CNTL);
		3521	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		3522	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		3523	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		3524	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3525	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3526	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		3527	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		3528	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		3529	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		3530	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		3531	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		3532	}
		3533	#endif
		3534
1963	serge	3535	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	3536	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		3537	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		3538	}
		3539
		3540	if (mode2) {
		3541	u32 grph2_cntl;
		3542	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		3543
		3544	if (stop_req > max_stop_req)
		3545	stop_req = max_stop_req;
		3546
		3547	/*
		3548	Find the drain rate of the display buffer.
		3549	*/
1963	serge	3550	temp_ff.full = dfixed_const((16/pixel_bytes2));
		3551	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	3552
		3553	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		3554	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		3555	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		3556	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		3557	if ((rdev->family == CHIP_R350) &&
		3558	(stop_req > 0x15)) {
		3559	stop_req -= 0x10;
		3560	}
		3561	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		3562	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		3563	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		3564	RADEON_GRPH_CRITICAL_AT_SOF \|
		3565	RADEON_GRPH_STOP_CNTL);
		3566
		3567	if ((rdev->family == CHIP_RS100) \|\|
		3568	(rdev->family == CHIP_RS200))
		3569	critical_point2 = 0;
		3570	else {
		3571	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	3572	temp_ff.full = dfixed_const(temp);
		3573	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	3574	if (sclk_ff.full < temp_ff.full)
		3575	temp_ff.full = sclk_ff.full;
		3576
		3577	read_return_rate.full = temp_ff.full;
		3578
		3579	if (mode1) {
		3580	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	3581	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	3582	} else {
		3583	time_disp1_drop_priority.full = 0;
		3584	}
		3585	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	3586	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		3587	crit_point_ff.full += dfixed_const_half(0);
1179	serge	3588
1963	serge	3589	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	3590
		3591	if (rdev->disp_priority == 2) {
		3592	critical_point2 = 0;
		3593	}
		3594
		3595	if (max_stop_req - critical_point2 < 4)
		3596	critical_point2 = 0;
		3597
		3598	}
		3599
		3600	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		3601	/* some R300 cards have problem with this set to 0 */
		3602	critical_point2 = 0x10;
		3603	}
		3604
		3605	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		3606	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		3607
		3608	if ((rdev->family == CHIP_RS400) \|\|
		3609	(rdev->family == CHIP_RS480)) {
		3610	#if 0
		3611	/* attempt to program RS400 disp2 regs correctly ??? */
		3612	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		3613	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		3614	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		3615	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		3616	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		3617	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		3618	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		3619	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		3620	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		3621	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		3622	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		3623	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		3624	#endif
		3625	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		3626	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		3627	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		3628	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		3629	}
		3630
1963	serge	3631	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	3632	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		3633	}
6104	serge	3634
		3635	/* Save number of lines the linebuffer leads before the scanout */
		3636	if (mode1)
		3637	rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
		3638
		3639	if (mode2)
		3640	rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
1179	serge	3641	}
		3642
2997	Serge	3643	int r100_ring_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3644	{
1412	serge	3645	uint32_t scratch;
		3646	uint32_t tmp = 0;
		3647	unsigned i;
		3648	int r;
1179	serge	3649
1412	serge	3650	r = radeon_scratch_get(rdev, &scratch);
		3651	if (r) {
		3652	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3653	return r;
		3654	}
		3655	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3656	r = radeon_ring_lock(rdev, ring, 2);
1412	serge	3657	if (r) {
		3658	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3659	radeon_scratch_free(rdev, scratch);
		3660	return r;
		3661	}
2997	Serge	3662	radeon_ring_write(ring, PACKET0(scratch, 0));
		3663	radeon_ring_write(ring, 0xDEADBEEF);
5078	serge	3664	radeon_ring_unlock_commit(rdev, ring, false);
1412	serge	3665	for (i = 0; i < rdev->usec_timeout; i++) {
		3666	tmp = RREG32(scratch);
		3667	if (tmp == 0xDEADBEEF) {
		3668	break;
		3669	}
		3670	DRM_UDELAY(1);
		3671	}
		3672	if (i < rdev->usec_timeout) {
		3673	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3674	} else {
1963	serge	3675	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3676	scratch, tmp);
		3677	r = -EINVAL;
		3678	}
		3679	radeon_scratch_free(rdev, scratch);
		3680	return r;
		3681	}
		3682
1963	serge	3683	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3684	{
2997	Serge	3685	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
		3686
		3687	if (ring->rptr_save_reg) {
		3688	u32 next_rptr = ring->wptr + 2 + 3;
		3689	radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
		3690	radeon_ring_write(ring, next_rptr);
		3691	}
		3692
		3693	radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
		3694	radeon_ring_write(ring, ib->gpu_addr);
		3695	radeon_ring_write(ring, ib->length_dw);
1963	serge	3696	}
		3697
2997	Serge	3698	int r100_ib_test(struct radeon_device rdev, struct radeon_ring ring)
1963	serge	3699	{
2997	Serge	3700	struct radeon_ib ib;
1963	serge	3701	uint32_t scratch;
		3702	uint32_t tmp = 0;
		3703	unsigned i;
		3704	int r;
		3705
		3706	r = radeon_scratch_get(rdev, &scratch);
		3707	if (r) {
		3708	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3709	return r;
		3710	}
		3711	WREG32(scratch, 0xCAFEDEAD);
2997	Serge	3712	r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
1963	serge	3713	if (r) {
2997	Serge	3714	DRM_ERROR("radeon: failed to get ib (%d).\n", r);
		3715	goto free_scratch;
1963	serge	3716	}
2997	Serge	3717	ib.ptr[0] = PACKET0(scratch, 0);
		3718	ib.ptr[1] = 0xDEADBEEF;
		3719	ib.ptr[2] = PACKET2(0);
		3720	ib.ptr[3] = PACKET2(0);
		3721	ib.ptr[4] = PACKET2(0);
		3722	ib.ptr[5] = PACKET2(0);
		3723	ib.ptr[6] = PACKET2(0);
		3724	ib.ptr[7] = PACKET2(0);
		3725	ib.length_dw = 8;
5078	serge	3726	r = radeon_ib_schedule(rdev, &ib, NULL, false);
1963	serge	3727	if (r) {
2997	Serge	3728	DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
		3729	goto free_ib;
1963	serge	3730	}
2997	Serge	3731	r = radeon_fence_wait(ib.fence, false);
1963	serge	3732	if (r) {
2997	Serge	3733	DRM_ERROR("radeon: fence wait failed (%d).\n", r);
		3734	goto free_ib;
1963	serge	3735	}
		3736	for (i = 0; i < rdev->usec_timeout; i++) {
		3737	tmp = RREG32(scratch);
		3738	if (tmp == 0xDEADBEEF) {
		3739	break;
		3740	}
		3741	DRM_UDELAY(1);
		3742	}
		3743	if (i < rdev->usec_timeout) {
		3744	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3745	} else {
		3746	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3747	scratch, tmp);
		3748	r = -EINVAL;
		3749	}
2997	Serge	3750	free_ib:
		3751	radeon_ib_free(rdev, &ib);
		3752	free_scratch:
1963	serge	3753	radeon_scratch_free(rdev, scratch);
		3754	return r;
		3755	}
		3756
1179	serge	3757	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3758	{
		3759	/* Shutdown CP we shouldn't need to do that but better be safe than
		3760	* sorry
		3761	*/
2997	Serge	3762	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1179	serge	3763	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3764
		3765	/* Save few CRTC registers */
1221	serge	3766	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3767	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3768	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3769	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3770	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3771	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3772	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3773	}
		3774
		3775	/* Disable VGA aperture access */
1221	serge	3776	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3777	/* Disable cursor, overlay, crtc */
		3778	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3779	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3780	S_000054_CRTC_DISPLAY_DIS(1));
		3781	WREG32(R_000050_CRTC_GEN_CNTL,
		3782	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3783	S_000050_CRTC_DISP_REQ_EN_B(1));
		3784	WREG32(R_000420_OV0_SCALE_CNTL,
		3785	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3786	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3787	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3788	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3789	S_000360_CUR2_LOCK(1));
		3790	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3791	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3792	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3793	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3794	WREG32(R_000360_CUR2_OFFSET,
		3795	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3796	}
		3797	}
		3798
		3799	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3800	{
		3801	/* Update base address for crtc */
1430	serge	3802	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3803	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3804	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3805	}
		3806	/* Restore CRTC registers */
1221	serge	3807	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3808	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3809	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3810	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3811	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3812	}
		3813	}
		3814
1221	serge	3815	void r100_vga_render_disable(struct radeon_device *rdev)
		3816	{
		3817	u32 tmp;
		3818
		3819	tmp = RREG8(R_0003C2_GENMO_WT);
		3820	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3821	}
		3822
		3823	static void r100_debugfs(struct radeon_device *rdev)
		3824	{
		3825	int r;
		3826
		3827	r = r100_debugfs_mc_info_init(rdev);
		3828	if (r)
		3829	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3830	}
		3831
		3832	static void r100_mc_program(struct radeon_device *rdev)
		3833	{
		3834	struct r100_mc_save save;
		3835
		3836	/* Stops all mc clients */
		3837	r100_mc_stop(rdev, &save);
		3838	if (rdev->flags & RADEON_IS_AGP) {
		3839	WREG32(R_00014C_MC_AGP_LOCATION,
		3840	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3841	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3842	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3843	if (rdev->family > CHIP_RV200)
		3844	WREG32(R_00015C_AGP_BASE_2,
		3845	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3846	} else {
		3847	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3848	WREG32(R_000170_AGP_BASE, 0);
		3849	if (rdev->family > CHIP_RV200)
		3850	WREG32(R_00015C_AGP_BASE_2, 0);
		3851	}
		3852	/* Wait for mc idle */
		3853	if (r100_mc_wait_for_idle(rdev))
		3854	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3855	/* Program MC, should be a 32bits limited address space */
		3856	WREG32(R_000148_MC_FB_LOCATION,
		3857	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3858	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3859	r100_mc_resume(rdev, &save);
		3860	}
		3861
2997	Serge	3862	static void r100_clock_startup(struct radeon_device *rdev)
1221	serge	3863	{
		3864	u32 tmp;
		3865
		3866	if (radeon_dynclks != -1 && radeon_dynclks)
		3867	radeon_legacy_set_clock_gating(rdev, 1);
		3868	/* We need to force on some of the block */
		3869	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3870	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3871	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3872	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3873	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3874	}
		3875
		3876	static int r100_startup(struct radeon_device *rdev)
		3877	{
		3878	int r;
		3879
1321	serge	3880	/* set common regs */
		3881	r100_set_common_regs(rdev);
		3882	/* program mc */
1221	serge	3883	r100_mc_program(rdev);
		3884	/* Resume clock */
		3885	r100_clock_startup(rdev);
		3886	/* Initialize GART (initialize after TTM so we can allocate
		3887	* memory through TTM but finalize after TTM) */
1321	serge	3888	r100_enable_bm(rdev);
1221	serge	3889	if (rdev->flags & RADEON_IS_PCI) {
		3890	r = r100_pci_gart_enable(rdev);
		3891	if (r)
		3892	return r;
		3893	}
2005	serge	3894
		3895	/* allocate wb buffer */
		3896	r = radeon_wb_init(rdev);
		3897	if (r)
		3898	return r;
		3899
3120	serge	3900	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
		3901	if (r) {
		3902	dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
		3903	return r;
		3904	}
		3905
1221	serge	3906	/* Enable IRQ */
3764	Serge	3907	if (!rdev->irq.installed) {
		3908	r = radeon_irq_kms_init(rdev);
		3909	if (r)
		3910	return r;
		3911	}
		3912
2005	serge	3913	r100_irq_set(rdev);
1404	serge	3914	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3915	/* 1M ring buffer */
6104	serge	3916	r = r100_cp_init(rdev, 1024 * 1024);
		3917	if (r) {
1963	serge	3918	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
6104	serge	3919	return r;
		3920	}
2997	Serge	3921
		3922	r = radeon_ib_pool_init(rdev);
2005	serge	3923	if (r) {
2997	Serge	3924	dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005	serge	3925	return r;
		3926	}
3120	serge	3927
1221	serge	3928	return 0;
		3929	}
		3930
6104	serge	3931	void r100_fini(struct radeon_device *rdev)
		3932	{
		3933	radeon_pm_fini(rdev);
		3934	r100_cp_fini(rdev);
		3935	radeon_wb_fini(rdev);
		3936	radeon_ib_pool_fini(rdev);
		3937	radeon_gem_fini(rdev);
		3938	if (rdev->flags & RADEON_IS_PCI)
		3939	r100_pci_gart_fini(rdev);
		3940	radeon_agp_fini(rdev);
		3941	radeon_irq_kms_fini(rdev);
		3942	radeon_fence_driver_fini(rdev);
		3943	radeon_bo_fini(rdev);
		3944	radeon_atombios_fini(rdev);
		3945	kfree(rdev->bios);
		3946	rdev->bios = NULL;
		3947	}
		3948
1963	serge	3949	/*
		3950	* Due to how kexec works, it can leave the hw fully initialised when it
		3951	* boots the new kernel. However doing our init sequence with the CP and
		3952	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3953	* do some quick sanity checks and restore sane values to avoid this
		3954	* problem.
		3955	*/
		3956	void r100_restore_sanity(struct radeon_device *rdev)
		3957	{
		3958	u32 tmp;
1221	serge	3959
1963	serge	3960	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3961	if (tmp) {
		3962	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3963	}
		3964	tmp = RREG32(RADEON_CP_RB_CNTL);
		3965	if (tmp) {
		3966	WREG32(RADEON_CP_RB_CNTL, 0);
		3967	}
		3968	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3969	if (tmp) {
		3970	WREG32(RADEON_SCRATCH_UMSK, 0);
		3971	}
		3972	}
1221	serge	3973
		3974	int r100_init(struct radeon_device *rdev)
		3975	{
		3976	int r;
		3977
		3978	/* Register debugfs file specific to this group of asics */
		3979	r100_debugfs(rdev);
		3980	/* Disable VGA */
		3981	r100_vga_render_disable(rdev);
		3982	/* Initialize scratch registers */
		3983	radeon_scratch_init(rdev);
		3984	/* Initialize surface registers */
		3985	radeon_surface_init(rdev);
1963	serge	3986	/* sanity check some register to avoid hangs like after kexec */
		3987	r100_restore_sanity(rdev);
1221	serge	3988	/* TODO: disable VGA need to use VGA request */
		3989	/* BIOS*/
		3990	if (!radeon_get_bios(rdev)) {
		3991	if (ASIC_IS_AVIVO(rdev))
		3992	return -EINVAL;
		3993	}
		3994	if (rdev->is_atom_bios) {
		3995	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3996	return -EINVAL;
		3997	} else {
		3998	r = radeon_combios_init(rdev);
		3999	if (r)
		4000	return r;
		4001	}
		4002	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	4003	if (radeon_asic_reset(rdev)) {
1221	serge	4004	dev_warn(rdev->dev,
		4005	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		4006	RREG32(R_000E40_RBBM_STATUS),
		4007	RREG32(R_0007C0_CP_STAT));
		4008	}
		4009	/* check if cards are posted or not */
1321	serge	4010	if (radeon_boot_test_post_card(rdev) == false)
		4011	return -EINVAL;
1221	serge	4012	/* Set asic errata */
		4013	r100_errata(rdev);
		4014	/* Initialize clocks */
		4015	radeon_get_clock_info(rdev->ddev);
1430	serge	4016	/* initialize AGP */
		4017	if (rdev->flags & RADEON_IS_AGP) {
		4018	r = radeon_agp_init(rdev);
		4019	if (r) {
		4020	radeon_agp_disable(rdev);
		4021	}
		4022	}
		4023	/* initialize VRAM */
		4024	r100_mc_init(rdev);
1221	serge	4025	/* Fence driver */
2005	serge	4026	r = radeon_fence_driver_init(rdev);
		4027	if (r)
		4028	return r;
1221	serge	4029	/* Memory manager */
1321	serge	4030	r = radeon_bo_init(rdev);
1221	serge	4031	if (r)
		4032	return r;
		4033	if (rdev->flags & RADEON_IS_PCI) {
		4034	r = r100_pci_gart_init(rdev);
		4035	if (r)
		4036	return r;
		4037	}
		4038	r100_set_safe_registers(rdev);
2997	Serge	4039
5078	serge	4040	/* Initialize power management */
		4041	radeon_pm_init(rdev);
		4042
1221	serge	4043	rdev->accel_working = true;
		4044	r = r100_startup(rdev);
		4045	if (r) {
		4046	/* Somethings want wront with the accel init stop accel */
		4047	dev_err(rdev->dev, "Disabling GPU acceleration\n");
6104	serge	4048	r100_cp_fini(rdev);
		4049	radeon_wb_fini(rdev);
		4050	radeon_ib_pool_fini(rdev);
		4051	radeon_irq_kms_fini(rdev);
1221	serge	4052	if (rdev->flags & RADEON_IS_PCI)
		4053	r100_pci_gart_fini(rdev);
		4054	rdev->accel_working = false;
		4055	}
		4056	return 0;
		4057	}
2997	Serge	4058
6104	serge	4059	uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
		4060	{
		4061	unsigned long flags;
		4062	uint32_t ret;
		4063
		4064	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		4065	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		4066	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		4067	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		4068	return ret;
		4069	}
		4070
		4071	void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		4072	{
		4073	unsigned long flags;
		4074
		4075	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		4076	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		4077	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		4078	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		4079	}
		4080
2997	Serge	4081	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
		4082	{
		4083	if (reg < rdev->rio_mem_size)
		4084	return ioread32(rdev->rio_mem + reg);
		4085	else {
		4086	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		4087	return ioread32(rdev->rio_mem + RADEON_MM_DATA);
		4088	}
		4089	}
		4090
		4091	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		4092	{
		4093	if (reg < rdev->rio_mem_size)
		4094	iowrite32(v, rdev->rio_mem + reg);
		4095	else {
		4096	iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
		4097	iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
		4098	}
		4099	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 6938