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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1963 | serge | 29 | #include |
2997 | Serge | 30 | #include |
31 | #include |
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1117 | serge | 32 | #include "radeon_reg.h" |
33 | #include "radeon.h" |
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1963 | serge | 34 | #include "radeon_asic.h" |
1179 | serge | 35 | #include "r100d.h" |
1221 | serge | 36 | #include "rs100d.h" |
37 | #include "rv200d.h" |
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38 | #include "rv250d.h" |
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1963 | serge | 39 | #include "atom.h" |
1117 | serge | 40 | |
1221 | serge | 41 | #include |
2997 | Serge | 42 | #include |
1221 | serge | 43 | |
1179 | serge | 44 | #include "r100_reg_safe.h" |
45 | #include "rn50_reg_safe.h" |
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1221 | serge | 46 | |
47 | /* Firmware Names */ |
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48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
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49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
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50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
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51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
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52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
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53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
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54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
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55 | |||
56 | MODULE_FIRMWARE(FIRMWARE_R100); |
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57 | MODULE_FIRMWARE(FIRMWARE_R200); |
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58 | MODULE_FIRMWARE(FIRMWARE_R300); |
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59 | MODULE_FIRMWARE(FIRMWARE_R420); |
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60 | MODULE_FIRMWARE(FIRMWARE_RS690); |
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61 | MODULE_FIRMWARE(FIRMWARE_RS600); |
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62 | MODULE_FIRMWARE(FIRMWARE_R520); |
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63 | |||
5078 | serge | 64 | #include "r100_track.h" |
1221 | serge | 65 | |
1117 | serge | 66 | /* This files gather functions specifics to: |
67 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
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2997 | Serge | 68 | * and others in some cases. |
1117 | serge | 69 | */ |
70 | |||
3764 | Serge | 71 | static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) |
72 | { |
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73 | if (crtc == 0) { |
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74 | if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) |
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75 | return true; |
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76 | else |
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77 | return false; |
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78 | } else { |
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79 | if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) |
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80 | return true; |
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81 | else |
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82 | return false; |
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83 | } |
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84 | } |
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85 | |||
86 | static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) |
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87 | { |
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88 | u32 vline1, vline2; |
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89 | |||
90 | if (crtc == 0) { |
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91 | vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
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92 | vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
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93 | } else { |
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94 | vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
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95 | vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
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96 | } |
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97 | if (vline1 != vline2) |
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98 | return true; |
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99 | else |
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100 | return false; |
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101 | } |
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102 | |||
2997 | Serge | 103 | /** |
104 | * r100_wait_for_vblank - vblank wait asic callback. |
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105 | * |
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106 | * @rdev: radeon_device pointer |
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107 | * @crtc: crtc to wait for vblank on |
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108 | * |
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109 | * Wait for vblank on the requested crtc (r1xx-r4xx). |
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110 | */ |
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111 | void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) |
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112 | { |
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3764 | Serge | 113 | unsigned i = 0; |
2997 | Serge | 114 | |
115 | if (crtc >= rdev->num_crtc) |
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116 | return; |
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117 | |||
118 | if (crtc == 0) { |
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3764 | Serge | 119 | if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) |
120 | return; |
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121 | } else { |
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122 | if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) |
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123 | return; |
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124 | } |
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125 | |||
126 | /* depending on when we hit vblank, we may be close to active; if so, |
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127 | * wait for another frame. |
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128 | */ |
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129 | while (r100_is_in_vblank(rdev, crtc)) { |
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130 | if (i++ % 100 == 0) { |
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131 | if (!r100_is_counter_moving(rdev, crtc)) |
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2997 | Serge | 132 | break; |
133 | } |
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134 | } |
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3764 | Serge | 135 | |
136 | while (!r100_is_in_vblank(rdev, crtc)) { |
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137 | if (i++ % 100 == 0) { |
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138 | if (!r100_is_counter_moving(rdev, crtc)) |
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2997 | Serge | 139 | break; |
140 | } |
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141 | } |
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142 | } |
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5078 | serge | 143 | |
144 | /** |
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145 | * r100_page_flip - pageflip callback. |
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146 | * |
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147 | * @rdev: radeon_device pointer |
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148 | * @crtc_id: crtc to cleanup pageflip on |
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149 | * @crtc_base: new address of the crtc (GPU MC address) |
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150 | * |
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151 | * Does the actual pageflip (r1xx-r4xx). |
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152 | * During vblank we take the crtc lock and wait for the update_pending |
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153 | * bit to go high, when it does, we release the lock, and allow the |
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154 | * double buffered update to take place. |
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155 | */ |
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156 | void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
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1963 | serge | 157 | { |
158 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
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159 | u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; |
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2997 | Serge | 160 | int i; |
1963 | serge | 161 | |
162 | /* Lock the graphics update lock */ |
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163 | /* update the scanout addresses */ |
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164 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
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165 | |||
166 | /* Wait for update_pending to go high. */ |
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2997 | Serge | 167 | for (i = 0; i < rdev->usec_timeout; i++) { |
168 | if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
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169 | break; |
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170 | udelay(1); |
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171 | } |
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1963 | serge | 172 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
173 | |||
174 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
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175 | tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; |
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176 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); |
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177 | |||
5078 | serge | 178 | } |
179 | |||
180 | /** |
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181 | * r100_page_flip_pending - check if page flip is still pending |
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182 | * |
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183 | * @rdev: radeon_device pointer |
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184 | * @crtc_id: crtc to check |
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185 | * |
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186 | * Check if the last pagefilp is still pending (r1xx-r4xx). |
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187 | * Returns the current update pending status. |
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188 | */ |
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189 | bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) |
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190 | { |
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191 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
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192 | |||
1963 | serge | 193 | /* Return current update_pending status: */ |
5078 | serge | 194 | return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & |
195 | RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); |
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1963 | serge | 196 | } |
5078 | serge | 197 | |
198 | /** |
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199 | * r100_pm_get_dynpm_state - look up dynpm power state callback. |
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200 | * |
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201 | * @rdev: radeon_device pointer |
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202 | * |
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203 | * Look up the optimal power state based on the |
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204 | * current state of the GPU (r1xx-r5xx). |
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205 | * Used for dynpm only. |
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206 | */ |
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207 | void r100_pm_get_dynpm_state(struct radeon_device *rdev) |
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208 | { |
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209 | int i; |
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210 | rdev->pm.dynpm_can_upclock = true; |
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211 | rdev->pm.dynpm_can_downclock = true; |
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212 | |||
213 | switch (rdev->pm.dynpm_planned_action) { |
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214 | case DYNPM_ACTION_MINIMUM: |
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215 | rdev->pm.requested_power_state_index = 0; |
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216 | rdev->pm.dynpm_can_downclock = false; |
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217 | break; |
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218 | case DYNPM_ACTION_DOWNCLOCK: |
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219 | if (rdev->pm.current_power_state_index == 0) { |
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220 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
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221 | rdev->pm.dynpm_can_downclock = false; |
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222 | } else { |
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223 | if (rdev->pm.active_crtc_count > 1) { |
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224 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
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225 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
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226 | continue; |
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227 | else if (i >= rdev->pm.current_power_state_index) { |
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228 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
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229 | break; |
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230 | } else { |
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231 | rdev->pm.requested_power_state_index = i; |
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232 | break; |
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233 | } |
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234 | } |
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235 | } else |
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236 | rdev->pm.requested_power_state_index = |
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237 | rdev->pm.current_power_state_index - 1; |
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238 | } |
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239 | /* don't use the power state if crtcs are active and no display flag is set */ |
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240 | if ((rdev->pm.active_crtc_count > 0) && |
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241 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & |
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242 | RADEON_PM_MODE_NO_DISPLAY)) { |
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243 | rdev->pm.requested_power_state_index++; |
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244 | } |
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245 | break; |
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246 | case DYNPM_ACTION_UPCLOCK: |
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247 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
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248 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
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249 | rdev->pm.dynpm_can_upclock = false; |
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250 | } else { |
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251 | if (rdev->pm.active_crtc_count > 1) { |
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252 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { |
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253 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
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254 | continue; |
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255 | else if (i <= rdev->pm.current_power_state_index) { |
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256 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
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257 | break; |
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258 | } else { |
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259 | rdev->pm.requested_power_state_index = i; |
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260 | break; |
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261 | } |
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262 | } |
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263 | } else |
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264 | rdev->pm.requested_power_state_index = |
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265 | rdev->pm.current_power_state_index + 1; |
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266 | } |
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267 | break; |
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268 | case DYNPM_ACTION_DEFAULT: |
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269 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
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270 | rdev->pm.dynpm_can_upclock = false; |
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271 | break; |
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272 | case DYNPM_ACTION_NONE: |
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273 | default: |
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274 | DRM_ERROR("Requested mode for not defined action\n"); |
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275 | return; |
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276 | } |
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277 | /* only one clock mode per power state */ |
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278 | rdev->pm.requested_clock_mode_index = 0; |
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279 | |||
280 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
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281 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
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282 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
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283 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
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284 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
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285 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
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286 | pcie_lanes); |
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287 | } |
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288 | |||
289 | /** |
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290 | * r100_pm_init_profile - Initialize power profiles callback. |
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291 | * |
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292 | * @rdev: radeon_device pointer |
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293 | * |
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294 | * Initialize the power states used in profile mode |
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295 | * (r1xx-r3xx). |
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296 | * Used for profile mode only. |
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297 | */ |
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298 | void r100_pm_init_profile(struct radeon_device *rdev) |
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299 | { |
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300 | /* default */ |
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301 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
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302 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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303 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
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304 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
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305 | /* low sh */ |
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306 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
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307 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
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308 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
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309 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
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310 | /* mid sh */ |
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311 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
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312 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; |
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313 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
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314 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
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315 | /* high sh */ |
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316 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
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317 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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318 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
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319 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
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320 | /* low mh */ |
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321 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
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322 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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323 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
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324 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
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325 | /* mid mh */ |
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326 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
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327 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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328 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
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329 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
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330 | /* high mh */ |
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331 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
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332 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
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333 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
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334 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
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335 | } |
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336 | |||
337 | /** |
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338 | * r100_pm_misc - set additional pm hw parameters callback. |
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339 | * |
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340 | * @rdev: radeon_device pointer |
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341 | * |
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342 | * Set non-clock parameters associated with a power state |
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343 | * (voltage, pcie lanes, etc.) (r1xx-r4xx). |
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344 | */ |
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345 | void r100_pm_misc(struct radeon_device *rdev) |
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346 | { |
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347 | int requested_index = rdev->pm.requested_power_state_index; |
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348 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
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349 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
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350 | u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; |
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351 | |||
352 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
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353 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
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354 | tmp = RREG32(voltage->gpio.reg); |
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355 | if (voltage->active_high) |
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356 | tmp |= voltage->gpio.mask; |
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357 | else |
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358 | tmp &= ~(voltage->gpio.mask); |
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359 | WREG32(voltage->gpio.reg, tmp); |
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360 | if (voltage->delay) |
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361 | udelay(voltage->delay); |
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362 | } else { |
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363 | tmp = RREG32(voltage->gpio.reg); |
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364 | if (voltage->active_high) |
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365 | tmp &= ~voltage->gpio.mask; |
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366 | else |
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367 | tmp |= voltage->gpio.mask; |
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368 | WREG32(voltage->gpio.reg, tmp); |
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369 | if (voltage->delay) |
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370 | udelay(voltage->delay); |
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371 | } |
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372 | } |
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373 | |||
374 | sclk_cntl = RREG32_PLL(SCLK_CNTL); |
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375 | sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); |
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376 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); |
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377 | sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); |
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378 | sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); |
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379 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
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380 | sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; |
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381 | if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) |
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382 | sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; |
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383 | else |
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384 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; |
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385 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) |
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386 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); |
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387 | else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) |
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388 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); |
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389 | } else |
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390 | sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; |
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391 | |||
392 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
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393 | sclk_more_cntl |= IO_CG_VOLTAGE_DROP; |
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394 | if (voltage->delay) { |
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395 | sclk_more_cntl |= VOLTAGE_DROP_SYNC; |
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396 | switch (voltage->delay) { |
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397 | case 33: |
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398 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); |
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399 | break; |
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400 | case 66: |
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401 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); |
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402 | break; |
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403 | case 99: |
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404 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); |
||
405 | break; |
||
406 | case 132: |
||
407 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); |
||
408 | break; |
||
409 | } |
||
410 | } else |
||
411 | sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; |
||
412 | } else |
||
413 | sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; |
||
414 | |||
415 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
||
416 | sclk_cntl &= ~FORCE_HDP; |
||
417 | else |
||
418 | sclk_cntl |= FORCE_HDP; |
||
419 | |||
420 | WREG32_PLL(SCLK_CNTL, sclk_cntl); |
||
421 | WREG32_PLL(SCLK_CNTL2, sclk_cntl2); |
||
422 | WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); |
||
423 | |||
424 | /* set pcie lanes */ |
||
425 | if ((rdev->flags & RADEON_IS_PCIE) && |
||
426 | !(rdev->flags & RADEON_IS_IGP) && |
||
427 | rdev->asic->pm.set_pcie_lanes && |
||
428 | (ps->pcie_lanes != |
||
429 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
||
430 | radeon_set_pcie_lanes(rdev, |
||
431 | ps->pcie_lanes); |
||
432 | DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); |
||
433 | } |
||
434 | } |
||
435 | |||
436 | /** |
||
437 | * r100_pm_prepare - pre-power state change callback. |
||
438 | * |
||
439 | * @rdev: radeon_device pointer |
||
440 | * |
||
441 | * Prepare for a power state change (r1xx-r4xx). |
||
442 | */ |
||
443 | void r100_pm_prepare(struct radeon_device *rdev) |
||
444 | { |
||
445 | struct drm_device *ddev = rdev->ddev; |
||
446 | struct drm_crtc *crtc; |
||
447 | struct radeon_crtc *radeon_crtc; |
||
448 | u32 tmp; |
||
449 | |||
450 | /* disable any active CRTCs */ |
||
451 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
||
452 | radeon_crtc = to_radeon_crtc(crtc); |
||
453 | if (radeon_crtc->enabled) { |
||
454 | if (radeon_crtc->crtc_id) { |
||
455 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
456 | tmp |= RADEON_CRTC2_DISP_REQ_EN_B; |
||
457 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
||
458 | } else { |
||
459 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); |
||
460 | tmp |= RADEON_CRTC_DISP_REQ_EN_B; |
||
461 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); |
||
462 | } |
||
463 | } |
||
464 | } |
||
465 | } |
||
466 | |||
467 | /** |
||
468 | * r100_pm_finish - post-power state change callback. |
||
469 | * |
||
470 | * @rdev: radeon_device pointer |
||
471 | * |
||
472 | * Clean up after a power state change (r1xx-r4xx). |
||
473 | */ |
||
474 | void r100_pm_finish(struct radeon_device *rdev) |
||
475 | { |
||
476 | struct drm_device *ddev = rdev->ddev; |
||
477 | struct drm_crtc *crtc; |
||
478 | struct radeon_crtc *radeon_crtc; |
||
479 | u32 tmp; |
||
480 | |||
481 | /* enable any active CRTCs */ |
||
482 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
||
483 | radeon_crtc = to_radeon_crtc(crtc); |
||
484 | if (radeon_crtc->enabled) { |
||
485 | if (radeon_crtc->crtc_id) { |
||
486 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
487 | tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; |
||
488 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
||
489 | } else { |
||
490 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); |
||
491 | tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; |
||
492 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); |
||
493 | } |
||
494 | } |
||
495 | } |
||
496 | } |
||
497 | |||
498 | /** |
||
499 | * r100_gui_idle - gui idle callback. |
||
500 | * |
||
501 | * @rdev: radeon_device pointer |
||
502 | * |
||
503 | * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). |
||
504 | * Returns true if idle, false if not. |
||
505 | */ |
||
1963 | serge | 506 | bool r100_gui_idle(struct radeon_device *rdev) |
507 | { |
||
508 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) |
||
509 | return false; |
||
510 | else |
||
511 | return true; |
||
512 | } |
||
513 | |||
1321 | serge | 514 | /* hpd for digital panel detect/disconnect */ |
2997 | Serge | 515 | /** |
516 | * r100_hpd_sense - hpd sense callback. |
||
517 | * |
||
518 | * @rdev: radeon_device pointer |
||
519 | * @hpd: hpd (hotplug detect) pin |
||
520 | * |
||
521 | * Checks if a digital monitor is connected (r1xx-r4xx). |
||
522 | * Returns true if connected, false if not connected. |
||
523 | */ |
||
1321 | serge | 524 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
525 | { |
||
526 | bool connected = false; |
||
527 | |||
528 | switch (hpd) { |
||
529 | case RADEON_HPD_1: |
||
530 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
||
531 | connected = true; |
||
532 | break; |
||
533 | case RADEON_HPD_2: |
||
534 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
||
535 | connected = true; |
||
536 | break; |
||
537 | default: |
||
538 | break; |
||
539 | } |
||
540 | return connected; |
||
541 | } |
||
542 | |||
2997 | Serge | 543 | /** |
544 | * r100_hpd_set_polarity - hpd set polarity callback. |
||
545 | * |
||
546 | * @rdev: radeon_device pointer |
||
547 | * @hpd: hpd (hotplug detect) pin |
||
548 | * |
||
549 | * Set the polarity of the hpd pin (r1xx-r4xx). |
||
550 | */ |
||
1321 | serge | 551 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
552 | enum radeon_hpd_id hpd) |
||
553 | { |
||
554 | u32 tmp; |
||
555 | bool connected = r100_hpd_sense(rdev, hpd); |
||
556 | |||
557 | switch (hpd) { |
||
558 | case RADEON_HPD_1: |
||
559 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
||
560 | if (connected) |
||
561 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
||
562 | else |
||
563 | tmp |= RADEON_FP_DETECT_INT_POL; |
||
564 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
||
565 | break; |
||
566 | case RADEON_HPD_2: |
||
567 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
||
568 | if (connected) |
||
569 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
||
570 | else |
||
571 | tmp |= RADEON_FP2_DETECT_INT_POL; |
||
572 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
||
573 | break; |
||
574 | default: |
||
575 | break; |
||
576 | } |
||
577 | } |
||
578 | |||
2997 | Serge | 579 | /** |
580 | * r100_hpd_init - hpd setup callback. |
||
581 | * |
||
582 | * @rdev: radeon_device pointer |
||
583 | * |
||
584 | * Setup the hpd pins used by the card (r1xx-r4xx). |
||
585 | * Set the polarity, and enable the hpd interrupts. |
||
586 | */ |
||
1321 | serge | 587 | void r100_hpd_init(struct radeon_device *rdev) |
588 | { |
||
589 | struct drm_device *dev = rdev->ddev; |
||
590 | struct drm_connector *connector; |
||
2997 | Serge | 591 | unsigned enable = 0; |
1321 | serge | 592 | |
593 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
594 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
2997 | Serge | 595 | enable |= 1 << radeon_connector->hpd.hpd; |
596 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
||
1321 | serge | 597 | } |
2997 | Serge | 598 | // radeon_irq_kms_enable_hpd(rdev, enable); |
1321 | serge | 599 | } |
600 | |||
2997 | Serge | 601 | /** |
602 | * r100_hpd_fini - hpd tear down callback. |
||
603 | * |
||
604 | * @rdev: radeon_device pointer |
||
605 | * |
||
606 | * Tear down the hpd pins used by the card (r1xx-r4xx). |
||
607 | * Disable the hpd interrupts. |
||
608 | */ |
||
1321 | serge | 609 | void r100_hpd_fini(struct radeon_device *rdev) |
610 | { |
||
611 | struct drm_device *dev = rdev->ddev; |
||
612 | struct drm_connector *connector; |
||
2997 | Serge | 613 | unsigned disable = 0; |
1321 | serge | 614 | |
615 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
616 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
2997 | Serge | 617 | disable |= 1 << radeon_connector->hpd.hpd; |
1321 | serge | 618 | } |
2997 | Serge | 619 | // radeon_irq_kms_disable_hpd(rdev, disable); |
1321 | serge | 620 | } |
621 | |||
1117 | serge | 622 | /* |
623 | * PCI GART |
||
624 | */ |
||
625 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
||
626 | { |
||
627 | /* TODO: can we do somethings here ? */ |
||
628 | /* It seems hw only cache one entry so we should discard this |
||
629 | * entry otherwise if first GPU GART read hit this entry it |
||
630 | * could end up in wrong address. */ |
||
631 | } |
||
632 | |||
1179 | serge | 633 | int r100_pci_gart_init(struct radeon_device *rdev) |
1117 | serge | 634 | { |
635 | int r; |
||
636 | |||
2997 | Serge | 637 | if (rdev->gart.ptr) { |
1963 | serge | 638 | WARN(1, "R100 PCI GART already initialized\n"); |
1179 | serge | 639 | return 0; |
640 | } |
||
1117 | serge | 641 | /* Initialize common gart structure */ |
642 | r = radeon_gart_init(rdev); |
||
1179 | serge | 643 | if (r) |
1117 | serge | 644 | return r; |
1268 | serge | 645 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
2997 | Serge | 646 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
647 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
||
1179 | serge | 648 | return radeon_gart_table_ram_alloc(rdev); |
649 | } |
||
650 | |||
651 | int r100_pci_gart_enable(struct radeon_device *rdev) |
||
652 | { |
||
653 | uint32_t tmp; |
||
654 | |||
1117 | serge | 655 | /* discard memory request outside of configured range */ |
656 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
||
657 | WREG32(RADEON_AIC_CNTL, tmp); |
||
658 | /* set address range for PCI address translate */ |
||
1430 | serge | 659 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
660 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); |
||
1117 | serge | 661 | /* set PCI GART page-table base address */ |
662 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
||
663 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
||
664 | WREG32(RADEON_AIC_CNTL, tmp); |
||
665 | r100_pci_gart_tlb_flush(rdev); |
||
2997 | Serge | 666 | DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", |
667 | (unsigned)(rdev->mc.gtt_size >> 20), |
||
668 | (unsigned long long)rdev->gart.table_addr); |
||
1117 | serge | 669 | rdev->gart.ready = true; |
670 | return 0; |
||
671 | } |
||
672 | |||
673 | void r100_pci_gart_disable(struct radeon_device *rdev) |
||
674 | { |
||
675 | uint32_t tmp; |
||
676 | |||
677 | /* discard memory request outside of configured range */ |
||
678 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
||
679 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
||
680 | WREG32(RADEON_AIC_LO_ADDR, 0); |
||
681 | WREG32(RADEON_AIC_HI_ADDR, 0); |
||
682 | } |
||
683 | |||
5078 | serge | 684 | void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, |
685 | uint64_t addr, uint32_t flags) |
||
1117 | serge | 686 | { |
2997 | Serge | 687 | u32 *gtt = rdev->gart.ptr; |
688 | gtt[i] = cpu_to_le32(lower_32_bits(addr)); |
||
1117 | serge | 689 | } |
690 | |||
1179 | serge | 691 | void r100_pci_gart_fini(struct radeon_device *rdev) |
1117 | serge | 692 | { |
1963 | serge | 693 | radeon_gart_fini(rdev); |
1117 | serge | 694 | r100_pci_gart_disable(rdev); |
1179 | serge | 695 | radeon_gart_table_ram_free(rdev); |
1117 | serge | 696 | } |
697 | |||
2005 | serge | 698 | int r100_irq_set(struct radeon_device *rdev) |
699 | { |
||
700 | uint32_t tmp = 0; |
||
1117 | serge | 701 | |
2005 | serge | 702 | if (!rdev->irq.installed) { |
703 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
||
704 | WREG32(R_000040_GEN_INT_CNTL, 0); |
||
705 | return -EINVAL; |
||
706 | } |
||
2997 | Serge | 707 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
2005 | serge | 708 | tmp |= RADEON_SW_INT_ENABLE; |
709 | } |
||
710 | if (rdev->irq.crtc_vblank_int[0] || |
||
2997 | Serge | 711 | atomic_read(&rdev->irq.pflip[0])) { |
2005 | serge | 712 | tmp |= RADEON_CRTC_VBLANK_MASK; |
713 | } |
||
714 | if (rdev->irq.crtc_vblank_int[1] || |
||
2997 | Serge | 715 | atomic_read(&rdev->irq.pflip[1])) { |
2005 | serge | 716 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
717 | } |
||
718 | if (rdev->irq.hpd[0]) { |
||
719 | tmp |= RADEON_FP_DETECT_MASK; |
||
720 | } |
||
721 | if (rdev->irq.hpd[1]) { |
||
722 | tmp |= RADEON_FP2_DETECT_MASK; |
||
723 | } |
||
724 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
||
725 | return 0; |
||
726 | } |
||
727 | |||
1221 | serge | 728 | void r100_irq_disable(struct radeon_device *rdev) |
1117 | serge | 729 | { |
1221 | serge | 730 | u32 tmp; |
1117 | serge | 731 | |
1221 | serge | 732 | WREG32(R_000040_GEN_INT_CNTL, 0); |
733 | /* Wait and acknowledge irq */ |
||
734 | mdelay(1); |
||
735 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
||
736 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
||
1117 | serge | 737 | } |
738 | |||
2997 | Serge | 739 | static uint32_t r100_irq_ack(struct radeon_device *rdev) |
1117 | serge | 740 | { |
1221 | serge | 741 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
1321 | serge | 742 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
743 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
||
744 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
||
1117 | serge | 745 | |
1221 | serge | 746 | if (irqs) { |
747 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
||
1129 | serge | 748 | } |
1221 | serge | 749 | return irqs & irq_mask; |
1117 | serge | 750 | } |
751 | |||
2005 | serge | 752 | int r100_irq_process(struct radeon_device *rdev) |
753 | { |
||
754 | uint32_t status, msi_rearm; |
||
755 | bool queue_hotplug = false; |
||
1117 | serge | 756 | |
2005 | serge | 757 | status = r100_irq_ack(rdev); |
758 | if (!status) { |
||
759 | return IRQ_NONE; |
||
760 | } |
||
761 | if (rdev->shutdown) { |
||
762 | return IRQ_NONE; |
||
763 | } |
||
764 | while (status) { |
||
765 | /* SW interrupt */ |
||
766 | if (status & RADEON_SW_INT_TEST) { |
||
2997 | Serge | 767 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2005 | serge | 768 | } |
769 | /* Vertical blank interrupts */ |
||
770 | if (status & RADEON_CRTC_VBLANK_STAT) { |
||
771 | if (rdev->irq.crtc_vblank_int[0]) { |
||
772 | // drm_handle_vblank(rdev->ddev, 0); |
||
773 | rdev->pm.vblank_sync = true; |
||
774 | // wake_up(&rdev->irq.vblank_queue); |
||
775 | } |
||
776 | // if (rdev->irq.pflip[0]) |
||
777 | // radeon_crtc_handle_flip(rdev, 0); |
||
778 | } |
||
779 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
||
780 | if (rdev->irq.crtc_vblank_int[1]) { |
||
781 | // drm_handle_vblank(rdev->ddev, 1); |
||
782 | rdev->pm.vblank_sync = true; |
||
783 | // wake_up(&rdev->irq.vblank_queue); |
||
784 | } |
||
785 | // if (rdev->irq.pflip[1]) |
||
786 | // radeon_crtc_handle_flip(rdev, 1); |
||
787 | } |
||
788 | if (status & RADEON_FP_DETECT_STAT) { |
||
789 | queue_hotplug = true; |
||
790 | DRM_DEBUG("HPD1\n"); |
||
791 | } |
||
792 | if (status & RADEON_FP2_DETECT_STAT) { |
||
793 | queue_hotplug = true; |
||
794 | DRM_DEBUG("HPD2\n"); |
||
795 | } |
||
796 | status = r100_irq_ack(rdev); |
||
797 | } |
||
798 | // if (queue_hotplug) |
||
799 | // schedule_work(&rdev->hotplug_work); |
||
800 | if (rdev->msi_enabled) { |
||
801 | switch (rdev->family) { |
||
802 | case CHIP_RS400: |
||
803 | case CHIP_RS480: |
||
804 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
||
805 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
||
806 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
||
807 | break; |
||
808 | default: |
||
2997 | Serge | 809 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
2005 | serge | 810 | break; |
811 | } |
||
812 | } |
||
813 | return IRQ_HANDLED; |
||
814 | } |
||
815 | |||
1403 | serge | 816 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
817 | { |
||
818 | if (crtc == 0) |
||
819 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
||
820 | else |
||
821 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
||
822 | } |
||
1117 | serge | 823 | |
5139 | serge | 824 | /** |
825 | * r100_ring_hdp_flush - flush Host Data Path via the ring buffer |
||
826 | * rdev: radeon device structure |
||
827 | * ring: ring buffer struct for emitting packets |
||
828 | */ |
||
829 | static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) |
||
830 | { |
||
831 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
||
832 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl | |
||
833 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
||
834 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
||
835 | radeon_ring_write(ring, rdev->config.r100.hdp_cntl); |
||
836 | } |
||
837 | |||
1404 | serge | 838 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
839 | * for enough space (today caller are ib schedule and buffer move) */ |
||
1117 | serge | 840 | void r100_fence_ring_emit(struct radeon_device *rdev, |
841 | struct radeon_fence *fence) |
||
842 | { |
||
2997 | Serge | 843 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
844 | |||
1404 | serge | 845 | /* We have to make sure that caches are flushed before |
846 | * CPU might read something from VRAM. */ |
||
2997 | Serge | 847 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
848 | radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); |
||
849 | radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); |
||
850 | radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); |
||
1117 | serge | 851 | /* Wait until IDLE & CLEAN */ |
2997 | Serge | 852 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
853 | radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
||
5078 | serge | 854 | r100_ring_hdp_flush(rdev, ring); |
1117 | serge | 855 | /* Emit fence sequence & fire IRQ */ |
2997 | Serge | 856 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
857 | radeon_ring_write(ring, fence->seq); |
||
858 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
||
859 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
||
1117 | serge | 860 | } |
861 | |||
5078 | serge | 862 | bool r100_semaphore_ring_emit(struct radeon_device *rdev, |
2997 | Serge | 863 | struct radeon_ring *ring, |
864 | struct radeon_semaphore *semaphore, |
||
865 | bool emit_wait) |
||
866 | { |
||
867 | /* Unused on older asics, since we don't have semaphores or multiple rings */ |
||
868 | BUG(); |
||
5078 | serge | 869 | return false; |
2997 | Serge | 870 | } |
871 | |||
5271 | serge | 872 | struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, |
1117 | serge | 873 | uint64_t src_offset, |
874 | uint64_t dst_offset, |
||
2997 | Serge | 875 | unsigned num_gpu_pages, |
5271 | serge | 876 | struct reservation_object *resv) |
1117 | serge | 877 | { |
2997 | Serge | 878 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
5271 | serge | 879 | struct radeon_fence *fence; |
1117 | serge | 880 | uint32_t cur_pages; |
2997 | Serge | 881 | uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
1117 | serge | 882 | uint32_t pitch; |
883 | uint32_t stride_pixels; |
||
884 | unsigned ndw; |
||
885 | int num_loops; |
||
886 | int r = 0; |
||
887 | |||
888 | /* radeon limited to 16k stride */ |
||
889 | stride_bytes &= 0x3fff; |
||
890 | /* radeon pitch is /64 */ |
||
891 | pitch = stride_bytes / 64; |
||
892 | stride_pixels = stride_bytes / 4; |
||
2997 | Serge | 893 | num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); |
1117 | serge | 894 | |
895 | /* Ask for enough room for blit + flush + fence */ |
||
896 | ndw = 64 + (10 * num_loops); |
||
2997 | Serge | 897 | r = radeon_ring_lock(rdev, ring, ndw); |
1117 | serge | 898 | if (r) { |
899 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
||
5271 | serge | 900 | return ERR_PTR(-EINVAL); |
1117 | serge | 901 | } |
2997 | Serge | 902 | while (num_gpu_pages > 0) { |
903 | cur_pages = num_gpu_pages; |
||
1117 | serge | 904 | if (cur_pages > 8191) { |
905 | cur_pages = 8191; |
||
906 | } |
||
2997 | Serge | 907 | num_gpu_pages -= cur_pages; |
1117 | serge | 908 | |
909 | /* pages are in Y direction - height |
||
910 | page width in X direction - width */ |
||
2997 | Serge | 911 | radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
912 | radeon_ring_write(ring, |
||
1117 | serge | 913 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
914 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
||
915 | RADEON_GMC_SRC_CLIPPING | |
||
916 | RADEON_GMC_DST_CLIPPING | |
||
917 | RADEON_GMC_BRUSH_NONE | |
||
918 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
||
919 | RADEON_GMC_SRC_DATATYPE_COLOR | |
||
920 | RADEON_ROP3_S | |
||
921 | RADEON_DP_SRC_SOURCE_MEMORY | |
||
922 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
||
923 | RADEON_GMC_WR_MSK_DIS); |
||
2997 | Serge | 924 | radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); |
925 | radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); |
||
926 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
||
927 | radeon_ring_write(ring, 0); |
||
928 | radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); |
||
929 | radeon_ring_write(ring, num_gpu_pages); |
||
930 | radeon_ring_write(ring, num_gpu_pages); |
||
931 | radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); |
||
1117 | serge | 932 | } |
2997 | Serge | 933 | radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
934 | radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); |
||
935 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
||
936 | radeon_ring_write(ring, |
||
1117 | serge | 937 | RADEON_WAIT_2D_IDLECLEAN | |
938 | RADEON_WAIT_HOST_IDLECLEAN | |
||
939 | RADEON_WAIT_DMA_GUI_IDLE); |
||
5271 | serge | 940 | r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); |
941 | if (r) { |
||
942 | radeon_ring_unlock_undo(rdev, ring); |
||
943 | return ERR_PTR(r); |
||
1117 | serge | 944 | } |
5078 | serge | 945 | radeon_ring_unlock_commit(rdev, ring, false); |
5271 | serge | 946 | return fence; |
1117 | serge | 947 | } |
948 | |||
1179 | serge | 949 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
950 | { |
||
951 | unsigned i; |
||
952 | u32 tmp; |
||
953 | |||
954 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
955 | tmp = RREG32(R_000E40_RBBM_STATUS); |
||
956 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
||
957 | return 0; |
||
958 | } |
||
959 | udelay(1); |
||
960 | } |
||
961 | return -1; |
||
962 | } |
||
963 | |||
2997 | Serge | 964 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
1117 | serge | 965 | { |
966 | int r; |
||
967 | |||
2997 | Serge | 968 | r = radeon_ring_lock(rdev, ring, 2); |
1117 | serge | 969 | if (r) { |
970 | return; |
||
971 | } |
||
2997 | Serge | 972 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
973 | radeon_ring_write(ring, |
||
1117 | serge | 974 | RADEON_ISYNC_ANY2D_IDLE3D | |
975 | RADEON_ISYNC_ANY3D_IDLE2D | |
||
976 | RADEON_ISYNC_WAIT_IDLEGUI | |
||
977 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
||
5078 | serge | 978 | radeon_ring_unlock_commit(rdev, ring, false); |
1117 | serge | 979 | } |
980 | |||
1221 | serge | 981 | |
982 | /* Load the microcode for the CP */ |
||
983 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
||
1117 | serge | 984 | { |
1221 | serge | 985 | const char *fw_name = NULL; |
986 | int err; |
||
1117 | serge | 987 | |
1963 | serge | 988 | DRM_DEBUG_KMS("\n"); |
1117 | serge | 989 | |
990 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
||
991 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
||
992 | (rdev->family == CHIP_RS200)) { |
||
993 | DRM_INFO("Loading R100 Microcode\n"); |
||
1221 | serge | 994 | fw_name = FIRMWARE_R100; |
1117 | serge | 995 | } else if ((rdev->family == CHIP_R200) || |
996 | (rdev->family == CHIP_RV250) || |
||
997 | (rdev->family == CHIP_RV280) || |
||
998 | (rdev->family == CHIP_RS300)) { |
||
999 | DRM_INFO("Loading R200 Microcode\n"); |
||
1221 | serge | 1000 | fw_name = FIRMWARE_R200; |
1117 | serge | 1001 | } else if ((rdev->family == CHIP_R300) || |
1002 | (rdev->family == CHIP_R350) || |
||
1003 | (rdev->family == CHIP_RV350) || |
||
1004 | (rdev->family == CHIP_RV380) || |
||
1005 | (rdev->family == CHIP_RS400) || |
||
1006 | (rdev->family == CHIP_RS480)) { |
||
1007 | DRM_INFO("Loading R300 Microcode\n"); |
||
1221 | serge | 1008 | fw_name = FIRMWARE_R300; |
1117 | serge | 1009 | } else if ((rdev->family == CHIP_R420) || |
1010 | (rdev->family == CHIP_R423) || |
||
1011 | (rdev->family == CHIP_RV410)) { |
||
1012 | DRM_INFO("Loading R400 Microcode\n"); |
||
1221 | serge | 1013 | fw_name = FIRMWARE_R420; |
1117 | serge | 1014 | } else if ((rdev->family == CHIP_RS690) || |
1015 | (rdev->family == CHIP_RS740)) { |
||
1016 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
||
1221 | serge | 1017 | fw_name = FIRMWARE_RS690; |
1117 | serge | 1018 | } else if (rdev->family == CHIP_RS600) { |
1019 | DRM_INFO("Loading RS600 Microcode\n"); |
||
1221 | serge | 1020 | fw_name = FIRMWARE_RS600; |
1117 | serge | 1021 | } else if ((rdev->family == CHIP_RV515) || |
1022 | (rdev->family == CHIP_R520) || |
||
1023 | (rdev->family == CHIP_RV530) || |
||
1024 | (rdev->family == CHIP_R580) || |
||
1025 | (rdev->family == CHIP_RV560) || |
||
1026 | (rdev->family == CHIP_RV570)) { |
||
1027 | DRM_INFO("Loading R500 Microcode\n"); |
||
1221 | serge | 1028 | fw_name = FIRMWARE_R520; |
1117 | serge | 1029 | } |
1221 | serge | 1030 | |
5078 | serge | 1031 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
1221 | serge | 1032 | if (err) { |
1033 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
||
1034 | fw_name); |
||
1035 | } else if (rdev->me_fw->size % 8) { |
||
1036 | printk(KERN_ERR |
||
1037 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
||
1038 | rdev->me_fw->size, fw_name); |
||
1039 | err = -EINVAL; |
||
1040 | release_firmware(rdev->me_fw); |
||
1041 | rdev->me_fw = NULL; |
||
1117 | serge | 1042 | } |
1221 | serge | 1043 | return err; |
1117 | serge | 1044 | } |
1045 | |||
5078 | serge | 1046 | u32 r100_gfx_get_rptr(struct radeon_device *rdev, |
1047 | struct radeon_ring *ring) |
||
1048 | { |
||
1049 | u32 rptr; |
||
1050 | |||
1051 | if (rdev->wb.enabled) |
||
1052 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
||
1053 | else |
||
1054 | rptr = RREG32(RADEON_CP_RB_RPTR); |
||
1055 | |||
1056 | return rptr; |
||
1057 | } |
||
1058 | |||
1059 | u32 r100_gfx_get_wptr(struct radeon_device *rdev, |
||
1060 | struct radeon_ring *ring) |
||
1061 | { |
||
1062 | u32 wptr; |
||
1063 | |||
1064 | wptr = RREG32(RADEON_CP_RB_WPTR); |
||
1065 | |||
1066 | return wptr; |
||
1067 | } |
||
1068 | |||
1069 | void r100_gfx_set_wptr(struct radeon_device *rdev, |
||
1070 | struct radeon_ring *ring) |
||
1071 | { |
||
1072 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); |
||
1073 | (void)RREG32(RADEON_CP_RB_WPTR); |
||
1074 | } |
||
1075 | |||
1221 | serge | 1076 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
1077 | { |
||
1078 | const __be32 *fw_data; |
||
1079 | int i, size; |
||
1080 | |||
1081 | if (r100_gui_wait_for_idle(rdev)) { |
||
1082 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
1083 | "programming pipes. Bad things might happen.\n"); |
||
1084 | } |
||
1085 | |||
1086 | if (rdev->me_fw) { |
||
1087 | size = rdev->me_fw->size / 4; |
||
1088 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
||
1089 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
||
1090 | for (i = 0; i < size; i += 2) { |
||
1091 | WREG32(RADEON_CP_ME_RAM_DATAH, |
||
1092 | be32_to_cpup(&fw_data[i])); |
||
1093 | WREG32(RADEON_CP_ME_RAM_DATAL, |
||
1094 | be32_to_cpup(&fw_data[i + 1])); |
||
1095 | } |
||
1096 | } |
||
1097 | } |
||
1098 | |||
1117 | serge | 1099 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
1100 | { |
||
2997 | Serge | 1101 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1117 | serge | 1102 | unsigned rb_bufsz; |
1103 | unsigned rb_blksz; |
||
1104 | unsigned max_fetch; |
||
1105 | unsigned pre_write_timer; |
||
1106 | unsigned pre_write_limit; |
||
1107 | unsigned indirect2_start; |
||
1108 | unsigned indirect1_start; |
||
1109 | uint32_t tmp; |
||
1110 | int r; |
||
1111 | |||
1129 | serge | 1112 | if (r100_debugfs_cp_init(rdev)) { |
1113 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
||
1114 | } |
||
1179 | serge | 1115 | if (!rdev->me_fw) { |
1116 | r = r100_cp_init_microcode(rdev); |
||
1117 | if (r) { |
||
1118 | DRM_ERROR("Failed to load firmware!\n"); |
||
1119 | return r; |
||
1120 | } |
||
1121 | } |
||
1122 | |||
1117 | serge | 1123 | /* Align ring size */ |
5078 | serge | 1124 | rb_bufsz = order_base_2(ring_size / 8); |
1117 | serge | 1125 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
1126 | r100_cp_load_microcode(rdev); |
||
2997 | Serge | 1127 | r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, |
5078 | serge | 1128 | RADEON_CP_PACKET2); |
1117 | serge | 1129 | if (r) { |
1130 | return r; |
||
1131 | } |
||
1132 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
||
1133 | * the rptr copy in system ram */ |
||
1134 | rb_blksz = 9; |
||
1135 | /* cp will read 128bytes at a time (4 dwords) */ |
||
1136 | max_fetch = 1; |
||
2997 | Serge | 1137 | ring->align_mask = 16 - 1; |
1117 | serge | 1138 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
1139 | pre_write_timer = 64; |
||
1140 | /* Force CP_RB_WPTR write if written more than one time before the |
||
1141 | * delay expire |
||
1142 | */ |
||
1143 | pre_write_limit = 0; |
||
1144 | /* Setup the cp cache like this (cache size is 96 dwords) : |
||
1145 | * RING 0 to 15 |
||
1146 | * INDIRECT1 16 to 79 |
||
1147 | * INDIRECT2 80 to 95 |
||
1148 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
1149 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
1150 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
||
1151 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
||
1152 | * so it gets the bigger cache. |
||
1153 | */ |
||
1154 | indirect2_start = 80; |
||
1155 | indirect1_start = 16; |
||
1156 | /* cp setup */ |
||
1157 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
||
1268 | serge | 1158 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
1117 | serge | 1159 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
1963 | serge | 1160 | REG_SET(RADEON_MAX_FETCH, max_fetch)); |
1268 | serge | 1161 | #ifdef __BIG_ENDIAN |
1162 | tmp |= RADEON_BUF_SWAP_32BIT; |
||
1163 | #endif |
||
1963 | serge | 1164 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); |
1268 | serge | 1165 | |
1117 | serge | 1166 | /* Set ring address */ |
2997 | Serge | 1167 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); |
1168 | WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); |
||
1117 | serge | 1169 | /* Force read & write ptr to 0 */ |
1963 | serge | 1170 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
1117 | serge | 1171 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
2997 | Serge | 1172 | ring->wptr = 0; |
1173 | WREG32(RADEON_CP_RB_WPTR, ring->wptr); |
||
1963 | serge | 1174 | |
1175 | /* set the wb address whether it's enabled or not */ |
||
1176 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
||
1177 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); |
||
1178 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); |
||
1179 | |||
1180 | if (rdev->wb.enabled) |
||
1181 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
||
1182 | else { |
||
1183 | tmp |= RADEON_RB_NO_UPDATE; |
||
1184 | WREG32(R_000770_SCRATCH_UMSK, 0); |
||
1185 | } |
||
1186 | |||
1117 | serge | 1187 | WREG32(RADEON_CP_RB_CNTL, tmp); |
1188 | udelay(10); |
||
1189 | /* Set cp mode to bus mastering & enable cp*/ |
||
1190 | WREG32(RADEON_CP_CSQ_MODE, |
||
1191 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
||
1192 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
||
1963 | serge | 1193 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
1194 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
||
1117 | serge | 1195 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
2997 | Serge | 1196 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1197 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
||
1117 | serge | 1198 | if (r) { |
1199 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
||
1200 | return r; |
||
1201 | } |
||
2997 | Serge | 1202 | ring->ready = true; |
3192 | Serge | 1203 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
1204 | |||
1205 | if (!ring->rptr_save_reg /* not resuming from suspend */ |
||
1206 | && radeon_ring_supports_scratch_reg(rdev, ring)) { |
||
1207 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); |
||
1208 | if (r) { |
||
1209 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); |
||
1210 | ring->rptr_save_reg = 0; |
||
1211 | } |
||
1212 | } |
||
1117 | serge | 1213 | return 0; |
1214 | } |
||
1215 | |||
1216 | void r100_cp_fini(struct radeon_device *rdev) |
||
1217 | { |
||
1179 | serge | 1218 | if (r100_cp_wait_for_idle(rdev)) { |
1219 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
||
1220 | } |
||
1117 | serge | 1221 | /* Disable ring */ |
1179 | serge | 1222 | r100_cp_disable(rdev); |
3192 | Serge | 1223 | radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); |
2997 | Serge | 1224 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1117 | serge | 1225 | DRM_INFO("radeon: cp finalized\n"); |
1226 | } |
||
1227 | |||
1228 | void r100_cp_disable(struct radeon_device *rdev) |
||
1229 | { |
||
1230 | /* Disable ring */ |
||
3192 | Serge | 1231 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
2997 | Serge | 1232 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1117 | serge | 1233 | WREG32(RADEON_CP_CSQ_MODE, 0); |
1234 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
1963 | serge | 1235 | WREG32(R_000770_SCRATCH_UMSK, 0); |
1117 | serge | 1236 | if (r100_gui_wait_for_idle(rdev)) { |
1237 | printk(KERN_WARNING "Failed to wait GUI idle while " |
||
1238 | "programming pipes. Bad things might happen.\n"); |
||
1239 | } |
||
1240 | } |
||
1241 | |||
2997 | Serge | 1242 | /* |
1243 | * CS functions |
||
1244 | */ |
||
1245 | int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
||
1246 | struct radeon_cs_packet *pkt, |
||
1247 | unsigned idx, |
||
1248 | unsigned reg) |
||
1179 | serge | 1249 | { |
2997 | Serge | 1250 | int r; |
1251 | u32 tile_flags = 0; |
||
1252 | u32 tmp; |
||
5271 | serge | 1253 | struct radeon_bo_list *reloc; |
2997 | Serge | 1254 | u32 value; |
1255 | |||
3764 | Serge | 1256 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
2997 | Serge | 1257 | if (r) { |
1258 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1259 | idx, reg); |
||
3764 | Serge | 1260 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1261 | return r; |
1262 | } |
||
1263 | |||
1264 | value = radeon_get_ib_value(p, idx); |
||
1265 | tmp = value & 0x003fffff; |
||
5078 | serge | 1266 | tmp += (((u32)reloc->gpu_offset) >> 10); |
2997 | Serge | 1267 | |
1268 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
||
5078 | serge | 1269 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
2997 | Serge | 1270 | tile_flags |= RADEON_DST_TILE_MACRO; |
5078 | serge | 1271 | if (reloc->tiling_flags & RADEON_TILING_MICRO) { |
2997 | Serge | 1272 | if (reg == RADEON_SRC_PITCH_OFFSET) { |
1273 | DRM_ERROR("Cannot src blit from microtiled surface\n"); |
||
3764 | Serge | 1274 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1275 | return -EINVAL; |
1276 | } |
||
1277 | tile_flags |= RADEON_DST_TILE_MICRO; |
||
1278 | } |
||
1279 | |||
1280 | tmp |= tile_flags; |
||
1281 | p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; |
||
1282 | } else |
||
1283 | p->ib.ptr[idx] = (value & 0xffc00000) | tmp; |
||
1284 | return 0; |
||
1179 | serge | 1285 | } |
1286 | |||
2997 | Serge | 1287 | int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, |
1288 | struct radeon_cs_packet *pkt, |
||
1289 | int idx) |
||
1290 | { |
||
1291 | unsigned c, i; |
||
5271 | serge | 1292 | struct radeon_bo_list *reloc; |
2997 | Serge | 1293 | struct r100_cs_track *track; |
1294 | int r = 0; |
||
1295 | volatile uint32_t *ib; |
||
1296 | u32 idx_value; |
||
1179 | serge | 1297 | |
2997 | Serge | 1298 | ib = p->ib.ptr; |
1299 | track = (struct r100_cs_track *)p->track; |
||
1300 | c = radeon_get_ib_value(p, idx++) & 0x1F; |
||
1301 | if (c > 16) { |
||
1302 | DRM_ERROR("Only 16 vertex buffers are allowed %d\n", |
||
1303 | pkt->opcode); |
||
3764 | Serge | 1304 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1305 | return -EINVAL; |
1306 | } |
||
1307 | track->num_arrays = c; |
||
1308 | for (i = 0; i < (c - 1); i+=2, idx+=3) { |
||
3764 | Serge | 1309 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
2997 | Serge | 1310 | if (r) { |
1311 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1312 | pkt->opcode); |
||
3764 | Serge | 1313 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1314 | return r; |
1315 | } |
||
1316 | idx_value = radeon_get_ib_value(p, idx); |
||
5078 | serge | 1317 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
2997 | Serge | 1318 | |
1319 | track->arrays[i + 0].esize = idx_value >> 8; |
||
1320 | track->arrays[i + 0].robj = reloc->robj; |
||
1321 | track->arrays[i + 0].esize &= 0x7F; |
||
3764 | Serge | 1322 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
2997 | Serge | 1323 | if (r) { |
1324 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1325 | pkt->opcode); |
||
3764 | Serge | 1326 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1327 | return r; |
1328 | } |
||
5078 | serge | 1329 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); |
2997 | Serge | 1330 | track->arrays[i + 1].robj = reloc->robj; |
1331 | track->arrays[i + 1].esize = idx_value >> 24; |
||
1332 | track->arrays[i + 1].esize &= 0x7F; |
||
1333 | } |
||
1334 | if (c & 1) { |
||
3764 | Serge | 1335 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
2997 | Serge | 1336 | if (r) { |
1337 | DRM_ERROR("No reloc for packet3 %d\n", |
||
1338 | pkt->opcode); |
||
3764 | Serge | 1339 | radeon_cs_dump_packet(p, pkt); |
2997 | Serge | 1340 | return r; |
1341 | } |
||
1342 | idx_value = radeon_get_ib_value(p, idx); |
||
5078 | serge | 1343 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
2997 | Serge | 1344 | track->arrays[i + 0].robj = reloc->robj; |
1345 | track->arrays[i + 0].esize = idx_value >> 8; |
||
1346 | track->arrays[i + 0].esize &= 0x7F; |
||
1347 | } |
||
1348 | return r; |
||
1349 | } |
||
1350 | |||
1117 | serge | 1351 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1352 | struct radeon_cs_packet *pkt, |
||
1353 | const unsigned *auth, unsigned n, |
||
1354 | radeon_packet0_check_t check) |
||
1355 | { |
||
1356 | unsigned reg; |
||
1357 | unsigned i, j, m; |
||
1358 | unsigned idx; |
||
1359 | int r; |
||
1360 | |||
1361 | idx = pkt->idx + 1; |
||
1362 | reg = pkt->reg; |
||
1363 | /* Check that register fall into register range |
||
1364 | * determined by the number of entry (n) in the |
||
1365 | * safe register bitmap. |
||
1366 | */ |
||
1367 | if (pkt->one_reg_wr) { |
||
1368 | if ((reg >> 7) > n) { |
||
1369 | return -EINVAL; |
||
1370 | } |
||
1371 | } else { |
||
1372 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
||
1373 | return -EINVAL; |
||
1374 | } |
||
1375 | } |
||
1376 | for (i = 0; i <= pkt->count; i++, idx++) { |
||
1377 | j = (reg >> 7); |
||
1378 | m = 1 << ((reg >> 2) & 31); |
||
1379 | if (auth[j] & m) { |
||
1380 | r = check(p, pkt, idx, reg); |
||
1381 | if (r) { |
||
1382 | return r; |
||
1383 | } |
||
1384 | } |
||
1385 | if (pkt->one_reg_wr) { |
||
1386 | if (!(auth[j] & m)) { |
||
1387 | break; |
||
1388 | } |
||
1389 | } else { |
||
1390 | reg += 4; |
||
1391 | } |
||
1392 | } |
||
1393 | return 0; |
||
1394 | } |
||
1395 | |||
1396 | /** |
||
1179 | serge | 1397 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
1398 | * @parser: parser structure holding parsing context. |
||
1399 | * |
||
1400 | * Userspace sends a special sequence for VLINE waits. |
||
1401 | * PACKET0 - VLINE_START_END + value |
||
1402 | * PACKET0 - WAIT_UNTIL +_value |
||
1403 | * RELOC (P3) - crtc_id in reloc. |
||
1404 | * |
||
1405 | * This function parses this and relocates the VLINE START END |
||
1406 | * and WAIT UNTIL packets to the correct crtc. |
||
1407 | * It also detects a switched off crtc and nulls out the |
||
1408 | * wait in that case. |
||
1409 | */ |
||
1410 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
||
1411 | { |
||
1412 | struct drm_crtc *crtc; |
||
1413 | struct radeon_crtc *radeon_crtc; |
||
1414 | struct radeon_cs_packet p3reloc, waitreloc; |
||
1415 | int crtc_id; |
||
1416 | int r; |
||
1417 | uint32_t header, h_idx, reg; |
||
1221 | serge | 1418 | volatile uint32_t *ib; |
1179 | serge | 1419 | |
2997 | Serge | 1420 | ib = p->ib.ptr; |
1179 | serge | 1421 | |
1422 | /* parse the wait until */ |
||
3764 | Serge | 1423 | r = radeon_cs_packet_parse(p, &waitreloc, p->idx); |
1179 | serge | 1424 | if (r) |
1425 | return r; |
||
1426 | |||
1427 | /* check its a wait until and only 1 count */ |
||
1428 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
||
1429 | waitreloc.count != 0) { |
||
1430 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
||
1963 | serge | 1431 | return -EINVAL; |
1179 | serge | 1432 | } |
1433 | |||
1221 | serge | 1434 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
1179 | serge | 1435 | DRM_ERROR("vline wait had illegal wait until\n"); |
1963 | serge | 1436 | return -EINVAL; |
1179 | serge | 1437 | } |
1438 | |||
1439 | /* jump over the NOP */ |
||
3764 | Serge | 1440 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
1179 | serge | 1441 | if (r) |
1442 | return r; |
||
1443 | |||
1444 | h_idx = p->idx - 2; |
||
1221 | serge | 1445 | p->idx += waitreloc.count + 2; |
1446 | p->idx += p3reloc.count + 2; |
||
1179 | serge | 1447 | |
1221 | serge | 1448 | header = radeon_get_ib_value(p, h_idx); |
1449 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
||
3764 | Serge | 1450 | reg = R100_CP_PACKET0_GET_REG(header); |
5078 | serge | 1451 | crtc = drm_crtc_find(p->rdev->ddev, crtc_id); |
1452 | if (!crtc) { |
||
1179 | serge | 1453 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
5078 | serge | 1454 | return -ENOENT; |
1179 | serge | 1455 | } |
1456 | radeon_crtc = to_radeon_crtc(crtc); |
||
1457 | crtc_id = radeon_crtc->crtc_id; |
||
1458 | |||
1459 | if (!crtc->enabled) { |
||
1460 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
||
1221 | serge | 1461 | ib[h_idx + 2] = PACKET2(0); |
1462 | ib[h_idx + 3] = PACKET2(0); |
||
1179 | serge | 1463 | } else if (crtc_id == 1) { |
1464 | switch (reg) { |
||
1465 | case AVIVO_D1MODE_VLINE_START_END: |
||
1221 | serge | 1466 | header &= ~R300_CP_PACKET0_REG_MASK; |
1179 | serge | 1467 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1468 | break; |
||
1469 | case RADEON_CRTC_GUI_TRIG_VLINE: |
||
1221 | serge | 1470 | header &= ~R300_CP_PACKET0_REG_MASK; |
1179 | serge | 1471 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1472 | break; |
||
1473 | default: |
||
1474 | DRM_ERROR("unknown crtc reloc\n"); |
||
1963 | serge | 1475 | return -EINVAL; |
1179 | serge | 1476 | } |
1221 | serge | 1477 | ib[h_idx] = header; |
1478 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
||
1179 | serge | 1479 | } |
1963 | serge | 1480 | |
1481 | return 0; |
||
1179 | serge | 1482 | } |
1483 | |||
1484 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
||
1485 | { |
||
1486 | int vtx_size; |
||
1487 | vtx_size = 2; |
||
1488 | /* ordered according to bits in spec */ |
||
1489 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
||
1490 | vtx_size++; |
||
1491 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
||
1492 | vtx_size += 3; |
||
1493 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
||
1494 | vtx_size++; |
||
1495 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
||
1496 | vtx_size++; |
||
1497 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
||
1498 | vtx_size += 3; |
||
1499 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
||
1500 | vtx_size++; |
||
1501 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
||
1502 | vtx_size++; |
||
1503 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
||
1504 | vtx_size += 2; |
||
1505 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
||
1506 | vtx_size += 2; |
||
1507 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
||
1508 | vtx_size++; |
||
1509 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
||
1510 | vtx_size += 2; |
||
1511 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
||
1512 | vtx_size++; |
||
1513 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
||
1514 | vtx_size += 2; |
||
1515 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
||
1516 | vtx_size++; |
||
1517 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
||
1518 | vtx_size++; |
||
1519 | /* blend weight */ |
||
1520 | if (vtx_fmt & (0x7 << 15)) |
||
1521 | vtx_size += (vtx_fmt >> 15) & 0x7; |
||
1522 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
||
1523 | vtx_size += 3; |
||
1524 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
||
1525 | vtx_size += 2; |
||
1526 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
||
1527 | vtx_size++; |
||
1528 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
||
1529 | vtx_size++; |
||
1530 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
||
1531 | vtx_size++; |
||
1532 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
||
1533 | vtx_size++; |
||
1534 | return vtx_size; |
||
1535 | } |
||
1536 | |||
1117 | serge | 1537 | static int r100_packet0_check(struct radeon_cs_parser *p, |
1179 | serge | 1538 | struct radeon_cs_packet *pkt, |
1539 | unsigned idx, unsigned reg) |
||
1117 | serge | 1540 | { |
5271 | serge | 1541 | struct radeon_bo_list *reloc; |
1179 | serge | 1542 | struct r100_cs_track *track; |
1117 | serge | 1543 | volatile uint32_t *ib; |
1544 | uint32_t tmp; |
||
1545 | int r; |
||
1179 | serge | 1546 | int i, face; |
1547 | u32 tile_flags = 0; |
||
1221 | serge | 1548 | u32 idx_value; |
1117 | serge | 1549 | |
2997 | Serge | 1550 | ib = p->ib.ptr; |
1179 | serge | 1551 | track = (struct r100_cs_track *)p->track; |
1552 | |||
1221 | serge | 1553 | idx_value = radeon_get_ib_value(p, idx); |
1554 | |||
1117 | serge | 1555 | switch (reg) { |
1179 | serge | 1556 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1557 | r = r100_cs_packet_parse_vline(p); |
||
1558 | if (r) { |
||
1559 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1560 | idx, reg); |
||
3764 | Serge | 1561 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1562 | return r; |
1563 | } |
||
1564 | break; |
||
1117 | serge | 1565 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1566 | * range access */ |
||
1567 | case RADEON_DST_PITCH_OFFSET: |
||
1568 | case RADEON_SRC_PITCH_OFFSET: |
||
1179 | serge | 1569 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
1570 | if (r) |
||
1571 | return r; |
||
1572 | break; |
||
1573 | case RADEON_RB3D_DEPTHOFFSET: |
||
3764 | Serge | 1574 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1117 | serge | 1575 | if (r) { |
1576 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1577 | idx, reg); |
||
3764 | Serge | 1578 | radeon_cs_dump_packet(p, pkt); |
1117 | serge | 1579 | return r; |
1580 | } |
||
1179 | serge | 1581 | track->zb.robj = reloc->robj; |
1221 | serge | 1582 | track->zb.offset = idx_value; |
1963 | serge | 1583 | track->zb_dirty = true; |
5078 | serge | 1584 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1117 | serge | 1585 | break; |
1586 | case RADEON_RB3D_COLOROFFSET: |
||
3764 | Serge | 1587 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1588 | if (r) { |
1589 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1590 | idx, reg); |
||
3764 | Serge | 1591 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1592 | return r; |
1593 | } |
||
1594 | track->cb[0].robj = reloc->robj; |
||
1221 | serge | 1595 | track->cb[0].offset = idx_value; |
1963 | serge | 1596 | track->cb_dirty = true; |
5078 | serge | 1597 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1598 | break; |
1117 | serge | 1599 | case RADEON_PP_TXOFFSET_0: |
1600 | case RADEON_PP_TXOFFSET_1: |
||
1601 | case RADEON_PP_TXOFFSET_2: |
||
1179 | serge | 1602 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
3764 | Serge | 1603 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1604 | if (r) { |
1605 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1606 | idx, reg); |
||
3764 | Serge | 1607 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1608 | return r; |
1609 | } |
||
2997 | Serge | 1610 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
5078 | serge | 1611 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
2997 | Serge | 1612 | tile_flags |= RADEON_TXO_MACRO_TILE; |
5078 | serge | 1613 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
2997 | Serge | 1614 | tile_flags |= RADEON_TXO_MICRO_TILE_X2; |
1615 | |||
1616 | tmp = idx_value & ~(0x7 << 2); |
||
1617 | tmp |= tile_flags; |
||
5078 | serge | 1618 | ib[idx] = tmp + ((u32)reloc->gpu_offset); |
2997 | Serge | 1619 | } else |
5078 | serge | 1620 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1621 | track->textures[i].robj = reloc->robj; |
1963 | serge | 1622 | track->tex_dirty = true; |
1179 | serge | 1623 | break; |
1624 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
||
1625 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
||
1626 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
||
1627 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
||
1628 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
||
1629 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
||
3764 | Serge | 1630 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1631 | if (r) { |
1632 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1633 | idx, reg); |
||
3764 | Serge | 1634 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1635 | return r; |
1636 | } |
||
1221 | serge | 1637 | track->textures[0].cube_info[i].offset = idx_value; |
5078 | serge | 1638 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1639 | track->textures[0].cube_info[i].robj = reloc->robj; |
1963 | serge | 1640 | track->tex_dirty = true; |
1179 | serge | 1641 | break; |
1642 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
||
1643 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
||
1644 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
||
1645 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
||
1646 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
||
1647 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
||
3764 | Serge | 1648 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1649 | if (r) { |
1650 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1651 | idx, reg); |
||
3764 | Serge | 1652 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1653 | return r; |
1654 | } |
||
1221 | serge | 1655 | track->textures[1].cube_info[i].offset = idx_value; |
5078 | serge | 1656 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1657 | track->textures[1].cube_info[i].robj = reloc->robj; |
1963 | serge | 1658 | track->tex_dirty = true; |
1179 | serge | 1659 | break; |
1660 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
||
1661 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
||
1662 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
||
1663 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
||
1664 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
||
1665 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
||
3764 | Serge | 1666 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1117 | serge | 1667 | if (r) { |
1668 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1669 | idx, reg); |
||
3764 | Serge | 1670 | radeon_cs_dump_packet(p, pkt); |
1117 | serge | 1671 | return r; |
1672 | } |
||
1221 | serge | 1673 | track->textures[2].cube_info[i].offset = idx_value; |
5078 | serge | 1674 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1675 | track->textures[2].cube_info[i].robj = reloc->robj; |
1963 | serge | 1676 | track->tex_dirty = true; |
1179 | serge | 1677 | break; |
1678 | case RADEON_RE_WIDTH_HEIGHT: |
||
1221 | serge | 1679 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1963 | serge | 1680 | track->cb_dirty = true; |
1681 | track->zb_dirty = true; |
||
1117 | serge | 1682 | break; |
1179 | serge | 1683 | case RADEON_RB3D_COLORPITCH: |
3764 | Serge | 1684 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1685 | if (r) { |
1686 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1687 | idx, reg); |
||
3764 | Serge | 1688 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1689 | return r; |
1690 | } |
||
2997 | Serge | 1691 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
5078 | serge | 1692 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
1179 | serge | 1693 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
5078 | serge | 1694 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
1179 | serge | 1695 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1696 | |||
1221 | serge | 1697 | tmp = idx_value & ~(0x7 << 16); |
1179 | serge | 1698 | tmp |= tile_flags; |
1699 | ib[idx] = tmp; |
||
2997 | Serge | 1700 | } else |
1701 | ib[idx] = idx_value; |
||
1179 | serge | 1702 | |
1221 | serge | 1703 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1963 | serge | 1704 | track->cb_dirty = true; |
1179 | serge | 1705 | break; |
1706 | case RADEON_RB3D_DEPTHPITCH: |
||
1221 | serge | 1707 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1963 | serge | 1708 | track->zb_dirty = true; |
1179 | serge | 1709 | break; |
1710 | case RADEON_RB3D_CNTL: |
||
1221 | serge | 1711 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1179 | serge | 1712 | case 7: |
1713 | case 8: |
||
1714 | case 9: |
||
1715 | case 11: |
||
1716 | case 12: |
||
1717 | track->cb[0].cpp = 1; |
||
1718 | break; |
||
1719 | case 3: |
||
1720 | case 4: |
||
1721 | case 15: |
||
1722 | track->cb[0].cpp = 2; |
||
1723 | break; |
||
1724 | case 6: |
||
1725 | track->cb[0].cpp = 4; |
||
1726 | break; |
||
1117 | serge | 1727 | default: |
1179 | serge | 1728 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1221 | serge | 1729 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1179 | serge | 1730 | return -EINVAL; |
1731 | } |
||
1221 | serge | 1732 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1963 | serge | 1733 | track->cb_dirty = true; |
1734 | track->zb_dirty = true; |
||
1179 | serge | 1735 | break; |
1736 | case RADEON_RB3D_ZSTENCILCNTL: |
||
1221 | serge | 1737 | switch (idx_value & 0xf) { |
1179 | serge | 1738 | case 0: |
1739 | track->zb.cpp = 2; |
||
1117 | serge | 1740 | break; |
1179 | serge | 1741 | case 2: |
1742 | case 3: |
||
1743 | case 4: |
||
1744 | case 5: |
||
1745 | case 9: |
||
1746 | case 11: |
||
1747 | track->zb.cpp = 4; |
||
1748 | break; |
||
1749 | default: |
||
1750 | break; |
||
1117 | serge | 1751 | } |
1963 | serge | 1752 | track->zb_dirty = true; |
1117 | serge | 1753 | break; |
1179 | serge | 1754 | case RADEON_RB3D_ZPASS_ADDR: |
3764 | Serge | 1755 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1179 | serge | 1756 | if (r) { |
1757 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
||
1758 | idx, reg); |
||
3764 | Serge | 1759 | radeon_cs_dump_packet(p, pkt); |
1179 | serge | 1760 | return r; |
1761 | } |
||
5078 | serge | 1762 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
1179 | serge | 1763 | break; |
1764 | case RADEON_PP_CNTL: |
||
1765 | { |
||
1221 | serge | 1766 | uint32_t temp = idx_value >> 4; |
1179 | serge | 1767 | for (i = 0; i < track->num_texture; i++) |
1768 | track->textures[i].enabled = !!(temp & (1 << i)); |
||
1963 | serge | 1769 | track->tex_dirty = true; |
1117 | serge | 1770 | } |
1179 | serge | 1771 | break; |
1772 | case RADEON_SE_VF_CNTL: |
||
1221 | serge | 1773 | track->vap_vf_cntl = idx_value; |
1179 | serge | 1774 | break; |
1775 | case RADEON_SE_VTX_FMT: |
||
1221 | serge | 1776 | track->vtx_size = r100_get_vtx_size(idx_value); |
1179 | serge | 1777 | break; |
1778 | case RADEON_PP_TEX_SIZE_0: |
||
1779 | case RADEON_PP_TEX_SIZE_1: |
||
1780 | case RADEON_PP_TEX_SIZE_2: |
||
1781 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
||
1221 | serge | 1782 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1783 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
||
1963 | serge | 1784 | track->tex_dirty = true; |
1179 | serge | 1785 | break; |
1786 | case RADEON_PP_TEX_PITCH_0: |
||
1787 | case RADEON_PP_TEX_PITCH_1: |
||
1788 | case RADEON_PP_TEX_PITCH_2: |
||
1789 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
||
1221 | serge | 1790 | track->textures[i].pitch = idx_value + 32; |
1963 | serge | 1791 | track->tex_dirty = true; |
1179 | serge | 1792 | break; |
1793 | case RADEON_PP_TXFILTER_0: |
||
1794 | case RADEON_PP_TXFILTER_1: |
||
1795 | case RADEON_PP_TXFILTER_2: |
||
1796 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
||
1221 | serge | 1797 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
1179 | serge | 1798 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
1221 | serge | 1799 | tmp = (idx_value >> 23) & 0x7; |
1179 | serge | 1800 | if (tmp == 2 || tmp == 6) |
1801 | track->textures[i].roundup_w = false; |
||
1221 | serge | 1802 | tmp = (idx_value >> 27) & 0x7; |
1179 | serge | 1803 | if (tmp == 2 || tmp == 6) |
1804 | track->textures[i].roundup_h = false; |
||
1963 | serge | 1805 | track->tex_dirty = true; |
1179 | serge | 1806 | break; |
1807 | case RADEON_PP_TXFORMAT_0: |
||
1808 | case RADEON_PP_TXFORMAT_1: |
||
1809 | case RADEON_PP_TXFORMAT_2: |
||
1810 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
||
1221 | serge | 1811 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
1179 | serge | 1812 | track->textures[i].use_pitch = 1; |
1813 | } else { |
||
1814 | track->textures[i].use_pitch = 0; |
||
1221 | serge | 1815 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1816 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
||
1179 | serge | 1817 | } |
1221 | serge | 1818 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
1179 | serge | 1819 | track->textures[i].tex_coord_type = 2; |
1221 | serge | 1820 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1179 | serge | 1821 | case RADEON_TXFORMAT_I8: |
1822 | case RADEON_TXFORMAT_RGB332: |
||
1823 | case RADEON_TXFORMAT_Y8: |
||
1824 | track->textures[i].cpp = 1; |
||
1963 | serge | 1825 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1179 | serge | 1826 | break; |
1827 | case RADEON_TXFORMAT_AI88: |
||
1828 | case RADEON_TXFORMAT_ARGB1555: |
||
1829 | case RADEON_TXFORMAT_RGB565: |
||
1830 | case RADEON_TXFORMAT_ARGB4444: |
||
1831 | case RADEON_TXFORMAT_VYUY422: |
||
1832 | case RADEON_TXFORMAT_YVYU422: |
||
1833 | case RADEON_TXFORMAT_SHADOW16: |
||
1834 | case RADEON_TXFORMAT_LDUDV655: |
||
1835 | case RADEON_TXFORMAT_DUDV88: |
||
1836 | track->textures[i].cpp = 2; |
||
1963 | serge | 1837 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1179 | serge | 1838 | break; |
1839 | case RADEON_TXFORMAT_ARGB8888: |
||
1840 | case RADEON_TXFORMAT_RGBA8888: |
||
1841 | case RADEON_TXFORMAT_SHADOW32: |
||
1842 | case RADEON_TXFORMAT_LDUDUV8888: |
||
1843 | track->textures[i].cpp = 4; |
||
1963 | serge | 1844 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
1179 | serge | 1845 | break; |
1403 | serge | 1846 | case RADEON_TXFORMAT_DXT1: |
1847 | track->textures[i].cpp = 1; |
||
1848 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
||
1849 | break; |
||
1850 | case RADEON_TXFORMAT_DXT23: |
||
1851 | case RADEON_TXFORMAT_DXT45: |
||
1852 | track->textures[i].cpp = 1; |
||
1853 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
||
1854 | break; |
||
1179 | serge | 1855 | } |
1221 | serge | 1856 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1857 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
||
1963 | serge | 1858 | track->tex_dirty = true; |
1179 | serge | 1859 | break; |
1860 | case RADEON_PP_CUBIC_FACES_0: |
||
1861 | case RADEON_PP_CUBIC_FACES_1: |
||
1862 | case RADEON_PP_CUBIC_FACES_2: |
||
1221 | serge | 1863 | tmp = idx_value; |
1179 | serge | 1864 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1865 | for (face = 0; face < 4; face++) { |
||
1866 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
||
1867 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
||
1868 | } |
||
1963 | serge | 1869 | track->tex_dirty = true; |
1179 | serge | 1870 | break; |
1871 | default: |
||
1872 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
||
1873 | reg, idx); |
||
1874 | return -EINVAL; |
||
1117 | serge | 1875 | } |
1876 | return 0; |
||
1877 | } |
||
1878 | |||
1879 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
||
1880 | struct radeon_cs_packet *pkt, |
||
1321 | serge | 1881 | struct radeon_bo *robj) |
1117 | serge | 1882 | { |
1883 | unsigned idx; |
||
1221 | serge | 1884 | u32 value; |
1117 | serge | 1885 | idx = pkt->idx + 1; |
1221 | serge | 1886 | value = radeon_get_ib_value(p, idx + 2); |
1321 | serge | 1887 | if ((value + 1) > radeon_bo_size(robj)) { |
1117 | serge | 1888 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1889 | "(need %u have %lu) !\n", |
||
1221 | serge | 1890 | value + 1, |
1321 | serge | 1891 | radeon_bo_size(robj)); |
1117 | serge | 1892 | return -EINVAL; |
1893 | } |
||
1894 | return 0; |
||
1895 | } |
||
1896 | |||
1897 | static int r100_packet3_check(struct radeon_cs_parser *p, |
||
1898 | struct radeon_cs_packet *pkt) |
||
1899 | { |
||
5271 | serge | 1900 | struct radeon_bo_list *reloc; |
1179 | serge | 1901 | struct r100_cs_track *track; |
1117 | serge | 1902 | unsigned idx; |
1903 | volatile uint32_t *ib; |
||
1904 | int r; |
||
1905 | |||
2997 | Serge | 1906 | ib = p->ib.ptr; |
1117 | serge | 1907 | idx = pkt->idx + 1; |
1179 | serge | 1908 | track = (struct r100_cs_track *)p->track; |
1117 | serge | 1909 | switch (pkt->opcode) { |
1910 | case PACKET3_3D_LOAD_VBPNTR: |
||
1221 | serge | 1911 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1912 | if (r) |
||
1117 | serge | 1913 | return r; |
1914 | break; |
||
1915 | case PACKET3_INDX_BUFFER: |
||
3764 | Serge | 1916 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1117 | serge | 1917 | if (r) { |
1918 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
3764 | Serge | 1919 | radeon_cs_dump_packet(p, pkt); |
1117 | serge | 1920 | return r; |
1921 | } |
||
5078 | serge | 1922 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); |
1117 | serge | 1923 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1924 | if (r) { |
||
1925 | return r; |
||
1926 | } |
||
1927 | break; |
||
1928 | case 0x23: |
||
1929 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
||
3764 | Serge | 1930 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
1117 | serge | 1931 | if (r) { |
1932 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
||
3764 | Serge | 1933 | radeon_cs_dump_packet(p, pkt); |
1117 | serge | 1934 | return r; |
1935 | } |
||
5078 | serge | 1936 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); |
1179 | serge | 1937 | track->num_arrays = 1; |
1221 | serge | 1938 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1179 | serge | 1939 | |
1940 | track->arrays[0].robj = reloc->robj; |
||
1941 | track->arrays[0].esize = track->vtx_size; |
||
1942 | |||
1221 | serge | 1943 | track->max_indx = radeon_get_ib_value(p, idx+1); |
1179 | serge | 1944 | |
1221 | serge | 1945 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
1179 | serge | 1946 | track->immd_dwords = pkt->count - 1; |
1947 | r = r100_cs_track_check(p->rdev, track); |
||
1948 | if (r) |
||
1949 | return r; |
||
1117 | serge | 1950 | break; |
1951 | case PACKET3_3D_DRAW_IMMD: |
||
1221 | serge | 1952 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1179 | serge | 1953 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1954 | return -EINVAL; |
||
1955 | } |
||
1403 | serge | 1956 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
1221 | serge | 1957 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1958 | track->immd_dwords = pkt->count - 1; |
1959 | r = r100_cs_track_check(p->rdev, track); |
||
1960 | if (r) |
||
1961 | return r; |
||
1962 | break; |
||
1117 | serge | 1963 | /* triggers drawing using in-packet vertex data */ |
1964 | case PACKET3_3D_DRAW_IMMD_2: |
||
1221 | serge | 1965 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1179 | serge | 1966 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1967 | return -EINVAL; |
||
1968 | } |
||
1221 | serge | 1969 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1970 | track->immd_dwords = pkt->count; |
1971 | r = r100_cs_track_check(p->rdev, track); |
||
1972 | if (r) |
||
1973 | return r; |
||
1974 | break; |
||
1117 | serge | 1975 | /* triggers drawing using in-packet vertex data */ |
1976 | case PACKET3_3D_DRAW_VBUF_2: |
||
1221 | serge | 1977 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1978 | r = r100_cs_track_check(p->rdev, track); |
1979 | if (r) |
||
1980 | return r; |
||
1981 | break; |
||
1117 | serge | 1982 | /* triggers drawing of vertex buffers setup elsewhere */ |
1983 | case PACKET3_3D_DRAW_INDX_2: |
||
1221 | serge | 1984 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1179 | serge | 1985 | r = r100_cs_track_check(p->rdev, track); |
1986 | if (r) |
||
1987 | return r; |
||
1988 | break; |
||
1117 | serge | 1989 | /* triggers drawing using indices to vertex buffer */ |
1990 | case PACKET3_3D_DRAW_VBUF: |
||
1221 | serge | 1991 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1992 | r = r100_cs_track_check(p->rdev, track); |
1993 | if (r) |
||
1994 | return r; |
||
1995 | break; |
||
1117 | serge | 1996 | /* triggers drawing of vertex buffers setup elsewhere */ |
1997 | case PACKET3_3D_DRAW_INDX: |
||
1221 | serge | 1998 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1179 | serge | 1999 | r = r100_cs_track_check(p->rdev, track); |
2000 | if (r) |
||
2001 | return r; |
||
2002 | break; |
||
1117 | serge | 2003 | /* triggers drawing using indices to vertex buffer */ |
1963 | serge | 2004 | case PACKET3_3D_CLEAR_HIZ: |
2005 | case PACKET3_3D_CLEAR_ZMASK: |
||
2006 | if (p->rdev->hyperz_filp != p->filp) |
||
2007 | return -EINVAL; |
||
2008 | break; |
||
1117 | serge | 2009 | case PACKET3_NOP: |
2010 | break; |
||
2011 | default: |
||
2012 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
||
2013 | return -EINVAL; |
||
2014 | } |
||
2015 | return 0; |
||
2016 | } |
||
2017 | |||
2018 | int r100_cs_parse(struct radeon_cs_parser *p) |
||
2019 | { |
||
2020 | struct radeon_cs_packet pkt; |
||
1179 | serge | 2021 | struct r100_cs_track *track; |
1117 | serge | 2022 | int r; |
2023 | |||
1179 | serge | 2024 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
2997 | Serge | 2025 | if (!track) |
2026 | return -ENOMEM; |
||
1179 | serge | 2027 | r100_cs_track_clear(p->rdev, track); |
2028 | p->track = track; |
||
1117 | serge | 2029 | do { |
3764 | Serge | 2030 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
1117 | serge | 2031 | if (r) { |
2032 | return r; |
||
2033 | } |
||
2034 | p->idx += pkt.count + 2; |
||
2035 | switch (pkt.type) { |
||
3764 | Serge | 2036 | case RADEON_PACKET_TYPE0: |
1179 | serge | 2037 | if (p->rdev->family >= CHIP_R200) |
2038 | r = r100_cs_parse_packet0(p, &pkt, |
||
2039 | p->rdev->config.r100.reg_safe_bm, |
||
2040 | p->rdev->config.r100.reg_safe_bm_size, |
||
2041 | &r200_packet0_check); |
||
2042 | else |
||
2043 | r = r100_cs_parse_packet0(p, &pkt, |
||
2044 | p->rdev->config.r100.reg_safe_bm, |
||
2045 | p->rdev->config.r100.reg_safe_bm_size, |
||
2046 | &r100_packet0_check); |
||
1117 | serge | 2047 | break; |
3764 | Serge | 2048 | case RADEON_PACKET_TYPE2: |
1117 | serge | 2049 | break; |
3764 | Serge | 2050 | case RADEON_PACKET_TYPE3: |
1117 | serge | 2051 | r = r100_packet3_check(p, &pkt); |
2052 | break; |
||
2053 | default: |
||
2054 | DRM_ERROR("Unknown packet type %d !\n", |
||
2055 | pkt.type); |
||
2056 | return -EINVAL; |
||
2057 | } |
||
3764 | Serge | 2058 | if (r) |
1117 | serge | 2059 | return r; |
5271 | serge | 2060 | } while (p->idx < p->chunk_ib->length_dw); |
1117 | serge | 2061 | return 0; |
2062 | } |
||
2063 | |||
2997 | Serge | 2064 | static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
2065 | { |
||
2066 | DRM_ERROR("pitch %d\n", t->pitch); |
||
2067 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
||
2068 | DRM_ERROR("width %d\n", t->width); |
||
2069 | DRM_ERROR("width_11 %d\n", t->width_11); |
||
2070 | DRM_ERROR("height %d\n", t->height); |
||
2071 | DRM_ERROR("height_11 %d\n", t->height_11); |
||
2072 | DRM_ERROR("num levels %d\n", t->num_levels); |
||
2073 | DRM_ERROR("depth %d\n", t->txdepth); |
||
2074 | DRM_ERROR("bpp %d\n", t->cpp); |
||
2075 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
||
2076 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
||
2077 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
||
2078 | DRM_ERROR("compress format %d\n", t->compress_format); |
||
2079 | } |
||
1117 | serge | 2080 | |
2997 | Serge | 2081 | static int r100_track_compress_size(int compress_format, int w, int h) |
1117 | serge | 2082 | { |
2997 | Serge | 2083 | int block_width, block_height, block_bytes; |
2084 | int wblocks, hblocks; |
||
2085 | int min_wblocks; |
||
2086 | int sz; |
||
1117 | serge | 2087 | |
2997 | Serge | 2088 | block_width = 4; |
2089 | block_height = 4; |
||
2090 | |||
2091 | switch (compress_format) { |
||
2092 | case R100_TRACK_COMP_DXT1: |
||
2093 | block_bytes = 8; |
||
2094 | min_wblocks = 4; |
||
2095 | break; |
||
2096 | default: |
||
2097 | case R100_TRACK_COMP_DXT35: |
||
2098 | block_bytes = 16; |
||
2099 | min_wblocks = 2; |
||
2100 | break; |
||
1117 | serge | 2101 | } |
2102 | |||
2997 | Serge | 2103 | hblocks = (h + block_height - 1) / block_height; |
2104 | wblocks = (w + block_width - 1) / block_width; |
||
2105 | if (wblocks < min_wblocks) |
||
2106 | wblocks = min_wblocks; |
||
2107 | sz = wblocks * hblocks * block_bytes; |
||
2108 | return sz; |
||
2109 | } |
||
2110 | |||
2111 | static int r100_cs_track_cube(struct radeon_device *rdev, |
||
2112 | struct r100_cs_track *track, unsigned idx) |
||
2113 | { |
||
2114 | unsigned face, w, h; |
||
2115 | struct radeon_bo *cube_robj; |
||
2116 | unsigned long size; |
||
2117 | unsigned compress_format = track->textures[idx].compress_format; |
||
2118 | |||
2119 | for (face = 0; face < 5; face++) { |
||
2120 | cube_robj = track->textures[idx].cube_info[face].robj; |
||
2121 | w = track->textures[idx].cube_info[face].width; |
||
2122 | h = track->textures[idx].cube_info[face].height; |
||
2123 | |||
2124 | if (compress_format) { |
||
2125 | size = r100_track_compress_size(compress_format, w, h); |
||
2126 | } else |
||
2127 | size = w * h; |
||
2128 | size *= track->textures[idx].cpp; |
||
2129 | |||
2130 | size += track->textures[idx].cube_info[face].offset; |
||
2131 | |||
2132 | if (size > radeon_bo_size(cube_robj)) { |
||
2133 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
||
2134 | size, radeon_bo_size(cube_robj)); |
||
2135 | r100_cs_track_texture_print(&track->textures[idx]); |
||
2136 | return -1; |
||
2137 | } |
||
1117 | serge | 2138 | } |
2997 | Serge | 2139 | return 0; |
1117 | serge | 2140 | } |
2141 | |||
2997 | Serge | 2142 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
2143 | struct r100_cs_track *track) |
||
1117 | serge | 2144 | { |
2997 | Serge | 2145 | struct radeon_bo *robj; |
2146 | unsigned long size; |
||
2147 | unsigned u, i, w, h, d; |
||
2148 | int ret; |
||
1117 | serge | 2149 | |
2997 | Serge | 2150 | for (u = 0; u < track->num_texture; u++) { |
2151 | if (!track->textures[u].enabled) |
||
2152 | continue; |
||
2153 | if (track->textures[u].lookup_disable) |
||
2154 | continue; |
||
2155 | robj = track->textures[u].robj; |
||
2156 | if (robj == NULL) { |
||
2157 | DRM_ERROR("No texture bound to unit %u\n", u); |
||
2158 | return -EINVAL; |
||
2159 | } |
||
2160 | size = 0; |
||
2161 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
||
2162 | if (track->textures[u].use_pitch) { |
||
2163 | if (rdev->family < CHIP_R300) |
||
2164 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); |
||
2165 | else |
||
2166 | w = track->textures[u].pitch / (1 << i); |
||
2167 | } else { |
||
2168 | w = track->textures[u].width; |
||
2169 | if (rdev->family >= CHIP_RV515) |
||
2170 | w |= track->textures[u].width_11; |
||
2171 | w = w / (1 << i); |
||
2172 | if (track->textures[u].roundup_w) |
||
2173 | w = roundup_pow_of_two(w); |
||
2174 | } |
||
2175 | h = track->textures[u].height; |
||
2176 | if (rdev->family >= CHIP_RV515) |
||
2177 | h |= track->textures[u].height_11; |
||
2178 | h = h / (1 << i); |
||
2179 | if (track->textures[u].roundup_h) |
||
2180 | h = roundup_pow_of_two(h); |
||
2181 | if (track->textures[u].tex_coord_type == 1) { |
||
2182 | d = (1 << track->textures[u].txdepth) / (1 << i); |
||
2183 | if (!d) |
||
2184 | d = 1; |
||
2185 | } else { |
||
2186 | d = 1; |
||
2187 | } |
||
2188 | if (track->textures[u].compress_format) { |
||
2189 | |||
2190 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
||
2191 | /* compressed textures are block based */ |
||
2192 | } else |
||
2193 | size += w * h * d; |
||
2194 | } |
||
2195 | size *= track->textures[u].cpp; |
||
2196 | |||
2197 | switch (track->textures[u].tex_coord_type) { |
||
2198 | case 0: |
||
2199 | case 1: |
||
2200 | break; |
||
2201 | case 2: |
||
2202 | if (track->separate_cube) { |
||
2203 | ret = r100_cs_track_cube(rdev, track, u); |
||
2204 | if (ret) |
||
2205 | return ret; |
||
2206 | } else |
||
2207 | size *= 6; |
||
2208 | break; |
||
2209 | default: |
||
2210 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
||
2211 | "%u\n", track->textures[u].tex_coord_type, u); |
||
2212 | return -EINVAL; |
||
2213 | } |
||
2214 | if (size > radeon_bo_size(robj)) { |
||
2215 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
||
2216 | "%lu\n", u, size, radeon_bo_size(robj)); |
||
2217 | r100_cs_track_texture_print(&track->textures[u]); |
||
2218 | return -EINVAL; |
||
2219 | } |
||
1117 | serge | 2220 | } |
2997 | Serge | 2221 | return 0; |
2222 | } |
||
2223 | |||
2224 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
||
2225 | { |
||
2226 | unsigned i; |
||
2227 | unsigned long size; |
||
2228 | unsigned prim_walk; |
||
2229 | unsigned nverts; |
||
2230 | unsigned num_cb = track->cb_dirty ? track->num_cb : 0; |
||
2231 | |||
2232 | if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && |
||
2233 | !track->blend_read_enable) |
||
2234 | num_cb = 0; |
||
2235 | |||
2236 | for (i = 0; i < num_cb; i++) { |
||
2237 | if (track->cb[i].robj == NULL) { |
||
2238 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
||
2239 | return -EINVAL; |
||
1117 | serge | 2240 | } |
2997 | Serge | 2241 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
2242 | size += track->cb[i].offset; |
||
2243 | if (size > radeon_bo_size(track->cb[i].robj)) { |
||
2244 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
||
2245 | "(need %lu have %lu) !\n", i, size, |
||
2246 | radeon_bo_size(track->cb[i].robj)); |
||
2247 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
||
2248 | i, track->cb[i].pitch, track->cb[i].cpp, |
||
2249 | track->cb[i].offset, track->maxy); |
||
2250 | return -EINVAL; |
||
2251 | } |
||
1117 | serge | 2252 | } |
2997 | Serge | 2253 | track->cb_dirty = false; |
2254 | |||
2255 | if (track->zb_dirty && track->z_enabled) { |
||
2256 | if (track->zb.robj == NULL) { |
||
2257 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
||
2258 | return -EINVAL; |
||
2259 | } |
||
2260 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
||
2261 | size += track->zb.offset; |
||
2262 | if (size > radeon_bo_size(track->zb.robj)) { |
||
2263 | DRM_ERROR("[drm] Buffer too small for z buffer " |
||
2264 | "(need %lu have %lu) !\n", size, |
||
2265 | radeon_bo_size(track->zb.robj)); |
||
2266 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
||
2267 | track->zb.pitch, track->zb.cpp, |
||
2268 | track->zb.offset, track->maxy); |
||
2269 | return -EINVAL; |
||
2270 | } |
||
2271 | } |
||
2272 | track->zb_dirty = false; |
||
2273 | |||
2274 | if (track->aa_dirty && track->aaresolve) { |
||
2275 | if (track->aa.robj == NULL) { |
||
2276 | DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); |
||
2277 | return -EINVAL; |
||
2278 | } |
||
2279 | /* I believe the format comes from colorbuffer0. */ |
||
2280 | size = track->aa.pitch * track->cb[0].cpp * track->maxy; |
||
2281 | size += track->aa.offset; |
||
2282 | if (size > radeon_bo_size(track->aa.robj)) { |
||
2283 | DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " |
||
2284 | "(need %lu have %lu) !\n", i, size, |
||
2285 | radeon_bo_size(track->aa.robj)); |
||
2286 | DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", |
||
2287 | i, track->aa.pitch, track->cb[0].cpp, |
||
2288 | track->aa.offset, track->maxy); |
||
2289 | return -EINVAL; |
||
2290 | } |
||
2291 | } |
||
2292 | track->aa_dirty = false; |
||
2293 | |||
2294 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
||
2295 | if (track->vap_vf_cntl & (1 << 14)) { |
||
2296 | nverts = track->vap_alt_nverts; |
||
2297 | } else { |
||
2298 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
||
2299 | } |
||
2300 | switch (prim_walk) { |
||
2301 | case 1: |
||
2302 | for (i = 0; i < track->num_arrays; i++) { |
||
2303 | size = track->arrays[i].esize * track->max_indx * 4; |
||
2304 | if (track->arrays[i].robj == NULL) { |
||
2305 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
||
2306 | "bound\n", prim_walk, i); |
||
2307 | return -EINVAL; |
||
2308 | } |
||
2309 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
||
2310 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
||
2311 | "need %lu dwords have %lu dwords\n", |
||
2312 | prim_walk, i, size >> 2, |
||
2313 | radeon_bo_size(track->arrays[i].robj) |
||
2314 | >> 2); |
||
2315 | DRM_ERROR("Max indices %u\n", track->max_indx); |
||
2316 | return -EINVAL; |
||
2317 | } |
||
2318 | } |
||
2319 | break; |
||
2320 | case 2: |
||
2321 | for (i = 0; i < track->num_arrays; i++) { |
||
2322 | size = track->arrays[i].esize * (nverts - 1) * 4; |
||
2323 | if (track->arrays[i].robj == NULL) { |
||
2324 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
||
2325 | "bound\n", prim_walk, i); |
||
2326 | return -EINVAL; |
||
2327 | } |
||
2328 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
||
2329 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
||
2330 | "need %lu dwords have %lu dwords\n", |
||
2331 | prim_walk, i, size >> 2, |
||
2332 | radeon_bo_size(track->arrays[i].robj) |
||
2333 | >> 2); |
||
2334 | return -EINVAL; |
||
2335 | } |
||
2336 | } |
||
2337 | break; |
||
2338 | case 3: |
||
2339 | size = track->vtx_size * nverts; |
||
2340 | if (size != track->immd_dwords) { |
||
2341 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
||
2342 | track->immd_dwords, size); |
||
2343 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
||
2344 | nverts, track->vtx_size); |
||
2345 | return -EINVAL; |
||
2346 | } |
||
2347 | break; |
||
2348 | default: |
||
2349 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
||
2350 | prim_walk); |
||
2351 | return -EINVAL; |
||
2352 | } |
||
2353 | |||
2354 | if (track->tex_dirty) { |
||
2355 | track->tex_dirty = false; |
||
2356 | return r100_cs_track_texture_check(rdev, track); |
||
2357 | } |
||
2358 | return 0; |
||
1117 | serge | 2359 | } |
2360 | |||
2997 | Serge | 2361 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
1117 | serge | 2362 | { |
2997 | Serge | 2363 | unsigned i, face; |
1117 | serge | 2364 | |
2997 | Serge | 2365 | track->cb_dirty = true; |
2366 | track->zb_dirty = true; |
||
2367 | track->tex_dirty = true; |
||
2368 | track->aa_dirty = true; |
||
1117 | serge | 2369 | |
2997 | Serge | 2370 | if (rdev->family < CHIP_R300) { |
2371 | track->num_cb = 1; |
||
2372 | if (rdev->family <= CHIP_RS200) |
||
2373 | track->num_texture = 3; |
||
2374 | else |
||
2375 | track->num_texture = 6; |
||
2376 | track->maxy = 2048; |
||
2377 | track->separate_cube = 1; |
||
2378 | } else { |
||
2379 | track->num_cb = 4; |
||
2380 | track->num_texture = 16; |
||
2381 | track->maxy = 4096; |
||
2382 | track->separate_cube = 0; |
||
2383 | track->aaresolve = false; |
||
2384 | track->aa.robj = NULL; |
||
2385 | } |
||
2386 | |||
2387 | for (i = 0; i < track->num_cb; i++) { |
||
2388 | track->cb[i].robj = NULL; |
||
2389 | track->cb[i].pitch = 8192; |
||
2390 | track->cb[i].cpp = 16; |
||
2391 | track->cb[i].offset = 0; |
||
2392 | } |
||
2393 | track->z_enabled = true; |
||
2394 | track->zb.robj = NULL; |
||
2395 | track->zb.pitch = 8192; |
||
2396 | track->zb.cpp = 4; |
||
2397 | track->zb.offset = 0; |
||
2398 | track->vtx_size = 0x7F; |
||
2399 | track->immd_dwords = 0xFFFFFFFFUL; |
||
2400 | track->num_arrays = 11; |
||
2401 | track->max_indx = 0x00FFFFFFUL; |
||
2402 | for (i = 0; i < track->num_arrays; i++) { |
||
2403 | track->arrays[i].robj = NULL; |
||
2404 | track->arrays[i].esize = 0x7F; |
||
2405 | } |
||
2406 | for (i = 0; i < track->num_texture; i++) { |
||
2407 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
||
2408 | track->textures[i].pitch = 16536; |
||
2409 | track->textures[i].width = 16536; |
||
2410 | track->textures[i].height = 16536; |
||
2411 | track->textures[i].width_11 = 1 << 11; |
||
2412 | track->textures[i].height_11 = 1 << 11; |
||
2413 | track->textures[i].num_levels = 12; |
||
2414 | if (rdev->family <= CHIP_RS200) { |
||
2415 | track->textures[i].tex_coord_type = 0; |
||
2416 | track->textures[i].txdepth = 0; |
||
2417 | } else { |
||
2418 | track->textures[i].txdepth = 16; |
||
2419 | track->textures[i].tex_coord_type = 1; |
||
1117 | serge | 2420 | } |
2997 | Serge | 2421 | track->textures[i].cpp = 64; |
2422 | track->textures[i].robj = NULL; |
||
2423 | /* CS IB emission code makes sure texture unit are disabled */ |
||
2424 | track->textures[i].enabled = false; |
||
2425 | track->textures[i].lookup_disable = false; |
||
2426 | track->textures[i].roundup_w = true; |
||
2427 | track->textures[i].roundup_h = true; |
||
2428 | if (track->separate_cube) |
||
2429 | for (face = 0; face < 5; face++) { |
||
2430 | track->textures[i].cube_info[face].robj = NULL; |
||
2431 | track->textures[i].cube_info[face].width = 16536; |
||
2432 | track->textures[i].cube_info[face].height = 16536; |
||
2433 | track->textures[i].cube_info[face].offset = 0; |
||
2434 | } |
||
1117 | serge | 2435 | } |
2436 | } |
||
2437 | |||
2997 | Serge | 2438 | /* |
2439 | * Global GPU functions |
||
2440 | */ |
||
2441 | static void r100_errata(struct radeon_device *rdev) |
||
1117 | serge | 2442 | { |
2997 | Serge | 2443 | rdev->pll_errata = 0; |
2444 | |||
2445 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
||
2446 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
||
2447 | } |
||
2448 | |||
2449 | if (rdev->family == CHIP_RV100 || |
||
2450 | rdev->family == CHIP_RS100 || |
||
2451 | rdev->family == CHIP_RS200) { |
||
2452 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
||
2453 | } |
||
2454 | } |
||
2455 | |||
2456 | static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
||
2457 | { |
||
1117 | serge | 2458 | unsigned i; |
2459 | uint32_t tmp; |
||
2460 | |||
2461 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
2462 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
||
2463 | if (tmp >= n) { |
||
2464 | return 0; |
||
2465 | } |
||
2466 | DRM_UDELAY(1); |
||
2467 | } |
||
2468 | return -1; |
||
2469 | } |
||
2470 | |||
2471 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
||
2472 | { |
||
2473 | unsigned i; |
||
2474 | uint32_t tmp; |
||
2475 | |||
2476 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
||
2477 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
||
2478 | " Bad things might happen.\n"); |
||
2479 | } |
||
2480 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
2481 | tmp = RREG32(RADEON_RBBM_STATUS); |
||
1430 | serge | 2482 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
1117 | serge | 2483 | return 0; |
2484 | } |
||
2485 | DRM_UDELAY(1); |
||
2486 | } |
||
2487 | return -1; |
||
2488 | } |
||
2489 | |||
2490 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
||
2491 | { |
||
2492 | unsigned i; |
||
2493 | uint32_t tmp; |
||
2494 | |||
2495 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
2496 | /* read MC_STATUS */ |
||
1430 | serge | 2497 | tmp = RREG32(RADEON_MC_STATUS); |
2498 | if (tmp & RADEON_MC_IDLE) { |
||
1117 | serge | 2499 | return 0; |
2500 | } |
||
2501 | DRM_UDELAY(1); |
||
2502 | } |
||
2503 | return -1; |
||
2504 | } |
||
2505 | |||
2997 | Serge | 2506 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
1117 | serge | 2507 | { |
1963 | serge | 2508 | u32 rbbm_status; |
1117 | serge | 2509 | |
1963 | serge | 2510 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2511 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
||
5078 | serge | 2512 | radeon_ring_lockup_update(rdev, ring); |
1963 | serge | 2513 | return false; |
1117 | serge | 2514 | } |
2997 | Serge | 2515 | return radeon_ring_test_lockup(rdev, ring); |
1117 | serge | 2516 | } |
2517 | |||
2997 | Serge | 2518 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
2519 | void r100_enable_bm(struct radeon_device *rdev) |
||
2520 | { |
||
2521 | uint32_t tmp; |
||
2522 | /* Enable bus mastering */ |
||
2523 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
||
2524 | WREG32(RADEON_BUS_CNTL, tmp); |
||
2525 | } |
||
2526 | |||
1963 | serge | 2527 | void r100_bm_disable(struct radeon_device *rdev) |
1117 | serge | 2528 | { |
1963 | serge | 2529 | u32 tmp; |
1117 | serge | 2530 | |
1963 | serge | 2531 | /* disable bus mastering */ |
2532 | tmp = RREG32(R_000030_BUS_CNTL); |
||
2533 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); |
||
2534 | mdelay(1); |
||
2535 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); |
||
2536 | mdelay(1); |
||
2537 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); |
||
2538 | tmp = RREG32(RADEON_BUS_CNTL); |
||
2539 | mdelay(1); |
||
2997 | Serge | 2540 | pci_clear_master(rdev->pdev); |
1963 | serge | 2541 | mdelay(1); |
2542 | } |
||
2543 | |||
2544 | int r100_asic_reset(struct radeon_device *rdev) |
||
2545 | { |
||
2546 | struct r100_mc_save save; |
||
2547 | u32 status, tmp; |
||
2548 | int ret = 0; |
||
2549 | |||
2550 | status = RREG32(R_000E40_RBBM_STATUS); |
||
2551 | if (!G_000E40_GUI_ACTIVE(status)) { |
||
2552 | return 0; |
||
1117 | serge | 2553 | } |
1963 | serge | 2554 | r100_mc_stop(rdev, &save); |
2555 | status = RREG32(R_000E40_RBBM_STATUS); |
||
2556 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
2557 | /* stop CP */ |
||
2558 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
2559 | tmp = RREG32(RADEON_CP_RB_CNTL); |
||
2560 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
||
2561 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
||
2562 | WREG32(RADEON_CP_RB_WPTR, 0); |
||
2563 | WREG32(RADEON_CP_RB_CNTL, tmp); |
||
2564 | /* save PCI state */ |
||
2565 | // pci_save_state(rdev->pdev); |
||
2566 | /* disable bus mastering */ |
||
2567 | r100_bm_disable(rdev); |
||
2568 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | |
||
2569 | S_0000F0_SOFT_RESET_RE(1) | |
||
2570 | S_0000F0_SOFT_RESET_PP(1) | |
||
2571 | S_0000F0_SOFT_RESET_RB(1)); |
||
2572 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
2573 | mdelay(500); |
||
2574 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
2575 | mdelay(1); |
||
2576 | status = RREG32(R_000E40_RBBM_STATUS); |
||
2577 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
1117 | serge | 2578 | /* reset CP */ |
1963 | serge | 2579 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
2580 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
||
2581 | mdelay(500); |
||
2582 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
||
2583 | mdelay(1); |
||
2584 | status = RREG32(R_000E40_RBBM_STATUS); |
||
2585 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
||
2586 | /* restore PCI & busmastering */ |
||
2587 | // pci_restore_state(rdev->pdev); |
||
2588 | r100_enable_bm(rdev); |
||
1117 | serge | 2589 | /* Check if GPU is idle */ |
1963 | serge | 2590 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
2591 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { |
||
2592 | dev_err(rdev->dev, "failed to reset GPU\n"); |
||
2593 | ret = -1; |
||
2594 | } else |
||
2595 | dev_info(rdev->dev, "GPU reset succeed\n"); |
||
2596 | r100_mc_resume(rdev, &save); |
||
2597 | return ret; |
||
1117 | serge | 2598 | } |
2599 | |||
1321 | serge | 2600 | void r100_set_common_regs(struct radeon_device *rdev) |
2601 | { |
||
1430 | serge | 2602 | struct drm_device *dev = rdev->ddev; |
2603 | bool force_dac2 = false; |
||
1963 | serge | 2604 | u32 tmp; |
1430 | serge | 2605 | |
1321 | serge | 2606 | /* set these so they don't interfere with anything */ |
2607 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
||
2608 | WREG32(RADEON_SUBPIC_CNTL, 0); |
||
2609 | WREG32(RADEON_VIPH_CONTROL, 0); |
||
2610 | WREG32(RADEON_I2C_CNTL_1, 0); |
||
2611 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
||
2612 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
||
2613 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
||
1430 | serge | 2614 | |
2615 | /* always set up dac2 on rn50 and some rv100 as lots |
||
2616 | * of servers seem to wire it up to a VGA port but |
||
2617 | * don't report it in the bios connector |
||
2618 | * table. |
||
2619 | */ |
||
2620 | switch (dev->pdev->device) { |
||
2621 | /* RN50 */ |
||
2622 | case 0x515e: |
||
2623 | case 0x5969: |
||
2624 | force_dac2 = true; |
||
2625 | break; |
||
2626 | /* RV100*/ |
||
2627 | case 0x5159: |
||
2628 | case 0x515a: |
||
2629 | /* DELL triple head servers */ |
||
2630 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && |
||
2631 | ((dev->pdev->subsystem_device == 0x016c) || |
||
2632 | (dev->pdev->subsystem_device == 0x016d) || |
||
2633 | (dev->pdev->subsystem_device == 0x016e) || |
||
2634 | (dev->pdev->subsystem_device == 0x016f) || |
||
2635 | (dev->pdev->subsystem_device == 0x0170) || |
||
2636 | (dev->pdev->subsystem_device == 0x017d) || |
||
2637 | (dev->pdev->subsystem_device == 0x017e) || |
||
2638 | (dev->pdev->subsystem_device == 0x0183) || |
||
2639 | (dev->pdev->subsystem_device == 0x018a) || |
||
2640 | (dev->pdev->subsystem_device == 0x019a))) |
||
2641 | force_dac2 = true; |
||
2642 | break; |
||
2643 | } |
||
2644 | |||
2645 | if (force_dac2) { |
||
2646 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
||
2647 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
2648 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
||
2649 | |||
2650 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
||
2651 | enable it, even it's detected. |
||
2652 | */ |
||
2653 | |||
2654 | /* force it to crtc0 */ |
||
2655 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
||
2656 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
||
2657 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
2658 | |||
2659 | /* set up the TV DAC */ |
||
2660 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | |
||
2661 | RADEON_TV_DAC_STD_MASK | |
||
2662 | RADEON_TV_DAC_RDACPD | |
||
2663 | RADEON_TV_DAC_GDACPD | |
||
2664 | RADEON_TV_DAC_BDACPD | |
||
2665 | RADEON_TV_DAC_BGADJ_MASK | |
||
2666 | RADEON_TV_DAC_DACADJ_MASK); |
||
2667 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
||
2668 | RADEON_TV_DAC_NHOLD | |
||
2669 | RADEON_TV_DAC_STD_PS2 | |
||
2670 | (0x58 << 16)); |
||
2671 | |||
2672 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
2673 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
2674 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
2675 | } |
||
1963 | serge | 2676 | |
2677 | /* switch PM block to ACPI mode */ |
||
2678 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
||
2679 | tmp &= ~RADEON_PM_MODE_SEL; |
||
2680 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
||
2681 | |||
1321 | serge | 2682 | } |
1117 | serge | 2683 | |
2684 | /* |
||
2685 | * VRAM info |
||
2686 | */ |
||
2687 | static void r100_vram_get_type(struct radeon_device *rdev) |
||
2688 | { |
||
2689 | uint32_t tmp; |
||
2690 | |||
2691 | rdev->mc.vram_is_ddr = false; |
||
2692 | if (rdev->flags & RADEON_IS_IGP) |
||
2693 | rdev->mc.vram_is_ddr = true; |
||
2694 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
||
2695 | rdev->mc.vram_is_ddr = true; |
||
2696 | if ((rdev->family == CHIP_RV100) || |
||
2697 | (rdev->family == CHIP_RS100) || |
||
2698 | (rdev->family == CHIP_RS200)) { |
||
2699 | tmp = RREG32(RADEON_MEM_CNTL); |
||
2700 | if (tmp & RV100_HALF_MODE) { |
||
2701 | rdev->mc.vram_width = 32; |
||
2702 | } else { |
||
2703 | rdev->mc.vram_width = 64; |
||
2704 | } |
||
2705 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
2706 | rdev->mc.vram_width /= 4; |
||
2707 | rdev->mc.vram_is_ddr = true; |
||
2708 | } |
||
2709 | } else if (rdev->family <= CHIP_RV280) { |
||
2710 | tmp = RREG32(RADEON_MEM_CNTL); |
||
2711 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
||
2712 | rdev->mc.vram_width = 128; |
||
2713 | } else { |
||
2714 | rdev->mc.vram_width = 64; |
||
2715 | } |
||
2716 | } else { |
||
2717 | /* newer IGPs */ |
||
2718 | rdev->mc.vram_width = 128; |
||
2719 | } |
||
2720 | } |
||
2721 | |||
1179 | serge | 2722 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
1117 | serge | 2723 | { |
1179 | serge | 2724 | u32 aper_size; |
2725 | u8 byte; |
||
1117 | serge | 2726 | |
1179 | serge | 2727 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
2728 | |||
2729 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
||
2730 | * that is has the 2nd generation multifunction PCI interface |
||
2731 | */ |
||
2732 | if (rdev->family == CHIP_RV280 || |
||
2733 | rdev->family >= CHIP_RV350) { |
||
2734 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
||
2735 | ~RADEON_HDP_APER_CNTL); |
||
2736 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
||
2737 | return aper_size * 2; |
||
2738 | } |
||
2739 | |||
2740 | /* Older cards have all sorts of funny issues to deal with. First |
||
2741 | * check if it's a multifunction card by reading the PCI config |
||
2742 | * header type... Limit those to one aperture size |
||
2743 | */ |
||
2744 | // pci_read_config_byte(rdev->pdev, 0xe, &byte); |
||
2745 | // if (byte & 0x80) { |
||
2746 | // DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
||
2747 | // DRM_INFO("Limiting VRAM to one aperture\n"); |
||
2748 | // return aper_size; |
||
2749 | // } |
||
2750 | |||
2751 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
||
2752 | * have set it up. We don't write this as it's broken on some ASICs but |
||
2753 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
||
2754 | */ |
||
2755 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
||
2756 | return aper_size * 2; |
||
2757 | return aper_size; |
||
2758 | } |
||
2759 | |||
2760 | void r100_vram_init_sizes(struct radeon_device *rdev) |
||
2761 | { |
||
2762 | u64 config_aper_size; |
||
2763 | |||
1430 | serge | 2764 | /* work out accessible VRAM */ |
1963 | serge | 2765 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
2766 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
1430 | serge | 2767 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
2768 | /* FIXME we don't use the second aperture yet when we could use it */ |
||
2769 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
||
2770 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
||
1179 | serge | 2771 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
1117 | serge | 2772 | if (rdev->flags & RADEON_IS_IGP) { |
2773 | uint32_t tom; |
||
2774 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
||
2775 | tom = RREG32(RADEON_NB_TOM); |
||
1179 | serge | 2776 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
2777 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
2778 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1117 | serge | 2779 | } else { |
1179 | serge | 2780 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
1117 | serge | 2781 | /* Some production boards of m6 will report 0 |
2782 | * if it's 8 MB |
||
2783 | */ |
||
1179 | serge | 2784 | if (rdev->mc.real_vram_size == 0) { |
2785 | rdev->mc.real_vram_size = 8192 * 1024; |
||
2786 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
||
1117 | serge | 2787 | } |
1179 | serge | 2788 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
1430 | serge | 2789 | * Novell bug 204882 + along with lots of ubuntu ones |
2790 | */ |
||
1963 | serge | 2791 | if (rdev->mc.aper_size > config_aper_size) |
2792 | config_aper_size = rdev->mc.aper_size; |
||
2793 | |||
1179 | serge | 2794 | if (config_aper_size > rdev->mc.real_vram_size) |
2795 | rdev->mc.mc_vram_size = config_aper_size; |
||
2796 | else |
||
2797 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
||
1117 | serge | 2798 | } |
2799 | } |
||
2800 | |||
1179 | serge | 2801 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2802 | { |
||
2803 | uint32_t temp; |
||
2804 | |||
2805 | temp = RREG32(RADEON_CONFIG_CNTL); |
||
2806 | if (state == false) { |
||
1963 | serge | 2807 | temp &= ~RADEON_CFG_VGA_RAM_EN; |
2808 | temp |= RADEON_CFG_VGA_IO_DIS; |
||
1179 | serge | 2809 | } else { |
1963 | serge | 2810 | temp &= ~RADEON_CFG_VGA_IO_DIS; |
1179 | serge | 2811 | } |
2812 | WREG32(RADEON_CONFIG_CNTL, temp); |
||
2813 | } |
||
2814 | |||
2997 | Serge | 2815 | static void r100_mc_init(struct radeon_device *rdev) |
1179 | serge | 2816 | { |
1430 | serge | 2817 | u64 base; |
2818 | |||
1179 | serge | 2819 | r100_vram_get_type(rdev); |
2820 | r100_vram_init_sizes(rdev); |
||
1430 | serge | 2821 | base = rdev->mc.aper_base; |
2822 | if (rdev->flags & RADEON_IS_IGP) |
||
2823 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
||
2824 | radeon_vram_location(rdev, &rdev->mc, base); |
||
1963 | serge | 2825 | rdev->mc.gtt_base_align = 0; |
1430 | serge | 2826 | if (!(rdev->flags & RADEON_IS_AGP)) |
2827 | radeon_gtt_location(rdev, &rdev->mc); |
||
1963 | serge | 2828 | radeon_update_bandwidth_info(rdev); |
1179 | serge | 2829 | } |
2830 | |||
2831 | |||
1117 | serge | 2832 | /* |
2833 | * Indirect registers accessor |
||
2834 | */ |
||
2835 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
||
2836 | { |
||
1963 | serge | 2837 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { |
1117 | serge | 2838 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
2839 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
||
1963 | serge | 2840 | } |
1117 | serge | 2841 | } |
2842 | |||
2843 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
||
2844 | { |
||
2845 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
||
2846 | * or the chip could hang on a subsequent access |
||
2847 | */ |
||
2848 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
||
2997 | Serge | 2849 | mdelay(5); |
1117 | serge | 2850 | } |
2851 | |||
2852 | /* This function is required to workaround a hardware bug in some (all?) |
||
2853 | * revisions of the R300. This workaround should be called after every |
||
2854 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
||
2855 | * may not be correct. |
||
2856 | */ |
||
2857 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
||
2858 | uint32_t save, tmp; |
||
2859 | |||
2860 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
||
2861 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
||
2862 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
||
2863 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
||
2864 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
||
2865 | } |
||
2866 | } |
||
2867 | |||
2868 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
||
2869 | { |
||
5078 | serge | 2870 | unsigned long flags; |
1117 | serge | 2871 | uint32_t data; |
2872 | |||
5078 | serge | 2873 | spin_lock_irqsave(&rdev->pll_idx_lock, flags); |
1117 | serge | 2874 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
2875 | r100_pll_errata_after_index(rdev); |
||
2876 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
||
2877 | r100_pll_errata_after_data(rdev); |
||
5078 | serge | 2878 | spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); |
1117 | serge | 2879 | return data; |
2880 | } |
||
2881 | |||
2882 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
2883 | { |
||
5078 | serge | 2884 | unsigned long flags; |
2885 | |||
2886 | spin_lock_irqsave(&rdev->pll_idx_lock, flags); |
||
1117 | serge | 2887 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
2888 | r100_pll_errata_after_index(rdev); |
||
2889 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
||
2890 | r100_pll_errata_after_data(rdev); |
||
5078 | serge | 2891 | spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); |
1117 | serge | 2892 | } |
2893 | |||
2997 | Serge | 2894 | static void r100_set_safe_registers(struct radeon_device *rdev) |
1117 | serge | 2895 | { |
1179 | serge | 2896 | if (ASIC_IS_RN50(rdev)) { |
2897 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
||
2898 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
||
2899 | } else if (rdev->family < CHIP_R200) { |
||
2900 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
||
2901 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
||
2902 | } else { |
||
1221 | serge | 2903 | r200_set_safe_registers(rdev); |
1117 | serge | 2904 | } |
2905 | } |
||
2906 | |||
1129 | serge | 2907 | /* |
2908 | * Debugfs info |
||
2909 | */ |
||
2910 | #if defined(CONFIG_DEBUG_FS) |
||
2911 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
||
2912 | { |
||
2913 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2914 | struct drm_device *dev = node->minor->dev; |
||
2915 | struct radeon_device *rdev = dev->dev_private; |
||
2916 | uint32_t reg, value; |
||
2917 | unsigned i; |
||
2918 | |||
2919 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
||
2920 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
||
2921 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
||
2922 | for (i = 0; i < 64; i++) { |
||
2923 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
||
2924 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
||
2925 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
||
2926 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
||
2927 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
||
2928 | } |
||
2929 | return 0; |
||
2930 | } |
||
2931 | |||
2932 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
||
2933 | { |
||
2934 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2935 | struct drm_device *dev = node->minor->dev; |
||
2936 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 2937 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
1129 | serge | 2938 | uint32_t rdp, wdp; |
2939 | unsigned count, i, j; |
||
2940 | |||
2997 | Serge | 2941 | radeon_ring_free_size(rdev, ring); |
1129 | serge | 2942 | rdp = RREG32(RADEON_CP_RB_RPTR); |
2943 | wdp = RREG32(RADEON_CP_RB_WPTR); |
||
2997 | Serge | 2944 | count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; |
1129 | serge | 2945 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
2946 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
||
2947 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
||
2997 | Serge | 2948 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
1129 | serge | 2949 | seq_printf(m, "%u dwords in ring\n", count); |
5078 | serge | 2950 | if (ring->ready) { |
1129 | serge | 2951 | for (j = 0; j <= count; j++) { |
2997 | Serge | 2952 | i = (rdp + j) & ring->ptr_mask; |
2953 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
||
1129 | serge | 2954 | } |
5078 | serge | 2955 | } |
1129 | serge | 2956 | return 0; |
2957 | } |
||
2958 | |||
2959 | |||
2960 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
||
2961 | { |
||
2962 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
2963 | struct drm_device *dev = node->minor->dev; |
||
2964 | struct radeon_device *rdev = dev->dev_private; |
||
2965 | uint32_t csq_stat, csq2_stat, tmp; |
||
2966 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
||
2967 | unsigned i; |
||
2968 | |||
2969 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
||
2970 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
||
2971 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
||
2972 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
||
2973 | r_rptr = (csq_stat >> 0) & 0x3ff; |
||
2974 | r_wptr = (csq_stat >> 10) & 0x3ff; |
||
2975 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
||
2976 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
||
2977 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
||
2978 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
||
2979 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
||
2980 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
||
2981 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
||
2982 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
||
2983 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
||
2984 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
||
2985 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
||
2986 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
||
2987 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
||
2988 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
||
2989 | seq_printf(m, "Ring fifo:\n"); |
||
2990 | for (i = 0; i < 256; i++) { |
||
2991 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
2992 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
2993 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
||
2994 | } |
||
2995 | seq_printf(m, "Indirect1 fifo:\n"); |
||
2996 | for (i = 256; i <= 512; i++) { |
||
2997 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
2998 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
2999 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
||
3000 | } |
||
3001 | seq_printf(m, "Indirect2 fifo:\n"); |
||
3002 | for (i = 640; i < ib1_wptr; i++) { |
||
3003 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
||
3004 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
||
3005 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
||
3006 | } |
||
3007 | return 0; |
||
3008 | } |
||
3009 | |||
3010 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
||
3011 | { |
||
3012 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
||
3013 | struct drm_device *dev = node->minor->dev; |
||
3014 | struct radeon_device *rdev = dev->dev_private; |
||
3015 | uint32_t tmp; |
||
3016 | |||
3017 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
||
3018 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
||
3019 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
||
3020 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
||
3021 | tmp = RREG32(RADEON_BUS_CNTL); |
||
3022 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
||
3023 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
||
3024 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
||
3025 | tmp = RREG32(RADEON_AGP_BASE); |
||
3026 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
||
3027 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
||
3028 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
||
3029 | tmp = RREG32(0x01D0); |
||
3030 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
||
3031 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
||
3032 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
||
3033 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
||
3034 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
||
3035 | tmp = RREG32(0x01E4); |
||
3036 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
||
3037 | return 0; |
||
3038 | } |
||
3039 | |||
3040 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
||
3041 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
||
3042 | }; |
||
3043 | |||
3044 | static struct drm_info_list r100_debugfs_cp_list[] = { |
||
3045 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
||
3046 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
||
3047 | }; |
||
3048 | |||
3049 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
||
3050 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
||
3051 | }; |
||
3052 | #endif |
||
3053 | |||
3054 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
||
3055 | { |
||
3056 | #if defined(CONFIG_DEBUG_FS) |
||
3057 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
||
3058 | #else |
||
3059 | return 0; |
||
3060 | #endif |
||
3061 | } |
||
3062 | |||
3063 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
||
3064 | { |
||
3065 | #if defined(CONFIG_DEBUG_FS) |
||
3066 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
||
3067 | #else |
||
3068 | return 0; |
||
3069 | #endif |
||
3070 | } |
||
3071 | |||
3072 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
||
3073 | { |
||
3074 | #if defined(CONFIG_DEBUG_FS) |
||
3075 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
||
3076 | #else |
||
3077 | return 0; |
||
3078 | #endif |
||
3079 | } |
||
1179 | serge | 3080 | |
3081 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
||
3082 | uint32_t tiling_flags, uint32_t pitch, |
||
3083 | uint32_t offset, uint32_t obj_size) |
||
3084 | { |
||
3085 | int surf_index = reg * 16; |
||
3086 | int flags = 0; |
||
3087 | |||
3088 | if (rdev->family <= CHIP_RS200) { |
||
3089 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
||
3090 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
||
3091 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
||
3092 | if (tiling_flags & RADEON_TILING_MACRO) |
||
3093 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
||
5078 | serge | 3094 | /* setting pitch to 0 disables tiling */ |
3095 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
||
3096 | == 0) |
||
3097 | pitch = 0; |
||
1179 | serge | 3098 | } else if (rdev->family <= CHIP_RV280) { |
3099 | if (tiling_flags & (RADEON_TILING_MACRO)) |
||
3100 | flags |= R200_SURF_TILE_COLOR_MACRO; |
||
3101 | if (tiling_flags & RADEON_TILING_MICRO) |
||
3102 | flags |= R200_SURF_TILE_COLOR_MICRO; |
||
3103 | } else { |
||
3104 | if (tiling_flags & RADEON_TILING_MACRO) |
||
3105 | flags |= R300_SURF_TILE_MACRO; |
||
3106 | if (tiling_flags & RADEON_TILING_MICRO) |
||
3107 | flags |= R300_SURF_TILE_MICRO; |
||
3108 | } |
||
3109 | |||
3110 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
||
3111 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
||
3112 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
||
3113 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
||
3114 | |||
1963 | serge | 3115 | /* r100/r200 divide by 16 */ |
3116 | if (rdev->family < CHIP_R300) |
||
3117 | flags |= pitch / 16; |
||
3118 | else |
||
3119 | flags |= pitch / 8; |
||
3120 | |||
3121 | |||
3122 | DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
||
1179 | serge | 3123 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
3124 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
||
3125 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
||
3126 | return 0; |
||
3127 | } |
||
3128 | |||
3129 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
||
3130 | { |
||
3131 | int surf_index = reg * 16; |
||
3132 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
||
3133 | } |
||
3134 | |||
3135 | void r100_bandwidth_update(struct radeon_device *rdev) |
||
3136 | { |
||
3137 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
||
3138 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
||
3139 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
||
3140 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
||
3141 | fixed20_12 memtcas_ff[8] = { |
||
1963 | serge | 3142 | dfixed_init(1), |
3143 | dfixed_init(2), |
||
3144 | dfixed_init(3), |
||
3145 | dfixed_init(0), |
||
3146 | dfixed_init_half(1), |
||
3147 | dfixed_init_half(2), |
||
3148 | dfixed_init(0), |
||
1179 | serge | 3149 | }; |
3150 | fixed20_12 memtcas_rs480_ff[8] = { |
||
1963 | serge | 3151 | dfixed_init(0), |
3152 | dfixed_init(1), |
||
3153 | dfixed_init(2), |
||
3154 | dfixed_init(3), |
||
3155 | dfixed_init(0), |
||
3156 | dfixed_init_half(1), |
||
3157 | dfixed_init_half(2), |
||
3158 | dfixed_init_half(3), |
||
1179 | serge | 3159 | }; |
3160 | fixed20_12 memtcas2_ff[8] = { |
||
1963 | serge | 3161 | dfixed_init(0), |
3162 | dfixed_init(1), |
||
3163 | dfixed_init(2), |
||
3164 | dfixed_init(3), |
||
3165 | dfixed_init(4), |
||
3166 | dfixed_init(5), |
||
3167 | dfixed_init(6), |
||
3168 | dfixed_init(7), |
||
1179 | serge | 3169 | }; |
3170 | fixed20_12 memtrbs[8] = { |
||
1963 | serge | 3171 | dfixed_init(1), |
3172 | dfixed_init_half(1), |
||
3173 | dfixed_init(2), |
||
3174 | dfixed_init_half(2), |
||
3175 | dfixed_init(3), |
||
3176 | dfixed_init_half(3), |
||
3177 | dfixed_init(4), |
||
3178 | dfixed_init_half(4) |
||
1179 | serge | 3179 | }; |
3180 | fixed20_12 memtrbs_r4xx[8] = { |
||
1963 | serge | 3181 | dfixed_init(4), |
3182 | dfixed_init(5), |
||
3183 | dfixed_init(6), |
||
3184 | dfixed_init(7), |
||
3185 | dfixed_init(8), |
||
3186 | dfixed_init(9), |
||
3187 | dfixed_init(10), |
||
3188 | dfixed_init(11) |
||
1179 | serge | 3189 | }; |
3190 | fixed20_12 min_mem_eff; |
||
3191 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
||
3192 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
||
3193 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
||
3194 | disp_drain_rate2, read_return_rate; |
||
3195 | fixed20_12 time_disp1_drop_priority; |
||
3196 | int c; |
||
3197 | int cur_size = 16; /* in octawords */ |
||
3198 | int critical_point = 0, critical_point2; |
||
3199 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
||
3200 | int stop_req, max_stop_req; |
||
3201 | struct drm_display_mode *mode1 = NULL; |
||
3202 | struct drm_display_mode *mode2 = NULL; |
||
3203 | uint32_t pixel_bytes1 = 0; |
||
3204 | uint32_t pixel_bytes2 = 0; |
||
3205 | |||
5271 | serge | 3206 | if (!rdev->mode_info.mode_config_initialized) |
3207 | return; |
||
3208 | |||
1963 | serge | 3209 | radeon_update_display_priority(rdev); |
3210 | |||
1179 | serge | 3211 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
3212 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
||
5078 | serge | 3213 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8; |
1179 | serge | 3214 | } |
1221 | serge | 3215 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
1179 | serge | 3216 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
3217 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
||
5078 | serge | 3218 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8; |
1179 | serge | 3219 | } |
1221 | serge | 3220 | } |
1179 | serge | 3221 | |
1963 | serge | 3222 | min_mem_eff.full = dfixed_const_8(0); |
1179 | serge | 3223 | /* get modes */ |
3224 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
||
3225 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
||
3226 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
3227 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
3228 | /* check crtc enables */ |
||
3229 | if (mode2) |
||
3230 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
3231 | if (mode1) |
||
3232 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
3233 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
||
3234 | } |
||
3235 | |||
3236 | /* |
||
3237 | * determine is there is enough bw for current mode |
||
3238 | */ |
||
1963 | serge | 3239 | sclk_ff = rdev->pm.sclk; |
3240 | mclk_ff = rdev->pm.mclk; |
||
1179 | serge | 3241 | |
3242 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
||
1963 | serge | 3243 | temp_ff.full = dfixed_const(temp); |
3244 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); |
||
1179 | serge | 3245 | |
3246 | pix_clk.full = 0; |
||
3247 | pix_clk2.full = 0; |
||
3248 | peak_disp_bw.full = 0; |
||
3249 | if (mode1) { |
||
1963 | serge | 3250 | temp_ff.full = dfixed_const(1000); |
3251 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ |
||
3252 | pix_clk.full = dfixed_div(pix_clk, temp_ff); |
||
3253 | temp_ff.full = dfixed_const(pixel_bytes1); |
||
3254 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); |
||
1179 | serge | 3255 | } |
3256 | if (mode2) { |
||
1963 | serge | 3257 | temp_ff.full = dfixed_const(1000); |
3258 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ |
||
3259 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); |
||
3260 | temp_ff.full = dfixed_const(pixel_bytes2); |
||
3261 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); |
||
1179 | serge | 3262 | } |
3263 | |||
1963 | serge | 3264 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
1179 | serge | 3265 | if (peak_disp_bw.full >= mem_bw.full) { |
3266 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
||
3267 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
||
3268 | } |
||
3269 | |||
3270 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
||
3271 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
||
3272 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
||
3273 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
||
3274 | mem_trp = ((temp & 0x3)) + 1; |
||
3275 | mem_tras = ((temp & 0x70) >> 4) + 1; |
||
3276 | } else if (rdev->family == CHIP_R300 || |
||
3277 | rdev->family == CHIP_R350) { /* r300, r350 */ |
||
3278 | mem_trcd = (temp & 0x7) + 1; |
||
3279 | mem_trp = ((temp >> 8) & 0x7) + 1; |
||
3280 | mem_tras = ((temp >> 11) & 0xf) + 4; |
||
3281 | } else if (rdev->family == CHIP_RV350 || |
||
3282 | rdev->family <= CHIP_RV380) { |
||
3283 | /* rv3x0 */ |
||
3284 | mem_trcd = (temp & 0x7) + 3; |
||
3285 | mem_trp = ((temp >> 8) & 0x7) + 3; |
||
3286 | mem_tras = ((temp >> 11) & 0xf) + 6; |
||
3287 | } else if (rdev->family == CHIP_R420 || |
||
3288 | rdev->family == CHIP_R423 || |
||
3289 | rdev->family == CHIP_RV410) { |
||
3290 | /* r4xx */ |
||
3291 | mem_trcd = (temp & 0xf) + 3; |
||
3292 | if (mem_trcd > 15) |
||
3293 | mem_trcd = 15; |
||
3294 | mem_trp = ((temp >> 8) & 0xf) + 3; |
||
3295 | if (mem_trp > 15) |
||
3296 | mem_trp = 15; |
||
3297 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
||
3298 | if (mem_tras > 31) |
||
3299 | mem_tras = 31; |
||
3300 | } else { /* RV200, R200 */ |
||
3301 | mem_trcd = (temp & 0x7) + 1; |
||
3302 | mem_trp = ((temp >> 8) & 0x7) + 1; |
||
3303 | mem_tras = ((temp >> 12) & 0xf) + 4; |
||
3304 | } |
||
3305 | /* convert to FF */ |
||
1963 | serge | 3306 | trcd_ff.full = dfixed_const(mem_trcd); |
3307 | trp_ff.full = dfixed_const(mem_trp); |
||
3308 | tras_ff.full = dfixed_const(mem_tras); |
||
1179 | serge | 3309 | |
3310 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
||
3311 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
||
3312 | data = (temp & (7 << 20)) >> 20; |
||
3313 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
||
3314 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
||
3315 | tcas_ff = memtcas_rs480_ff[data]; |
||
3316 | else |
||
3317 | tcas_ff = memtcas_ff[data]; |
||
3318 | } else |
||
3319 | tcas_ff = memtcas2_ff[data]; |
||
3320 | |||
3321 | if (rdev->family == CHIP_RS400 || |
||
3322 | rdev->family == CHIP_RS480) { |
||
3323 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
||
3324 | data = (temp >> 23) & 0x7; |
||
3325 | if (data < 5) |
||
1963 | serge | 3326 | tcas_ff.full += dfixed_const(data); |
1179 | serge | 3327 | } |
3328 | |||
3329 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
||
3330 | /* on the R300, Tcas is included in Trbs. |
||
3331 | */ |
||
3332 | temp = RREG32(RADEON_MEM_CNTL); |
||
3333 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
||
3334 | if (data == 1) { |
||
3335 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
||
3336 | temp = RREG32(R300_MC_IND_INDEX); |
||
3337 | temp &= ~R300_MC_IND_ADDR_MASK; |
||
3338 | temp |= R300_MC_READ_CNTL_CD_mcind; |
||
3339 | WREG32(R300_MC_IND_INDEX, temp); |
||
3340 | temp = RREG32(R300_MC_IND_DATA); |
||
3341 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
||
3342 | } else { |
||
3343 | temp = RREG32(R300_MC_READ_CNTL_AB); |
||
3344 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
||
3345 | } |
||
3346 | } else { |
||
3347 | temp = RREG32(R300_MC_READ_CNTL_AB); |
||
3348 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
||
3349 | } |
||
3350 | if (rdev->family == CHIP_RV410 || |
||
3351 | rdev->family == CHIP_R420 || |
||
3352 | rdev->family == CHIP_R423) |
||
3353 | trbs_ff = memtrbs_r4xx[data]; |
||
3354 | else |
||
3355 | trbs_ff = memtrbs[data]; |
||
3356 | tcas_ff.full += trbs_ff.full; |
||
3357 | } |
||
3358 | |||
3359 | sclk_eff_ff.full = sclk_ff.full; |
||
3360 | |||
3361 | if (rdev->flags & RADEON_IS_AGP) { |
||
3362 | fixed20_12 agpmode_ff; |
||
1963 | serge | 3363 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
3364 | temp_ff.full = dfixed_const_666(16); |
||
3365 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); |
||
1179 | serge | 3366 | } |
3367 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
||
3368 | |||
3369 | if (ASIC_IS_R300(rdev)) { |
||
1963 | serge | 3370 | sclk_delay_ff.full = dfixed_const(250); |
1179 | serge | 3371 | } else { |
3372 | if ((rdev->family == CHIP_RV100) || |
||
3373 | rdev->flags & RADEON_IS_IGP) { |
||
3374 | if (rdev->mc.vram_is_ddr) |
||
1963 | serge | 3375 | sclk_delay_ff.full = dfixed_const(41); |
1179 | serge | 3376 | else |
1963 | serge | 3377 | sclk_delay_ff.full = dfixed_const(33); |
1179 | serge | 3378 | } else { |
3379 | if (rdev->mc.vram_width == 128) |
||
1963 | serge | 3380 | sclk_delay_ff.full = dfixed_const(57); |
1179 | serge | 3381 | else |
1963 | serge | 3382 | sclk_delay_ff.full = dfixed_const(41); |
1179 | serge | 3383 | } |
3384 | } |
||
3385 | |||
1963 | serge | 3386 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
1179 | serge | 3387 | |
3388 | if (rdev->mc.vram_is_ddr) { |
||
3389 | if (rdev->mc.vram_width == 32) { |
||
1963 | serge | 3390 | k1.full = dfixed_const(40); |
1179 | serge | 3391 | c = 3; |
3392 | } else { |
||
1963 | serge | 3393 | k1.full = dfixed_const(20); |
1179 | serge | 3394 | c = 1; |
3395 | } |
||
3396 | } else { |
||
1963 | serge | 3397 | k1.full = dfixed_const(40); |
1179 | serge | 3398 | c = 3; |
3399 | } |
||
3400 | |||
1963 | serge | 3401 | temp_ff.full = dfixed_const(2); |
3402 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); |
||
3403 | temp_ff.full = dfixed_const(c); |
||
3404 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); |
||
3405 | temp_ff.full = dfixed_const(4); |
||
3406 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); |
||
3407 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); |
||
1179 | serge | 3408 | mc_latency_mclk.full += k1.full; |
3409 | |||
1963 | serge | 3410 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
3411 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); |
||
1179 | serge | 3412 | |
3413 | /* |
||
3414 | HW cursor time assuming worst case of full size colour cursor. |
||
3415 | */ |
||
1963 | serge | 3416 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
1179 | serge | 3417 | temp_ff.full += trcd_ff.full; |
3418 | if (temp_ff.full < tras_ff.full) |
||
3419 | temp_ff.full = tras_ff.full; |
||
1963 | serge | 3420 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
1179 | serge | 3421 | |
1963 | serge | 3422 | temp_ff.full = dfixed_const(cur_size); |
3423 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); |
||
1179 | serge | 3424 | /* |
3425 | Find the total latency for the display data. |
||
3426 | */ |
||
1963 | serge | 3427 | disp_latency_overhead.full = dfixed_const(8); |
3428 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); |
||
1179 | serge | 3429 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
3430 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
||
3431 | |||
3432 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
||
3433 | disp_latency.full = mc_latency_mclk.full; |
||
3434 | else |
||
3435 | disp_latency.full = mc_latency_sclk.full; |
||
3436 | |||
3437 | /* setup Max GRPH_STOP_REQ default value */ |
||
3438 | if (ASIC_IS_RV100(rdev)) |
||
3439 | max_stop_req = 0x5c; |
||
3440 | else |
||
3441 | max_stop_req = 0x7c; |
||
3442 | |||
3443 | if (mode1) { |
||
3444 | /* CRTC1 |
||
3445 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
||
3446 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
||
3447 | */ |
||
3448 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
||
3449 | |||
3450 | if (stop_req > max_stop_req) |
||
3451 | stop_req = max_stop_req; |
||
3452 | |||
3453 | /* |
||
3454 | Find the drain rate of the display buffer. |
||
3455 | */ |
||
1963 | serge | 3456 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
3457 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); |
||
1179 | serge | 3458 | |
3459 | /* |
||
3460 | Find the critical point of the display buffer. |
||
3461 | */ |
||
1963 | serge | 3462 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
3463 | crit_point_ff.full += dfixed_const_half(0); |
||
1179 | serge | 3464 | |
1963 | serge | 3465 | critical_point = dfixed_trunc(crit_point_ff); |
1179 | serge | 3466 | |
3467 | if (rdev->disp_priority == 2) { |
||
3468 | critical_point = 0; |
||
3469 | } |
||
3470 | |||
3471 | /* |
||
3472 | The critical point should never be above max_stop_req-4. Setting |
||
3473 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
||
3474 | */ |
||
3475 | if (max_stop_req - critical_point < 4) |
||
3476 | critical_point = 0; |
||
3477 | |||
3478 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
||
3479 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
||
3480 | critical_point = 0x10; |
||
3481 | } |
||
3482 | |||
3483 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
||
3484 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
||
3485 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
||
3486 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
||
3487 | if ((rdev->family == CHIP_R350) && |
||
3488 | (stop_req > 0x15)) { |
||
3489 | stop_req -= 0x10; |
||
3490 | } |
||
3491 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
||
3492 | temp |= RADEON_GRPH_BUFFER_SIZE; |
||
3493 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
||
3494 | RADEON_GRPH_CRITICAL_AT_SOF | |
||
3495 | RADEON_GRPH_STOP_CNTL); |
||
3496 | /* |
||
3497 | Write the result into the register. |
||
3498 | */ |
||
3499 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
||
3500 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
||
3501 | |||
3502 | #if 0 |
||
3503 | if ((rdev->family == CHIP_RS400) || |
||
3504 | (rdev->family == CHIP_RS480)) { |
||
3505 | /* attempt to program RS400 disp regs correctly ??? */ |
||
3506 | temp = RREG32(RS400_DISP1_REG_CNTL); |
||
3507 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
||
3508 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
||
3509 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
||
3510 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
||
3511 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
||
3512 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
||
3513 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
||
3514 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
||
3515 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
||
3516 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
||
3517 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
||
3518 | } |
||
3519 | #endif |
||
3520 | |||
1963 | serge | 3521 | DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", |
1179 | serge | 3522 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
3523 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
||
3524 | } |
||
3525 | |||
3526 | if (mode2) { |
||
3527 | u32 grph2_cntl; |
||
3528 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
||
3529 | |||
3530 | if (stop_req > max_stop_req) |
||
3531 | stop_req = max_stop_req; |
||
3532 | |||
3533 | /* |
||
3534 | Find the drain rate of the display buffer. |
||
3535 | */ |
||
1963 | serge | 3536 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
3537 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); |
||
1179 | serge | 3538 | |
3539 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
||
3540 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
||
3541 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
||
3542 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
||
3543 | if ((rdev->family == CHIP_R350) && |
||
3544 | (stop_req > 0x15)) { |
||
3545 | stop_req -= 0x10; |
||
3546 | } |
||
3547 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
||
3548 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
||
3549 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
||
3550 | RADEON_GRPH_CRITICAL_AT_SOF | |
||
3551 | RADEON_GRPH_STOP_CNTL); |
||
3552 | |||
3553 | if ((rdev->family == CHIP_RS100) || |
||
3554 | (rdev->family == CHIP_RS200)) |
||
3555 | critical_point2 = 0; |
||
3556 | else { |
||
3557 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
||
1963 | serge | 3558 | temp_ff.full = dfixed_const(temp); |
3559 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); |
||
1179 | serge | 3560 | if (sclk_ff.full < temp_ff.full) |
3561 | temp_ff.full = sclk_ff.full; |
||
3562 | |||
3563 | read_return_rate.full = temp_ff.full; |
||
3564 | |||
3565 | if (mode1) { |
||
3566 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
||
1963 | serge | 3567 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
1179 | serge | 3568 | } else { |
3569 | time_disp1_drop_priority.full = 0; |
||
3570 | } |
||
3571 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
||
1963 | serge | 3572 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
3573 | crit_point_ff.full += dfixed_const_half(0); |
||
1179 | serge | 3574 | |
1963 | serge | 3575 | critical_point2 = dfixed_trunc(crit_point_ff); |
1179 | serge | 3576 | |
3577 | if (rdev->disp_priority == 2) { |
||
3578 | critical_point2 = 0; |
||
3579 | } |
||
3580 | |||
3581 | if (max_stop_req - critical_point2 < 4) |
||
3582 | critical_point2 = 0; |
||
3583 | |||
3584 | } |
||
3585 | |||
3586 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
||
3587 | /* some R300 cards have problem with this set to 0 */ |
||
3588 | critical_point2 = 0x10; |
||
3589 | } |
||
3590 | |||
3591 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
||
3592 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
||
3593 | |||
3594 | if ((rdev->family == CHIP_RS400) || |
||
3595 | (rdev->family == CHIP_RS480)) { |
||
3596 | #if 0 |
||
3597 | /* attempt to program RS400 disp2 regs correctly ??? */ |
||
3598 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
||
3599 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
||
3600 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
||
3601 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
||
3602 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
||
3603 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
||
3604 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
||
3605 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
||
3606 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
||
3607 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
||
3608 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
||
3609 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
||
3610 | #endif |
||
3611 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
||
3612 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
||
3613 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
||
3614 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
||
3615 | } |
||
3616 | |||
1963 | serge | 3617 | DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", |
1179 | serge | 3618 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
3619 | } |
||
3620 | } |
||
3621 | |||
2997 | Serge | 3622 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
1963 | serge | 3623 | { |
1412 | serge | 3624 | uint32_t scratch; |
3625 | uint32_t tmp = 0; |
||
3626 | unsigned i; |
||
3627 | int r; |
||
1179 | serge | 3628 | |
1412 | serge | 3629 | r = radeon_scratch_get(rdev, &scratch); |
3630 | if (r) { |
||
3631 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
||
3632 | return r; |
||
3633 | } |
||
3634 | WREG32(scratch, 0xCAFEDEAD); |
||
2997 | Serge | 3635 | r = radeon_ring_lock(rdev, ring, 2); |
1412 | serge | 3636 | if (r) { |
3637 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
3638 | radeon_scratch_free(rdev, scratch); |
||
3639 | return r; |
||
3640 | } |
||
2997 | Serge | 3641 | radeon_ring_write(ring, PACKET0(scratch, 0)); |
3642 | radeon_ring_write(ring, 0xDEADBEEF); |
||
5078 | serge | 3643 | radeon_ring_unlock_commit(rdev, ring, false); |
1412 | serge | 3644 | for (i = 0; i < rdev->usec_timeout; i++) { |
3645 | tmp = RREG32(scratch); |
||
3646 | if (tmp == 0xDEADBEEF) { |
||
3647 | break; |
||
3648 | } |
||
3649 | DRM_UDELAY(1); |
||
3650 | } |
||
3651 | if (i < rdev->usec_timeout) { |
||
3652 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
||
3653 | } else { |
||
1963 | serge | 3654 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", |
1412 | serge | 3655 | scratch, tmp); |
3656 | r = -EINVAL; |
||
3657 | } |
||
3658 | radeon_scratch_free(rdev, scratch); |
||
3659 | return r; |
||
3660 | } |
||
3661 | |||
1963 | serge | 3662 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
3663 | { |
||
2997 | Serge | 3664 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3665 | |||
3666 | if (ring->rptr_save_reg) { |
||
3667 | u32 next_rptr = ring->wptr + 2 + 3; |
||
3668 | radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); |
||
3669 | radeon_ring_write(ring, next_rptr); |
||
3670 | } |
||
3671 | |||
3672 | radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); |
||
3673 | radeon_ring_write(ring, ib->gpu_addr); |
||
3674 | radeon_ring_write(ring, ib->length_dw); |
||
1963 | serge | 3675 | } |
3676 | |||
2997 | Serge | 3677 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
1963 | serge | 3678 | { |
2997 | Serge | 3679 | struct radeon_ib ib; |
1963 | serge | 3680 | uint32_t scratch; |
3681 | uint32_t tmp = 0; |
||
3682 | unsigned i; |
||
3683 | int r; |
||
3684 | |||
3685 | r = radeon_scratch_get(rdev, &scratch); |
||
3686 | if (r) { |
||
3687 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
||
3688 | return r; |
||
3689 | } |
||
3690 | WREG32(scratch, 0xCAFEDEAD); |
||
2997 | Serge | 3691 | r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); |
1963 | serge | 3692 | if (r) { |
2997 | Serge | 3693 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
3694 | goto free_scratch; |
||
1963 | serge | 3695 | } |
2997 | Serge | 3696 | ib.ptr[0] = PACKET0(scratch, 0); |
3697 | ib.ptr[1] = 0xDEADBEEF; |
||
3698 | ib.ptr[2] = PACKET2(0); |
||
3699 | ib.ptr[3] = PACKET2(0); |
||
3700 | ib.ptr[4] = PACKET2(0); |
||
3701 | ib.ptr[5] = PACKET2(0); |
||
3702 | ib.ptr[6] = PACKET2(0); |
||
3703 | ib.ptr[7] = PACKET2(0); |
||
3704 | ib.length_dw = 8; |
||
5078 | serge | 3705 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
1963 | serge | 3706 | if (r) { |
2997 | Serge | 3707 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
3708 | goto free_ib; |
||
1963 | serge | 3709 | } |
2997 | Serge | 3710 | r = radeon_fence_wait(ib.fence, false); |
1963 | serge | 3711 | if (r) { |
2997 | Serge | 3712 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
3713 | goto free_ib; |
||
1963 | serge | 3714 | } |
3715 | for (i = 0; i < rdev->usec_timeout; i++) { |
||
3716 | tmp = RREG32(scratch); |
||
3717 | if (tmp == 0xDEADBEEF) { |
||
3718 | break; |
||
3719 | } |
||
3720 | DRM_UDELAY(1); |
||
3721 | } |
||
3722 | if (i < rdev->usec_timeout) { |
||
3723 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
||
3724 | } else { |
||
3725 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
||
3726 | scratch, tmp); |
||
3727 | r = -EINVAL; |
||
3728 | } |
||
2997 | Serge | 3729 | free_ib: |
3730 | radeon_ib_free(rdev, &ib); |
||
3731 | free_scratch: |
||
1963 | serge | 3732 | radeon_scratch_free(rdev, scratch); |
3733 | return r; |
||
3734 | } |
||
3735 | |||
1179 | serge | 3736 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
3737 | { |
||
3738 | /* Shutdown CP we shouldn't need to do that but better be safe than |
||
3739 | * sorry |
||
3740 | */ |
||
2997 | Serge | 3741 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1179 | serge | 3742 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
3743 | |||
3744 | /* Save few CRTC registers */ |
||
1221 | serge | 3745 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
1179 | serge | 3746 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3747 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
||
3748 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
||
3749 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
3750 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
||
3751 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
||
3752 | } |
||
3753 | |||
3754 | /* Disable VGA aperture access */ |
||
1221 | serge | 3755 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
1179 | serge | 3756 | /* Disable cursor, overlay, crtc */ |
3757 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
||
3758 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
||
3759 | S_000054_CRTC_DISPLAY_DIS(1)); |
||
3760 | WREG32(R_000050_CRTC_GEN_CNTL, |
||
3761 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
||
3762 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
||
3763 | WREG32(R_000420_OV0_SCALE_CNTL, |
||
3764 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
||
3765 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
||
3766 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
3767 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
||
3768 | S_000360_CUR2_LOCK(1)); |
||
3769 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
||
3770 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
||
3771 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
||
3772 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
||
3773 | WREG32(R_000360_CUR2_OFFSET, |
||
3774 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
||
3775 | } |
||
3776 | } |
||
3777 | |||
3778 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
||
3779 | { |
||
3780 | /* Update base address for crtc */ |
||
1430 | serge | 3781 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
1179 | serge | 3782 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
1430 | serge | 3783 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
1179 | serge | 3784 | } |
3785 | /* Restore CRTC registers */ |
||
1221 | serge | 3786 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
1179 | serge | 3787 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3788 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
||
3789 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
||
3790 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
||
3791 | } |
||
3792 | } |
||
3793 | |||
1221 | serge | 3794 | void r100_vga_render_disable(struct radeon_device *rdev) |
3795 | { |
||
3796 | u32 tmp; |
||
3797 | |||
3798 | tmp = RREG8(R_0003C2_GENMO_WT); |
||
3799 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
||
3800 | } |
||
3801 | |||
3802 | static void r100_debugfs(struct radeon_device *rdev) |
||
3803 | { |
||
3804 | int r; |
||
3805 | |||
3806 | r = r100_debugfs_mc_info_init(rdev); |
||
3807 | if (r) |
||
3808 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
||
3809 | } |
||
3810 | |||
3811 | static void r100_mc_program(struct radeon_device *rdev) |
||
3812 | { |
||
3813 | struct r100_mc_save save; |
||
3814 | |||
3815 | /* Stops all mc clients */ |
||
3816 | r100_mc_stop(rdev, &save); |
||
3817 | if (rdev->flags & RADEON_IS_AGP) { |
||
3818 | WREG32(R_00014C_MC_AGP_LOCATION, |
||
3819 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
||
3820 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
||
3821 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
||
3822 | if (rdev->family > CHIP_RV200) |
||
3823 | WREG32(R_00015C_AGP_BASE_2, |
||
3824 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
||
3825 | } else { |
||
3826 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
||
3827 | WREG32(R_000170_AGP_BASE, 0); |
||
3828 | if (rdev->family > CHIP_RV200) |
||
3829 | WREG32(R_00015C_AGP_BASE_2, 0); |
||
3830 | } |
||
3831 | /* Wait for mc idle */ |
||
3832 | if (r100_mc_wait_for_idle(rdev)) |
||
3833 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
||
3834 | /* Program MC, should be a 32bits limited address space */ |
||
3835 | WREG32(R_000148_MC_FB_LOCATION, |
||
3836 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
||
3837 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
||
3838 | r100_mc_resume(rdev, &save); |
||
3839 | } |
||
3840 | |||
2997 | Serge | 3841 | static void r100_clock_startup(struct radeon_device *rdev) |
1221 | serge | 3842 | { |
3843 | u32 tmp; |
||
3844 | |||
3845 | if (radeon_dynclks != -1 && radeon_dynclks) |
||
3846 | radeon_legacy_set_clock_gating(rdev, 1); |
||
3847 | /* We need to force on some of the block */ |
||
3848 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
||
3849 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
||
3850 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
||
3851 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
||
3852 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
||
3853 | } |
||
3854 | |||
3855 | static int r100_startup(struct radeon_device *rdev) |
||
3856 | { |
||
3857 | int r; |
||
3858 | |||
1321 | serge | 3859 | /* set common regs */ |
3860 | r100_set_common_regs(rdev); |
||
3861 | /* program mc */ |
||
1221 | serge | 3862 | r100_mc_program(rdev); |
3863 | /* Resume clock */ |
||
3864 | r100_clock_startup(rdev); |
||
3865 | /* Initialize GART (initialize after TTM so we can allocate |
||
3866 | * memory through TTM but finalize after TTM) */ |
||
1321 | serge | 3867 | r100_enable_bm(rdev); |
1221 | serge | 3868 | if (rdev->flags & RADEON_IS_PCI) { |
3869 | r = r100_pci_gart_enable(rdev); |
||
3870 | if (r) |
||
3871 | return r; |
||
3872 | } |
||
2005 | serge | 3873 | |
3874 | /* allocate wb buffer */ |
||
3875 | r = radeon_wb_init(rdev); |
||
3876 | if (r) |
||
3877 | return r; |
||
3878 | |||
3120 | serge | 3879 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3880 | if (r) { |
||
3881 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
||
3882 | return r; |
||
3883 | } |
||
3884 | |||
1221 | serge | 3885 | /* Enable IRQ */ |
3764 | Serge | 3886 | if (!rdev->irq.installed) { |
3887 | r = radeon_irq_kms_init(rdev); |
||
3888 | if (r) |
||
3889 | return r; |
||
3890 | } |
||
3891 | |||
2005 | serge | 3892 | r100_irq_set(rdev); |
1404 | serge | 3893 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 3894 | /* 1M ring buffer */ |
1412 | serge | 3895 | r = r100_cp_init(rdev, 1024 * 1024); |
3896 | if (r) { |
||
1963 | serge | 3897 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1412 | serge | 3898 | return r; |
3899 | } |
||
2997 | Serge | 3900 | |
3901 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 3902 | if (r) { |
2997 | Serge | 3903 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 3904 | return r; |
3905 | } |
||
3120 | serge | 3906 | |
1221 | serge | 3907 | return 0; |
3908 | } |
||
3909 | |||
1963 | serge | 3910 | /* |
3911 | * Due to how kexec works, it can leave the hw fully initialised when it |
||
3912 | * boots the new kernel. However doing our init sequence with the CP and |
||
3913 | * WB stuff setup causes GPU hangs on the RN50 at least. So at startup |
||
3914 | * do some quick sanity checks and restore sane values to avoid this |
||
3915 | * problem. |
||
3916 | */ |
||
3917 | void r100_restore_sanity(struct radeon_device *rdev) |
||
3918 | { |
||
3919 | u32 tmp; |
||
1221 | serge | 3920 | |
1963 | serge | 3921 | tmp = RREG32(RADEON_CP_CSQ_CNTL); |
3922 | if (tmp) { |
||
3923 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
||
3924 | } |
||
3925 | tmp = RREG32(RADEON_CP_RB_CNTL); |
||
3926 | if (tmp) { |
||
3927 | WREG32(RADEON_CP_RB_CNTL, 0); |
||
3928 | } |
||
3929 | tmp = RREG32(RADEON_SCRATCH_UMSK); |
||
3930 | if (tmp) { |
||
3931 | WREG32(RADEON_SCRATCH_UMSK, 0); |
||
3932 | } |
||
3933 | } |
||
1221 | serge | 3934 | |
3935 | int r100_init(struct radeon_device *rdev) |
||
3936 | { |
||
3937 | int r; |
||
3938 | |||
3939 | /* Register debugfs file specific to this group of asics */ |
||
3940 | r100_debugfs(rdev); |
||
3941 | /* Disable VGA */ |
||
3942 | r100_vga_render_disable(rdev); |
||
3943 | /* Initialize scratch registers */ |
||
3944 | radeon_scratch_init(rdev); |
||
3945 | /* Initialize surface registers */ |
||
3946 | radeon_surface_init(rdev); |
||
1963 | serge | 3947 | /* sanity check some register to avoid hangs like after kexec */ |
3948 | r100_restore_sanity(rdev); |
||
1221 | serge | 3949 | /* TODO: disable VGA need to use VGA request */ |
3950 | /* BIOS*/ |
||
3951 | if (!radeon_get_bios(rdev)) { |
||
3952 | if (ASIC_IS_AVIVO(rdev)) |
||
3953 | return -EINVAL; |
||
3954 | } |
||
3955 | if (rdev->is_atom_bios) { |
||
3956 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
||
3957 | return -EINVAL; |
||
3958 | } else { |
||
3959 | r = radeon_combios_init(rdev); |
||
3960 | if (r) |
||
3961 | return r; |
||
3962 | } |
||
3963 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 3964 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 3965 | dev_warn(rdev->dev, |
3966 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
3967 | RREG32(R_000E40_RBBM_STATUS), |
||
3968 | RREG32(R_0007C0_CP_STAT)); |
||
3969 | } |
||
3970 | /* check if cards are posted or not */ |
||
1321 | serge | 3971 | if (radeon_boot_test_post_card(rdev) == false) |
3972 | return -EINVAL; |
||
1221 | serge | 3973 | /* Set asic errata */ |
3974 | r100_errata(rdev); |
||
3975 | /* Initialize clocks */ |
||
3976 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 3977 | /* initialize AGP */ |
3978 | if (rdev->flags & RADEON_IS_AGP) { |
||
3979 | r = radeon_agp_init(rdev); |
||
3980 | if (r) { |
||
3981 | radeon_agp_disable(rdev); |
||
3982 | } |
||
3983 | } |
||
3984 | /* initialize VRAM */ |
||
3985 | r100_mc_init(rdev); |
||
1221 | serge | 3986 | /* Fence driver */ |
2005 | serge | 3987 | r = radeon_fence_driver_init(rdev); |
3988 | if (r) |
||
3989 | return r; |
||
1221 | serge | 3990 | /* Memory manager */ |
1321 | serge | 3991 | r = radeon_bo_init(rdev); |
1221 | serge | 3992 | if (r) |
3993 | return r; |
||
3994 | if (rdev->flags & RADEON_IS_PCI) { |
||
3995 | r = r100_pci_gart_init(rdev); |
||
3996 | if (r) |
||
3997 | return r; |
||
3998 | } |
||
3999 | r100_set_safe_registers(rdev); |
||
2997 | Serge | 4000 | |
5078 | serge | 4001 | /* Initialize power management */ |
4002 | radeon_pm_init(rdev); |
||
4003 | |||
1221 | serge | 4004 | rdev->accel_working = true; |
4005 | r = r100_startup(rdev); |
||
4006 | if (r) { |
||
4007 | /* Somethings want wront with the accel init stop accel */ |
||
4008 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
4009 | if (rdev->flags & RADEON_IS_PCI) |
||
4010 | r100_pci_gart_fini(rdev); |
||
4011 | rdev->accel_working = false; |
||
4012 | } |
||
4013 | return 0; |
||
4014 | } |
||
2997 | Serge | 4015 | |
4016 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
||
4017 | { |
||
4018 | if (reg < rdev->rio_mem_size) |
||
4019 | return ioread32(rdev->rio_mem + reg); |
||
4020 | else { |
||
4021 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
||
4022 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
||
4023 | } |
||
4024 | } |
||
4025 | |||
4026 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
||
4027 | { |
||
4028 | if (reg < rdev->rio_mem_size) |
||
4029 | iowrite32(v, rdev->rio_mem + reg); |
||
4030 | else { |
||
4031 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
||
4032 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
||
4033 | } |
||
4034 | }>>>>>>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>>=>>>><>=>><>><>><>><>>=>=>><>>><>=>><>>=>>>><>><>=>><>>>>>=>><>><>>>>=>>>>><>>><>><>><>><>><>><>>=>>>>>><>><>>><>><>><>><>><>>><>><>><>><>=>><>>><>><>>>><>><>><>><>><>><>><>><>=>>> |