WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1963	serge	29	#include
1125	serge	30	#include "drmP.h"
		31	#include "drm.h"
1117	serge	32	#include "radeon_drm.h"
		33	#include "radeon_reg.h"
		34	#include "radeon.h"
1963	serge	35	#include "radeon_asic.h"
1179	serge	36	#include "r100d.h"
1221	serge	37	#include "rs100d.h"
		38	#include "rv200d.h"
		39	#include "rv250d.h"
1963	serge	40	#include "atom.h"
1117	serge	41
1221	serge	42	#include
		43
1179	serge	44	#include "r100_reg_safe.h"
		45	#include "rn50_reg_safe.h"
1221	serge	46
		47	/* Firmware Names */
		48	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		49	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		50	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		51	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		52	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		53	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		54	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		55
		56	MODULE_FIRMWARE(FIRMWARE_R100);
		57	MODULE_FIRMWARE(FIRMWARE_R200);
		58	MODULE_FIRMWARE(FIRMWARE_R300);
		59	MODULE_FIRMWARE(FIRMWARE_R420);
		60	MODULE_FIRMWARE(FIRMWARE_RS690);
		61	MODULE_FIRMWARE(FIRMWARE_RS600);
		62	MODULE_FIRMWARE(FIRMWARE_R520);
		63
		64
1117	serge	65	/* This files gather functions specifics to:
		66	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		67	*/
		68
1963	serge	69	u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		70	{
		71	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		72	u32 tmp = ((u32)crtc_base) \| RADEON_CRTC_OFFSET__OFFSET_LOCK;
		73
		74	/* Lock the graphics update lock */
		75	/* update the scanout addresses */
		76	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		77
		78	/* Wait for update_pending to go high. */
		79	while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
		80	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
		81
		82	/* Unlock the lock, so double-buffering can take place inside vblank */
		83	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
		84	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
		85
		86	/* Return current update_pending status: */
		87	return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
		88	}
		89	bool r100_gui_idle(struct radeon_device *rdev)
		90	{
		91	if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		92	return false;
		93	else
		94	return true;
		95	}
		96
1321	serge	97	/* hpd for digital panel detect/disconnect */
		98	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		99	{
		100	bool connected = false;
		101
		102	switch (hpd) {
		103	case RADEON_HPD_1:
		104	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		105	connected = true;
		106	break;
		107	case RADEON_HPD_2:
		108	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		109	connected = true;
		110	break;
		111	default:
		112	break;
		113	}
		114	return connected;
		115	}
		116
		117	void r100_hpd_set_polarity(struct radeon_device *rdev,
		118	enum radeon_hpd_id hpd)
		119	{
		120	u32 tmp;
		121	bool connected = r100_hpd_sense(rdev, hpd);
		122
		123	switch (hpd) {
		124	case RADEON_HPD_1:
		125	tmp = RREG32(RADEON_FP_GEN_CNTL);
		126	if (connected)
		127	tmp &= ~RADEON_FP_DETECT_INT_POL;
		128	else
		129	tmp \|= RADEON_FP_DETECT_INT_POL;
		130	WREG32(RADEON_FP_GEN_CNTL, tmp);
		131	break;
		132	case RADEON_HPD_2:
		133	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		134	if (connected)
		135	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		136	else
		137	tmp \|= RADEON_FP2_DETECT_INT_POL;
		138	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		139	break;
		140	default:
		141	break;
		142	}
		143	}
		144
		145	void r100_hpd_init(struct radeon_device *rdev)
		146	{
		147	struct drm_device *dev = rdev->ddev;
		148	struct drm_connector *connector;
		149
		150	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		151	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		152	switch (radeon_connector->hpd.hpd) {
		153	case RADEON_HPD_1:
2005	serge	154	rdev->irq.hpd[0] = true;
1321	serge	155	break;
		156	case RADEON_HPD_2:
2005	serge	157	rdev->irq.hpd[1] = true;
1321	serge	158	break;
		159	default:
		160	break;
		161	}
		162	}
2005	serge	163	if (rdev->irq.installed)
		164	r100_irq_set(rdev);
1321	serge	165	}
		166
		167	void r100_hpd_fini(struct radeon_device *rdev)
		168	{
		169	struct drm_device *dev = rdev->ddev;
		170	struct drm_connector *connector;
		171
		172	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		173	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		174	switch (radeon_connector->hpd.hpd) {
		175	case RADEON_HPD_1:
2005	serge	176	rdev->irq.hpd[0] = false;
1321	serge	177	break;
		178	case RADEON_HPD_2:
2005	serge	179	rdev->irq.hpd[1] = false;
1321	serge	180	break;
		181	default:
		182	break;
		183	}
		184	}
		185	}
		186
1117	serge	187	/*
		188	* PCI GART
		189	*/
		190	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		191	{
		192	/* TODO: can we do somethings here ? */
		193	/* It seems hw only cache one entry so we should discard this
		194	* entry otherwise if first GPU GART read hit this entry it
		195	* could end up in wrong address. */
		196	}
		197
1179	serge	198	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	199	{
		200	int r;
		201
1179	serge	202	if (rdev->gart.table.ram.ptr) {
1963	serge	203	WARN(1, "R100 PCI GART already initialized\n");
1179	serge	204	return 0;
		205	}
1117	serge	206	/* Initialize common gart structure */
		207	r = radeon_gart_init(rdev);
1179	serge	208	if (r)
1117	serge	209	return r;
1268	serge	210	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	211	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		212	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		213	return radeon_gart_table_ram_alloc(rdev);
		214	}
		215
1321	serge	216	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		217	void r100_enable_bm(struct radeon_device *rdev)
		218	{
		219	uint32_t tmp;
		220	/* Enable bus mastering */
		221	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		222	WREG32(RADEON_BUS_CNTL, tmp);
		223	}
		224
1179	serge	225	int r100_pci_gart_enable(struct radeon_device *rdev)
		226	{
		227	uint32_t tmp;
		228
1430	serge	229	radeon_gart_restore(rdev);
1117	serge	230	/* discard memory request outside of configured range */
		231	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		232	WREG32(RADEON_AIC_CNTL, tmp);
		233	/* set address range for PCI address translate */
1430	serge	234	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		235	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	236	/* set PCI GART page-table base address */
		237	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		238	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		239	WREG32(RADEON_AIC_CNTL, tmp);
		240	r100_pci_gart_tlb_flush(rdev);
		241	rdev->gart.ready = true;
		242	return 0;
		243	}
		244
		245	void r100_pci_gart_disable(struct radeon_device *rdev)
		246	{
		247	uint32_t tmp;
		248
		249	/* discard memory request outside of configured range */
		250	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		251	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		252	WREG32(RADEON_AIC_LO_ADDR, 0);
		253	WREG32(RADEON_AIC_HI_ADDR, 0);
		254	}
		255
		256	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		257	{
		258	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		259	return -EINVAL;
		260	}
1179	serge	261	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	262	return 0;
		263	}
		264
1179	serge	265	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	266	{
1963	serge	267	radeon_gart_fini(rdev);
1117	serge	268	r100_pci_gart_disable(rdev);
1179	serge	269	radeon_gart_table_ram_free(rdev);
1117	serge	270	}
		271
2005	serge	272	int r100_irq_set(struct radeon_device *rdev)
		273	{
		274	uint32_t tmp = 0;
1117	serge	275
2005	serge	276	if (!rdev->irq.installed) {
		277	WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
		278	WREG32(R_000040_GEN_INT_CNTL, 0);
		279	return -EINVAL;
		280	}
		281	if (rdev->irq.sw_int) {
		282	tmp \|= RADEON_SW_INT_ENABLE;
		283	}
		284	if (rdev->irq.gui_idle) {
		285	tmp \|= RADEON_GUI_IDLE_MASK;
		286	}
		287	if (rdev->irq.crtc_vblank_int[0] \|\|
		288	rdev->irq.pflip[0]) {
		289	tmp \|= RADEON_CRTC_VBLANK_MASK;
		290	}
		291	if (rdev->irq.crtc_vblank_int[1] \|\|
		292	rdev->irq.pflip[1]) {
		293	tmp \|= RADEON_CRTC2_VBLANK_MASK;
		294	}
		295	if (rdev->irq.hpd[0]) {
		296	tmp \|= RADEON_FP_DETECT_MASK;
		297	}
		298	if (rdev->irq.hpd[1]) {
		299	tmp \|= RADEON_FP2_DETECT_MASK;
		300	}
		301	WREG32(RADEON_GEN_INT_CNTL, tmp);
		302	return 0;
		303	}
		304
1221	serge	305	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	306	{
1221	serge	307	u32 tmp;
1117	serge	308
1221	serge	309	WREG32(R_000040_GEN_INT_CNTL, 0);
		310	/* Wait and acknowledge irq */
		311	mdelay(1);
		312	tmp = RREG32(R_000044_GEN_INT_STATUS);
		313	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	314	}
		315
1221	serge	316	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	317	{
1221	serge	318	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	319	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		320	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		321	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	322
1963	serge	323	/* the interrupt works, but the status bit is permanently asserted */
		324	if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
		325	if (!rdev->irq.gui_idle_acked)
		326	irq_mask \|= RADEON_GUI_IDLE_STAT;
		327	}
		328
1221	serge	329	if (irqs) {
		330	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	331	}
1221	serge	332	return irqs & irq_mask;
1117	serge	333	}
		334
2005	serge	335	int r100_irq_process(struct radeon_device *rdev)
		336	{
		337	uint32_t status, msi_rearm;
		338	bool queue_hotplug = false;
1117	serge	339
2005	serge	340	/* reset gui idle ack. the status bit is broken */
		341	rdev->irq.gui_idle_acked = false;
1963	serge	342
2005	serge	343	status = r100_irq_ack(rdev);
		344	if (!status) {
		345	return IRQ_NONE;
		346	}
		347	if (rdev->shutdown) {
		348	return IRQ_NONE;
		349	}
		350	while (status) {
		351	/* SW interrupt */
		352	if (status & RADEON_SW_INT_TEST) {
		353	radeon_fence_process(rdev);
		354	}
		355	/* gui idle interrupt */
		356	if (status & RADEON_GUI_IDLE_STAT) {
		357	rdev->irq.gui_idle_acked = true;
		358	rdev->pm.gui_idle = true;
		359	// wake_up(&rdev->irq.idle_queue);
		360	}
		361	/* Vertical blank interrupts */
		362	if (status & RADEON_CRTC_VBLANK_STAT) {
		363	if (rdev->irq.crtc_vblank_int[0]) {
		364	// drm_handle_vblank(rdev->ddev, 0);
		365	rdev->pm.vblank_sync = true;
		366	// wake_up(&rdev->irq.vblank_queue);
		367	}
		368	// if (rdev->irq.pflip[0])
		369	// radeon_crtc_handle_flip(rdev, 0);
		370	}
		371	if (status & RADEON_CRTC2_VBLANK_STAT) {
		372	if (rdev->irq.crtc_vblank_int[1]) {
		373	// drm_handle_vblank(rdev->ddev, 1);
		374	rdev->pm.vblank_sync = true;
		375	// wake_up(&rdev->irq.vblank_queue);
		376	}
		377	// if (rdev->irq.pflip[1])
		378	// radeon_crtc_handle_flip(rdev, 1);
		379	}
		380	if (status & RADEON_FP_DETECT_STAT) {
		381	queue_hotplug = true;
		382	DRM_DEBUG("HPD1\n");
		383	}
		384	if (status & RADEON_FP2_DETECT_STAT) {
		385	queue_hotplug = true;
		386	DRM_DEBUG("HPD2\n");
		387	}
		388	status = r100_irq_ack(rdev);
		389	}
		390	/* reset gui idle ack. the status bit is broken */
		391	rdev->irq.gui_idle_acked = false;
		392	// if (queue_hotplug)
		393	// schedule_work(&rdev->hotplug_work);
		394	if (rdev->msi_enabled) {
		395	switch (rdev->family) {
		396	case CHIP_RS400:
		397	case CHIP_RS480:
		398	msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
		399	WREG32(RADEON_AIC_CNTL, msi_rearm);
		400	WREG32(RADEON_AIC_CNTL, msi_rearm \| RS400_MSI_REARM);
		401	break;
		402	default:
		403	msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
		404	WREG32(RADEON_MSI_REARM_EN, msi_rearm);
		405	WREG32(RADEON_MSI_REARM_EN, msi_rearm \| RV370_MSI_REARM_EN);
		406	break;
		407	}
		408	}
		409	return IRQ_HANDLED;
		410	}
		411
1403	serge	412	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		413	{
		414	if (crtc == 0)
		415	return RREG32(RADEON_CRTC_CRNT_FRAME);
		416	else
		417	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		418	}
1117	serge	419
1404	serge	420	/* Who ever call radeon_fence_emit should call ring_lock and ask
		421	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	422	void r100_fence_ring_emit(struct radeon_device *rdev,
		423	struct radeon_fence *fence)
		424	{
1404	serge	425	/* We have to make sure that caches are flushed before
		426	* CPU might read something from VRAM. */
		427	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		428	radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
		429	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		430	radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	431	/* Wait until IDLE & CLEAN */
1430	serge	432	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		433	radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
1403	serge	434	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		435	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl \|
		436	RADEON_HDP_READ_BUFFER_INVALIDATE);
		437	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		438	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
1117	serge	439	/* Emit fence sequence & fire IRQ */
		440	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		441	radeon_ring_write(rdev, fence->seq);
		442	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		443	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		444	}
		445
		446	int r100_copy_blit(struct radeon_device *rdev,
		447	uint64_t src_offset,
		448	uint64_t dst_offset,
		449	unsigned num_pages,
		450	struct radeon_fence *fence)
		451	{
		452	uint32_t cur_pages;
		453	uint32_t stride_bytes = PAGE_SIZE;
		454	uint32_t pitch;
		455	uint32_t stride_pixels;
		456	unsigned ndw;
		457	int num_loops;
		458	int r = 0;
		459
		460	/* radeon limited to 16k stride */
		461	stride_bytes &= 0x3fff;
		462	/* radeon pitch is /64 */
		463	pitch = stride_bytes / 64;
		464	stride_pixels = stride_bytes / 4;
		465	num_loops = DIV_ROUND_UP(num_pages, 8191);
		466
		467	/* Ask for enough room for blit + flush + fence */
		468	ndw = 64 + (10 * num_loops);
		469	r = radeon_ring_lock(rdev, ndw);
		470	if (r) {
		471	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		472	return -EINVAL;
		473	}
		474	while (num_pages > 0) {
		475	cur_pages = num_pages;
		476	if (cur_pages > 8191) {
		477	cur_pages = 8191;
		478	}
		479	num_pages -= cur_pages;
		480
		481	/* pages are in Y direction - height
		482	page width in X direction - width */
		483	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		484	radeon_ring_write(rdev,
		485	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		486	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		487	RADEON_GMC_SRC_CLIPPING \|
		488	RADEON_GMC_DST_CLIPPING \|
		489	RADEON_GMC_BRUSH_NONE \|
		490	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		491	RADEON_GMC_SRC_DATATYPE_COLOR \|
		492	RADEON_ROP3_S \|
		493	RADEON_DP_SRC_SOURCE_MEMORY \|
		494	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		495	RADEON_GMC_WR_MSK_DIS);
		496	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		497	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		498	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		499	radeon_ring_write(rdev, 0);
		500	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		501	radeon_ring_write(rdev, num_pages);
		502	radeon_ring_write(rdev, num_pages);
		503	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		504	}
		505	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		506	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		507	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		508	radeon_ring_write(rdev,
		509	RADEON_WAIT_2D_IDLECLEAN \|
		510	RADEON_WAIT_HOST_IDLECLEAN \|
		511	RADEON_WAIT_DMA_GUI_IDLE);
		512	if (fence) {
		513	r = radeon_fence_emit(rdev, fence);
		514	}
		515	radeon_ring_unlock_commit(rdev);
		516	return r;
		517	}
		518
1179	serge	519	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		520	{
		521	unsigned i;
		522	u32 tmp;
		523
		524	for (i = 0; i < rdev->usec_timeout; i++) {
		525	tmp = RREG32(R_000E40_RBBM_STATUS);
		526	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		527	return 0;
		528	}
		529	udelay(1);
		530	}
		531	return -1;
		532	}
		533
1117	serge	534	void r100_ring_start(struct radeon_device *rdev)
		535	{
		536	int r;
		537
		538	r = radeon_ring_lock(rdev, 2);
		539	if (r) {
		540	return;
		541	}
		542	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		543	radeon_ring_write(rdev,
		544	RADEON_ISYNC_ANY2D_IDLE3D \|
		545	RADEON_ISYNC_ANY3D_IDLE2D \|
		546	RADEON_ISYNC_WAIT_IDLEGUI \|
		547	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		548	radeon_ring_unlock_commit(rdev);
		549	}
		550
1221	serge	551
		552	/* Load the microcode for the CP */
		553	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	554	{
1221	serge	555	struct platform_device *pdev;
		556	const char *fw_name = NULL;
		557	int err;
1117	serge	558
1963	serge	559	DRM_DEBUG_KMS("\n");
1117	serge	560
1412	serge	561	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		562	err = IS_ERR(pdev);
		563	if (err) {
		564	printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		565	return -EINVAL;
		566	}
1117	serge	567	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		568	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		569	(rdev->family == CHIP_RS200)) {
		570	DRM_INFO("Loading R100 Microcode\n");
1221	serge	571	fw_name = FIRMWARE_R100;
1117	serge	572	} else if ((rdev->family == CHIP_R200) \|\|
		573	(rdev->family == CHIP_RV250) \|\|
		574	(rdev->family == CHIP_RV280) \|\|
		575	(rdev->family == CHIP_RS300)) {
		576	DRM_INFO("Loading R200 Microcode\n");
1221	serge	577	fw_name = FIRMWARE_R200;
1117	serge	578	} else if ((rdev->family == CHIP_R300) \|\|
		579	(rdev->family == CHIP_R350) \|\|
		580	(rdev->family == CHIP_RV350) \|\|
		581	(rdev->family == CHIP_RV380) \|\|
		582	(rdev->family == CHIP_RS400) \|\|
		583	(rdev->family == CHIP_RS480)) {
		584	DRM_INFO("Loading R300 Microcode\n");
1221	serge	585	fw_name = FIRMWARE_R300;
1117	serge	586	} else if ((rdev->family == CHIP_R420) \|\|
		587	(rdev->family == CHIP_R423) \|\|
		588	(rdev->family == CHIP_RV410)) {
		589	DRM_INFO("Loading R400 Microcode\n");
1221	serge	590	fw_name = FIRMWARE_R420;
1117	serge	591	} else if ((rdev->family == CHIP_RS690) \|\|
		592	(rdev->family == CHIP_RS740)) {
		593	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	594	fw_name = FIRMWARE_RS690;
1117	serge	595	} else if (rdev->family == CHIP_RS600) {
		596	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	597	fw_name = FIRMWARE_RS600;
1117	serge	598	} else if ((rdev->family == CHIP_RV515) \|\|
		599	(rdev->family == CHIP_R520) \|\|
		600	(rdev->family == CHIP_RV530) \|\|
		601	(rdev->family == CHIP_R580) \|\|
		602	(rdev->family == CHIP_RV560) \|\|
		603	(rdev->family == CHIP_RV570)) {
		604	DRM_INFO("Loading R500 Microcode\n");
1221	serge	605	fw_name = FIRMWARE_R520;
1117	serge	606	}
1221	serge	607
1412	serge	608	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		609	platform_device_unregister(pdev);
1221	serge	610	if (err) {
		611	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		612	fw_name);
		613	} else if (rdev->me_fw->size % 8) {
		614	printk(KERN_ERR
		615	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		616	rdev->me_fw->size, fw_name);
		617	err = -EINVAL;
		618	release_firmware(rdev->me_fw);
		619	rdev->me_fw = NULL;
1117	serge	620	}
1221	serge	621	return err;
1117	serge	622	}
		623
1221	serge	624	static void r100_cp_load_microcode(struct radeon_device *rdev)
		625	{
		626	const __be32 *fw_data;
		627	int i, size;
		628
		629	if (r100_gui_wait_for_idle(rdev)) {
		630	printk(KERN_WARNING "Failed to wait GUI idle while "
		631	"programming pipes. Bad things might happen.\n");
		632	}
		633
		634	if (rdev->me_fw) {
		635	size = rdev->me_fw->size / 4;
		636	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		637	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		638	for (i = 0; i < size; i += 2) {
		639	WREG32(RADEON_CP_ME_RAM_DATAH,
		640	be32_to_cpup(&fw_data[i]));
		641	WREG32(RADEON_CP_ME_RAM_DATAL,
		642	be32_to_cpup(&fw_data[i + 1]));
		643	}
		644	}
		645	}
		646
1117	serge	647	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		648	{
		649	unsigned rb_bufsz;
		650	unsigned rb_blksz;
		651	unsigned max_fetch;
		652	unsigned pre_write_timer;
		653	unsigned pre_write_limit;
		654	unsigned indirect2_start;
		655	unsigned indirect1_start;
		656	uint32_t tmp;
		657	int r;
		658
1129	serge	659	if (r100_debugfs_cp_init(rdev)) {
		660	DRM_ERROR("Failed to register debugfs file for CP !\n");
		661	}
1179	serge	662	if (!rdev->me_fw) {
		663	r = r100_cp_init_microcode(rdev);
		664	if (r) {
		665	DRM_ERROR("Failed to load firmware!\n");
		666	return r;
		667	}
		668	}
		669
1117	serge	670	/* Align ring size */
		671	rb_bufsz = drm_order(ring_size / 8);
		672	ring_size = (1 << (rb_bufsz + 1)) * 4;
		673	r100_cp_load_microcode(rdev);
		674	r = radeon_ring_init(rdev, ring_size);
		675	if (r) {
		676	return r;
		677	}
		678	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		679	* the rptr copy in system ram */
		680	rb_blksz = 9;
		681	/* cp will read 128bytes at a time (4 dwords) */
		682	max_fetch = 1;
		683	rdev->cp.align_mask = 16 - 1;
		684	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		685	pre_write_timer = 64;
		686	/* Force CP_RB_WPTR write if written more than one time before the
		687	* delay expire
		688	*/
		689	pre_write_limit = 0;
		690	/* Setup the cp cache like this (cache size is 96 dwords) :
		691	* RING 0 to 15
		692	* INDIRECT1 16 to 79
		693	* INDIRECT2 80 to 95
		694	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		695	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		696	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		697	* Idea being that most of the gpu cmd will be through indirect1 buffer
		698	* so it gets the bigger cache.
		699	*/
		700	indirect2_start = 80;
		701	indirect1_start = 16;
		702	/* cp setup */
		703	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	704	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	705	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
1963	serge	706	REG_SET(RADEON_MAX_FETCH, max_fetch));
1268	serge	707	#ifdef __BIG_ENDIAN
		708	tmp \|= RADEON_BUF_SWAP_32BIT;
		709	#endif
1963	serge	710	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE);
1268	serge	711
1117	serge	712	/* Set ring address */
		713	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		714	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		715	/* Force read & write ptr to 0 */
1963	serge	716	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE);
1117	serge	717	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		718	WREG32(RADEON_CP_RB_WPTR, 0);
1963	serge	719
		720	/* set the wb address whether it's enabled or not */
		721	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		722	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
		723	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
		724
		725	if (rdev->wb.enabled)
		726	WREG32(R_000770_SCRATCH_UMSK, 0xff);
		727	else {
		728	tmp \|= RADEON_RB_NO_UPDATE;
		729	WREG32(R_000770_SCRATCH_UMSK, 0);
		730	}
		731
1117	serge	732	WREG32(RADEON_CP_RB_CNTL, tmp);
		733	udelay(10);
		734	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		735	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1963	serge	736	/* protect against crazy HW on resume */
		737	rdev->cp.wptr &= rdev->cp.ptr_mask;
1117	serge	738	/* Set cp mode to bus mastering & enable cp*/
		739	WREG32(RADEON_CP_CSQ_MODE,
		740	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		741	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1963	serge	742	WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
		743	WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1117	serge	744	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		745	radeon_ring_start(rdev);
		746	r = radeon_ring_test(rdev);
		747	if (r) {
		748	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		749	return r;
		750	}
		751	rdev->cp.ready = true;
1963	serge	752	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1117	serge	753	return 0;
		754	}
		755
		756	void r100_cp_fini(struct radeon_device *rdev)
		757	{
1179	serge	758	if (r100_cp_wait_for_idle(rdev)) {
		759	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		760	}
1117	serge	761	/* Disable ring */
1179	serge	762	r100_cp_disable(rdev);
1117	serge	763	radeon_ring_fini(rdev);
		764	DRM_INFO("radeon: cp finalized\n");
		765	}
		766
		767	void r100_cp_disable(struct radeon_device *rdev)
		768	{
		769	/* Disable ring */
1963	serge	770	// radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1117	serge	771	rdev->cp.ready = false;
		772	WREG32(RADEON_CP_CSQ_MODE, 0);
		773	WREG32(RADEON_CP_CSQ_CNTL, 0);
1963	serge	774	WREG32(R_000770_SCRATCH_UMSK, 0);
1117	serge	775	if (r100_gui_wait_for_idle(rdev)) {
		776	printk(KERN_WARNING "Failed to wait GUI idle while "
		777	"programming pipes. Bad things might happen.\n");
		778	}
		779	}
		780
1179	serge	781	void r100_cp_commit(struct radeon_device *rdev)
		782	{
		783	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		784	(void)RREG32(RADEON_CP_RB_WPTR);
		785	}
		786
		787
1117	serge	788	#if 0
		789	/*
		790	* CS functions
		791	*/
		792	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		793	struct radeon_cs_packet *pkt,
		794	const unsigned *auth, unsigned n,
		795	radeon_packet0_check_t check)
		796	{
		797	unsigned reg;
		798	unsigned i, j, m;
		799	unsigned idx;
		800	int r;
		801
		802	idx = pkt->idx + 1;
		803	reg = pkt->reg;
		804	/* Check that register fall into register range
		805	* determined by the number of entry (n) in the
		806	* safe register bitmap.
		807	*/
		808	if (pkt->one_reg_wr) {
		809	if ((reg >> 7) > n) {
		810	return -EINVAL;
		811	}
		812	} else {
		813	if (((reg + (pkt->count << 2)) >> 7) > n) {
		814	return -EINVAL;
		815	}
		816	}
		817	for (i = 0; i <= pkt->count; i++, idx++) {
		818	j = (reg >> 7);
		819	m = 1 << ((reg >> 2) & 31);
		820	if (auth[j] & m) {
		821	r = check(p, pkt, idx, reg);
		822	if (r) {
		823	return r;
		824	}
		825	}
		826	if (pkt->one_reg_wr) {
		827	if (!(auth[j] & m)) {
		828	break;
		829	}
		830	} else {
		831	reg += 4;
		832	}
		833	}
		834	return 0;
		835	}
		836
		837	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		838	struct radeon_cs_packet *pkt)
		839	{
		840	volatile uint32_t *ib;
		841	unsigned i;
		842	unsigned idx;
		843
		844	ib = p->ib->ptr;
		845	idx = pkt->idx;
		846	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		847	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		848	}
		849	}
		850
		851	/**
		852	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		853	* @parser: parser structure holding parsing context.
		854	* @pkt: where to store packet informations
		855	*
		856	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		857	* if packet is bigger than remaining ib size. or if packets is unknown.
		858	**/
		859	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		860	struct radeon_cs_packet *pkt,
		861	unsigned idx)
		862	{
		863	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	864	uint32_t header;
1117	serge	865
		866	if (idx >= ib_chunk->length_dw) {
		867	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		868	idx, ib_chunk->length_dw);
		869	return -EINVAL;
		870	}
1221	serge	871	header = radeon_get_ib_value(p, idx);
1117	serge	872	pkt->idx = idx;
		873	pkt->type = CP_PACKET_GET_TYPE(header);
		874	pkt->count = CP_PACKET_GET_COUNT(header);
		875	switch (pkt->type) {
		876	case PACKET_TYPE0:
		877	pkt->reg = CP_PACKET0_GET_REG(header);
		878	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		879	break;
		880	case PACKET_TYPE3:
		881	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		882	break;
		883	case PACKET_TYPE2:
		884	pkt->count = -1;
		885	break;
		886	default:
		887	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		888	return -EINVAL;
		889	}
		890	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		891	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		892	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		893	return -EINVAL;
		894	}
		895	return 0;
		896	}
		897
		898	/**
1179	serge	899	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		900	* @parser: parser structure holding parsing context.
		901	*
		902	* Userspace sends a special sequence for VLINE waits.
		903	* PACKET0 - VLINE_START_END + value
		904	* PACKET0 - WAIT_UNTIL +_value
		905	* RELOC (P3) - crtc_id in reloc.
		906	*
		907	* This function parses this and relocates the VLINE START END
		908	* and WAIT UNTIL packets to the correct crtc.
		909	* It also detects a switched off crtc and nulls out the
		910	* wait in that case.
		911	*/
		912	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		913	{
		914	struct drm_mode_object *obj;
		915	struct drm_crtc *crtc;
		916	struct radeon_crtc *radeon_crtc;
		917	struct radeon_cs_packet p3reloc, waitreloc;
		918	int crtc_id;
		919	int r;
		920	uint32_t header, h_idx, reg;
1221	serge	921	volatile uint32_t *ib;
1179	serge	922
1221	serge	923	ib = p->ib->ptr;
1179	serge	924
		925	/* parse the wait until */
		926	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		927	if (r)
		928	return r;
		929
		930	/* check its a wait until and only 1 count */
		931	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		932	waitreloc.count != 0) {
		933	DRM_ERROR("vline wait had illegal wait until segment\n");
1963	serge	934	return -EINVAL;
1179	serge	935	}
		936
1221	serge	937	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	938	DRM_ERROR("vline wait had illegal wait until\n");
1963	serge	939	return -EINVAL;
1179	serge	940	}
		941
		942	/* jump over the NOP */
1221	serge	943	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	944	if (r)
		945	return r;
		946
		947	h_idx = p->idx - 2;
1221	serge	948	p->idx += waitreloc.count + 2;
		949	p->idx += p3reloc.count + 2;
1179	serge	950
1221	serge	951	header = radeon_get_ib_value(p, h_idx);
		952	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		953	reg = CP_PACKET0_GET_REG(header);
1179	serge	954	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		955	if (!obj) {
		956	DRM_ERROR("cannot find crtc %d\n", crtc_id);
1963	serge	957	return -EINVAL;
1179	serge	958	}
		959	crtc = obj_to_crtc(obj);
		960	radeon_crtc = to_radeon_crtc(crtc);
		961	crtc_id = radeon_crtc->crtc_id;
		962
		963	if (!crtc->enabled) {
		964	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	965	ib[h_idx + 2] = PACKET2(0);
		966	ib[h_idx + 3] = PACKET2(0);
1179	serge	967	} else if (crtc_id == 1) {
		968	switch (reg) {
		969	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	970	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	971	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		972	break;
		973	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	974	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	975	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		976	break;
		977	default:
		978	DRM_ERROR("unknown crtc reloc\n");
1963	serge	979	return -EINVAL;
1179	serge	980	}
1221	serge	981	ib[h_idx] = header;
		982	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	983	}
1963	serge	984
		985	return 0;
1179	serge	986	}
		987
		988	/**
1117	serge	989	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		990	* @parser: parser structure holding parsing context.
		991	* @data: pointer to relocation data
		992	* @offset_start: starting offset
		993	* @offset_mask: offset mask (to align start offset on)
		994	* @reloc: reloc informations
		995	*
		996	* Check next packet is relocation packet3, do bo validation and compute
		997	* GPU offset using the provided start.
		998	**/
		999	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		1000	struct radeon_cs_reloc **cs_reloc)
		1001	{
		1002	struct radeon_cs_chunk *relocs_chunk;
		1003	struct radeon_cs_packet p3reloc;
		1004	unsigned idx;
		1005	int r;
		1006
		1007	if (p->chunk_relocs_idx == -1) {
		1008	DRM_ERROR("No relocation chunk !\n");
		1009	return -EINVAL;
		1010	}
		1011	*cs_reloc = NULL;
		1012	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		1013	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		1014	if (r) {
		1015	return r;
		1016	}
		1017	p->idx += p3reloc.count + 2;
		1018	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		1019	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		1020	p3reloc.idx);
		1021	r100_cs_dump_packet(p, &p3reloc);
		1022	return -EINVAL;
		1023	}
1221	serge	1024	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	1025	if (idx >= relocs_chunk->length_dw) {
		1026	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		1027	idx, relocs_chunk->length_dw);
		1028	r100_cs_dump_packet(p, &p3reloc);
		1029	return -EINVAL;
		1030	}
		1031	/* FIXME: we assume reloc size is 4 dwords */
		1032	*cs_reloc = p->relocs_ptr[(idx / 4)];
		1033	return 0;
		1034	}
		1035
1179	serge	1036	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1037	{
		1038	int vtx_size;
		1039	vtx_size = 2;
		1040	/* ordered according to bits in spec */
		1041	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1042	vtx_size++;
		1043	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1044	vtx_size += 3;
		1045	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1046	vtx_size++;
		1047	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1048	vtx_size++;
		1049	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1050	vtx_size += 3;
		1051	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1052	vtx_size++;
		1053	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1054	vtx_size++;
		1055	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1056	vtx_size += 2;
		1057	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1058	vtx_size += 2;
		1059	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1060	vtx_size++;
		1061	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1062	vtx_size += 2;
		1063	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1064	vtx_size++;
		1065	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1066	vtx_size += 2;
		1067	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1068	vtx_size++;
		1069	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1070	vtx_size++;
		1071	/* blend weight */
		1072	if (vtx_fmt & (0x7 << 15))
		1073	vtx_size += (vtx_fmt >> 15) & 0x7;
		1074	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1075	vtx_size += 3;
		1076	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1077	vtx_size += 2;
		1078	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1079	vtx_size++;
		1080	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1081	vtx_size++;
		1082	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1083	vtx_size++;
		1084	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1085	vtx_size++;
		1086	return vtx_size;
		1087	}
		1088
1117	serge	1089	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1090	struct radeon_cs_packet *pkt,
		1091	unsigned idx, unsigned reg)
1117	serge	1092	{
		1093	struct radeon_cs_reloc *reloc;
1179	serge	1094	struct r100_cs_track *track;
1117	serge	1095	volatile uint32_t *ib;
		1096	uint32_t tmp;
		1097	int r;
1179	serge	1098	int i, face;
		1099	u32 tile_flags = 0;
1221	serge	1100	u32 idx_value;
1117	serge	1101
		1102	ib = p->ib->ptr;
1179	serge	1103	track = (struct r100_cs_track *)p->track;
		1104
1221	serge	1105	idx_value = radeon_get_ib_value(p, idx);
		1106
1117	serge	1107	switch (reg) {
1179	serge	1108	case RADEON_CRTC_GUI_TRIG_VLINE:
		1109	r = r100_cs_packet_parse_vline(p);
		1110	if (r) {
		1111	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1112	idx, reg);
		1113	r100_cs_dump_packet(p, pkt);
		1114	return r;
		1115	}
		1116	break;
1117	serge	1117	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1118	* range access */
		1119	case RADEON_DST_PITCH_OFFSET:
		1120	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1121	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1122	if (r)
		1123	return r;
		1124	break;
		1125	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1126	r = r100_cs_packet_next_reloc(p, &reloc);
		1127	if (r) {
		1128	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1129	idx, reg);
		1130	r100_cs_dump_packet(p, pkt);
		1131	return r;
		1132	}
1179	serge	1133	track->zb.robj = reloc->robj;
1221	serge	1134	track->zb.offset = idx_value;
1963	serge	1135	track->zb_dirty = true;
1221	serge	1136	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1137	break;
		1138	case RADEON_RB3D_COLOROFFSET:
1179	serge	1139	r = r100_cs_packet_next_reloc(p, &reloc);
		1140	if (r) {
		1141	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1142	idx, reg);
		1143	r100_cs_dump_packet(p, pkt);
		1144	return r;
		1145	}
		1146	track->cb[0].robj = reloc->robj;
1221	serge	1147	track->cb[0].offset = idx_value;
1963	serge	1148	track->cb_dirty = true;
1221	serge	1149	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1150	break;
1117	serge	1151	case RADEON_PP_TXOFFSET_0:
		1152	case RADEON_PP_TXOFFSET_1:
		1153	case RADEON_PP_TXOFFSET_2:
1179	serge	1154	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1155	r = r100_cs_packet_next_reloc(p, &reloc);
		1156	if (r) {
		1157	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1158	idx, reg);
		1159	r100_cs_dump_packet(p, pkt);
		1160	return r;
		1161	}
1221	serge	1162	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1163	track->textures[i].robj = reloc->robj;
1963	serge	1164	track->tex_dirty = true;
1179	serge	1165	break;
		1166	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1167	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1168	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1169	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1170	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1171	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1172	r = r100_cs_packet_next_reloc(p, &reloc);
		1173	if (r) {
		1174	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1175	idx, reg);
		1176	r100_cs_dump_packet(p, pkt);
		1177	return r;
		1178	}
1221	serge	1179	track->textures[0].cube_info[i].offset = idx_value;
		1180	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1181	track->textures[0].cube_info[i].robj = reloc->robj;
1963	serge	1182	track->tex_dirty = true;
1179	serge	1183	break;
		1184	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1185	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1186	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1187	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1188	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1189	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1190	r = r100_cs_packet_next_reloc(p, &reloc);
		1191	if (r) {
		1192	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1193	idx, reg);
		1194	r100_cs_dump_packet(p, pkt);
		1195	return r;
		1196	}
1221	serge	1197	track->textures[1].cube_info[i].offset = idx_value;
		1198	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1199	track->textures[1].cube_info[i].robj = reloc->robj;
1963	serge	1200	track->tex_dirty = true;
1179	serge	1201	break;
		1202	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1203	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1204	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1205	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1206	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1207	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1208	r = r100_cs_packet_next_reloc(p, &reloc);
		1209	if (r) {
		1210	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1211	idx, reg);
		1212	r100_cs_dump_packet(p, pkt);
		1213	return r;
		1214	}
1221	serge	1215	track->textures[2].cube_info[i].offset = idx_value;
		1216	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1217	track->textures[2].cube_info[i].robj = reloc->robj;
1963	serge	1218	track->tex_dirty = true;
1179	serge	1219	break;
		1220	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1221	track->maxy = ((idx_value >> 16) & 0x7FF);
1963	serge	1222	track->cb_dirty = true;
		1223	track->zb_dirty = true;
1117	serge	1224	break;
1179	serge	1225	case RADEON_RB3D_COLORPITCH:
		1226	r = r100_cs_packet_next_reloc(p, &reloc);
		1227	if (r) {
		1228	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1229	idx, reg);
		1230	r100_cs_dump_packet(p, pkt);
		1231	return r;
		1232	}
		1233
		1234	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1235	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1236	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1237	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1238
1221	serge	1239	tmp = idx_value & ~(0x7 << 16);
1179	serge	1240	tmp \|= tile_flags;
		1241	ib[idx] = tmp;
		1242
1221	serge	1243	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1963	serge	1244	track->cb_dirty = true;
1179	serge	1245	break;
		1246	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1247	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1963	serge	1248	track->zb_dirty = true;
1179	serge	1249	break;
		1250	case RADEON_RB3D_CNTL:
1221	serge	1251	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1252	case 7:
		1253	case 8:
		1254	case 9:
		1255	case 11:
		1256	case 12:
		1257	track->cb[0].cpp = 1;
		1258	break;
		1259	case 3:
		1260	case 4:
		1261	case 15:
		1262	track->cb[0].cpp = 2;
		1263	break;
		1264	case 6:
		1265	track->cb[0].cpp = 4;
		1266	break;
1117	serge	1267	default:
1179	serge	1268	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1269	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1270	return -EINVAL;
		1271	}
1221	serge	1272	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1963	serge	1273	track->cb_dirty = true;
		1274	track->zb_dirty = true;
1179	serge	1275	break;
		1276	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1277	switch (idx_value & 0xf) {
1179	serge	1278	case 0:
		1279	track->zb.cpp = 2;
1117	serge	1280	break;
1179	serge	1281	case 2:
		1282	case 3:
		1283	case 4:
		1284	case 5:
		1285	case 9:
		1286	case 11:
		1287	track->zb.cpp = 4;
		1288	break;
		1289	default:
		1290	break;
1117	serge	1291	}
1963	serge	1292	track->zb_dirty = true;
1117	serge	1293	break;
1179	serge	1294	case RADEON_RB3D_ZPASS_ADDR:
		1295	r = r100_cs_packet_next_reloc(p, &reloc);
		1296	if (r) {
		1297	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1298	idx, reg);
		1299	r100_cs_dump_packet(p, pkt);
		1300	return r;
		1301	}
1221	serge	1302	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1303	break;
		1304	case RADEON_PP_CNTL:
		1305	{
1221	serge	1306	uint32_t temp = idx_value >> 4;
1179	serge	1307	for (i = 0; i < track->num_texture; i++)
		1308	track->textures[i].enabled = !!(temp & (1 << i));
1963	serge	1309	track->tex_dirty = true;
1117	serge	1310	}
1179	serge	1311	break;
		1312	case RADEON_SE_VF_CNTL:
1221	serge	1313	track->vap_vf_cntl = idx_value;
1179	serge	1314	break;
		1315	case RADEON_SE_VTX_FMT:
1221	serge	1316	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1317	break;
		1318	case RADEON_PP_TEX_SIZE_0:
		1319	case RADEON_PP_TEX_SIZE_1:
		1320	case RADEON_PP_TEX_SIZE_2:
		1321	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1322	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1323	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1963	serge	1324	track->tex_dirty = true;
1179	serge	1325	break;
		1326	case RADEON_PP_TEX_PITCH_0:
		1327	case RADEON_PP_TEX_PITCH_1:
		1328	case RADEON_PP_TEX_PITCH_2:
		1329	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1330	track->textures[i].pitch = idx_value + 32;
1963	serge	1331	track->tex_dirty = true;
1179	serge	1332	break;
		1333	case RADEON_PP_TXFILTER_0:
		1334	case RADEON_PP_TXFILTER_1:
		1335	case RADEON_PP_TXFILTER_2:
		1336	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1337	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1338	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1339	tmp = (idx_value >> 23) & 0x7;
1179	serge	1340	if (tmp == 2 \|\| tmp == 6)
		1341	track->textures[i].roundup_w = false;
1221	serge	1342	tmp = (idx_value >> 27) & 0x7;
1179	serge	1343	if (tmp == 2 \|\| tmp == 6)
		1344	track->textures[i].roundup_h = false;
1963	serge	1345	track->tex_dirty = true;
1179	serge	1346	break;
		1347	case RADEON_PP_TXFORMAT_0:
		1348	case RADEON_PP_TXFORMAT_1:
		1349	case RADEON_PP_TXFORMAT_2:
		1350	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1351	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1352	track->textures[i].use_pitch = 1;
		1353	} else {
		1354	track->textures[i].use_pitch = 0;
1221	serge	1355	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1356	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1357	}
1221	serge	1358	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1359	track->textures[i].tex_coord_type = 2;
1221	serge	1360	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1361	case RADEON_TXFORMAT_I8:
		1362	case RADEON_TXFORMAT_RGB332:
		1363	case RADEON_TXFORMAT_Y8:
		1364	track->textures[i].cpp = 1;
1963	serge	1365	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1366	break;
		1367	case RADEON_TXFORMAT_AI88:
		1368	case RADEON_TXFORMAT_ARGB1555:
		1369	case RADEON_TXFORMAT_RGB565:
		1370	case RADEON_TXFORMAT_ARGB4444:
		1371	case RADEON_TXFORMAT_VYUY422:
		1372	case RADEON_TXFORMAT_YVYU422:
		1373	case RADEON_TXFORMAT_SHADOW16:
		1374	case RADEON_TXFORMAT_LDUDV655:
		1375	case RADEON_TXFORMAT_DUDV88:
		1376	track->textures[i].cpp = 2;
1963	serge	1377	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1378	break;
		1379	case RADEON_TXFORMAT_ARGB8888:
		1380	case RADEON_TXFORMAT_RGBA8888:
		1381	case RADEON_TXFORMAT_SHADOW32:
		1382	case RADEON_TXFORMAT_LDUDUV8888:
		1383	track->textures[i].cpp = 4;
1963	serge	1384	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1179	serge	1385	break;
1403	serge	1386	case RADEON_TXFORMAT_DXT1:
		1387	track->textures[i].cpp = 1;
		1388	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1389	break;
		1390	case RADEON_TXFORMAT_DXT23:
		1391	case RADEON_TXFORMAT_DXT45:
		1392	track->textures[i].cpp = 1;
		1393	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1394	break;
1179	serge	1395	}
1221	serge	1396	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1397	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1963	serge	1398	track->tex_dirty = true;
1179	serge	1399	break;
		1400	case RADEON_PP_CUBIC_FACES_0:
		1401	case RADEON_PP_CUBIC_FACES_1:
		1402	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1403	tmp = idx_value;
1179	serge	1404	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1405	for (face = 0; face < 4; face++) {
		1406	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1407	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1408	}
1963	serge	1409	track->tex_dirty = true;
1179	serge	1410	break;
		1411	default:
		1412	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1413	reg, idx);
		1414	return -EINVAL;
1117	serge	1415	}
		1416	return 0;
		1417	}
		1418
		1419	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1420	struct radeon_cs_packet *pkt,
1321	serge	1421	struct radeon_bo *robj)
1117	serge	1422	{
		1423	unsigned idx;
1221	serge	1424	u32 value;
1117	serge	1425	idx = pkt->idx + 1;
1221	serge	1426	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1427	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1428	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1429	"(need %u have %lu) !\n",
1221	serge	1430	value + 1,
1321	serge	1431	radeon_bo_size(robj));
1117	serge	1432	return -EINVAL;
		1433	}
		1434	return 0;
		1435	}
		1436
		1437	static int r100_packet3_check(struct radeon_cs_parser *p,
		1438	struct radeon_cs_packet *pkt)
		1439	{
		1440	struct radeon_cs_reloc *reloc;
1179	serge	1441	struct r100_cs_track *track;
1117	serge	1442	unsigned idx;
		1443	volatile uint32_t *ib;
		1444	int r;
		1445
		1446	ib = p->ib->ptr;
		1447	idx = pkt->idx + 1;
1179	serge	1448	track = (struct r100_cs_track *)p->track;
1117	serge	1449	switch (pkt->opcode) {
		1450	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1451	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1452	if (r)
1117	serge	1453	return r;
		1454	break;
		1455	case PACKET3_INDX_BUFFER:
		1456	r = r100_cs_packet_next_reloc(p, &reloc);
		1457	if (r) {
		1458	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1459	r100_cs_dump_packet(p, pkt);
		1460	return r;
		1461	}
1221	serge	1462	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1463	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1464	if (r) {
		1465	return r;
		1466	}
		1467	break;
		1468	case 0x23:
		1469	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1470	r = r100_cs_packet_next_reloc(p, &reloc);
		1471	if (r) {
		1472	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1473	r100_cs_dump_packet(p, pkt);
		1474	return r;
		1475	}
1221	serge	1476	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1477	track->num_arrays = 1;
1221	serge	1478	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1479
		1480	track->arrays[0].robj = reloc->robj;
		1481	track->arrays[0].esize = track->vtx_size;
		1482
1221	serge	1483	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1484
1221	serge	1485	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1486	track->immd_dwords = pkt->count - 1;
		1487	r = r100_cs_track_check(p->rdev, track);
		1488	if (r)
		1489	return r;
1117	serge	1490	break;
		1491	case PACKET3_3D_DRAW_IMMD:
1221	serge	1492	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1493	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1494	return -EINVAL;
		1495	}
1403	serge	1496	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1497	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1498	track->immd_dwords = pkt->count - 1;
		1499	r = r100_cs_track_check(p->rdev, track);
		1500	if (r)
		1501	return r;
		1502	break;
1117	serge	1503	/* triggers drawing using in-packet vertex data */
		1504	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1505	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1506	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1507	return -EINVAL;
		1508	}
1221	serge	1509	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1510	track->immd_dwords = pkt->count;
		1511	r = r100_cs_track_check(p->rdev, track);
		1512	if (r)
		1513	return r;
		1514	break;
1117	serge	1515	/* triggers drawing using in-packet vertex data */
		1516	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1517	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1518	r = r100_cs_track_check(p->rdev, track);
		1519	if (r)
		1520	return r;
		1521	break;
1117	serge	1522	/* triggers drawing of vertex buffers setup elsewhere */
		1523	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1524	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1525	r = r100_cs_track_check(p->rdev, track);
		1526	if (r)
		1527	return r;
		1528	break;
1117	serge	1529	/* triggers drawing using indices to vertex buffer */
		1530	case PACKET3_3D_DRAW_VBUF:
1221	serge	1531	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1532	r = r100_cs_track_check(p->rdev, track);
		1533	if (r)
		1534	return r;
		1535	break;
1117	serge	1536	/* triggers drawing of vertex buffers setup elsewhere */
		1537	case PACKET3_3D_DRAW_INDX:
1221	serge	1538	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1539	r = r100_cs_track_check(p->rdev, track);
		1540	if (r)
		1541	return r;
		1542	break;
1117	serge	1543	/* triggers drawing using indices to vertex buffer */
1963	serge	1544	case PACKET3_3D_CLEAR_HIZ:
		1545	case PACKET3_3D_CLEAR_ZMASK:
		1546	if (p->rdev->hyperz_filp != p->filp)
		1547	return -EINVAL;
		1548	break;
1117	serge	1549	case PACKET3_NOP:
		1550	break;
		1551	default:
		1552	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1553	return -EINVAL;
		1554	}
		1555	return 0;
		1556	}
		1557
		1558	int r100_cs_parse(struct radeon_cs_parser *p)
		1559	{
		1560	struct radeon_cs_packet pkt;
1179	serge	1561	struct r100_cs_track *track;
1117	serge	1562	int r;
		1563
1179	serge	1564	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1565	r100_cs_track_clear(p->rdev, track);
		1566	p->track = track;
1117	serge	1567	do {
		1568	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1569	if (r) {
		1570	return r;
		1571	}
		1572	p->idx += pkt.count + 2;
		1573	switch (pkt.type) {
		1574	case PACKET_TYPE0:
1179	serge	1575	if (p->rdev->family >= CHIP_R200)
		1576	r = r100_cs_parse_packet0(p, &pkt,
		1577	p->rdev->config.r100.reg_safe_bm,
		1578	p->rdev->config.r100.reg_safe_bm_size,
		1579	&r200_packet0_check);
		1580	else
		1581	r = r100_cs_parse_packet0(p, &pkt,
		1582	p->rdev->config.r100.reg_safe_bm,
		1583	p->rdev->config.r100.reg_safe_bm_size,
		1584	&r100_packet0_check);
1117	serge	1585	break;
		1586	case PACKET_TYPE2:
		1587	break;
		1588	case PACKET_TYPE3:
		1589	r = r100_packet3_check(p, &pkt);
		1590	break;
		1591	default:
		1592	DRM_ERROR("Unknown packet type %d !\n",
		1593	pkt.type);
		1594	return -EINVAL;
		1595	}
		1596	if (r) {
		1597	return r;
		1598	}
		1599	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1600	return 0;
		1601	}
		1602
1128	serge	1603	#endif
1117	serge	1604
		1605	/*
		1606	* Global GPU functions
		1607	*/
		1608	void r100_errata(struct radeon_device *rdev)
		1609	{
		1610	rdev->pll_errata = 0;
		1611
		1612	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1613	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1614	}
		1615
		1616	if (rdev->family == CHIP_RV100 \|\|
		1617	rdev->family == CHIP_RS100 \|\|
		1618	rdev->family == CHIP_RS200) {
		1619	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1620	}
		1621	}
		1622
		1623	/* Wait for vertical sync on primary CRTC */
		1624	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1625	{
		1626	uint32_t crtc_gen_cntl, tmp;
		1627	int i;
		1628
		1629	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1630	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1631	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1632	return;
		1633	}
		1634	/* Clear the CRTC_VBLANK_SAVE bit */
		1635	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1636	for (i = 0; i < rdev->usec_timeout; i++) {
		1637	tmp = RREG32(RADEON_CRTC_STATUS);
		1638	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1639	return;
		1640	}
		1641	DRM_UDELAY(1);
		1642	}
		1643	}
		1644
		1645	/* Wait for vertical sync on secondary CRTC */
		1646	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1647	{
		1648	uint32_t crtc2_gen_cntl, tmp;
		1649	int i;
		1650
		1651	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1652	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1653	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1654	return;
		1655
		1656	/* Clear the CRTC_VBLANK_SAVE bit */
		1657	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1658	for (i = 0; i < rdev->usec_timeout; i++) {
		1659	tmp = RREG32(RADEON_CRTC2_STATUS);
		1660	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1661	return;
		1662	}
		1663	DRM_UDELAY(1);
		1664	}
		1665	}
		1666
		1667	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1668	{
		1669	unsigned i;
		1670	uint32_t tmp;
		1671
		1672	for (i = 0; i < rdev->usec_timeout; i++) {
		1673	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1674	if (tmp >= n) {
		1675	return 0;
		1676	}
		1677	DRM_UDELAY(1);
		1678	}
		1679	return -1;
		1680	}
		1681
		1682	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1683	{
		1684	unsigned i;
		1685	uint32_t tmp;
		1686
		1687	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1688	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1689	" Bad things might happen.\n");
		1690	}
		1691	for (i = 0; i < rdev->usec_timeout; i++) {
		1692	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	1693	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	1694	return 0;
		1695	}
		1696	DRM_UDELAY(1);
		1697	}
		1698	return -1;
		1699	}
		1700
		1701	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1702	{
		1703	unsigned i;
		1704	uint32_t tmp;
		1705
		1706	for (i = 0; i < rdev->usec_timeout; i++) {
		1707	/* read MC_STATUS */
1430	serge	1708	tmp = RREG32(RADEON_MC_STATUS);
		1709	if (tmp & RADEON_MC_IDLE) {
1117	serge	1710	return 0;
		1711	}
		1712	DRM_UDELAY(1);
		1713	}
		1714	return -1;
		1715	}
		1716
1963	serge	1717	void r100_gpu_lockup_update(struct r100_gpu_lockup lockup, struct radeon_cp cp)
1117	serge	1718	{
1963	serge	1719	lockup->last_cp_rptr = cp->rptr;
2005	serge	1720	lockup->last_jiffies = GetTimerTicks();
1117	serge	1721	}
		1722
1963	serge	1723	/**
		1724	* r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
		1725	* @rdev: radeon device structure
		1726	* @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
		1727	* @cp: radeon_cp structure holding CP information
		1728	*
		1729	* We don't need to initialize the lockup tracking information as we will either
		1730	* have CP rptr to a different value of jiffies wrap around which will force
		1731	* initialization of the lockup tracking informations.
		1732	*
		1733	* A possible false positivie is if we get call after while and last_cp_rptr ==
		1734	* the current CP rptr, even if it's unlikely it might happen. To avoid this
		1735	* if the elapsed time since last call is bigger than 2 second than we return
		1736	* false and update the tracking information. Due to this the caller must call
		1737	* r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
		1738	* the fencing code should be cautious about that.
		1739	*
		1740	* Caller should write to the ring to force CP to do something so we don't get
		1741	* false positive when CP is just gived nothing to do.
		1742	*
		1743	**/
		1744	bool r100_gpu_cp_is_lockup(struct radeon_device rdev, struct r100_gpu_lockup lockup, struct radeon_cp *cp)
1117	serge	1745	{
1963	serge	1746	unsigned long cjiffies, elapsed;
1117	serge	1747
2005	serge	1748	cjiffies = GetTimerTicks();
1963	serge	1749	if (!time_after(cjiffies, lockup->last_jiffies)) {
		1750	/* likely a wrap around */
		1751	lockup->last_cp_rptr = cp->rptr;
2005	serge	1752	lockup->last_jiffies = GetTimerTicks();
1963	serge	1753	return false;
		1754	}
		1755	if (cp->rptr != lockup->last_cp_rptr) {
		1756	/* CP is still working no lockup */
		1757	lockup->last_cp_rptr = cp->rptr;
2005	serge	1758	lockup->last_jiffies = GetTimerTicks();
1963	serge	1759	return false;
		1760	}
		1761	elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
		1762	if (elapsed >= 10000) {
		1763	dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
		1764	return true;
		1765	}
		1766	/* give a chance to the GPU ... */
		1767	return false;
1117	serge	1768	}
		1769
1963	serge	1770	bool r100_gpu_is_lockup(struct radeon_device *rdev)
1117	serge	1771	{
1963	serge	1772	u32 rbbm_status;
		1773	int r;
1117	serge	1774
1963	serge	1775	rbbm_status = RREG32(R_000E40_RBBM_STATUS);
		1776	if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
		1777	r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
		1778	return false;
1117	serge	1779	}
1963	serge	1780	/* force CP activities */
		1781	r = radeon_ring_lock(rdev, 2);
		1782	if (!r) {
		1783	/* PACKET2 NOP */
		1784	radeon_ring_write(rdev, 0x80000000);
		1785	radeon_ring_write(rdev, 0x80000000);
		1786	radeon_ring_unlock_commit(rdev);
1117	serge	1787	}
1963	serge	1788	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		1789	return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
1117	serge	1790	}
		1791
1963	serge	1792	void r100_bm_disable(struct radeon_device *rdev)
1117	serge	1793	{
1963	serge	1794	u32 tmp;
1117	serge	1795
1963	serge	1796	/* disable bus mastering */
		1797	tmp = RREG32(R_000030_BUS_CNTL);
		1798	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000044);
		1799	mdelay(1);
		1800	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000042);
		1801	mdelay(1);
		1802	WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) \| 0x00000040);
		1803	tmp = RREG32(RADEON_BUS_CNTL);
		1804	mdelay(1);
		1805	tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);
		1806	PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);
		1807	mdelay(1);
		1808	}
		1809
		1810	int r100_asic_reset(struct radeon_device *rdev)
		1811	{
		1812	struct r100_mc_save save;
		1813	u32 status, tmp;
		1814	int ret = 0;
		1815
		1816	status = RREG32(R_000E40_RBBM_STATUS);
		1817	if (!G_000E40_GUI_ACTIVE(status)) {
		1818	return 0;
1117	serge	1819	}
1963	serge	1820	r100_mc_stop(rdev, &save);
		1821	status = RREG32(R_000E40_RBBM_STATUS);
		1822	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		1823	/* stop CP */
		1824	WREG32(RADEON_CP_CSQ_CNTL, 0);
		1825	tmp = RREG32(RADEON_CP_RB_CNTL);
		1826	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		1827	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		1828	WREG32(RADEON_CP_RB_WPTR, 0);
		1829	WREG32(RADEON_CP_RB_CNTL, tmp);
		1830	/* save PCI state */
		1831	// pci_save_state(rdev->pdev);
		1832	/* disable bus mastering */
		1833	r100_bm_disable(rdev);
		1834	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) \|
		1835	S_0000F0_SOFT_RESET_RE(1) \|
		1836	S_0000F0_SOFT_RESET_PP(1) \|
		1837	S_0000F0_SOFT_RESET_RB(1));
		1838	RREG32(R_0000F0_RBBM_SOFT_RESET);
		1839	mdelay(500);
		1840	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		1841	mdelay(1);
		1842	status = RREG32(R_000E40_RBBM_STATUS);
		1843	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
1117	serge	1844	/* reset CP */
1963	serge	1845	WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
		1846	RREG32(R_0000F0_RBBM_SOFT_RESET);
		1847	mdelay(500);
		1848	WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
		1849	mdelay(1);
		1850	status = RREG32(R_000E40_RBBM_STATUS);
		1851	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
		1852	/* restore PCI & busmastering */
		1853	// pci_restore_state(rdev->pdev);
		1854	r100_enable_bm(rdev);
1117	serge	1855	/* Check if GPU is idle */
1963	serge	1856	if (G_000E40_SE_BUSY(status) \|\| G_000E40_RE_BUSY(status) \|\|
		1857	G_000E40_TAM_BUSY(status) \|\| G_000E40_PB_BUSY(status)) {
		1858	dev_err(rdev->dev, "failed to reset GPU\n");
		1859	rdev->gpu_lockup = true;
		1860	ret = -1;
		1861	} else
		1862	dev_info(rdev->dev, "GPU reset succeed\n");
		1863	r100_mc_resume(rdev, &save);
		1864	return ret;
1117	serge	1865	}
		1866
1321	serge	1867	void r100_set_common_regs(struct radeon_device *rdev)
		1868	{
1430	serge	1869	struct drm_device *dev = rdev->ddev;
		1870	bool force_dac2 = false;
1963	serge	1871	u32 tmp;
1430	serge	1872
1321	serge	1873	/* set these so they don't interfere with anything */
		1874	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		1875	WREG32(RADEON_SUBPIC_CNTL, 0);
		1876	WREG32(RADEON_VIPH_CONTROL, 0);
		1877	WREG32(RADEON_I2C_CNTL_1, 0);
		1878	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		1879	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		1880	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	1881
		1882	/* always set up dac2 on rn50 and some rv100 as lots
		1883	* of servers seem to wire it up to a VGA port but
		1884	* don't report it in the bios connector
		1885	* table.
		1886	*/
		1887	switch (dev->pdev->device) {
		1888	/* RN50 */
		1889	case 0x515e:
		1890	case 0x5969:
		1891	force_dac2 = true;
		1892	break;
		1893	/* RV100*/
		1894	case 0x5159:
		1895	case 0x515a:
		1896	/* DELL triple head servers */
		1897	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		1898	((dev->pdev->subsystem_device == 0x016c) \|\|
		1899	(dev->pdev->subsystem_device == 0x016d) \|\|
		1900	(dev->pdev->subsystem_device == 0x016e) \|\|
		1901	(dev->pdev->subsystem_device == 0x016f) \|\|
		1902	(dev->pdev->subsystem_device == 0x0170) \|\|
		1903	(dev->pdev->subsystem_device == 0x017d) \|\|
		1904	(dev->pdev->subsystem_device == 0x017e) \|\|
		1905	(dev->pdev->subsystem_device == 0x0183) \|\|
		1906	(dev->pdev->subsystem_device == 0x018a) \|\|
		1907	(dev->pdev->subsystem_device == 0x019a)))
		1908	force_dac2 = true;
		1909	break;
		1910	}
		1911
		1912	if (force_dac2) {
		1913	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1914	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1915	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		1916
		1917	/* For CRT on DAC2, don't turn it on if BIOS didn't
		1918	enable it, even it's detected.
		1919	*/
		1920
		1921	/* force it to crtc0 */
		1922	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		1923	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		1924	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1925
		1926	/* set up the TV DAC */
		1927	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		1928	RADEON_TV_DAC_STD_MASK \|
		1929	RADEON_TV_DAC_RDACPD \|
		1930	RADEON_TV_DAC_GDACPD \|
		1931	RADEON_TV_DAC_BDACPD \|
		1932	RADEON_TV_DAC_BGADJ_MASK \|
		1933	RADEON_TV_DAC_DACADJ_MASK);
		1934	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		1935	RADEON_TV_DAC_NHOLD \|
		1936	RADEON_TV_DAC_STD_PS2 \|
		1937	(0x58 << 16));
		1938
		1939	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1940	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1941	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1942	}
1963	serge	1943
		1944	/* switch PM block to ACPI mode */
		1945	tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
		1946	tmp &= ~RADEON_PM_MODE_SEL;
		1947	WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
		1948
1321	serge	1949	}
1117	serge	1950
		1951	/*
		1952	* VRAM info
		1953	*/
		1954	static void r100_vram_get_type(struct radeon_device *rdev)
		1955	{
		1956	uint32_t tmp;
		1957
		1958	rdev->mc.vram_is_ddr = false;
		1959	if (rdev->flags & RADEON_IS_IGP)
		1960	rdev->mc.vram_is_ddr = true;
		1961	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1962	rdev->mc.vram_is_ddr = true;
		1963	if ((rdev->family == CHIP_RV100) \|\|
		1964	(rdev->family == CHIP_RS100) \|\|
		1965	(rdev->family == CHIP_RS200)) {
		1966	tmp = RREG32(RADEON_MEM_CNTL);
		1967	if (tmp & RV100_HALF_MODE) {
		1968	rdev->mc.vram_width = 32;
		1969	} else {
		1970	rdev->mc.vram_width = 64;
		1971	}
		1972	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1973	rdev->mc.vram_width /= 4;
		1974	rdev->mc.vram_is_ddr = true;
		1975	}
		1976	} else if (rdev->family <= CHIP_RV280) {
		1977	tmp = RREG32(RADEON_MEM_CNTL);
		1978	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1979	rdev->mc.vram_width = 128;
		1980	} else {
		1981	rdev->mc.vram_width = 64;
		1982	}
		1983	} else {
		1984	/* newer IGPs */
		1985	rdev->mc.vram_width = 128;
		1986	}
		1987	}
		1988
1179	serge	1989	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1990	{
1179	serge	1991	u32 aper_size;
		1992	u8 byte;
1117	serge	1993
1179	serge	1994	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1995
		1996	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1997	* that is has the 2nd generation multifunction PCI interface
		1998	*/
		1999	if (rdev->family == CHIP_RV280 \|\|
		2000	rdev->family >= CHIP_RV350) {
		2001	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		2002	~RADEON_HDP_APER_CNTL);
		2003	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		2004	return aper_size * 2;
		2005	}
		2006
		2007	/* Older cards have all sorts of funny issues to deal with. First
		2008	* check if it's a multifunction card by reading the PCI config
		2009	* header type... Limit those to one aperture size
		2010	*/
		2011	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		2012	// if (byte & 0x80) {
		2013	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		2014	// DRM_INFO("Limiting VRAM to one aperture\n");
		2015	// return aper_size;
		2016	// }
		2017
		2018	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		2019	* have set it up. We don't write this as it's broken on some ASICs but
		2020	* we expect the BIOS to have done the right thing (might be too optimistic...)
		2021	*/
		2022	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		2023	return aper_size * 2;
		2024	return aper_size;
		2025	}
		2026
		2027	void r100_vram_init_sizes(struct radeon_device *rdev)
		2028	{
		2029	u64 config_aper_size;
		2030
1430	serge	2031	/* work out accessible VRAM */
1963	serge	2032	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
		2033	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1430	serge	2034	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		2035	/* FIXME we don't use the second aperture yet when we could use it */
		2036	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		2037	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	2038	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	2039	if (rdev->flags & RADEON_IS_IGP) {
		2040	uint32_t tom;
		2041	/* read NB_TOM to get the amount of ram stolen for the GPU */
		2042	tom = RREG32(RADEON_NB_TOM);
1179	serge	2043	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		2044	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		2045	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2046	} else {
1179	serge	2047	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	2048	/* Some production boards of m6 will report 0
		2049	* if it's 8 MB
		2050	*/
1179	serge	2051	if (rdev->mc.real_vram_size == 0) {
		2052	rdev->mc.real_vram_size = 8192 * 1024;
		2053	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	2054	}
1179	serge	2055	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	2056	* Novell bug 204882 + along with lots of ubuntu ones
		2057	*/
1963	serge	2058	if (rdev->mc.aper_size > config_aper_size)
		2059	config_aper_size = rdev->mc.aper_size;
		2060
1179	serge	2061	if (config_aper_size > rdev->mc.real_vram_size)
		2062	rdev->mc.mc_vram_size = config_aper_size;
		2063	else
		2064	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	2065	}
		2066	}
		2067
1179	serge	2068	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		2069	{
		2070	uint32_t temp;
		2071
		2072	temp = RREG32(RADEON_CONFIG_CNTL);
		2073	if (state == false) {
1963	serge	2074	temp &= ~RADEON_CFG_VGA_RAM_EN;
		2075	temp \|= RADEON_CFG_VGA_IO_DIS;
1179	serge	2076	} else {
1963	serge	2077	temp &= ~RADEON_CFG_VGA_IO_DIS;
1179	serge	2078	}
		2079	WREG32(RADEON_CONFIG_CNTL, temp);
		2080	}
		2081
1430	serge	2082	void r100_mc_init(struct radeon_device *rdev)
1179	serge	2083	{
1430	serge	2084	u64 base;
		2085
1179	serge	2086	r100_vram_get_type(rdev);
		2087	r100_vram_init_sizes(rdev);
1430	serge	2088	base = rdev->mc.aper_base;
		2089	if (rdev->flags & RADEON_IS_IGP)
		2090	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		2091	radeon_vram_location(rdev, &rdev->mc, base);
1963	serge	2092	rdev->mc.gtt_base_align = 0;
1430	serge	2093	if (!(rdev->flags & RADEON_IS_AGP))
		2094	radeon_gtt_location(rdev, &rdev->mc);
1963	serge	2095	radeon_update_bandwidth_info(rdev);
1179	serge	2096	}
		2097
		2098
1117	serge	2099	/*
		2100	* Indirect registers accessor
		2101	*/
		2102	void r100_pll_errata_after_index(struct radeon_device *rdev)
		2103	{
1963	serge	2104	if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
1117	serge	2105	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		2106	(void)RREG32(RADEON_CRTC_GEN_CNTL);
1963	serge	2107	}
1117	serge	2108	}
		2109
		2110	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		2111	{
		2112	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		2113	* or the chip could hang on a subsequent access
		2114	*/
		2115	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		2116	udelay(5000);
		2117	}
		2118
		2119	/* This function is required to workaround a hardware bug in some (all?)
		2120	* revisions of the R300. This workaround should be called after every
		2121	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		2122	* may not be correct.
		2123	*/
		2124	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		2125	uint32_t save, tmp;
		2126
		2127	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		2128	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		2129	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		2130	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		2131	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		2132	}
		2133	}
		2134
		2135	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		2136	{
		2137	uint32_t data;
		2138
		2139	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		2140	r100_pll_errata_after_index(rdev);
		2141	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		2142	r100_pll_errata_after_data(rdev);
		2143	return data;
		2144	}
		2145
		2146	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2147	{
		2148	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2149	r100_pll_errata_after_index(rdev);
		2150	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2151	r100_pll_errata_after_data(rdev);
		2152	}
		2153
1221	serge	2154	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2155	{
1179	serge	2156	if (ASIC_IS_RN50(rdev)) {
		2157	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2158	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2159	} else if (rdev->family < CHIP_R200) {
		2160	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2161	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2162	} else {
1221	serge	2163	r200_set_safe_registers(rdev);
1117	serge	2164	}
		2165	}
		2166
1129	serge	2167	/*
		2168	* Debugfs info
		2169	*/
		2170	#if defined(CONFIG_DEBUG_FS)
		2171	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2172	{
		2173	struct drm_info_node node = (struct drm_info_node ) m->private;
		2174	struct drm_device *dev = node->minor->dev;
		2175	struct radeon_device *rdev = dev->dev_private;
		2176	uint32_t reg, value;
		2177	unsigned i;
		2178
		2179	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2180	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2181	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2182	for (i = 0; i < 64; i++) {
		2183	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2184	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2185	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2186	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2187	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2188	}
		2189	return 0;
		2190	}
		2191
		2192	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2193	{
		2194	struct drm_info_node node = (struct drm_info_node ) m->private;
		2195	struct drm_device *dev = node->minor->dev;
		2196	struct radeon_device *rdev = dev->dev_private;
		2197	uint32_t rdp, wdp;
		2198	unsigned count, i, j;
		2199
		2200	radeon_ring_free_size(rdev);
		2201	rdp = RREG32(RADEON_CP_RB_RPTR);
		2202	wdp = RREG32(RADEON_CP_RB_WPTR);
		2203	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		2204	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2205	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2206	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		2207	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		2208	seq_printf(m, "%u dwords in ring\n", count);
		2209	for (j = 0; j <= count; j++) {
		2210	i = (rdp + j) & rdev->cp.ptr_mask;
		2211	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		2212	}
		2213	return 0;
		2214	}
		2215
		2216
		2217	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2218	{
		2219	struct drm_info_node node = (struct drm_info_node ) m->private;
		2220	struct drm_device *dev = node->minor->dev;
		2221	struct radeon_device *rdev = dev->dev_private;
		2222	uint32_t csq_stat, csq2_stat, tmp;
		2223	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2224	unsigned i;
		2225
		2226	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2227	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2228	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2229	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2230	r_rptr = (csq_stat >> 0) & 0x3ff;
		2231	r_wptr = (csq_stat >> 10) & 0x3ff;
		2232	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2233	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2234	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2235	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2236	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2237	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2238	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2239	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2240	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2241	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2242	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2243	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2244	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2245	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2246	seq_printf(m, "Ring fifo:\n");
		2247	for (i = 0; i < 256; i++) {
		2248	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2249	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2250	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2251	}
		2252	seq_printf(m, "Indirect1 fifo:\n");
		2253	for (i = 256; i <= 512; i++) {
		2254	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2255	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2256	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2257	}
		2258	seq_printf(m, "Indirect2 fifo:\n");
		2259	for (i = 640; i < ib1_wptr; i++) {
		2260	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2261	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2262	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2263	}
		2264	return 0;
		2265	}
		2266
		2267	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2268	{
		2269	struct drm_info_node node = (struct drm_info_node ) m->private;
		2270	struct drm_device *dev = node->minor->dev;
		2271	struct radeon_device *rdev = dev->dev_private;
		2272	uint32_t tmp;
		2273
		2274	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2275	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2276	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2277	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2278	tmp = RREG32(RADEON_BUS_CNTL);
		2279	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2280	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2281	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2282	tmp = RREG32(RADEON_AGP_BASE);
		2283	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2284	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2285	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2286	tmp = RREG32(0x01D0);
		2287	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2288	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2289	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2290	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2291	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2292	tmp = RREG32(0x01E4);
		2293	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2294	return 0;
		2295	}
		2296
		2297	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2298	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2299	};
		2300
		2301	static struct drm_info_list r100_debugfs_cp_list[] = {
		2302	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2303	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2304	};
		2305
		2306	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2307	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2308	};
		2309	#endif
		2310
		2311	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2312	{
		2313	#if defined(CONFIG_DEBUG_FS)
		2314	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2315	#else
		2316	return 0;
		2317	#endif
		2318	}
		2319
		2320	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2321	{
		2322	#if defined(CONFIG_DEBUG_FS)
		2323	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2324	#else
		2325	return 0;
		2326	#endif
		2327	}
		2328
		2329	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2330	{
		2331	#if defined(CONFIG_DEBUG_FS)
		2332	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2333	#else
		2334	return 0;
		2335	#endif
		2336	}
1179	serge	2337
		2338	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2339	uint32_t tiling_flags, uint32_t pitch,
		2340	uint32_t offset, uint32_t obj_size)
		2341	{
		2342	int surf_index = reg * 16;
		2343	int flags = 0;
		2344
		2345	if (rdev->family <= CHIP_RS200) {
		2346	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2347	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2348	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2349	if (tiling_flags & RADEON_TILING_MACRO)
		2350	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2351	} else if (rdev->family <= CHIP_RV280) {
		2352	if (tiling_flags & (RADEON_TILING_MACRO))
		2353	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2354	if (tiling_flags & RADEON_TILING_MICRO)
		2355	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2356	} else {
		2357	if (tiling_flags & RADEON_TILING_MACRO)
		2358	flags \|= R300_SURF_TILE_MACRO;
		2359	if (tiling_flags & RADEON_TILING_MICRO)
		2360	flags \|= R300_SURF_TILE_MICRO;
		2361	}
		2362
		2363	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2364	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2365	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2366	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2367
1963	serge	2368	/* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
		2369	if (tiling_flags & (RADEON_TILING_SWAP_16BIT \| RADEON_TILING_SWAP_32BIT)) {
		2370	if (!(tiling_flags & (RADEON_TILING_MACRO \| RADEON_TILING_MICRO)))
		2371	if (ASIC_IS_RN50(rdev))
		2372	pitch /= 16;
		2373	}
		2374
		2375	/* r100/r200 divide by 16 */
		2376	if (rdev->family < CHIP_R300)
		2377	flags \|= pitch / 16;
		2378	else
		2379	flags \|= pitch / 8;
		2380
		2381
		2382	DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1179	serge	2383	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2384	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2385	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2386	return 0;
		2387	}
		2388
		2389	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2390	{
		2391	int surf_index = reg * 16;
		2392	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2393	}
		2394
		2395	void r100_bandwidth_update(struct radeon_device *rdev)
		2396	{
		2397	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2398	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2399	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2400	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2401	fixed20_12 memtcas_ff[8] = {
1963	serge	2402	dfixed_init(1),
		2403	dfixed_init(2),
		2404	dfixed_init(3),
		2405	dfixed_init(0),
		2406	dfixed_init_half(1),
		2407	dfixed_init_half(2),
		2408	dfixed_init(0),
1179	serge	2409	};
		2410	fixed20_12 memtcas_rs480_ff[8] = {
1963	serge	2411	dfixed_init(0),
		2412	dfixed_init(1),
		2413	dfixed_init(2),
		2414	dfixed_init(3),
		2415	dfixed_init(0),
		2416	dfixed_init_half(1),
		2417	dfixed_init_half(2),
		2418	dfixed_init_half(3),
1179	serge	2419	};
		2420	fixed20_12 memtcas2_ff[8] = {
1963	serge	2421	dfixed_init(0),
		2422	dfixed_init(1),
		2423	dfixed_init(2),
		2424	dfixed_init(3),
		2425	dfixed_init(4),
		2426	dfixed_init(5),
		2427	dfixed_init(6),
		2428	dfixed_init(7),
1179	serge	2429	};
		2430	fixed20_12 memtrbs[8] = {
1963	serge	2431	dfixed_init(1),
		2432	dfixed_init_half(1),
		2433	dfixed_init(2),
		2434	dfixed_init_half(2),
		2435	dfixed_init(3),
		2436	dfixed_init_half(3),
		2437	dfixed_init(4),
		2438	dfixed_init_half(4)
1179	serge	2439	};
		2440	fixed20_12 memtrbs_r4xx[8] = {
1963	serge	2441	dfixed_init(4),
		2442	dfixed_init(5),
		2443	dfixed_init(6),
		2444	dfixed_init(7),
		2445	dfixed_init(8),
		2446	dfixed_init(9),
		2447	dfixed_init(10),
		2448	dfixed_init(11)
1179	serge	2449	};
		2450	fixed20_12 min_mem_eff;
		2451	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2452	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2453	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2454	disp_drain_rate2, read_return_rate;
		2455	fixed20_12 time_disp1_drop_priority;
		2456	int c;
		2457	int cur_size = 16; /* in octawords */
		2458	int critical_point = 0, critical_point2;
		2459	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2460	int stop_req, max_stop_req;
		2461	struct drm_display_mode *mode1 = NULL;
		2462	struct drm_display_mode *mode2 = NULL;
		2463	uint32_t pixel_bytes1 = 0;
		2464	uint32_t pixel_bytes2 = 0;
		2465
1963	serge	2466	radeon_update_display_priority(rdev);
		2467
1179	serge	2468	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2469	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2470	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2471	}
1221	serge	2472	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2473	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2474	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2475	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2476	}
1221	serge	2477	}
1179	serge	2478
1963	serge	2479	min_mem_eff.full = dfixed_const_8(0);
1179	serge	2480	/* get modes */
		2481	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2482	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2483	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2484	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2485	/* check crtc enables */
		2486	if (mode2)
		2487	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2488	if (mode1)
		2489	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2490	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2491	}
		2492
		2493	/*
		2494	* determine is there is enough bw for current mode
		2495	*/
1963	serge	2496	sclk_ff = rdev->pm.sclk;
		2497	mclk_ff = rdev->pm.mclk;
1179	serge	2498
		2499	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1963	serge	2500	temp_ff.full = dfixed_const(temp);
		2501	mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2502
		2503	pix_clk.full = 0;
		2504	pix_clk2.full = 0;
		2505	peak_disp_bw.full = 0;
		2506	if (mode1) {
1963	serge	2507	temp_ff.full = dfixed_const(1000);
		2508	pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
		2509	pix_clk.full = dfixed_div(pix_clk, temp_ff);
		2510	temp_ff.full = dfixed_const(pixel_bytes1);
		2511	peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
1179	serge	2512	}
		2513	if (mode2) {
1963	serge	2514	temp_ff.full = dfixed_const(1000);
		2515	pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
		2516	pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
		2517	temp_ff.full = dfixed_const(pixel_bytes2);
		2518	peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
1179	serge	2519	}
		2520
1963	serge	2521	mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
1179	serge	2522	if (peak_disp_bw.full >= mem_bw.full) {
		2523	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2524	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2525	}
		2526
		2527	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2528	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2529	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2530	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2531	mem_trp = ((temp & 0x3)) + 1;
		2532	mem_tras = ((temp & 0x70) >> 4) + 1;
		2533	} else if (rdev->family == CHIP_R300 \|\|
		2534	rdev->family == CHIP_R350) { /* r300, r350 */
		2535	mem_trcd = (temp & 0x7) + 1;
		2536	mem_trp = ((temp >> 8) & 0x7) + 1;
		2537	mem_tras = ((temp >> 11) & 0xf) + 4;
		2538	} else if (rdev->family == CHIP_RV350 \|\|
		2539	rdev->family <= CHIP_RV380) {
		2540	/* rv3x0 */
		2541	mem_trcd = (temp & 0x7) + 3;
		2542	mem_trp = ((temp >> 8) & 0x7) + 3;
		2543	mem_tras = ((temp >> 11) & 0xf) + 6;
		2544	} else if (rdev->family == CHIP_R420 \|\|
		2545	rdev->family == CHIP_R423 \|\|
		2546	rdev->family == CHIP_RV410) {
		2547	/* r4xx */
		2548	mem_trcd = (temp & 0xf) + 3;
		2549	if (mem_trcd > 15)
		2550	mem_trcd = 15;
		2551	mem_trp = ((temp >> 8) & 0xf) + 3;
		2552	if (mem_trp > 15)
		2553	mem_trp = 15;
		2554	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2555	if (mem_tras > 31)
		2556	mem_tras = 31;
		2557	} else { /* RV200, R200 */
		2558	mem_trcd = (temp & 0x7) + 1;
		2559	mem_trp = ((temp >> 8) & 0x7) + 1;
		2560	mem_tras = ((temp >> 12) & 0xf) + 4;
		2561	}
		2562	/* convert to FF */
1963	serge	2563	trcd_ff.full = dfixed_const(mem_trcd);
		2564	trp_ff.full = dfixed_const(mem_trp);
		2565	tras_ff.full = dfixed_const(mem_tras);
1179	serge	2566
		2567	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2568	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2569	data = (temp & (7 << 20)) >> 20;
		2570	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2571	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2572	tcas_ff = memtcas_rs480_ff[data];
		2573	else
		2574	tcas_ff = memtcas_ff[data];
		2575	} else
		2576	tcas_ff = memtcas2_ff[data];
		2577
		2578	if (rdev->family == CHIP_RS400 \|\|
		2579	rdev->family == CHIP_RS480) {
		2580	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2581	data = (temp >> 23) & 0x7;
		2582	if (data < 5)
1963	serge	2583	tcas_ff.full += dfixed_const(data);
1179	serge	2584	}
		2585
		2586	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2587	/* on the R300, Tcas is included in Trbs.
		2588	*/
		2589	temp = RREG32(RADEON_MEM_CNTL);
		2590	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2591	if (data == 1) {
		2592	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2593	temp = RREG32(R300_MC_IND_INDEX);
		2594	temp &= ~R300_MC_IND_ADDR_MASK;
		2595	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2596	WREG32(R300_MC_IND_INDEX, temp);
		2597	temp = RREG32(R300_MC_IND_DATA);
		2598	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2599	} else {
		2600	temp = RREG32(R300_MC_READ_CNTL_AB);
		2601	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2602	}
		2603	} else {
		2604	temp = RREG32(R300_MC_READ_CNTL_AB);
		2605	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2606	}
		2607	if (rdev->family == CHIP_RV410 \|\|
		2608	rdev->family == CHIP_R420 \|\|
		2609	rdev->family == CHIP_R423)
		2610	trbs_ff = memtrbs_r4xx[data];
		2611	else
		2612	trbs_ff = memtrbs[data];
		2613	tcas_ff.full += trbs_ff.full;
		2614	}
		2615
		2616	sclk_eff_ff.full = sclk_ff.full;
		2617
		2618	if (rdev->flags & RADEON_IS_AGP) {
		2619	fixed20_12 agpmode_ff;
1963	serge	2620	agpmode_ff.full = dfixed_const(radeon_agpmode);
		2621	temp_ff.full = dfixed_const_666(16);
		2622	sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
1179	serge	2623	}
		2624	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2625
		2626	if (ASIC_IS_R300(rdev)) {
1963	serge	2627	sclk_delay_ff.full = dfixed_const(250);
1179	serge	2628	} else {
		2629	if ((rdev->family == CHIP_RV100) \|\|
		2630	rdev->flags & RADEON_IS_IGP) {
		2631	if (rdev->mc.vram_is_ddr)
1963	serge	2632	sclk_delay_ff.full = dfixed_const(41);
1179	serge	2633	else
1963	serge	2634	sclk_delay_ff.full = dfixed_const(33);
1179	serge	2635	} else {
		2636	if (rdev->mc.vram_width == 128)
1963	serge	2637	sclk_delay_ff.full = dfixed_const(57);
1179	serge	2638	else
1963	serge	2639	sclk_delay_ff.full = dfixed_const(41);
1179	serge	2640	}
		2641	}
		2642
1963	serge	2643	mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
1179	serge	2644
		2645	if (rdev->mc.vram_is_ddr) {
		2646	if (rdev->mc.vram_width == 32) {
1963	serge	2647	k1.full = dfixed_const(40);
1179	serge	2648	c = 3;
		2649	} else {
1963	serge	2650	k1.full = dfixed_const(20);
1179	serge	2651	c = 1;
		2652	}
		2653	} else {
1963	serge	2654	k1.full = dfixed_const(40);
1179	serge	2655	c = 3;
		2656	}
		2657
1963	serge	2658	temp_ff.full = dfixed_const(2);
		2659	mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
		2660	temp_ff.full = dfixed_const(c);
		2661	mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
		2662	temp_ff.full = dfixed_const(4);
		2663	mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
		2664	mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
1179	serge	2665	mc_latency_mclk.full += k1.full;
		2666
1963	serge	2667	mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
		2668	mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	2669
		2670	/*
		2671	HW cursor time assuming worst case of full size colour cursor.
		2672	*/
1963	serge	2673	temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
1179	serge	2674	temp_ff.full += trcd_ff.full;
		2675	if (temp_ff.full < tras_ff.full)
		2676	temp_ff.full = tras_ff.full;
1963	serge	2677	cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
1179	serge	2678
1963	serge	2679	temp_ff.full = dfixed_const(cur_size);
		2680	cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
1179	serge	2681	/*
		2682	Find the total latency for the display data.
		2683	*/
1963	serge	2684	disp_latency_overhead.full = dfixed_const(8);
		2685	disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
1179	serge	2686	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2687	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2688
		2689	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2690	disp_latency.full = mc_latency_mclk.full;
		2691	else
		2692	disp_latency.full = mc_latency_sclk.full;
		2693
		2694	/* setup Max GRPH_STOP_REQ default value */
		2695	if (ASIC_IS_RV100(rdev))
		2696	max_stop_req = 0x5c;
		2697	else
		2698	max_stop_req = 0x7c;
		2699
		2700	if (mode1) {
		2701	/* CRTC1
		2702	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2703	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2704	*/
		2705	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2706
		2707	if (stop_req > max_stop_req)
		2708	stop_req = max_stop_req;
		2709
		2710	/*
		2711	Find the drain rate of the display buffer.
		2712	*/
1963	serge	2713	temp_ff.full = dfixed_const((16/pixel_bytes1));
		2714	disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
1179	serge	2715
		2716	/*
		2717	Find the critical point of the display buffer.
		2718	*/
1963	serge	2719	crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
		2720	crit_point_ff.full += dfixed_const_half(0);
1179	serge	2721
1963	serge	2722	critical_point = dfixed_trunc(crit_point_ff);
1179	serge	2723
		2724	if (rdev->disp_priority == 2) {
		2725	critical_point = 0;
		2726	}
		2727
		2728	/*
		2729	The critical point should never be above max_stop_req-4. Setting
		2730	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2731	*/
		2732	if (max_stop_req - critical_point < 4)
		2733	critical_point = 0;
		2734
		2735	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2736	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2737	critical_point = 0x10;
		2738	}
		2739
		2740	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2741	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2742	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2743	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2744	if ((rdev->family == CHIP_R350) &&
		2745	(stop_req > 0x15)) {
		2746	stop_req -= 0x10;
		2747	}
		2748	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2749	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2750	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2751	RADEON_GRPH_CRITICAL_AT_SOF \|
		2752	RADEON_GRPH_STOP_CNTL);
		2753	/*
		2754	Write the result into the register.
		2755	*/
		2756	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2757	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2758
		2759	#if 0
		2760	if ((rdev->family == CHIP_RS400) \|\|
		2761	(rdev->family == CHIP_RS480)) {
		2762	/* attempt to program RS400 disp regs correctly ??? */
		2763	temp = RREG32(RS400_DISP1_REG_CNTL);
		2764	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2765	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2766	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2767	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2768	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2769	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2770	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2771	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2772	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2773	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2774	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2775	}
		2776	#endif
		2777
1963	serge	2778	DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
1179	serge	2779	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2780	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2781	}
		2782
		2783	if (mode2) {
		2784	u32 grph2_cntl;
		2785	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2786
		2787	if (stop_req > max_stop_req)
		2788	stop_req = max_stop_req;
		2789
		2790	/*
		2791	Find the drain rate of the display buffer.
		2792	*/
1963	serge	2793	temp_ff.full = dfixed_const((16/pixel_bytes2));
		2794	disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
1179	serge	2795
		2796	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2797	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2798	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2799	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2800	if ((rdev->family == CHIP_R350) &&
		2801	(stop_req > 0x15)) {
		2802	stop_req -= 0x10;
		2803	}
		2804	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2805	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2806	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2807	RADEON_GRPH_CRITICAL_AT_SOF \|
		2808	RADEON_GRPH_STOP_CNTL);
		2809
		2810	if ((rdev->family == CHIP_RS100) \|\|
		2811	(rdev->family == CHIP_RS200))
		2812	critical_point2 = 0;
		2813	else {
		2814	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
1963	serge	2815	temp_ff.full = dfixed_const(temp);
		2816	temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
1179	serge	2817	if (sclk_ff.full < temp_ff.full)
		2818	temp_ff.full = sclk_ff.full;
		2819
		2820	read_return_rate.full = temp_ff.full;
		2821
		2822	if (mode1) {
		2823	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
1963	serge	2824	time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
1179	serge	2825	} else {
		2826	time_disp1_drop_priority.full = 0;
		2827	}
		2828	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
1963	serge	2829	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
		2830	crit_point_ff.full += dfixed_const_half(0);
1179	serge	2831
1963	serge	2832	critical_point2 = dfixed_trunc(crit_point_ff);
1179	serge	2833
		2834	if (rdev->disp_priority == 2) {
		2835	critical_point2 = 0;
		2836	}
		2837
		2838	if (max_stop_req - critical_point2 < 4)
		2839	critical_point2 = 0;
		2840
		2841	}
		2842
		2843	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2844	/* some R300 cards have problem with this set to 0 */
		2845	critical_point2 = 0x10;
		2846	}
		2847
		2848	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2849	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2850
		2851	if ((rdev->family == CHIP_RS400) \|\|
		2852	(rdev->family == CHIP_RS480)) {
		2853	#if 0
		2854	/* attempt to program RS400 disp2 regs correctly ??? */
		2855	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2856	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2857	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2858	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2859	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2860	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2861	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2862	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2863	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2864	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2865	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2866	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2867	#endif
		2868	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2869	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2870	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2871	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2872	}
		2873
1963	serge	2874	DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
1179	serge	2875	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2876	}
		2877	}
		2878
1963	serge	2879	#if 0
		2880	static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
		2881	{
		2882	DRM_ERROR("pitch %d\n", t->pitch);
		2883	DRM_ERROR("use_pitch %d\n", t->use_pitch);
		2884	DRM_ERROR("width %d\n", t->width);
		2885	DRM_ERROR("width_11 %d\n", t->width_11);
		2886	DRM_ERROR("height %d\n", t->height);
		2887	DRM_ERROR("height_11 %d\n", t->height_11);
		2888	DRM_ERROR("num levels %d\n", t->num_levels);
		2889	DRM_ERROR("depth %d\n", t->txdepth);
		2890	DRM_ERROR("bpp %d\n", t->cpp);
		2891	DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
		2892	DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
		2893	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
		2894	DRM_ERROR("compress format %d\n", t->compress_format);
		2895	}
1179	serge	2896
1963	serge	2897	static int r100_track_compress_size(int compress_format, int w, int h)
		2898	{
		2899	int block_width, block_height, block_bytes;
		2900	int wblocks, hblocks;
		2901	int min_wblocks;
		2902	int sz;
1179	serge	2903
1963	serge	2904	block_width = 4;
		2905	block_height = 4;
		2906
		2907	switch (compress_format) {
		2908	case R100_TRACK_COMP_DXT1:
		2909	block_bytes = 8;
		2910	min_wblocks = 4;
		2911	break;
		2912	default:
		2913	case R100_TRACK_COMP_DXT35:
		2914	block_bytes = 16;
		2915	min_wblocks = 2;
		2916	break;
		2917	}
		2918
		2919	hblocks = (h + block_height - 1) / block_height;
		2920	wblocks = (w + block_width - 1) / block_width;
		2921	if (wblocks < min_wblocks)
		2922	wblocks = min_wblocks;
		2923	sz = wblocks * hblocks * block_bytes;
		2924	return sz;
		2925	}
		2926
		2927	static int r100_cs_track_cube(struct radeon_device *rdev,
		2928	struct r100_cs_track *track, unsigned idx)
		2929	{
		2930	unsigned face, w, h;
		2931	struct radeon_bo *cube_robj;
		2932	unsigned long size;
		2933	unsigned compress_format = track->textures[idx].compress_format;
		2934
		2935	for (face = 0; face < 5; face++) {
		2936	cube_robj = track->textures[idx].cube_info[face].robj;
		2937	w = track->textures[idx].cube_info[face].width;
		2938	h = track->textures[idx].cube_info[face].height;
		2939
		2940	if (compress_format) {
		2941	size = r100_track_compress_size(compress_format, w, h);
		2942	} else
		2943	size = w * h;
		2944	size *= track->textures[idx].cpp;
		2945
		2946	size += track->textures[idx].cube_info[face].offset;
		2947
		2948	if (size > radeon_bo_size(cube_robj)) {
		2949	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
		2950	size, radeon_bo_size(cube_robj));
		2951	r100_cs_track_texture_print(&track->textures[idx]);
		2952	return -1;
		2953	}
		2954	}
		2955	return 0;
		2956	}
		2957
		2958	static int r100_cs_track_texture_check(struct radeon_device *rdev,
		2959	struct r100_cs_track *track)
		2960	{
		2961	struct radeon_bo *robj;
		2962	unsigned long size;
		2963	unsigned u, i, w, h, d;
		2964	int ret;
		2965
		2966	for (u = 0; u < track->num_texture; u++) {
		2967	if (!track->textures[u].enabled)
		2968	continue;
		2969	if (track->textures[u].lookup_disable)
		2970	continue;
		2971	robj = track->textures[u].robj;
		2972	if (robj == NULL) {
		2973	DRM_ERROR("No texture bound to unit %u\n", u);
		2974	return -EINVAL;
		2975	}
		2976	size = 0;
		2977	for (i = 0; i <= track->textures[u].num_levels; i++) {
		2978	if (track->textures[u].use_pitch) {
		2979	if (rdev->family < CHIP_R300)
		2980	w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		2981	else
		2982	w = track->textures[u].pitch / (1 << i);
		2983	} else {
		2984	w = track->textures[u].width;
		2985	if (rdev->family >= CHIP_RV515)
		2986	w \|= track->textures[u].width_11;
		2987	w = w / (1 << i);
		2988	if (track->textures[u].roundup_w)
		2989	w = roundup_pow_of_two(w);
		2990	}
		2991	h = track->textures[u].height;
		2992	if (rdev->family >= CHIP_RV515)
		2993	h \|= track->textures[u].height_11;
		2994	h = h / (1 << i);
		2995	if (track->textures[u].roundup_h)
		2996	h = roundup_pow_of_two(h);
		2997	if (track->textures[u].tex_coord_type == 1) {
		2998	d = (1 << track->textures[u].txdepth) / (1 << i);
		2999	if (!d)
		3000	d = 1;
		3001	} else {
		3002	d = 1;
		3003	}
		3004	if (track->textures[u].compress_format) {
		3005
		3006	size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		3007	/* compressed textures are block based */
		3008	} else
		3009	size += w * h * d;
		3010	}
		3011	size *= track->textures[u].cpp;
		3012
		3013	switch (track->textures[u].tex_coord_type) {
		3014	case 0:
		3015	case 1:
		3016	break;
		3017	case 2:
		3018	if (track->separate_cube) {
		3019	ret = r100_cs_track_cube(rdev, track, u);
		3020	if (ret)
		3021	return ret;
		3022	} else
		3023	size *= 6;
		3024	break;
		3025	default:
		3026	DRM_ERROR("Invalid texture coordinate type %u for unit "
		3027	"%u\n", track->textures[u].tex_coord_type, u);
		3028	return -EINVAL;
		3029	}
		3030	if (size > radeon_bo_size(robj)) {
		3031	DRM_ERROR("Texture of unit %u needs %lu bytes but is "
		3032	"%lu\n", u, size, radeon_bo_size(robj));
		3033	r100_cs_track_texture_print(&track->textures[u]);
		3034	return -EINVAL;
		3035	}
		3036	}
		3037	return 0;
		3038	}
		3039
		3040	int r100_cs_track_check(struct radeon_device rdev, struct r100_cs_track track)
		3041	{
		3042	unsigned i;
		3043	unsigned long size;
		3044	unsigned prim_walk;
		3045	unsigned nverts;
		3046	unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
		3047
		3048	if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
		3049	!track->blend_read_enable)
		3050	num_cb = 0;
		3051
		3052	for (i = 0; i < num_cb; i++) {
		3053	if (track->cb[i].robj == NULL) {
		3054	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
		3055	return -EINVAL;
		3056	}
		3057	size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
		3058	size += track->cb[i].offset;
		3059	if (size > radeon_bo_size(track->cb[i].robj)) {
		3060	DRM_ERROR("[drm] Buffer too small for color buffer %d "
		3061	"(need %lu have %lu) !\n", i, size,
		3062	radeon_bo_size(track->cb[i].robj));
		3063	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
		3064	i, track->cb[i].pitch, track->cb[i].cpp,
		3065	track->cb[i].offset, track->maxy);
		3066	return -EINVAL;
		3067	}
		3068	}
		3069	track->cb_dirty = false;
		3070
		3071	if (track->zb_dirty && track->z_enabled) {
		3072	if (track->zb.robj == NULL) {
		3073	DRM_ERROR("[drm] No buffer for z buffer !\n");
		3074	return -EINVAL;
		3075	}
		3076	size = track->zb.pitch * track->zb.cpp * track->maxy;
		3077	size += track->zb.offset;
		3078	if (size > radeon_bo_size(track->zb.robj)) {
		3079	DRM_ERROR("[drm] Buffer too small for z buffer "
		3080	"(need %lu have %lu) !\n", size,
		3081	radeon_bo_size(track->zb.robj));
		3082	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
		3083	track->zb.pitch, track->zb.cpp,
		3084	track->zb.offset, track->maxy);
		3085	return -EINVAL;
		3086	}
		3087	}
		3088	track->zb_dirty = false;
		3089
		3090	if (track->aa_dirty && track->aaresolve) {
		3091	if (track->aa.robj == NULL) {
		3092	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
		3093	return -EINVAL;
		3094	}
		3095	/* I believe the format comes from colorbuffer0. */
		3096	size = track->aa.pitch * track->cb[0].cpp * track->maxy;
		3097	size += track->aa.offset;
		3098	if (size > radeon_bo_size(track->aa.robj)) {
		3099	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
		3100	"(need %lu have %lu) !\n", i, size,
		3101	radeon_bo_size(track->aa.robj));
		3102	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
		3103	i, track->aa.pitch, track->cb[0].cpp,
		3104	track->aa.offset, track->maxy);
		3105	return -EINVAL;
		3106	}
		3107	}
		3108	track->aa_dirty = false;
		3109
		3110	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
		3111	if (track->vap_vf_cntl & (1 << 14)) {
		3112	nverts = track->vap_alt_nverts;
		3113	} else {
		3114	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
		3115	}
		3116	switch (prim_walk) {
		3117	case 1:
		3118	for (i = 0; i < track->num_arrays; i++) {
		3119	size = track->arrays[i].esize * track->max_indx * 4;
		3120	if (track->arrays[i].robj == NULL) {
		3121	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		3122	"bound\n", prim_walk, i);
		3123	return -EINVAL;
		3124	}
		3125	if (size > radeon_bo_size(track->arrays[i].robj)) {
		3126	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		3127	"need %lu dwords have %lu dwords\n",
		3128	prim_walk, i, size >> 2,
		3129	radeon_bo_size(track->arrays[i].robj)
		3130	>> 2);
		3131	DRM_ERROR("Max indices %u\n", track->max_indx);
		3132	return -EINVAL;
		3133	}
		3134	}
		3135	break;
		3136	case 2:
		3137	for (i = 0; i < track->num_arrays; i++) {
		3138	size = track->arrays[i].esize * (nverts - 1) * 4;
		3139	if (track->arrays[i].robj == NULL) {
		3140	DRM_ERROR("(PW %u) Vertex array %u no buffer "
		3141	"bound\n", prim_walk, i);
		3142	return -EINVAL;
		3143	}
		3144	if (size > radeon_bo_size(track->arrays[i].robj)) {
		3145	dev_err(rdev->dev, "(PW %u) Vertex array %u "
		3146	"need %lu dwords have %lu dwords\n",
		3147	prim_walk, i, size >> 2,
		3148	radeon_bo_size(track->arrays[i].robj)
		3149	>> 2);
		3150	return -EINVAL;
		3151	}
		3152	}
		3153	break;
		3154	case 3:
		3155	size = track->vtx_size * nverts;
		3156	if (size != track->immd_dwords) {
		3157	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
		3158	track->immd_dwords, size);
		3159	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
		3160	nverts, track->vtx_size);
		3161	return -EINVAL;
		3162	}
		3163	break;
		3164	default:
		3165	DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
		3166	prim_walk);
		3167	return -EINVAL;
		3168	}
		3169
		3170	if (track->tex_dirty) {
		3171	track->tex_dirty = false;
		3172	return r100_cs_track_texture_check(rdev, track);
		3173	}
		3174	return 0;
		3175	}
		3176
		3177	void r100_cs_track_clear(struct radeon_device rdev, struct r100_cs_track track)
		3178	{
		3179	unsigned i, face;
		3180
		3181	track->cb_dirty = true;
		3182	track->zb_dirty = true;
		3183	track->tex_dirty = true;
		3184	track->aa_dirty = true;
		3185
		3186	if (rdev->family < CHIP_R300) {
		3187	track->num_cb = 1;
		3188	if (rdev->family <= CHIP_RS200)
		3189	track->num_texture = 3;
		3190	else
		3191	track->num_texture = 6;
		3192	track->maxy = 2048;
		3193	track->separate_cube = 1;
		3194	} else {
		3195	track->num_cb = 4;
		3196	track->num_texture = 16;
		3197	track->maxy = 4096;
		3198	track->separate_cube = 0;
		3199	track->aaresolve = false;
		3200	track->aa.robj = NULL;
		3201	}
		3202
		3203	for (i = 0; i < track->num_cb; i++) {
		3204	track->cb[i].robj = NULL;
		3205	track->cb[i].pitch = 8192;
		3206	track->cb[i].cpp = 16;
		3207	track->cb[i].offset = 0;
		3208	}
		3209	track->z_enabled = true;
		3210	track->zb.robj = NULL;
		3211	track->zb.pitch = 8192;
		3212	track->zb.cpp = 4;
		3213	track->zb.offset = 0;
		3214	track->vtx_size = 0x7F;
		3215	track->immd_dwords = 0xFFFFFFFFUL;
		3216	track->num_arrays = 11;
		3217	track->max_indx = 0x00FFFFFFUL;
		3218	for (i = 0; i < track->num_arrays; i++) {
		3219	track->arrays[i].robj = NULL;
		3220	track->arrays[i].esize = 0x7F;
		3221	}
		3222	for (i = 0; i < track->num_texture; i++) {
		3223	track->textures[i].compress_format = R100_TRACK_COMP_NONE;
		3224	track->textures[i].pitch = 16536;
		3225	track->textures[i].width = 16536;
		3226	track->textures[i].height = 16536;
		3227	track->textures[i].width_11 = 1 << 11;
		3228	track->textures[i].height_11 = 1 << 11;
		3229	track->textures[i].num_levels = 12;
		3230	if (rdev->family <= CHIP_RS200) {
		3231	track->textures[i].tex_coord_type = 0;
		3232	track->textures[i].txdepth = 0;
		3233	} else {
		3234	track->textures[i].txdepth = 16;
		3235	track->textures[i].tex_coord_type = 1;
		3236	}
		3237	track->textures[i].cpp = 64;
		3238	track->textures[i].robj = NULL;
		3239	/* CS IB emission code makes sure texture unit are disabled */
		3240	track->textures[i].enabled = false;
		3241	track->textures[i].lookup_disable = false;
		3242	track->textures[i].roundup_w = true;
		3243	track->textures[i].roundup_h = true;
		3244	if (track->separate_cube)
		3245	for (face = 0; face < 5; face++) {
		3246	track->textures[i].cube_info[face].robj = NULL;
		3247	track->textures[i].cube_info[face].width = 16536;
		3248	track->textures[i].cube_info[face].height = 16536;
		3249	track->textures[i].cube_info[face].offset = 0;
		3250	}
		3251	}
		3252	}
		3253	#endif
		3254
1412	serge	3255	int r100_ring_test(struct radeon_device *rdev)
		3256	{
		3257	uint32_t scratch;
		3258	uint32_t tmp = 0;
		3259	unsigned i;
		3260	int r;
1179	serge	3261
1412	serge	3262	r = radeon_scratch_get(rdev, &scratch);
		3263	if (r) {
		3264	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		3265	return r;
		3266	}
		3267	WREG32(scratch, 0xCAFEDEAD);
		3268	r = radeon_ring_lock(rdev, 2);
		3269	if (r) {
		3270	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		3271	radeon_scratch_free(rdev, scratch);
		3272	return r;
		3273	}
		3274	radeon_ring_write(rdev, PACKET0(scratch, 0));
		3275	radeon_ring_write(rdev, 0xDEADBEEF);
		3276	radeon_ring_unlock_commit(rdev);
		3277	for (i = 0; i < rdev->usec_timeout; i++) {
		3278	tmp = RREG32(scratch);
		3279	if (tmp == 0xDEADBEEF) {
		3280	break;
		3281	}
		3282	DRM_UDELAY(1);
		3283	}
		3284	if (i < rdev->usec_timeout) {
		3285	DRM_INFO("ring test succeeded in %d usecs\n", i);
		3286	} else {
1963	serge	3287	DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1412	serge	3288	scratch, tmp);
		3289	r = -EINVAL;
		3290	}
		3291	radeon_scratch_free(rdev, scratch);
		3292	return r;
		3293	}
		3294
1963	serge	3295	void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		3296	{
		3297	radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
		3298	radeon_ring_write(rdev, ib->gpu_addr);
		3299	radeon_ring_write(rdev, ib->length_dw);
		3300	}
		3301
		3302	int r100_ib_test(struct radeon_device *rdev)
		3303	{
		3304	struct radeon_ib *ib;
		3305	uint32_t scratch;
		3306	uint32_t tmp = 0;
		3307	unsigned i;
		3308	int r;
		3309
		3310	r = radeon_scratch_get(rdev, &scratch);
		3311	if (r) {
		3312	DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
		3313	return r;
		3314	}
		3315	WREG32(scratch, 0xCAFEDEAD);
		3316	r = radeon_ib_get(rdev, &ib);
		3317	if (r) {
		3318	return r;
		3319	}
		3320	ib->ptr[0] = PACKET0(scratch, 0);
		3321	ib->ptr[1] = 0xDEADBEEF;
		3322	ib->ptr[2] = PACKET2(0);
		3323	ib->ptr[3] = PACKET2(0);
		3324	ib->ptr[4] = PACKET2(0);
		3325	ib->ptr[5] = PACKET2(0);
		3326	ib->ptr[6] = PACKET2(0);
		3327	ib->ptr[7] = PACKET2(0);
		3328	ib->length_dw = 8;
		3329	r = radeon_ib_schedule(rdev, ib);
		3330	if (r) {
		3331	radeon_scratch_free(rdev, scratch);
		3332	radeon_ib_free(rdev, &ib);
		3333	return r;
		3334	}
		3335	r = radeon_fence_wait(ib->fence, false);
		3336	if (r) {
		3337	return r;
		3338	}
		3339	for (i = 0; i < rdev->usec_timeout; i++) {
		3340	tmp = RREG32(scratch);
		3341	if (tmp == 0xDEADBEEF) {
		3342	break;
		3343	}
		3344	DRM_UDELAY(1);
		3345	}
		3346	if (i < rdev->usec_timeout) {
		3347	DRM_INFO("ib test succeeded in %u usecs\n", i);
		3348	} else {
		3349	DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
		3350	scratch, tmp);
		3351	r = -EINVAL;
		3352	}
		3353	radeon_scratch_free(rdev, scratch);
		3354	radeon_ib_free(rdev, &ib);
		3355	return r;
		3356	}
		3357
		3358	void r100_ib_fini(struct radeon_device *rdev)
		3359	{
		3360	radeon_ib_pool_fini(rdev);
		3361	}
		3362
		3363	int r100_ib_init(struct radeon_device *rdev)
		3364	{
		3365	int r;
		3366
		3367	r = radeon_ib_pool_init(rdev);
		3368	if (r) {
		3369	dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
		3370	r100_ib_fini(rdev);
		3371	return r;
		3372	}
		3373	r = r100_ib_test(rdev);
		3374	if (r) {
		3375	dev_err(rdev->dev, "failed testing IB (%d).\n", r);
		3376	r100_ib_fini(rdev);
		3377	return r;
		3378	}
		3379	return 0;
		3380	}
		3381
1179	serge	3382	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		3383	{
		3384	/* Shutdown CP we shouldn't need to do that but better be safe than
		3385	* sorry
		3386	*/
		3387	rdev->cp.ready = false;
		3388	WREG32(R_000740_CP_CSQ_CNTL, 0);
		3389
		3390	/* Save few CRTC registers */
1221	serge	3391	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	3392	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		3393	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		3394	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		3395	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3396	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		3397	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		3398	}
		3399
		3400	/* Disable VGA aperture access */
1221	serge	3401	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	3402	/* Disable cursor, overlay, crtc */
		3403	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		3404	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		3405	S_000054_CRTC_DISPLAY_DIS(1));
		3406	WREG32(R_000050_CRTC_GEN_CNTL,
		3407	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		3408	S_000050_CRTC_DISP_REQ_EN_B(1));
		3409	WREG32(R_000420_OV0_SCALE_CNTL,
		3410	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		3411	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		3412	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3413	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		3414	S_000360_CUR2_LOCK(1));
		3415	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		3416	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		3417	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		3418	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		3419	WREG32(R_000360_CUR2_OFFSET,
		3420	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		3421	}
		3422	}
		3423
		3424	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		3425	{
		3426	/* Update base address for crtc */
1430	serge	3427	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3428	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	3429	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	3430	}
		3431	/* Restore CRTC registers */
1221	serge	3432	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	3433	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		3434	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		3435	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		3436	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		3437	}
		3438	}
		3439
1221	serge	3440	void r100_vga_render_disable(struct radeon_device *rdev)
		3441	{
		3442	u32 tmp;
		3443
		3444	tmp = RREG8(R_0003C2_GENMO_WT);
		3445	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		3446	}
		3447
		3448	static void r100_debugfs(struct radeon_device *rdev)
		3449	{
		3450	int r;
		3451
		3452	r = r100_debugfs_mc_info_init(rdev);
		3453	if (r)
		3454	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		3455	}
		3456
		3457
1179	serge	3458	int drm_order(unsigned long size)
		3459	{
		3460	int order;
		3461	unsigned long tmp;
		3462
		3463	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		3464
		3465	if (size & (size - 1))
		3466	++order;
		3467
		3468	return order;
		3469	}
		3470
1221	serge	3471	static void r100_mc_program(struct radeon_device *rdev)
		3472	{
		3473	struct r100_mc_save save;
		3474
		3475	/* Stops all mc clients */
		3476	r100_mc_stop(rdev, &save);
		3477	if (rdev->flags & RADEON_IS_AGP) {
		3478	WREG32(R_00014C_MC_AGP_LOCATION,
		3479	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		3480	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		3481	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		3482	if (rdev->family > CHIP_RV200)
		3483	WREG32(R_00015C_AGP_BASE_2,
		3484	upper_32_bits(rdev->mc.agp_base) & 0xff);
		3485	} else {
		3486	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		3487	WREG32(R_000170_AGP_BASE, 0);
		3488	if (rdev->family > CHIP_RV200)
		3489	WREG32(R_00015C_AGP_BASE_2, 0);
		3490	}
		3491	/* Wait for mc idle */
		3492	if (r100_mc_wait_for_idle(rdev))
		3493	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		3494	/* Program MC, should be a 32bits limited address space */
		3495	WREG32(R_000148_MC_FB_LOCATION,
		3496	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		3497	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		3498	r100_mc_resume(rdev, &save);
		3499	}
		3500
		3501	void r100_clock_startup(struct radeon_device *rdev)
		3502	{
		3503	u32 tmp;
		3504
		3505	if (radeon_dynclks != -1 && radeon_dynclks)
		3506	radeon_legacy_set_clock_gating(rdev, 1);
		3507	/* We need to force on some of the block */
		3508	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		3509	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		3510	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		3511	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		3512	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		3513	}
		3514
		3515	static int r100_startup(struct radeon_device *rdev)
		3516	{
		3517	int r;
		3518
1321	serge	3519	/* set common regs */
		3520	r100_set_common_regs(rdev);
		3521	/* program mc */
1221	serge	3522	r100_mc_program(rdev);
		3523	/* Resume clock */
		3524	r100_clock_startup(rdev);
		3525	/* Initialize GART (initialize after TTM so we can allocate
		3526	* memory through TTM but finalize after TTM) */
1321	serge	3527	r100_enable_bm(rdev);
1221	serge	3528	if (rdev->flags & RADEON_IS_PCI) {
		3529	r = r100_pci_gart_enable(rdev);
		3530	if (r)
		3531	return r;
		3532	}
2005	serge	3533
		3534	/* allocate wb buffer */
		3535	r = radeon_wb_init(rdev);
		3536	if (r)
		3537	return r;
		3538
1221	serge	3539	/* Enable IRQ */
2005	serge	3540	r100_irq_set(rdev);
1404	serge	3541	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	3542	/* 1M ring buffer */
1412	serge	3543	r = r100_cp_init(rdev, 1024 * 1024);
		3544	if (r) {
1963	serge	3545	dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412	serge	3546	return r;
		3547	}
2005	serge	3548	r = r100_ib_init(rdev);
		3549	if (r) {
		3550	dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
		3551	return r;
		3552	}
1221	serge	3553	return 0;
		3554	}
		3555
1963	serge	3556	/*
		3557	* Due to how kexec works, it can leave the hw fully initialised when it
		3558	* boots the new kernel. However doing our init sequence with the CP and
		3559	* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
		3560	* do some quick sanity checks and restore sane values to avoid this
		3561	* problem.
		3562	*/
		3563	void r100_restore_sanity(struct radeon_device *rdev)
		3564	{
		3565	u32 tmp;
1221	serge	3566
1963	serge	3567	tmp = RREG32(RADEON_CP_CSQ_CNTL);
		3568	if (tmp) {
		3569	WREG32(RADEON_CP_CSQ_CNTL, 0);
		3570	}
		3571	tmp = RREG32(RADEON_CP_RB_CNTL);
		3572	if (tmp) {
		3573	WREG32(RADEON_CP_RB_CNTL, 0);
		3574	}
		3575	tmp = RREG32(RADEON_SCRATCH_UMSK);
		3576	if (tmp) {
		3577	WREG32(RADEON_SCRATCH_UMSK, 0);
		3578	}
		3579	}
1221	serge	3580
		3581	int r100_init(struct radeon_device *rdev)
		3582	{
		3583	int r;
		3584
		3585	/* Register debugfs file specific to this group of asics */
		3586	r100_debugfs(rdev);
		3587	/* Disable VGA */
		3588	r100_vga_render_disable(rdev);
		3589	/* Initialize scratch registers */
		3590	radeon_scratch_init(rdev);
		3591	/* Initialize surface registers */
		3592	radeon_surface_init(rdev);
1963	serge	3593	/* sanity check some register to avoid hangs like after kexec */
		3594	r100_restore_sanity(rdev);
1221	serge	3595	/* TODO: disable VGA need to use VGA request */
		3596	/* BIOS*/
		3597	if (!radeon_get_bios(rdev)) {
		3598	if (ASIC_IS_AVIVO(rdev))
		3599	return -EINVAL;
		3600	}
		3601	if (rdev->is_atom_bios) {
		3602	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		3603	return -EINVAL;
		3604	} else {
		3605	r = radeon_combios_init(rdev);
		3606	if (r)
		3607	return r;
		3608	}
		3609	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963	serge	3610	if (radeon_asic_reset(rdev)) {
1221	serge	3611	dev_warn(rdev->dev,
		3612	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		3613	RREG32(R_000E40_RBBM_STATUS),
		3614	RREG32(R_0007C0_CP_STAT));
		3615	}
		3616	/* check if cards are posted or not */
1321	serge	3617	if (radeon_boot_test_post_card(rdev) == false)
		3618	return -EINVAL;
1221	serge	3619	/* Set asic errata */
		3620	r100_errata(rdev);
		3621	/* Initialize clocks */
		3622	radeon_get_clock_info(rdev->ddev);
1430	serge	3623	/* initialize AGP */
		3624	if (rdev->flags & RADEON_IS_AGP) {
		3625	r = radeon_agp_init(rdev);
		3626	if (r) {
		3627	radeon_agp_disable(rdev);
		3628	}
		3629	}
		3630	/* initialize VRAM */
		3631	r100_mc_init(rdev);
1221	serge	3632	/* Fence driver */
2005	serge	3633	r = radeon_fence_driver_init(rdev);
		3634	if (r)
		3635	return r;
		3636	r = radeon_irq_kms_init(rdev);
		3637	if (r)
		3638	return r;
1221	serge	3639	/* Memory manager */
1321	serge	3640	r = radeon_bo_init(rdev);
1221	serge	3641	if (r)
		3642	return r;
		3643	if (rdev->flags & RADEON_IS_PCI) {
		3644	r = r100_pci_gart_init(rdev);
		3645	if (r)
		3646	return r;
		3647	}
		3648	r100_set_safe_registers(rdev);
		3649	rdev->accel_working = true;
		3650	r = r100_startup(rdev);
		3651	if (r) {
		3652	/* Somethings want wront with the accel init stop accel */
		3653	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		3654	if (rdev->flags & RADEON_IS_PCI)
		3655	r100_pci_gart_fini(rdev);
		3656	rdev->accel_working = false;
		3657	}
		3658	return 0;
		3659	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 2005