WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1117	serge	31	#include "radeon_drm.h"
		32	#include "radeon_reg.h"
		33	#include "radeon.h"
1179	serge	34	#include "r100d.h"
1221	serge	35	#include "rs100d.h"
		36	#include "rv200d.h"
		37	#include "rv250d.h"
1117	serge	38
1221	serge	39	#include
		40
1179	serge	41	#include "r100_reg_safe.h"
		42	#include "rn50_reg_safe.h"
1221	serge	43
		44	/* Firmware Names */
		45	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		46	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		47	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		48	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		49	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		50	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		51	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		52
		53	MODULE_FIRMWARE(FIRMWARE_R100);
		54	MODULE_FIRMWARE(FIRMWARE_R200);
		55	MODULE_FIRMWARE(FIRMWARE_R300);
		56	MODULE_FIRMWARE(FIRMWARE_R420);
		57	MODULE_FIRMWARE(FIRMWARE_RS690);
		58	MODULE_FIRMWARE(FIRMWARE_RS600);
		59	MODULE_FIRMWARE(FIRMWARE_R520);
		60
		61
1117	serge	62	/* This files gather functions specifics to:
		63	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		64	*/
		65
1321	serge	66	/* hpd for digital panel detect/disconnect */
		67	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		68	{
		69	bool connected = false;
		70
		71	switch (hpd) {
		72	case RADEON_HPD_1:
		73	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		74	connected = true;
		75	break;
		76	case RADEON_HPD_2:
		77	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		78	connected = true;
		79	break;
		80	default:
		81	break;
		82	}
		83	return connected;
		84	}
		85
		86	void r100_hpd_set_polarity(struct radeon_device *rdev,
		87	enum radeon_hpd_id hpd)
		88	{
		89	u32 tmp;
		90	bool connected = r100_hpd_sense(rdev, hpd);
		91
		92	switch (hpd) {
		93	case RADEON_HPD_1:
		94	tmp = RREG32(RADEON_FP_GEN_CNTL);
		95	if (connected)
		96	tmp &= ~RADEON_FP_DETECT_INT_POL;
		97	else
		98	tmp \|= RADEON_FP_DETECT_INT_POL;
		99	WREG32(RADEON_FP_GEN_CNTL, tmp);
		100	break;
		101	case RADEON_HPD_2:
		102	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		103	if (connected)
		104	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		105	else
		106	tmp \|= RADEON_FP2_DETECT_INT_POL;
		107	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		108	break;
		109	default:
		110	break;
		111	}
		112	}
		113
		114	void r100_hpd_init(struct radeon_device *rdev)
		115	{
		116	struct drm_device *dev = rdev->ddev;
		117	struct drm_connector *connector;
		118
		119	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		120	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		121	switch (radeon_connector->hpd.hpd) {
		122	case RADEON_HPD_1:
1403	serge	123	// rdev->irq.hpd[0] = true;
1321	serge	124	break;
		125	case RADEON_HPD_2:
1403	serge	126	// rdev->irq.hpd[1] = true;
1321	serge	127	break;
		128	default:
		129	break;
		130	}
		131	}
1403	serge	132	// if (rdev->irq.installed)
		133	// r100_irq_set(rdev);
1321	serge	134	}
		135
		136	void r100_hpd_fini(struct radeon_device *rdev)
		137	{
		138	struct drm_device *dev = rdev->ddev;
		139	struct drm_connector *connector;
		140
		141	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		142	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		143	switch (radeon_connector->hpd.hpd) {
		144	case RADEON_HPD_1:
1403	serge	145	// rdev->irq.hpd[0] = false;
1321	serge	146	break;
		147	case RADEON_HPD_2:
1403	serge	148	// rdev->irq.hpd[1] = false;
1321	serge	149	break;
		150	default:
		151	break;
		152	}
		153	}
		154	}
		155
1117	serge	156	/*
		157	* PCI GART
		158	*/
		159	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		160	{
		161	/* TODO: can we do somethings here ? */
		162	/* It seems hw only cache one entry so we should discard this
		163	* entry otherwise if first GPU GART read hit this entry it
		164	* could end up in wrong address. */
		165	}
		166
1179	serge	167	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	168	{
		169	int r;
		170
1179	serge	171	if (rdev->gart.table.ram.ptr) {
		172	WARN(1, "R100 PCI GART already initialized.\n");
		173	return 0;
		174	}
1117	serge	175	/* Initialize common gart structure */
		176	r = radeon_gart_init(rdev);
1179	serge	177	if (r)
1117	serge	178	return r;
1268	serge	179	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	180	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		181	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		182	return radeon_gart_table_ram_alloc(rdev);
		183	}
		184
1321	serge	185	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		186	void r100_enable_bm(struct radeon_device *rdev)
		187	{
		188	uint32_t tmp;
		189	/* Enable bus mastering */
		190	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		191	WREG32(RADEON_BUS_CNTL, tmp);
		192	}
		193
1179	serge	194	int r100_pci_gart_enable(struct radeon_device *rdev)
		195	{
		196	uint32_t tmp;
		197
1430	serge	198	radeon_gart_restore(rdev);
1117	serge	199	/* discard memory request outside of configured range */
		200	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		201	WREG32(RADEON_AIC_CNTL, tmp);
		202	/* set address range for PCI address translate */
1430	serge	203	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
		204	WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
1117	serge	205	/* set PCI GART page-table base address */
		206	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		207	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		208	WREG32(RADEON_AIC_CNTL, tmp);
		209	r100_pci_gart_tlb_flush(rdev);
		210	rdev->gart.ready = true;
		211	return 0;
		212	}
		213
		214	void r100_pci_gart_disable(struct radeon_device *rdev)
		215	{
		216	uint32_t tmp;
		217
		218	/* discard memory request outside of configured range */
		219	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		220	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		221	WREG32(RADEON_AIC_LO_ADDR, 0);
		222	WREG32(RADEON_AIC_HI_ADDR, 0);
		223	}
		224
		225	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		226	{
		227	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		228	return -EINVAL;
		229	}
1179	serge	230	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	231	return 0;
		232	}
		233
1179	serge	234	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	235	{
		236	r100_pci_gart_disable(rdev);
1179	serge	237	radeon_gart_table_ram_free(rdev);
		238	radeon_gart_fini(rdev);
1117	serge	239	}
		240
		241
1221	serge	242	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	243	{
1221	serge	244	u32 tmp;
1117	serge	245
1221	serge	246	WREG32(R_000040_GEN_INT_CNTL, 0);
		247	/* Wait and acknowledge irq */
		248	mdelay(1);
		249	tmp = RREG32(R_000044_GEN_INT_STATUS);
		250	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	251	}
		252
1221	serge	253	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	254	{
1221	serge	255	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	256	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		257	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		258	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	259
1221	serge	260	if (irqs) {
		261	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	262	}
1221	serge	263	return irqs & irq_mask;
1117	serge	264	}
		265
		266
1403	serge	267	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		268	{
		269	if (crtc == 0)
		270	return RREG32(RADEON_CRTC_CRNT_FRAME);
		271	else
		272	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		273	}
1117	serge	274
1404	serge	275	/* Who ever call radeon_fence_emit should call ring_lock and ask
		276	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	277	void r100_fence_ring_emit(struct radeon_device *rdev,
		278	struct radeon_fence *fence)
		279	{
1404	serge	280	/* We have to make sure that caches are flushed before
		281	* CPU might read something from VRAM. */
		282	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		283	radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
		284	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		285	radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	286	/* Wait until IDLE & CLEAN */
1430	serge	287	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		288	radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN \| RADEON_WAIT_3D_IDLECLEAN);
1403	serge	289	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		290	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl \|
		291	RADEON_HDP_READ_BUFFER_INVALIDATE);
		292	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		293	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
1117	serge	294	/* Emit fence sequence & fire IRQ */
		295	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		296	radeon_ring_write(rdev, fence->seq);
		297	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		298	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		299	}
		300
1128	serge	301	#if 0
1117	serge	302	/*
		303	* Writeback
		304	*/
		305	int r100_wb_init(struct radeon_device *rdev)
		306	{
		307	int r;
		308
		309	if (rdev->wb.wb_obj == NULL) {
1321	serge	310	r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1117	serge	311	RADEON_GEM_DOMAIN_GTT,
1321	serge	312	&rdev->wb.wb_obj);
1117	serge	313	if (r) {
1321	serge	314	dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
1117	serge	315	return r;
		316	}
1321	serge	317	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		318	if (unlikely(r != 0))
		319	return r;
		320	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1117	serge	321	&rdev->wb.gpu_addr);
		322	if (r) {
1321	serge	323	dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
		324	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	325	return r;
		326	}
1321	serge	327	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		328	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	329	if (r) {
1321	serge	330	dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
1117	serge	331	return r;
		332	}
		333	}
1179	serge	334	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
		335	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		336	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
		337	WREG32(R_000770_SCRATCH_UMSK, 0xff);
1117	serge	338	return 0;
		339	}
		340
1179	serge	341	void r100_wb_disable(struct radeon_device *rdev)
		342	{
		343	WREG32(R_000770_SCRATCH_UMSK, 0);
		344	}
		345
1117	serge	346	void r100_wb_fini(struct radeon_device *rdev)
		347	{
1321	serge	348	int r;
		349
1179	serge	350	r100_wb_disable(rdev);
1117	serge	351	if (rdev->wb.wb_obj) {
1404	serge	352	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		353	if (unlikely(r != 0)) {
		354	dev_err(rdev->dev, "(%d) can't finish WB\n", r);
		355	return;
		356	}
		357	radeon_bo_kunmap(rdev->wb.wb_obj);
		358	radeon_bo_unpin(rdev->wb.wb_obj);
		359	radeon_bo_unreserve(rdev->wb.wb_obj);
		360	radeon_bo_unref(&rdev->wb.wb_obj);
1117	serge	361	rdev->wb.wb = NULL;
		362	rdev->wb.wb_obj = NULL;
		363	}
		364	}
		365
		366	int r100_copy_blit(struct radeon_device *rdev,
		367	uint64_t src_offset,
		368	uint64_t dst_offset,
		369	unsigned num_pages,
		370	struct radeon_fence *fence)
		371	{
		372	uint32_t cur_pages;
		373	uint32_t stride_bytes = PAGE_SIZE;
		374	uint32_t pitch;
		375	uint32_t stride_pixels;
		376	unsigned ndw;
		377	int num_loops;
		378	int r = 0;
		379
		380	/* radeon limited to 16k stride */
		381	stride_bytes &= 0x3fff;
		382	/* radeon pitch is /64 */
		383	pitch = stride_bytes / 64;
		384	stride_pixels = stride_bytes / 4;
		385	num_loops = DIV_ROUND_UP(num_pages, 8191);
		386
		387	/* Ask for enough room for blit + flush + fence */
		388	ndw = 64 + (10 * num_loops);
		389	r = radeon_ring_lock(rdev, ndw);
		390	if (r) {
		391	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		392	return -EINVAL;
		393	}
		394	while (num_pages > 0) {
		395	cur_pages = num_pages;
		396	if (cur_pages > 8191) {
		397	cur_pages = 8191;
		398	}
		399	num_pages -= cur_pages;
		400
		401	/* pages are in Y direction - height
		402	page width in X direction - width */
		403	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		404	radeon_ring_write(rdev,
		405	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		406	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		407	RADEON_GMC_SRC_CLIPPING \|
		408	RADEON_GMC_DST_CLIPPING \|
		409	RADEON_GMC_BRUSH_NONE \|
		410	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		411	RADEON_GMC_SRC_DATATYPE_COLOR \|
		412	RADEON_ROP3_S \|
		413	RADEON_DP_SRC_SOURCE_MEMORY \|
		414	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		415	RADEON_GMC_WR_MSK_DIS);
		416	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		417	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		418	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		419	radeon_ring_write(rdev, 0);
		420	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		421	radeon_ring_write(rdev, num_pages);
		422	radeon_ring_write(rdev, num_pages);
		423	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		424	}
		425	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		426	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		427	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		428	radeon_ring_write(rdev,
		429	RADEON_WAIT_2D_IDLECLEAN \|
		430	RADEON_WAIT_HOST_IDLECLEAN \|
		431	RADEON_WAIT_DMA_GUI_IDLE);
		432	if (fence) {
		433	r = radeon_fence_emit(rdev, fence);
		434	}
		435	radeon_ring_unlock_commit(rdev);
		436	return r;
		437	}
		438
1128	serge	439	#endif
1117	serge	440
1221	serge	441
1179	serge	442	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		443	{
		444	unsigned i;
		445	u32 tmp;
		446
		447	for (i = 0; i < rdev->usec_timeout; i++) {
		448	tmp = RREG32(R_000E40_RBBM_STATUS);
		449	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		450	return 0;
		451	}
		452	udelay(1);
		453	}
		454	return -1;
		455	}
		456
1117	serge	457	void r100_ring_start(struct radeon_device *rdev)
		458	{
		459	int r;
		460
		461	r = radeon_ring_lock(rdev, 2);
		462	if (r) {
		463	return;
		464	}
		465	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		466	radeon_ring_write(rdev,
		467	RADEON_ISYNC_ANY2D_IDLE3D \|
		468	RADEON_ISYNC_ANY3D_IDLE2D \|
		469	RADEON_ISYNC_WAIT_IDLEGUI \|
		470	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		471	radeon_ring_unlock_commit(rdev);
		472	}
		473
1221	serge	474
		475	/* Load the microcode for the CP */
		476	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	477	{
1221	serge	478	struct platform_device *pdev;
		479	const char *fw_name = NULL;
		480	int err;
1117	serge	481
1430	serge	482	DRM_DEBUG("\n");
1117	serge	483
1412	serge	484	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		485	err = IS_ERR(pdev);
		486	if (err) {
		487	printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		488	return -EINVAL;
		489	}
1117	serge	490	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		491	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		492	(rdev->family == CHIP_RS200)) {
		493	DRM_INFO("Loading R100 Microcode\n");
1221	serge	494	fw_name = FIRMWARE_R100;
1117	serge	495	} else if ((rdev->family == CHIP_R200) \|\|
		496	(rdev->family == CHIP_RV250) \|\|
		497	(rdev->family == CHIP_RV280) \|\|
		498	(rdev->family == CHIP_RS300)) {
		499	DRM_INFO("Loading R200 Microcode\n");
1221	serge	500	fw_name = FIRMWARE_R200;
1117	serge	501	} else if ((rdev->family == CHIP_R300) \|\|
		502	(rdev->family == CHIP_R350) \|\|
		503	(rdev->family == CHIP_RV350) \|\|
		504	(rdev->family == CHIP_RV380) \|\|
		505	(rdev->family == CHIP_RS400) \|\|
		506	(rdev->family == CHIP_RS480)) {
		507	DRM_INFO("Loading R300 Microcode\n");
1221	serge	508	fw_name = FIRMWARE_R300;
1117	serge	509	} else if ((rdev->family == CHIP_R420) \|\|
		510	(rdev->family == CHIP_R423) \|\|
		511	(rdev->family == CHIP_RV410)) {
		512	DRM_INFO("Loading R400 Microcode\n");
1221	serge	513	fw_name = FIRMWARE_R420;
1117	serge	514	} else if ((rdev->family == CHIP_RS690) \|\|
		515	(rdev->family == CHIP_RS740)) {
		516	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	517	fw_name = FIRMWARE_RS690;
1117	serge	518	} else if (rdev->family == CHIP_RS600) {
		519	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	520	fw_name = FIRMWARE_RS600;
1117	serge	521	} else if ((rdev->family == CHIP_RV515) \|\|
		522	(rdev->family == CHIP_R520) \|\|
		523	(rdev->family == CHIP_RV530) \|\|
		524	(rdev->family == CHIP_R580) \|\|
		525	(rdev->family == CHIP_RV560) \|\|
		526	(rdev->family == CHIP_RV570)) {
		527	DRM_INFO("Loading R500 Microcode\n");
1221	serge	528	fw_name = FIRMWARE_R520;
1117	serge	529	}
1221	serge	530
1412	serge	531	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		532	platform_device_unregister(pdev);
1221	serge	533	if (err) {
		534	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		535	fw_name);
		536	} else if (rdev->me_fw->size % 8) {
		537	printk(KERN_ERR
		538	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		539	rdev->me_fw->size, fw_name);
		540	err = -EINVAL;
		541	release_firmware(rdev->me_fw);
		542	rdev->me_fw = NULL;
1117	serge	543	}
1221	serge	544	return err;
1117	serge	545	}
		546
1221	serge	547	static void r100_cp_load_microcode(struct radeon_device *rdev)
		548	{
		549	const __be32 *fw_data;
		550	int i, size;
		551
		552	if (r100_gui_wait_for_idle(rdev)) {
		553	printk(KERN_WARNING "Failed to wait GUI idle while "
		554	"programming pipes. Bad things might happen.\n");
		555	}
		556
		557	if (rdev->me_fw) {
		558	size = rdev->me_fw->size / 4;
		559	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		560	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		561	for (i = 0; i < size; i += 2) {
		562	WREG32(RADEON_CP_ME_RAM_DATAH,
		563	be32_to_cpup(&fw_data[i]));
		564	WREG32(RADEON_CP_ME_RAM_DATAL,
		565	be32_to_cpup(&fw_data[i + 1]));
		566	}
		567	}
		568	}
		569
1117	serge	570	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		571	{
		572	unsigned rb_bufsz;
		573	unsigned rb_blksz;
		574	unsigned max_fetch;
		575	unsigned pre_write_timer;
		576	unsigned pre_write_limit;
		577	unsigned indirect2_start;
		578	unsigned indirect1_start;
		579	uint32_t tmp;
		580	int r;
		581
1129	serge	582	if (r100_debugfs_cp_init(rdev)) {
		583	DRM_ERROR("Failed to register debugfs file for CP !\n");
		584	}
1117	serge	585	/* Reset CP */
		586	tmp = RREG32(RADEON_CP_CSQ_STAT);
		587	if ((tmp & (1 << 31))) {
		588	DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
		589	WREG32(RADEON_CP_CSQ_MODE, 0);
		590	WREG32(RADEON_CP_CSQ_CNTL, 0);
		591	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		592	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		593	mdelay(2);
		594	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		595	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		596	mdelay(2);
		597	tmp = RREG32(RADEON_CP_CSQ_STAT);
		598	if ((tmp & (1 << 31))) {
		599	DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
		600	}
		601	} else {
		602	DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
		603	}
1179	serge	604
		605	if (!rdev->me_fw) {
		606	r = r100_cp_init_microcode(rdev);
		607	if (r) {
		608	DRM_ERROR("Failed to load firmware!\n");
		609	return r;
		610	}
		611	}
		612
1117	serge	613	/* Align ring size */
		614	rb_bufsz = drm_order(ring_size / 8);
		615	ring_size = (1 << (rb_bufsz + 1)) * 4;
		616	r100_cp_load_microcode(rdev);
		617	r = radeon_ring_init(rdev, ring_size);
		618	if (r) {
		619	return r;
		620	}
		621	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		622	* the rptr copy in system ram */
		623	rb_blksz = 9;
		624	/* cp will read 128bytes at a time (4 dwords) */
		625	max_fetch = 1;
		626	rdev->cp.align_mask = 16 - 1;
		627	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		628	pre_write_timer = 64;
		629	/* Force CP_RB_WPTR write if written more than one time before the
		630	* delay expire
		631	*/
		632	pre_write_limit = 0;
		633	/* Setup the cp cache like this (cache size is 96 dwords) :
		634	* RING 0 to 15
		635	* INDIRECT1 16 to 79
		636	* INDIRECT2 80 to 95
		637	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		638	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		639	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		640	* Idea being that most of the gpu cmd will be through indirect1 buffer
		641	* so it gets the bigger cache.
		642	*/
		643	indirect2_start = 80;
		644	indirect1_start = 16;
		645	/* cp setup */
		646	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	647	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	648	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
		649	REG_SET(RADEON_MAX_FETCH, max_fetch) \|
		650	RADEON_RB_NO_UPDATE);
1268	serge	651	#ifdef __BIG_ENDIAN
		652	tmp \|= RADEON_BUF_SWAP_32BIT;
		653	#endif
		654	WREG32(RADEON_CP_RB_CNTL, tmp);
		655
1117	serge	656	/* Set ring address */
		657	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		658	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		659	/* Force read & write ptr to 0 */
		660	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		661	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		662	WREG32(RADEON_CP_RB_WPTR, 0);
		663	WREG32(RADEON_CP_RB_CNTL, tmp);
		664	udelay(10);
		665	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		666	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
		667	/* Set cp mode to bus mastering & enable cp*/
		668	WREG32(RADEON_CP_CSQ_MODE,
		669	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		670	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
		671	WREG32(0x718, 0);
		672	WREG32(0x744, 0x00004D4D);
		673	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		674	radeon_ring_start(rdev);
		675	r = radeon_ring_test(rdev);
		676	if (r) {
		677	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		678	return r;
		679	}
		680	rdev->cp.ready = true;
		681	return 0;
		682	}
		683
		684	void r100_cp_fini(struct radeon_device *rdev)
		685	{
1179	serge	686	if (r100_cp_wait_for_idle(rdev)) {
		687	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		688	}
1117	serge	689	/* Disable ring */
1179	serge	690	r100_cp_disable(rdev);
1117	serge	691	radeon_ring_fini(rdev);
		692	DRM_INFO("radeon: cp finalized\n");
		693	}
		694
		695	void r100_cp_disable(struct radeon_device *rdev)
		696	{
		697	/* Disable ring */
		698	rdev->cp.ready = false;
		699	WREG32(RADEON_CP_CSQ_MODE, 0);
		700	WREG32(RADEON_CP_CSQ_CNTL, 0);
		701	if (r100_gui_wait_for_idle(rdev)) {
		702	printk(KERN_WARNING "Failed to wait GUI idle while "
		703	"programming pipes. Bad things might happen.\n");
		704	}
		705	}
		706
		707	int r100_cp_reset(struct radeon_device *rdev)
		708	{
		709	uint32_t tmp;
		710	bool reinit_cp;
		711	int i;
		712
		713	reinit_cp = rdev->cp.ready;
		714	rdev->cp.ready = false;
		715	WREG32(RADEON_CP_CSQ_MODE, 0);
		716	WREG32(RADEON_CP_CSQ_CNTL, 0);
		717	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		718	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		719	udelay(200);
		720	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		721	/* Wait to prevent race in RBBM_STATUS */
		722	mdelay(1);
		723	for (i = 0; i < rdev->usec_timeout; i++) {
		724	tmp = RREG32(RADEON_RBBM_STATUS);
		725	if (!(tmp & (1 << 16))) {
		726	DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
		727	tmp);
		728	if (reinit_cp) {
		729	return r100_cp_init(rdev, rdev->cp.ring_size);
		730	}
		731	return 0;
		732	}
		733	DRM_UDELAY(1);
		734	}
		735	tmp = RREG32(RADEON_RBBM_STATUS);
		736	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
		737	return -1;
		738	}
		739
1179	serge	740	void r100_cp_commit(struct radeon_device *rdev)
		741	{
		742	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		743	(void)RREG32(RADEON_CP_RB_WPTR);
		744	}
		745
		746
1117	serge	747	#if 0
		748	/*
		749	* CS functions
		750	*/
		751	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		752	struct radeon_cs_packet *pkt,
		753	const unsigned *auth, unsigned n,
		754	radeon_packet0_check_t check)
		755	{
		756	unsigned reg;
		757	unsigned i, j, m;
		758	unsigned idx;
		759	int r;
		760
		761	idx = pkt->idx + 1;
		762	reg = pkt->reg;
		763	/* Check that register fall into register range
		764	* determined by the number of entry (n) in the
		765	* safe register bitmap.
		766	*/
		767	if (pkt->one_reg_wr) {
		768	if ((reg >> 7) > n) {
		769	return -EINVAL;
		770	}
		771	} else {
		772	if (((reg + (pkt->count << 2)) >> 7) > n) {
		773	return -EINVAL;
		774	}
		775	}
		776	for (i = 0; i <= pkt->count; i++, idx++) {
		777	j = (reg >> 7);
		778	m = 1 << ((reg >> 2) & 31);
		779	if (auth[j] & m) {
		780	r = check(p, pkt, idx, reg);
		781	if (r) {
		782	return r;
		783	}
		784	}
		785	if (pkt->one_reg_wr) {
		786	if (!(auth[j] & m)) {
		787	break;
		788	}
		789	} else {
		790	reg += 4;
		791	}
		792	}
		793	return 0;
		794	}
		795
		796	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		797	struct radeon_cs_packet *pkt)
		798	{
		799	volatile uint32_t *ib;
		800	unsigned i;
		801	unsigned idx;
		802
		803	ib = p->ib->ptr;
		804	idx = pkt->idx;
		805	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		806	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		807	}
		808	}
		809
		810	/**
		811	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		812	* @parser: parser structure holding parsing context.
		813	* @pkt: where to store packet informations
		814	*
		815	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		816	* if packet is bigger than remaining ib size. or if packets is unknown.
		817	**/
		818	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		819	struct radeon_cs_packet *pkt,
		820	unsigned idx)
		821	{
		822	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	823	uint32_t header;
1117	serge	824
		825	if (idx >= ib_chunk->length_dw) {
		826	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		827	idx, ib_chunk->length_dw);
		828	return -EINVAL;
		829	}
1221	serge	830	header = radeon_get_ib_value(p, idx);
1117	serge	831	pkt->idx = idx;
		832	pkt->type = CP_PACKET_GET_TYPE(header);
		833	pkt->count = CP_PACKET_GET_COUNT(header);
		834	switch (pkt->type) {
		835	case PACKET_TYPE0:
		836	pkt->reg = CP_PACKET0_GET_REG(header);
		837	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		838	break;
		839	case PACKET_TYPE3:
		840	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		841	break;
		842	case PACKET_TYPE2:
		843	pkt->count = -1;
		844	break;
		845	default:
		846	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		847	return -EINVAL;
		848	}
		849	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		850	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		851	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		852	return -EINVAL;
		853	}
		854	return 0;
		855	}
		856
		857	/**
1179	serge	858	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		859	* @parser: parser structure holding parsing context.
		860	*
		861	* Userspace sends a special sequence for VLINE waits.
		862	* PACKET0 - VLINE_START_END + value
		863	* PACKET0 - WAIT_UNTIL +_value
		864	* RELOC (P3) - crtc_id in reloc.
		865	*
		866	* This function parses this and relocates the VLINE START END
		867	* and WAIT UNTIL packets to the correct crtc.
		868	* It also detects a switched off crtc and nulls out the
		869	* wait in that case.
		870	*/
		871	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		872	{
		873	struct drm_mode_object *obj;
		874	struct drm_crtc *crtc;
		875	struct radeon_crtc *radeon_crtc;
		876	struct radeon_cs_packet p3reloc, waitreloc;
		877	int crtc_id;
		878	int r;
		879	uint32_t header, h_idx, reg;
1221	serge	880	volatile uint32_t *ib;
1179	serge	881
1221	serge	882	ib = p->ib->ptr;
1179	serge	883
		884	/* parse the wait until */
		885	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		886	if (r)
		887	return r;
		888
		889	/* check its a wait until and only 1 count */
		890	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		891	waitreloc.count != 0) {
		892	DRM_ERROR("vline wait had illegal wait until segment\n");
		893	r = -EINVAL;
		894	return r;
		895	}
		896
1221	serge	897	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	898	DRM_ERROR("vline wait had illegal wait until\n");
		899	r = -EINVAL;
		900	return r;
		901	}
		902
		903	/* jump over the NOP */
1221	serge	904	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	905	if (r)
		906	return r;
		907
		908	h_idx = p->idx - 2;
1221	serge	909	p->idx += waitreloc.count + 2;
		910	p->idx += p3reloc.count + 2;
1179	serge	911
1221	serge	912	header = radeon_get_ib_value(p, h_idx);
		913	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		914	reg = CP_PACKET0_GET_REG(header);
1179	serge	915	mutex_lock(&p->rdev->ddev->mode_config.mutex);
		916	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		917	if (!obj) {
		918	DRM_ERROR("cannot find crtc %d\n", crtc_id);
		919	r = -EINVAL;
		920	goto out;
		921	}
		922	crtc = obj_to_crtc(obj);
		923	radeon_crtc = to_radeon_crtc(crtc);
		924	crtc_id = radeon_crtc->crtc_id;
		925
		926	if (!crtc->enabled) {
		927	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	928	ib[h_idx + 2] = PACKET2(0);
		929	ib[h_idx + 3] = PACKET2(0);
1179	serge	930	} else if (crtc_id == 1) {
		931	switch (reg) {
		932	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	933	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	934	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		935	break;
		936	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	937	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	938	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		939	break;
		940	default:
		941	DRM_ERROR("unknown crtc reloc\n");
		942	r = -EINVAL;
		943	goto out;
		944	}
1221	serge	945	ib[h_idx] = header;
		946	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	947	}
		948	out:
		949	mutex_unlock(&p->rdev->ddev->mode_config.mutex);
		950	return r;
		951	}
		952
		953	/**
1117	serge	954	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		955	* @parser: parser structure holding parsing context.
		956	* @data: pointer to relocation data
		957	* @offset_start: starting offset
		958	* @offset_mask: offset mask (to align start offset on)
		959	* @reloc: reloc informations
		960	*
		961	* Check next packet is relocation packet3, do bo validation and compute
		962	* GPU offset using the provided start.
		963	**/
		964	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		965	struct radeon_cs_reloc **cs_reloc)
		966	{
		967	struct radeon_cs_chunk *relocs_chunk;
		968	struct radeon_cs_packet p3reloc;
		969	unsigned idx;
		970	int r;
		971
		972	if (p->chunk_relocs_idx == -1) {
		973	DRM_ERROR("No relocation chunk !\n");
		974	return -EINVAL;
		975	}
		976	*cs_reloc = NULL;
		977	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		978	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		979	if (r) {
		980	return r;
		981	}
		982	p->idx += p3reloc.count + 2;
		983	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		984	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		985	p3reloc.idx);
		986	r100_cs_dump_packet(p, &p3reloc);
		987	return -EINVAL;
		988	}
1221	serge	989	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	990	if (idx >= relocs_chunk->length_dw) {
		991	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		992	idx, relocs_chunk->length_dw);
		993	r100_cs_dump_packet(p, &p3reloc);
		994	return -EINVAL;
		995	}
		996	/* FIXME: we assume reloc size is 4 dwords */
		997	*cs_reloc = p->relocs_ptr[(idx / 4)];
		998	return 0;
		999	}
		1000
1179	serge	1001	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1002	{
		1003	int vtx_size;
		1004	vtx_size = 2;
		1005	/* ordered according to bits in spec */
		1006	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1007	vtx_size++;
		1008	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1009	vtx_size += 3;
		1010	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1011	vtx_size++;
		1012	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1013	vtx_size++;
		1014	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1015	vtx_size += 3;
		1016	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1017	vtx_size++;
		1018	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1019	vtx_size++;
		1020	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1021	vtx_size += 2;
		1022	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1023	vtx_size += 2;
		1024	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1025	vtx_size++;
		1026	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1027	vtx_size += 2;
		1028	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1029	vtx_size++;
		1030	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1031	vtx_size += 2;
		1032	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1033	vtx_size++;
		1034	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1035	vtx_size++;
		1036	/* blend weight */
		1037	if (vtx_fmt & (0x7 << 15))
		1038	vtx_size += (vtx_fmt >> 15) & 0x7;
		1039	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1040	vtx_size += 3;
		1041	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1042	vtx_size += 2;
		1043	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1044	vtx_size++;
		1045	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1046	vtx_size++;
		1047	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1048	vtx_size++;
		1049	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1050	vtx_size++;
		1051	return vtx_size;
		1052	}
		1053
1117	serge	1054	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1055	struct radeon_cs_packet *pkt,
		1056	unsigned idx, unsigned reg)
1117	serge	1057	{
		1058	struct radeon_cs_reloc *reloc;
1179	serge	1059	struct r100_cs_track *track;
1117	serge	1060	volatile uint32_t *ib;
		1061	uint32_t tmp;
		1062	int r;
1179	serge	1063	int i, face;
		1064	u32 tile_flags = 0;
1221	serge	1065	u32 idx_value;
1117	serge	1066
		1067	ib = p->ib->ptr;
1179	serge	1068	track = (struct r100_cs_track *)p->track;
		1069
1221	serge	1070	idx_value = radeon_get_ib_value(p, idx);
		1071
1117	serge	1072	switch (reg) {
1179	serge	1073	case RADEON_CRTC_GUI_TRIG_VLINE:
		1074	r = r100_cs_packet_parse_vline(p);
		1075	if (r) {
		1076	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1077	idx, reg);
		1078	r100_cs_dump_packet(p, pkt);
		1079	return r;
		1080	}
		1081	break;
1117	serge	1082	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1083	* range access */
		1084	case RADEON_DST_PITCH_OFFSET:
		1085	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1086	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1087	if (r)
		1088	return r;
		1089	break;
		1090	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1091	r = r100_cs_packet_next_reloc(p, &reloc);
		1092	if (r) {
		1093	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1094	idx, reg);
		1095	r100_cs_dump_packet(p, pkt);
		1096	return r;
		1097	}
1179	serge	1098	track->zb.robj = reloc->robj;
1221	serge	1099	track->zb.offset = idx_value;
		1100	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1101	break;
		1102	case RADEON_RB3D_COLOROFFSET:
1179	serge	1103	r = r100_cs_packet_next_reloc(p, &reloc);
		1104	if (r) {
		1105	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1106	idx, reg);
		1107	r100_cs_dump_packet(p, pkt);
		1108	return r;
		1109	}
		1110	track->cb[0].robj = reloc->robj;
1221	serge	1111	track->cb[0].offset = idx_value;
		1112	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1113	break;
1117	serge	1114	case RADEON_PP_TXOFFSET_0:
		1115	case RADEON_PP_TXOFFSET_1:
		1116	case RADEON_PP_TXOFFSET_2:
1179	serge	1117	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1118	r = r100_cs_packet_next_reloc(p, &reloc);
		1119	if (r) {
		1120	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1121	idx, reg);
		1122	r100_cs_dump_packet(p, pkt);
		1123	return r;
		1124	}
1221	serge	1125	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1126	track->textures[i].robj = reloc->robj;
		1127	break;
		1128	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1129	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1130	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1131	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1132	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1133	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1134	r = r100_cs_packet_next_reloc(p, &reloc);
		1135	if (r) {
		1136	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1137	idx, reg);
		1138	r100_cs_dump_packet(p, pkt);
		1139	return r;
		1140	}
1221	serge	1141	track->textures[0].cube_info[i].offset = idx_value;
		1142	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1143	track->textures[0].cube_info[i].robj = reloc->robj;
		1144	break;
		1145	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1146	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1147	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1148	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1149	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1150	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1151	r = r100_cs_packet_next_reloc(p, &reloc);
		1152	if (r) {
		1153	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1154	idx, reg);
		1155	r100_cs_dump_packet(p, pkt);
		1156	return r;
		1157	}
1221	serge	1158	track->textures[1].cube_info[i].offset = idx_value;
		1159	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1160	track->textures[1].cube_info[i].robj = reloc->robj;
		1161	break;
		1162	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1163	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1164	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1165	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1166	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1167	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1168	r = r100_cs_packet_next_reloc(p, &reloc);
		1169	if (r) {
		1170	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1171	idx, reg);
		1172	r100_cs_dump_packet(p, pkt);
		1173	return r;
		1174	}
1221	serge	1175	track->textures[2].cube_info[i].offset = idx_value;
		1176	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1177	track->textures[2].cube_info[i].robj = reloc->robj;
		1178	break;
		1179	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1180	track->maxy = ((idx_value >> 16) & 0x7FF);
1117	serge	1181	break;
1179	serge	1182	case RADEON_RB3D_COLORPITCH:
		1183	r = r100_cs_packet_next_reloc(p, &reloc);
		1184	if (r) {
		1185	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1186	idx, reg);
		1187	r100_cs_dump_packet(p, pkt);
		1188	return r;
		1189	}
		1190
		1191	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1192	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1193	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1194	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1195
1221	serge	1196	tmp = idx_value & ~(0x7 << 16);
1179	serge	1197	tmp \|= tile_flags;
		1198	ib[idx] = tmp;
		1199
1221	serge	1200	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1179	serge	1201	break;
		1202	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1203	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1179	serge	1204	break;
		1205	case RADEON_RB3D_CNTL:
1221	serge	1206	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1207	case 7:
		1208	case 8:
		1209	case 9:
		1210	case 11:
		1211	case 12:
		1212	track->cb[0].cpp = 1;
		1213	break;
		1214	case 3:
		1215	case 4:
		1216	case 15:
		1217	track->cb[0].cpp = 2;
		1218	break;
		1219	case 6:
		1220	track->cb[0].cpp = 4;
		1221	break;
1117	serge	1222	default:
1179	serge	1223	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1224	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1225	return -EINVAL;
		1226	}
1221	serge	1227	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1179	serge	1228	break;
		1229	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1230	switch (idx_value & 0xf) {
1179	serge	1231	case 0:
		1232	track->zb.cpp = 2;
1117	serge	1233	break;
1179	serge	1234	case 2:
		1235	case 3:
		1236	case 4:
		1237	case 5:
		1238	case 9:
		1239	case 11:
		1240	track->zb.cpp = 4;
		1241	break;
		1242	default:
		1243	break;
1117	serge	1244	}
		1245	break;
1179	serge	1246	case RADEON_RB3D_ZPASS_ADDR:
		1247	r = r100_cs_packet_next_reloc(p, &reloc);
		1248	if (r) {
		1249	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1250	idx, reg);
		1251	r100_cs_dump_packet(p, pkt);
		1252	return r;
		1253	}
1221	serge	1254	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1255	break;
		1256	case RADEON_PP_CNTL:
		1257	{
1221	serge	1258	uint32_t temp = idx_value >> 4;
1179	serge	1259	for (i = 0; i < track->num_texture; i++)
		1260	track->textures[i].enabled = !!(temp & (1 << i));
1117	serge	1261	}
1179	serge	1262	break;
		1263	case RADEON_SE_VF_CNTL:
1221	serge	1264	track->vap_vf_cntl = idx_value;
1179	serge	1265	break;
		1266	case RADEON_SE_VTX_FMT:
1221	serge	1267	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1268	break;
		1269	case RADEON_PP_TEX_SIZE_0:
		1270	case RADEON_PP_TEX_SIZE_1:
		1271	case RADEON_PP_TEX_SIZE_2:
		1272	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1273	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1274	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1179	serge	1275	break;
		1276	case RADEON_PP_TEX_PITCH_0:
		1277	case RADEON_PP_TEX_PITCH_1:
		1278	case RADEON_PP_TEX_PITCH_2:
		1279	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1280	track->textures[i].pitch = idx_value + 32;
1179	serge	1281	break;
		1282	case RADEON_PP_TXFILTER_0:
		1283	case RADEON_PP_TXFILTER_1:
		1284	case RADEON_PP_TXFILTER_2:
		1285	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1286	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1287	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1288	tmp = (idx_value >> 23) & 0x7;
1179	serge	1289	if (tmp == 2 \|\| tmp == 6)
		1290	track->textures[i].roundup_w = false;
1221	serge	1291	tmp = (idx_value >> 27) & 0x7;
1179	serge	1292	if (tmp == 2 \|\| tmp == 6)
		1293	track->textures[i].roundup_h = false;
		1294	break;
		1295	case RADEON_PP_TXFORMAT_0:
		1296	case RADEON_PP_TXFORMAT_1:
		1297	case RADEON_PP_TXFORMAT_2:
		1298	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1299	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1300	track->textures[i].use_pitch = 1;
		1301	} else {
		1302	track->textures[i].use_pitch = 0;
1221	serge	1303	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1304	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1305	}
1221	serge	1306	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1307	track->textures[i].tex_coord_type = 2;
1221	serge	1308	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1309	case RADEON_TXFORMAT_I8:
		1310	case RADEON_TXFORMAT_RGB332:
		1311	case RADEON_TXFORMAT_Y8:
		1312	track->textures[i].cpp = 1;
		1313	break;
		1314	case RADEON_TXFORMAT_AI88:
		1315	case RADEON_TXFORMAT_ARGB1555:
		1316	case RADEON_TXFORMAT_RGB565:
		1317	case RADEON_TXFORMAT_ARGB4444:
		1318	case RADEON_TXFORMAT_VYUY422:
		1319	case RADEON_TXFORMAT_YVYU422:
		1320	case RADEON_TXFORMAT_SHADOW16:
		1321	case RADEON_TXFORMAT_LDUDV655:
		1322	case RADEON_TXFORMAT_DUDV88:
		1323	track->textures[i].cpp = 2;
		1324	break;
		1325	case RADEON_TXFORMAT_ARGB8888:
		1326	case RADEON_TXFORMAT_RGBA8888:
		1327	case RADEON_TXFORMAT_SHADOW32:
		1328	case RADEON_TXFORMAT_LDUDUV8888:
		1329	track->textures[i].cpp = 4;
		1330	break;
1403	serge	1331	case RADEON_TXFORMAT_DXT1:
		1332	track->textures[i].cpp = 1;
		1333	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1334	break;
		1335	case RADEON_TXFORMAT_DXT23:
		1336	case RADEON_TXFORMAT_DXT45:
		1337	track->textures[i].cpp = 1;
		1338	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1339	break;
1179	serge	1340	}
1221	serge	1341	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1342	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1179	serge	1343	break;
		1344	case RADEON_PP_CUBIC_FACES_0:
		1345	case RADEON_PP_CUBIC_FACES_1:
		1346	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1347	tmp = idx_value;
1179	serge	1348	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1349	for (face = 0; face < 4; face++) {
		1350	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1351	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1352	}
		1353	break;
		1354	default:
		1355	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1356	reg, idx);
		1357	return -EINVAL;
1117	serge	1358	}
		1359	return 0;
		1360	}
		1361
		1362	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1363	struct radeon_cs_packet *pkt,
1321	serge	1364	struct radeon_bo *robj)
1117	serge	1365	{
		1366	unsigned idx;
1221	serge	1367	u32 value;
1117	serge	1368	idx = pkt->idx + 1;
1221	serge	1369	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1370	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1371	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1372	"(need %u have %lu) !\n",
1221	serge	1373	value + 1,
1321	serge	1374	radeon_bo_size(robj));
1117	serge	1375	return -EINVAL;
		1376	}
		1377	return 0;
		1378	}
		1379
		1380	static int r100_packet3_check(struct radeon_cs_parser *p,
		1381	struct radeon_cs_packet *pkt)
		1382	{
		1383	struct radeon_cs_reloc *reloc;
1179	serge	1384	struct r100_cs_track *track;
1117	serge	1385	unsigned idx;
		1386	volatile uint32_t *ib;
		1387	int r;
		1388
		1389	ib = p->ib->ptr;
		1390	idx = pkt->idx + 1;
1179	serge	1391	track = (struct r100_cs_track *)p->track;
1117	serge	1392	switch (pkt->opcode) {
		1393	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1394	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1395	if (r)
1117	serge	1396	return r;
		1397	break;
		1398	case PACKET3_INDX_BUFFER:
		1399	r = r100_cs_packet_next_reloc(p, &reloc);
		1400	if (r) {
		1401	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1402	r100_cs_dump_packet(p, pkt);
		1403	return r;
		1404	}
1221	serge	1405	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1406	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1407	if (r) {
		1408	return r;
		1409	}
		1410	break;
		1411	case 0x23:
		1412	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1413	r = r100_cs_packet_next_reloc(p, &reloc);
		1414	if (r) {
		1415	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1416	r100_cs_dump_packet(p, pkt);
		1417	return r;
		1418	}
1221	serge	1419	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1420	track->num_arrays = 1;
1221	serge	1421	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1422
		1423	track->arrays[0].robj = reloc->robj;
		1424	track->arrays[0].esize = track->vtx_size;
		1425
1221	serge	1426	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1427
1221	serge	1428	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1429	track->immd_dwords = pkt->count - 1;
		1430	r = r100_cs_track_check(p->rdev, track);
		1431	if (r)
		1432	return r;
1117	serge	1433	break;
		1434	case PACKET3_3D_DRAW_IMMD:
1221	serge	1435	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1436	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1437	return -EINVAL;
		1438	}
1403	serge	1439	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1440	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1441	track->immd_dwords = pkt->count - 1;
		1442	r = r100_cs_track_check(p->rdev, track);
		1443	if (r)
		1444	return r;
		1445	break;
1117	serge	1446	/* triggers drawing using in-packet vertex data */
		1447	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1448	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1449	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1450	return -EINVAL;
		1451	}
1221	serge	1452	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1453	track->immd_dwords = pkt->count;
		1454	r = r100_cs_track_check(p->rdev, track);
		1455	if (r)
		1456	return r;
		1457	break;
1117	serge	1458	/* triggers drawing using in-packet vertex data */
		1459	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1460	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1461	r = r100_cs_track_check(p->rdev, track);
		1462	if (r)
		1463	return r;
		1464	break;
1117	serge	1465	/* triggers drawing of vertex buffers setup elsewhere */
		1466	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1467	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1468	r = r100_cs_track_check(p->rdev, track);
		1469	if (r)
		1470	return r;
		1471	break;
1117	serge	1472	/* triggers drawing using indices to vertex buffer */
		1473	case PACKET3_3D_DRAW_VBUF:
1221	serge	1474	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1475	r = r100_cs_track_check(p->rdev, track);
		1476	if (r)
		1477	return r;
		1478	break;
1117	serge	1479	/* triggers drawing of vertex buffers setup elsewhere */
		1480	case PACKET3_3D_DRAW_INDX:
1221	serge	1481	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1482	r = r100_cs_track_check(p->rdev, track);
		1483	if (r)
		1484	return r;
		1485	break;
1117	serge	1486	/* triggers drawing using indices to vertex buffer */
		1487	case PACKET3_NOP:
		1488	break;
		1489	default:
		1490	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1491	return -EINVAL;
		1492	}
		1493	return 0;
		1494	}
		1495
		1496	int r100_cs_parse(struct radeon_cs_parser *p)
		1497	{
		1498	struct radeon_cs_packet pkt;
1179	serge	1499	struct r100_cs_track *track;
1117	serge	1500	int r;
		1501
1179	serge	1502	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1503	r100_cs_track_clear(p->rdev, track);
		1504	p->track = track;
1117	serge	1505	do {
		1506	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1507	if (r) {
		1508	return r;
		1509	}
		1510	p->idx += pkt.count + 2;
		1511	switch (pkt.type) {
		1512	case PACKET_TYPE0:
1179	serge	1513	if (p->rdev->family >= CHIP_R200)
		1514	r = r100_cs_parse_packet0(p, &pkt,
		1515	p->rdev->config.r100.reg_safe_bm,
		1516	p->rdev->config.r100.reg_safe_bm_size,
		1517	&r200_packet0_check);
		1518	else
		1519	r = r100_cs_parse_packet0(p, &pkt,
		1520	p->rdev->config.r100.reg_safe_bm,
		1521	p->rdev->config.r100.reg_safe_bm_size,
		1522	&r100_packet0_check);
1117	serge	1523	break;
		1524	case PACKET_TYPE2:
		1525	break;
		1526	case PACKET_TYPE3:
		1527	r = r100_packet3_check(p, &pkt);
		1528	break;
		1529	default:
		1530	DRM_ERROR("Unknown packet type %d !\n",
		1531	pkt.type);
		1532	return -EINVAL;
		1533	}
		1534	if (r) {
		1535	return r;
		1536	}
		1537	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1538	return 0;
		1539	}
		1540
1128	serge	1541	#endif
1117	serge	1542
		1543	/*
		1544	* Global GPU functions
		1545	*/
		1546	void r100_errata(struct radeon_device *rdev)
		1547	{
		1548	rdev->pll_errata = 0;
		1549
		1550	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1551	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1552	}
		1553
		1554	if (rdev->family == CHIP_RV100 \|\|
		1555	rdev->family == CHIP_RS100 \|\|
		1556	rdev->family == CHIP_RS200) {
		1557	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1558	}
		1559	}
		1560
		1561	/* Wait for vertical sync on primary CRTC */
		1562	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1563	{
		1564	uint32_t crtc_gen_cntl, tmp;
		1565	int i;
		1566
		1567	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1568	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1569	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1570	return;
		1571	}
		1572	/* Clear the CRTC_VBLANK_SAVE bit */
		1573	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1574	for (i = 0; i < rdev->usec_timeout; i++) {
		1575	tmp = RREG32(RADEON_CRTC_STATUS);
		1576	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1577	return;
		1578	}
		1579	DRM_UDELAY(1);
		1580	}
		1581	}
		1582
		1583	/* Wait for vertical sync on secondary CRTC */
		1584	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1585	{
		1586	uint32_t crtc2_gen_cntl, tmp;
		1587	int i;
		1588
		1589	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1590	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1591	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1592	return;
		1593
		1594	/* Clear the CRTC_VBLANK_SAVE bit */
		1595	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1596	for (i = 0; i < rdev->usec_timeout; i++) {
		1597	tmp = RREG32(RADEON_CRTC2_STATUS);
		1598	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1599	return;
		1600	}
		1601	DRM_UDELAY(1);
		1602	}
		1603	}
		1604
		1605	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1606	{
		1607	unsigned i;
		1608	uint32_t tmp;
		1609
		1610	for (i = 0; i < rdev->usec_timeout; i++) {
		1611	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1612	if (tmp >= n) {
		1613	return 0;
		1614	}
		1615	DRM_UDELAY(1);
		1616	}
		1617	return -1;
		1618	}
		1619
		1620	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1621	{
		1622	unsigned i;
		1623	uint32_t tmp;
		1624
		1625	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1626	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1627	" Bad things might happen.\n");
		1628	}
		1629	for (i = 0; i < rdev->usec_timeout; i++) {
		1630	tmp = RREG32(RADEON_RBBM_STATUS);
1430	serge	1631	if (!(tmp & RADEON_RBBM_ACTIVE)) {
1117	serge	1632	return 0;
		1633	}
		1634	DRM_UDELAY(1);
		1635	}
		1636	return -1;
		1637	}
		1638
		1639	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1640	{
		1641	unsigned i;
		1642	uint32_t tmp;
		1643
		1644	for (i = 0; i < rdev->usec_timeout; i++) {
		1645	/* read MC_STATUS */
1430	serge	1646	tmp = RREG32(RADEON_MC_STATUS);
		1647	if (tmp & RADEON_MC_IDLE) {
1117	serge	1648	return 0;
		1649	}
		1650	DRM_UDELAY(1);
		1651	}
		1652	return -1;
		1653	}
		1654
		1655	void r100_gpu_init(struct radeon_device *rdev)
		1656	{
		1657	/* TODO: anythings to do here ? pipes ? */
		1658	r100_hdp_reset(rdev);
		1659	}
		1660
		1661	void r100_hdp_reset(struct radeon_device *rdev)
		1662	{
		1663	uint32_t tmp;
		1664
		1665	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		1666	tmp \|= (7 << 28);
		1667	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		1668	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1669	udelay(200);
		1670	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1671	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		1672	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1673	}
		1674
		1675	int r100_rb2d_reset(struct radeon_device *rdev)
		1676	{
		1677	uint32_t tmp;
		1678	int i;
		1679
		1680	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
		1681	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		1682	udelay(200);
		1683	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1684	/* Wait to prevent race in RBBM_STATUS */
		1685	mdelay(1);
		1686	for (i = 0; i < rdev->usec_timeout; i++) {
		1687	tmp = RREG32(RADEON_RBBM_STATUS);
		1688	if (!(tmp & (1 << 26))) {
		1689	DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
		1690	tmp);
		1691	return 0;
		1692	}
		1693	DRM_UDELAY(1);
		1694	}
		1695	tmp = RREG32(RADEON_RBBM_STATUS);
		1696	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
		1697	return -1;
		1698	}
		1699
		1700	int r100_gpu_reset(struct radeon_device *rdev)
		1701	{
		1702	uint32_t status;
		1703
		1704	/* reset order likely matter */
		1705	status = RREG32(RADEON_RBBM_STATUS);
		1706	/* reset HDP */
		1707	r100_hdp_reset(rdev);
		1708	/* reset rb2d */
		1709	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		1710	r100_rb2d_reset(rdev);
		1711	}
		1712	/* TODO: reset 3D engine */
		1713	/* reset CP */
		1714	status = RREG32(RADEON_RBBM_STATUS);
		1715	if (status & (1 << 16)) {
		1716	r100_cp_reset(rdev);
		1717	}
		1718	/* Check if GPU is idle */
		1719	status = RREG32(RADEON_RBBM_STATUS);
1430	serge	1720	if (status & RADEON_RBBM_ACTIVE) {
1117	serge	1721	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		1722	return -1;
		1723	}
		1724	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		1725	return 0;
		1726	}
		1727
1321	serge	1728	void r100_set_common_regs(struct radeon_device *rdev)
		1729	{
1430	serge	1730	struct drm_device *dev = rdev->ddev;
		1731	bool force_dac2 = false;
		1732
1321	serge	1733	/* set these so they don't interfere with anything */
		1734	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		1735	WREG32(RADEON_SUBPIC_CNTL, 0);
		1736	WREG32(RADEON_VIPH_CONTROL, 0);
		1737	WREG32(RADEON_I2C_CNTL_1, 0);
		1738	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		1739	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		1740	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1430	serge	1741
		1742	/* always set up dac2 on rn50 and some rv100 as lots
		1743	* of servers seem to wire it up to a VGA port but
		1744	* don't report it in the bios connector
		1745	* table.
		1746	*/
		1747	switch (dev->pdev->device) {
		1748	/* RN50 */
		1749	case 0x515e:
		1750	case 0x5969:
		1751	force_dac2 = true;
		1752	break;
		1753	/* RV100*/
		1754	case 0x5159:
		1755	case 0x515a:
		1756	/* DELL triple head servers */
		1757	if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
		1758	((dev->pdev->subsystem_device == 0x016c) \|\|
		1759	(dev->pdev->subsystem_device == 0x016d) \|\|
		1760	(dev->pdev->subsystem_device == 0x016e) \|\|
		1761	(dev->pdev->subsystem_device == 0x016f) \|\|
		1762	(dev->pdev->subsystem_device == 0x0170) \|\|
		1763	(dev->pdev->subsystem_device == 0x017d) \|\|
		1764	(dev->pdev->subsystem_device == 0x017e) \|\|
		1765	(dev->pdev->subsystem_device == 0x0183) \|\|
		1766	(dev->pdev->subsystem_device == 0x018a) \|\|
		1767	(dev->pdev->subsystem_device == 0x019a)))
		1768	force_dac2 = true;
		1769	break;
		1770	}
		1771
		1772	if (force_dac2) {
		1773	u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1774	u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1775	u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		1776
		1777	/* For CRT on DAC2, don't turn it on if BIOS didn't
		1778	enable it, even it's detected.
		1779	*/
		1780
		1781	/* force it to crtc0 */
		1782	dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
		1783	dac2_cntl \|= RADEON_DAC2_DAC2_CLK_SEL;
		1784	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1785
		1786	/* set up the TV DAC */
		1787	tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL \|
		1788	RADEON_TV_DAC_STD_MASK \|
		1789	RADEON_TV_DAC_RDACPD \|
		1790	RADEON_TV_DAC_GDACPD \|
		1791	RADEON_TV_DAC_BDACPD \|
		1792	RADEON_TV_DAC_BGADJ_MASK \|
		1793	RADEON_TV_DAC_DACADJ_MASK);
		1794	tv_dac_cntl \|= (RADEON_TV_DAC_NBLANK \|
		1795	RADEON_TV_DAC_NHOLD \|
		1796	RADEON_TV_DAC_STD_PS2 \|
		1797	(0x58 << 16));
		1798
		1799	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1800	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1801	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1802	}
1321	serge	1803	}
1117	serge	1804
		1805	/*
		1806	* VRAM info
		1807	*/
		1808	static void r100_vram_get_type(struct radeon_device *rdev)
		1809	{
		1810	uint32_t tmp;
		1811
		1812	rdev->mc.vram_is_ddr = false;
		1813	if (rdev->flags & RADEON_IS_IGP)
		1814	rdev->mc.vram_is_ddr = true;
		1815	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1816	rdev->mc.vram_is_ddr = true;
		1817	if ((rdev->family == CHIP_RV100) \|\|
		1818	(rdev->family == CHIP_RS100) \|\|
		1819	(rdev->family == CHIP_RS200)) {
		1820	tmp = RREG32(RADEON_MEM_CNTL);
		1821	if (tmp & RV100_HALF_MODE) {
		1822	rdev->mc.vram_width = 32;
		1823	} else {
		1824	rdev->mc.vram_width = 64;
		1825	}
		1826	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1827	rdev->mc.vram_width /= 4;
		1828	rdev->mc.vram_is_ddr = true;
		1829	}
		1830	} else if (rdev->family <= CHIP_RV280) {
		1831	tmp = RREG32(RADEON_MEM_CNTL);
		1832	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1833	rdev->mc.vram_width = 128;
		1834	} else {
		1835	rdev->mc.vram_width = 64;
		1836	}
		1837	} else {
		1838	/* newer IGPs */
		1839	rdev->mc.vram_width = 128;
		1840	}
		1841	}
		1842
1179	serge	1843	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1844	{
1179	serge	1845	u32 aper_size;
		1846	u8 byte;
1117	serge	1847
1179	serge	1848	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1849
		1850	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1851	* that is has the 2nd generation multifunction PCI interface
		1852	*/
		1853	if (rdev->family == CHIP_RV280 \|\|
		1854	rdev->family >= CHIP_RV350) {
		1855	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		1856	~RADEON_HDP_APER_CNTL);
		1857	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		1858	return aper_size * 2;
		1859	}
		1860
		1861	/* Older cards have all sorts of funny issues to deal with. First
		1862	* check if it's a multifunction card by reading the PCI config
		1863	* header type... Limit those to one aperture size
		1864	*/
		1865	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		1866	// if (byte & 0x80) {
		1867	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		1868	// DRM_INFO("Limiting VRAM to one aperture\n");
		1869	// return aper_size;
		1870	// }
		1871
		1872	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		1873	* have set it up. We don't write this as it's broken on some ASICs but
		1874	* we expect the BIOS to have done the right thing (might be too optimistic...)
		1875	*/
		1876	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		1877	return aper_size * 2;
		1878	return aper_size;
		1879	}
		1880
		1881	void r100_vram_init_sizes(struct radeon_device *rdev)
		1882	{
		1883	u64 config_aper_size;
		1884
1430	serge	1885	/* work out accessible VRAM */
		1886	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		1887	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
		1888	rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
		1889	/* FIXME we don't use the second aperture yet when we could use it */
		1890	if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
		1891	rdev->mc.visible_vram_size = rdev->mc.aper_size;
1179	serge	1892	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1117	serge	1893	if (rdev->flags & RADEON_IS_IGP) {
		1894	uint32_t tom;
		1895	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1896	tom = RREG32(RADEON_NB_TOM);
1179	serge	1897	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1898	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		1899	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1900	} else {
1179	serge	1901	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	1902	/* Some production boards of m6 will report 0
		1903	* if it's 8 MB
		1904	*/
1179	serge	1905	if (rdev->mc.real_vram_size == 0) {
		1906	rdev->mc.real_vram_size = 8192 * 1024;
		1907	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	1908	}
1179	serge	1909	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1430	serge	1910	* Novell bug 204882 + along with lots of ubuntu ones
		1911	*/
1179	serge	1912	if (config_aper_size > rdev->mc.real_vram_size)
		1913	rdev->mc.mc_vram_size = config_aper_size;
		1914	else
		1915	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1916	}
1430	serge	1917	/* FIXME remove this once we support unmappable VRAM */
		1918	if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1179	serge	1919	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		1920	rdev->mc.real_vram_size = rdev->mc.aper_size;
1430	serge	1921	}
1117	serge	1922	}
		1923
1179	serge	1924	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		1925	{
		1926	uint32_t temp;
		1927
		1928	temp = RREG32(RADEON_CONFIG_CNTL);
		1929	if (state == false) {
		1930	temp &= ~(1<<8);
		1931	temp \|= (1<<9);
		1932	} else {
		1933	temp &= ~(1<<9);
		1934	}
		1935	WREG32(RADEON_CONFIG_CNTL, temp);
		1936	}
		1937
1430	serge	1938	void r100_mc_init(struct radeon_device *rdev)
1179	serge	1939	{
1430	serge	1940	u64 base;
		1941
1179	serge	1942	r100_vram_get_type(rdev);
		1943	r100_vram_init_sizes(rdev);
1430	serge	1944	base = rdev->mc.aper_base;
		1945	if (rdev->flags & RADEON_IS_IGP)
		1946	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
		1947	radeon_vram_location(rdev, &rdev->mc, base);
		1948	if (!(rdev->flags & RADEON_IS_AGP))
		1949	radeon_gtt_location(rdev, &rdev->mc);
1179	serge	1950	}
		1951
		1952
1117	serge	1953	/*
		1954	* Indirect registers accessor
		1955	*/
		1956	void r100_pll_errata_after_index(struct radeon_device *rdev)
		1957	{
		1958	if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
		1959	return;
		1960	}
		1961	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		1962	(void)RREG32(RADEON_CRTC_GEN_CNTL);
		1963	}
		1964
		1965	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		1966	{
		1967	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		1968	* or the chip could hang on a subsequent access
		1969	*/
		1970	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		1971	udelay(5000);
		1972	}
		1973
		1974	/* This function is required to workaround a hardware bug in some (all?)
		1975	* revisions of the R300. This workaround should be called after every
		1976	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1977	* may not be correct.
		1978	*/
		1979	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		1980	uint32_t save, tmp;
		1981
		1982	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		1983	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		1984	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		1985	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		1986	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		1987	}
		1988	}
		1989
		1990	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		1991	{
		1992	uint32_t data;
		1993
		1994	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		1995	r100_pll_errata_after_index(rdev);
		1996	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		1997	r100_pll_errata_after_data(rdev);
		1998	return data;
		1999	}
		2000
		2001	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2002	{
		2003	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		2004	r100_pll_errata_after_index(rdev);
		2005	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		2006	r100_pll_errata_after_data(rdev);
		2007	}
		2008
1221	serge	2009	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	2010	{
1179	serge	2011	if (ASIC_IS_RN50(rdev)) {
		2012	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		2013	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		2014	} else if (rdev->family < CHIP_R200) {
		2015	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		2016	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		2017	} else {
1221	serge	2018	r200_set_safe_registers(rdev);
1117	serge	2019	}
		2020	}
		2021
1129	serge	2022	/*
		2023	* Debugfs info
		2024	*/
		2025	#if defined(CONFIG_DEBUG_FS)
		2026	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		2027	{
		2028	struct drm_info_node node = (struct drm_info_node ) m->private;
		2029	struct drm_device *dev = node->minor->dev;
		2030	struct radeon_device *rdev = dev->dev_private;
		2031	uint32_t reg, value;
		2032	unsigned i;
		2033
		2034	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		2035	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		2036	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2037	for (i = 0; i < 64; i++) {
		2038	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		2039	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		2040	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		2041	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		2042	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		2043	}
		2044	return 0;
		2045	}
		2046
		2047	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		2048	{
		2049	struct drm_info_node node = (struct drm_info_node ) m->private;
		2050	struct drm_device *dev = node->minor->dev;
		2051	struct radeon_device *rdev = dev->dev_private;
		2052	uint32_t rdp, wdp;
		2053	unsigned count, i, j;
		2054
		2055	radeon_ring_free_size(rdev);
		2056	rdp = RREG32(RADEON_CP_RB_RPTR);
		2057	wdp = RREG32(RADEON_CP_RB_WPTR);
		2058	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		2059	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2060	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2061	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		2062	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		2063	seq_printf(m, "%u dwords in ring\n", count);
		2064	for (j = 0; j <= count; j++) {
		2065	i = (rdp + j) & rdev->cp.ptr_mask;
		2066	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		2067	}
		2068	return 0;
		2069	}
		2070
		2071
		2072	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2073	{
		2074	struct drm_info_node node = (struct drm_info_node ) m->private;
		2075	struct drm_device *dev = node->minor->dev;
		2076	struct radeon_device *rdev = dev->dev_private;
		2077	uint32_t csq_stat, csq2_stat, tmp;
		2078	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2079	unsigned i;
		2080
		2081	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2082	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2083	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2084	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2085	r_rptr = (csq_stat >> 0) & 0x3ff;
		2086	r_wptr = (csq_stat >> 10) & 0x3ff;
		2087	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2088	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2089	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2090	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2091	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2092	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2093	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2094	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2095	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2096	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2097	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2098	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2099	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2100	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2101	seq_printf(m, "Ring fifo:\n");
		2102	for (i = 0; i < 256; i++) {
		2103	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2104	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2105	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2106	}
		2107	seq_printf(m, "Indirect1 fifo:\n");
		2108	for (i = 256; i <= 512; i++) {
		2109	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2110	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2111	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2112	}
		2113	seq_printf(m, "Indirect2 fifo:\n");
		2114	for (i = 640; i < ib1_wptr; i++) {
		2115	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2116	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2117	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2118	}
		2119	return 0;
		2120	}
		2121
		2122	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2123	{
		2124	struct drm_info_node node = (struct drm_info_node ) m->private;
		2125	struct drm_device *dev = node->minor->dev;
		2126	struct radeon_device *rdev = dev->dev_private;
		2127	uint32_t tmp;
		2128
		2129	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2130	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2131	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2132	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2133	tmp = RREG32(RADEON_BUS_CNTL);
		2134	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2135	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2136	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2137	tmp = RREG32(RADEON_AGP_BASE);
		2138	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2139	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2140	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2141	tmp = RREG32(0x01D0);
		2142	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2143	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2144	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2145	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2146	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2147	tmp = RREG32(0x01E4);
		2148	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2149	return 0;
		2150	}
		2151
		2152	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2153	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2154	};
		2155
		2156	static struct drm_info_list r100_debugfs_cp_list[] = {
		2157	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2158	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2159	};
		2160
		2161	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2162	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2163	};
		2164	#endif
		2165
		2166	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2167	{
		2168	#if defined(CONFIG_DEBUG_FS)
		2169	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2170	#else
		2171	return 0;
		2172	#endif
		2173	}
		2174
		2175	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2176	{
		2177	#if defined(CONFIG_DEBUG_FS)
		2178	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2179	#else
		2180	return 0;
		2181	#endif
		2182	}
		2183
		2184	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2185	{
		2186	#if defined(CONFIG_DEBUG_FS)
		2187	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2188	#else
		2189	return 0;
		2190	#endif
		2191	}
1179	serge	2192
		2193	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2194	uint32_t tiling_flags, uint32_t pitch,
		2195	uint32_t offset, uint32_t obj_size)
		2196	{
		2197	int surf_index = reg * 16;
		2198	int flags = 0;
		2199
		2200	/* r100/r200 divide by 16 */
		2201	if (rdev->family < CHIP_R300)
		2202	flags = pitch / 16;
		2203	else
		2204	flags = pitch / 8;
		2205
		2206	if (rdev->family <= CHIP_RS200) {
		2207	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2208	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2209	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2210	if (tiling_flags & RADEON_TILING_MACRO)
		2211	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2212	} else if (rdev->family <= CHIP_RV280) {
		2213	if (tiling_flags & (RADEON_TILING_MACRO))
		2214	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2215	if (tiling_flags & RADEON_TILING_MICRO)
		2216	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2217	} else {
		2218	if (tiling_flags & RADEON_TILING_MACRO)
		2219	flags \|= R300_SURF_TILE_MACRO;
		2220	if (tiling_flags & RADEON_TILING_MICRO)
		2221	flags \|= R300_SURF_TILE_MICRO;
		2222	}
		2223
		2224	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2225	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2226	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2227	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2228
		2229	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
		2230	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2231	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2232	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2233	return 0;
		2234	}
		2235
		2236	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2237	{
		2238	int surf_index = reg * 16;
		2239	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2240	}
		2241
		2242	void r100_bandwidth_update(struct radeon_device *rdev)
		2243	{
		2244	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2245	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2246	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2247	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2248	fixed20_12 memtcas_ff[8] = {
		2249	fixed_init(1),
		2250	fixed_init(2),
		2251	fixed_init(3),
		2252	fixed_init(0),
		2253	fixed_init_half(1),
		2254	fixed_init_half(2),
		2255	fixed_init(0),
		2256	};
		2257	fixed20_12 memtcas_rs480_ff[8] = {
		2258	fixed_init(0),
		2259	fixed_init(1),
		2260	fixed_init(2),
		2261	fixed_init(3),
		2262	fixed_init(0),
		2263	fixed_init_half(1),
		2264	fixed_init_half(2),
		2265	fixed_init_half(3),
		2266	};
		2267	fixed20_12 memtcas2_ff[8] = {
		2268	fixed_init(0),
		2269	fixed_init(1),
		2270	fixed_init(2),
		2271	fixed_init(3),
		2272	fixed_init(4),
		2273	fixed_init(5),
		2274	fixed_init(6),
		2275	fixed_init(7),
		2276	};
		2277	fixed20_12 memtrbs[8] = {
		2278	fixed_init(1),
		2279	fixed_init_half(1),
		2280	fixed_init(2),
		2281	fixed_init_half(2),
		2282	fixed_init(3),
		2283	fixed_init_half(3),
		2284	fixed_init(4),
		2285	fixed_init_half(4)
		2286	};
		2287	fixed20_12 memtrbs_r4xx[8] = {
		2288	fixed_init(4),
		2289	fixed_init(5),
		2290	fixed_init(6),
		2291	fixed_init(7),
		2292	fixed_init(8),
		2293	fixed_init(9),
		2294	fixed_init(10),
		2295	fixed_init(11)
		2296	};
		2297	fixed20_12 min_mem_eff;
		2298	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2299	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2300	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2301	disp_drain_rate2, read_return_rate;
		2302	fixed20_12 time_disp1_drop_priority;
		2303	int c;
		2304	int cur_size = 16; /* in octawords */
		2305	int critical_point = 0, critical_point2;
		2306	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2307	int stop_req, max_stop_req;
		2308	struct drm_display_mode *mode1 = NULL;
		2309	struct drm_display_mode *mode2 = NULL;
		2310	uint32_t pixel_bytes1 = 0;
		2311	uint32_t pixel_bytes2 = 0;
		2312
		2313	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2314	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2315	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2316	}
1221	serge	2317	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2318	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2319	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2320	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2321	}
1221	serge	2322	}
1179	serge	2323
		2324	min_mem_eff.full = rfixed_const_8(0);
		2325	/* get modes */
		2326	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2327	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2328	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2329	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2330	/* check crtc enables */
		2331	if (mode2)
		2332	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2333	if (mode1)
		2334	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2335	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2336	}
		2337
		2338	/*
		2339	* determine is there is enough bw for current mode
		2340	*/
		2341	mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
		2342	temp_ff.full = rfixed_const(100);
		2343	mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
		2344	sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
		2345	sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
		2346
		2347	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
		2348	temp_ff.full = rfixed_const(temp);
		2349	mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
		2350
		2351	pix_clk.full = 0;
		2352	pix_clk2.full = 0;
		2353	peak_disp_bw.full = 0;
		2354	if (mode1) {
		2355	temp_ff.full = rfixed_const(1000);
		2356	pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
		2357	pix_clk.full = rfixed_div(pix_clk, temp_ff);
		2358	temp_ff.full = rfixed_const(pixel_bytes1);
		2359	peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
		2360	}
		2361	if (mode2) {
		2362	temp_ff.full = rfixed_const(1000);
		2363	pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
		2364	pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
		2365	temp_ff.full = rfixed_const(pixel_bytes2);
		2366	peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
		2367	}
		2368
		2369	mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
		2370	if (peak_disp_bw.full >= mem_bw.full) {
		2371	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2372	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2373	}
		2374
		2375	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2376	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2377	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2378	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2379	mem_trp = ((temp & 0x3)) + 1;
		2380	mem_tras = ((temp & 0x70) >> 4) + 1;
		2381	} else if (rdev->family == CHIP_R300 \|\|
		2382	rdev->family == CHIP_R350) { /* r300, r350 */
		2383	mem_trcd = (temp & 0x7) + 1;
		2384	mem_trp = ((temp >> 8) & 0x7) + 1;
		2385	mem_tras = ((temp >> 11) & 0xf) + 4;
		2386	} else if (rdev->family == CHIP_RV350 \|\|
		2387	rdev->family <= CHIP_RV380) {
		2388	/* rv3x0 */
		2389	mem_trcd = (temp & 0x7) + 3;
		2390	mem_trp = ((temp >> 8) & 0x7) + 3;
		2391	mem_tras = ((temp >> 11) & 0xf) + 6;
		2392	} else if (rdev->family == CHIP_R420 \|\|
		2393	rdev->family == CHIP_R423 \|\|
		2394	rdev->family == CHIP_RV410) {
		2395	/* r4xx */
		2396	mem_trcd = (temp & 0xf) + 3;
		2397	if (mem_trcd > 15)
		2398	mem_trcd = 15;
		2399	mem_trp = ((temp >> 8) & 0xf) + 3;
		2400	if (mem_trp > 15)
		2401	mem_trp = 15;
		2402	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2403	if (mem_tras > 31)
		2404	mem_tras = 31;
		2405	} else { /* RV200, R200 */
		2406	mem_trcd = (temp & 0x7) + 1;
		2407	mem_trp = ((temp >> 8) & 0x7) + 1;
		2408	mem_tras = ((temp >> 12) & 0xf) + 4;
		2409	}
		2410	/* convert to FF */
		2411	trcd_ff.full = rfixed_const(mem_trcd);
		2412	trp_ff.full = rfixed_const(mem_trp);
		2413	tras_ff.full = rfixed_const(mem_tras);
		2414
		2415	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2416	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2417	data = (temp & (7 << 20)) >> 20;
		2418	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2419	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2420	tcas_ff = memtcas_rs480_ff[data];
		2421	else
		2422	tcas_ff = memtcas_ff[data];
		2423	} else
		2424	tcas_ff = memtcas2_ff[data];
		2425
		2426	if (rdev->family == CHIP_RS400 \|\|
		2427	rdev->family == CHIP_RS480) {
		2428	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2429	data = (temp >> 23) & 0x7;
		2430	if (data < 5)
		2431	tcas_ff.full += rfixed_const(data);
		2432	}
		2433
		2434	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2435	/* on the R300, Tcas is included in Trbs.
		2436	*/
		2437	temp = RREG32(RADEON_MEM_CNTL);
		2438	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2439	if (data == 1) {
		2440	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2441	temp = RREG32(R300_MC_IND_INDEX);
		2442	temp &= ~R300_MC_IND_ADDR_MASK;
		2443	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2444	WREG32(R300_MC_IND_INDEX, temp);
		2445	temp = RREG32(R300_MC_IND_DATA);
		2446	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2447	} else {
		2448	temp = RREG32(R300_MC_READ_CNTL_AB);
		2449	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2450	}
		2451	} else {
		2452	temp = RREG32(R300_MC_READ_CNTL_AB);
		2453	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2454	}
		2455	if (rdev->family == CHIP_RV410 \|\|
		2456	rdev->family == CHIP_R420 \|\|
		2457	rdev->family == CHIP_R423)
		2458	trbs_ff = memtrbs_r4xx[data];
		2459	else
		2460	trbs_ff = memtrbs[data];
		2461	tcas_ff.full += trbs_ff.full;
		2462	}
		2463
		2464	sclk_eff_ff.full = sclk_ff.full;
		2465
		2466	if (rdev->flags & RADEON_IS_AGP) {
		2467	fixed20_12 agpmode_ff;
		2468	agpmode_ff.full = rfixed_const(radeon_agpmode);
		2469	temp_ff.full = rfixed_const_666(16);
		2470	sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
		2471	}
		2472	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2473
		2474	if (ASIC_IS_R300(rdev)) {
		2475	sclk_delay_ff.full = rfixed_const(250);
		2476	} else {
		2477	if ((rdev->family == CHIP_RV100) \|\|
		2478	rdev->flags & RADEON_IS_IGP) {
		2479	if (rdev->mc.vram_is_ddr)
		2480	sclk_delay_ff.full = rfixed_const(41);
		2481	else
		2482	sclk_delay_ff.full = rfixed_const(33);
		2483	} else {
		2484	if (rdev->mc.vram_width == 128)
		2485	sclk_delay_ff.full = rfixed_const(57);
		2486	else
		2487	sclk_delay_ff.full = rfixed_const(41);
		2488	}
		2489	}
		2490
		2491	mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
		2492
		2493	if (rdev->mc.vram_is_ddr) {
		2494	if (rdev->mc.vram_width == 32) {
		2495	k1.full = rfixed_const(40);
		2496	c = 3;
		2497	} else {
		2498	k1.full = rfixed_const(20);
		2499	c = 1;
		2500	}
		2501	} else {
		2502	k1.full = rfixed_const(40);
		2503	c = 3;
		2504	}
		2505
		2506	temp_ff.full = rfixed_const(2);
		2507	mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
		2508	temp_ff.full = rfixed_const(c);
		2509	mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
		2510	temp_ff.full = rfixed_const(4);
		2511	mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
		2512	mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
		2513	mc_latency_mclk.full += k1.full;
		2514
		2515	mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
		2516	mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
		2517
		2518	/*
		2519	HW cursor time assuming worst case of full size colour cursor.
		2520	*/
		2521	temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
		2522	temp_ff.full += trcd_ff.full;
		2523	if (temp_ff.full < tras_ff.full)
		2524	temp_ff.full = tras_ff.full;
		2525	cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
		2526
		2527	temp_ff.full = rfixed_const(cur_size);
		2528	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
		2529	/*
		2530	Find the total latency for the display data.
		2531	*/
1268	serge	2532	disp_latency_overhead.full = rfixed_const(8);
1179	serge	2533	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
		2534	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2535	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2536
		2537	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2538	disp_latency.full = mc_latency_mclk.full;
		2539	else
		2540	disp_latency.full = mc_latency_sclk.full;
		2541
		2542	/* setup Max GRPH_STOP_REQ default value */
		2543	if (ASIC_IS_RV100(rdev))
		2544	max_stop_req = 0x5c;
		2545	else
		2546	max_stop_req = 0x7c;
		2547
		2548	if (mode1) {
		2549	/* CRTC1
		2550	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2551	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2552	*/
		2553	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2554
		2555	if (stop_req > max_stop_req)
		2556	stop_req = max_stop_req;
		2557
		2558	/*
		2559	Find the drain rate of the display buffer.
		2560	*/
		2561	temp_ff.full = rfixed_const((16/pixel_bytes1));
		2562	disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
		2563
		2564	/*
		2565	Find the critical point of the display buffer.
		2566	*/
		2567	crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
		2568	crit_point_ff.full += rfixed_const_half(0);
		2569
		2570	critical_point = rfixed_trunc(crit_point_ff);
		2571
		2572	if (rdev->disp_priority == 2) {
		2573	critical_point = 0;
		2574	}
		2575
		2576	/*
		2577	The critical point should never be above max_stop_req-4. Setting
		2578	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2579	*/
		2580	if (max_stop_req - critical_point < 4)
		2581	critical_point = 0;
		2582
		2583	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2584	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2585	critical_point = 0x10;
		2586	}
		2587
		2588	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2589	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2590	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2591	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2592	if ((rdev->family == CHIP_R350) &&
		2593	(stop_req > 0x15)) {
		2594	stop_req -= 0x10;
		2595	}
		2596	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2597	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2598	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2599	RADEON_GRPH_CRITICAL_AT_SOF \|
		2600	RADEON_GRPH_STOP_CNTL);
		2601	/*
		2602	Write the result into the register.
		2603	*/
		2604	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2605	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2606
		2607	#if 0
		2608	if ((rdev->family == CHIP_RS400) \|\|
		2609	(rdev->family == CHIP_RS480)) {
		2610	/* attempt to program RS400 disp regs correctly ??? */
		2611	temp = RREG32(RS400_DISP1_REG_CNTL);
		2612	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2613	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2614	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2615	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2616	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2617	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2618	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2619	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2620	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2621	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2622	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2623	}
		2624	#endif
		2625
		2626	DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
		2627	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2628	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2629	}
		2630
		2631	if (mode2) {
		2632	u32 grph2_cntl;
		2633	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2634
		2635	if (stop_req > max_stop_req)
		2636	stop_req = max_stop_req;
		2637
		2638	/*
		2639	Find the drain rate of the display buffer.
		2640	*/
		2641	temp_ff.full = rfixed_const((16/pixel_bytes2));
		2642	disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
		2643
		2644	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2645	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2646	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2647	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2648	if ((rdev->family == CHIP_R350) &&
		2649	(stop_req > 0x15)) {
		2650	stop_req -= 0x10;
		2651	}
		2652	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2653	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2654	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2655	RADEON_GRPH_CRITICAL_AT_SOF \|
		2656	RADEON_GRPH_STOP_CNTL);
		2657
		2658	if ((rdev->family == CHIP_RS100) \|\|
		2659	(rdev->family == CHIP_RS200))
		2660	critical_point2 = 0;
		2661	else {
		2662	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
		2663	temp_ff.full = rfixed_const(temp);
		2664	temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
		2665	if (sclk_ff.full < temp_ff.full)
		2666	temp_ff.full = sclk_ff.full;
		2667
		2668	read_return_rate.full = temp_ff.full;
		2669
		2670	if (mode1) {
		2671	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
		2672	time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
		2673	} else {
		2674	time_disp1_drop_priority.full = 0;
		2675	}
		2676	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
		2677	crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
		2678	crit_point_ff.full += rfixed_const_half(0);
		2679
		2680	critical_point2 = rfixed_trunc(crit_point_ff);
		2681
		2682	if (rdev->disp_priority == 2) {
		2683	critical_point2 = 0;
		2684	}
		2685
		2686	if (max_stop_req - critical_point2 < 4)
		2687	critical_point2 = 0;
		2688
		2689	}
		2690
		2691	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2692	/* some R300 cards have problem with this set to 0 */
		2693	critical_point2 = 0x10;
		2694	}
		2695
		2696	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2697	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2698
		2699	if ((rdev->family == CHIP_RS400) \|\|
		2700	(rdev->family == CHIP_RS480)) {
		2701	#if 0
		2702	/* attempt to program RS400 disp2 regs correctly ??? */
		2703	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2704	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2705	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2706	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2707	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2708	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2709	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2710	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2711	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2712	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2713	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2714	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2715	#endif
		2716	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2717	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2718	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2719	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2720	}
		2721
		2722	DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
		2723	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2724	}
		2725	}
		2726
		2727
		2728
1412	serge	2729	int r100_ring_test(struct radeon_device *rdev)
		2730	{
		2731	uint32_t scratch;
		2732	uint32_t tmp = 0;
		2733	unsigned i;
		2734	int r;
1179	serge	2735
1412	serge	2736	r = radeon_scratch_get(rdev, &scratch);
		2737	if (r) {
		2738	DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
		2739	return r;
		2740	}
		2741	WREG32(scratch, 0xCAFEDEAD);
		2742	r = radeon_ring_lock(rdev, 2);
		2743	if (r) {
		2744	DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
		2745	radeon_scratch_free(rdev, scratch);
		2746	return r;
		2747	}
		2748	radeon_ring_write(rdev, PACKET0(scratch, 0));
		2749	radeon_ring_write(rdev, 0xDEADBEEF);
		2750	radeon_ring_unlock_commit(rdev);
		2751	for (i = 0; i < rdev->usec_timeout; i++) {
		2752	tmp = RREG32(scratch);
		2753	if (tmp == 0xDEADBEEF) {
		2754	break;
		2755	}
		2756	DRM_UDELAY(1);
		2757	}
		2758	if (i < rdev->usec_timeout) {
		2759	DRM_INFO("ring test succeeded in %d usecs\n", i);
		2760	} else {
		2761	DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
		2762	scratch, tmp);
		2763	r = -EINVAL;
		2764	}
		2765	radeon_scratch_free(rdev, scratch);
		2766	return r;
		2767	}
		2768
1179	serge	2769	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		2770	{
		2771	/* Shutdown CP we shouldn't need to do that but better be safe than
		2772	* sorry
		2773	*/
		2774	rdev->cp.ready = false;
		2775	WREG32(R_000740_CP_CSQ_CNTL, 0);
		2776
		2777	/* Save few CRTC registers */
1221	serge	2778	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	2779	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		2780	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		2781	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		2782	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2783	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		2784	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		2785	}
		2786
		2787	/* Disable VGA aperture access */
1221	serge	2788	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	2789	/* Disable cursor, overlay, crtc */
		2790	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		2791	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		2792	S_000054_CRTC_DISPLAY_DIS(1));
		2793	WREG32(R_000050_CRTC_GEN_CNTL,
		2794	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		2795	S_000050_CRTC_DISP_REQ_EN_B(1));
		2796	WREG32(R_000420_OV0_SCALE_CNTL,
		2797	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		2798	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		2799	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2800	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		2801	S_000360_CUR2_LOCK(1));
		2802	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		2803	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		2804	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		2805	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		2806	WREG32(R_000360_CUR2_OFFSET,
		2807	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		2808	}
		2809	}
		2810
		2811	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		2812	{
		2813	/* Update base address for crtc */
1430	serge	2814	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	2815	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1430	serge	2816	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
1179	serge	2817	}
		2818	/* Restore CRTC registers */
1221	serge	2819	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	2820	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		2821	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		2822	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2823	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		2824	}
		2825	}
		2826
1221	serge	2827	void r100_vga_render_disable(struct radeon_device *rdev)
		2828	{
		2829	u32 tmp;
		2830
		2831	tmp = RREG8(R_0003C2_GENMO_WT);
		2832	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		2833	}
		2834
		2835	static void r100_debugfs(struct radeon_device *rdev)
		2836	{
		2837	int r;
		2838
		2839	r = r100_debugfs_mc_info_init(rdev);
		2840	if (r)
		2841	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		2842	}
		2843
		2844
1179	serge	2845	int drm_order(unsigned long size)
		2846	{
		2847	int order;
		2848	unsigned long tmp;
		2849
		2850	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		2851
		2852	if (size & (size - 1))
		2853	++order;
		2854
		2855	return order;
		2856	}
		2857
1221	serge	2858	static void r100_mc_program(struct radeon_device *rdev)
		2859	{
		2860	struct r100_mc_save save;
		2861
		2862	/* Stops all mc clients */
		2863	r100_mc_stop(rdev, &save);
		2864	if (rdev->flags & RADEON_IS_AGP) {
		2865	WREG32(R_00014C_MC_AGP_LOCATION,
		2866	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		2867	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		2868	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		2869	if (rdev->family > CHIP_RV200)
		2870	WREG32(R_00015C_AGP_BASE_2,
		2871	upper_32_bits(rdev->mc.agp_base) & 0xff);
		2872	} else {
		2873	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		2874	WREG32(R_000170_AGP_BASE, 0);
		2875	if (rdev->family > CHIP_RV200)
		2876	WREG32(R_00015C_AGP_BASE_2, 0);
		2877	}
		2878	/* Wait for mc idle */
		2879	if (r100_mc_wait_for_idle(rdev))
		2880	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		2881	/* Program MC, should be a 32bits limited address space */
		2882	WREG32(R_000148_MC_FB_LOCATION,
		2883	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		2884	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		2885	r100_mc_resume(rdev, &save);
		2886	}
		2887
		2888	void r100_clock_startup(struct radeon_device *rdev)
		2889	{
		2890	u32 tmp;
		2891
		2892	if (radeon_dynclks != -1 && radeon_dynclks)
		2893	radeon_legacy_set_clock_gating(rdev, 1);
		2894	/* We need to force on some of the block */
		2895	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		2896	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		2897	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		2898	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		2899	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		2900	}
		2901
		2902	static int r100_startup(struct radeon_device *rdev)
		2903	{
		2904	int r;
		2905
1321	serge	2906	/* set common regs */
		2907	r100_set_common_regs(rdev);
		2908	/* program mc */
1221	serge	2909	r100_mc_program(rdev);
		2910	/* Resume clock */
		2911	r100_clock_startup(rdev);
		2912	/* Initialize GPU configuration (# pipes, ...) */
		2913	r100_gpu_init(rdev);
		2914	/* Initialize GART (initialize after TTM so we can allocate
		2915	* memory through TTM but finalize after TTM) */
1321	serge	2916	r100_enable_bm(rdev);
1221	serge	2917	if (rdev->flags & RADEON_IS_PCI) {
		2918	r = r100_pci_gart_enable(rdev);
		2919	if (r)
		2920	return r;
		2921	}
		2922	/* Enable IRQ */
		2923	// r100_irq_set(rdev);
1404	serge	2924	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	2925	/* 1M ring buffer */
1412	serge	2926	r = r100_cp_init(rdev, 1024 * 1024);
		2927	if (r) {
		2928	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		2929	return r;
		2930	}
1221	serge	2931	// r = r100_wb_init(rdev);
		2932	// if (r)
		2933	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		2934	// r = r100_ib_init(rdev);
		2935	// if (r) {
		2936	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		2937	// return r;
		2938	// }
		2939	return 0;
		2940	}
		2941
		2942
		2943
		2944	int r100_init(struct radeon_device *rdev)
		2945	{
		2946	int r;
		2947
		2948	/* Register debugfs file specific to this group of asics */
		2949	r100_debugfs(rdev);
		2950	/* Disable VGA */
		2951	r100_vga_render_disable(rdev);
		2952	/* Initialize scratch registers */
		2953	radeon_scratch_init(rdev);
		2954	/* Initialize surface registers */
		2955	radeon_surface_init(rdev);
		2956	/* TODO: disable VGA need to use VGA request */
		2957	/* BIOS*/
		2958	if (!radeon_get_bios(rdev)) {
		2959	if (ASIC_IS_AVIVO(rdev))
		2960	return -EINVAL;
		2961	}
		2962	if (rdev->is_atom_bios) {
		2963	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		2964	return -EINVAL;
		2965	} else {
		2966	r = radeon_combios_init(rdev);
		2967	if (r)
		2968	return r;
		2969	}
		2970	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		2971	if (radeon_gpu_reset(rdev)) {
		2972	dev_warn(rdev->dev,
		2973	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		2974	RREG32(R_000E40_RBBM_STATUS),
		2975	RREG32(R_0007C0_CP_STAT));
		2976	}
		2977	/* check if cards are posted or not */
1321	serge	2978	if (radeon_boot_test_post_card(rdev) == false)
		2979	return -EINVAL;
1221	serge	2980	/* Set asic errata */
		2981	r100_errata(rdev);
		2982	/* Initialize clocks */
		2983	radeon_get_clock_info(rdev->ddev);
1403	serge	2984	/* Initialize power management */
		2985	radeon_pm_init(rdev);
1430	serge	2986	/* initialize AGP */
		2987	if (rdev->flags & RADEON_IS_AGP) {
		2988	r = radeon_agp_init(rdev);
		2989	if (r) {
		2990	radeon_agp_disable(rdev);
		2991	}
		2992	}
		2993	/* initialize VRAM */
		2994	r100_mc_init(rdev);
1221	serge	2995	/* Fence driver */
		2996	// r = radeon_fence_driver_init(rdev);
		2997	// if (r)
		2998	// return r;
		2999	// r = radeon_irq_kms_init(rdev);
		3000	// if (r)
		3001	// return r;
		3002	/* Memory manager */
1321	serge	3003	r = radeon_bo_init(rdev);
1221	serge	3004	if (r)
		3005	return r;
		3006	if (rdev->flags & RADEON_IS_PCI) {
		3007	r = r100_pci_gart_init(rdev);
		3008	if (r)
		3009	return r;
		3010	}
		3011	r100_set_safe_registers(rdev);
		3012	rdev->accel_working = true;
		3013	r = r100_startup(rdev);
		3014	if (r) {
		3015	/* Somethings want wront with the accel init stop accel */
		3016	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		3017	// r100_cp_fini(rdev);
		3018	// r100_wb_fini(rdev);
		3019	// r100_ib_fini(rdev);
		3020	if (rdev->flags & RADEON_IS_PCI)
		3021	r100_pci_gart_fini(rdev);
		3022	// radeon_irq_kms_fini(rdev);
		3023	rdev->accel_working = false;
		3024	}
		3025	return 0;
		3026	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 1430