WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
1179	serge	28	#include
1125	serge	29	#include "drmP.h"
		30	#include "drm.h"
1117	serge	31	#include "radeon_drm.h"
		32	#include "radeon_reg.h"
		33	#include "radeon.h"
1179	serge	34	#include "r100d.h"
1221	serge	35	#include "rs100d.h"
		36	#include "rv200d.h"
		37	#include "rv250d.h"
1117	serge	38
1221	serge	39	#include
		40
1179	serge	41	#include "r100_reg_safe.h"
		42	#include "rn50_reg_safe.h"
1221	serge	43
		44	/* Firmware Names */
		45	#define FIRMWARE_R100 "radeon/R100_cp.bin"
		46	#define FIRMWARE_R200 "radeon/R200_cp.bin"
		47	#define FIRMWARE_R300 "radeon/R300_cp.bin"
		48	#define FIRMWARE_R420 "radeon/R420_cp.bin"
		49	#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
		50	#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
		51	#define FIRMWARE_R520 "radeon/R520_cp.bin"
		52
		53	MODULE_FIRMWARE(FIRMWARE_R100);
		54	MODULE_FIRMWARE(FIRMWARE_R200);
		55	MODULE_FIRMWARE(FIRMWARE_R300);
		56	MODULE_FIRMWARE(FIRMWARE_R420);
		57	MODULE_FIRMWARE(FIRMWARE_RS690);
		58	MODULE_FIRMWARE(FIRMWARE_RS600);
		59	MODULE_FIRMWARE(FIRMWARE_R520);
		60
		61
1117	serge	62	/* This files gather functions specifics to:
		63	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		64	*/
		65
1321	serge	66	/* hpd for digital panel detect/disconnect */
		67	bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		68	{
		69	bool connected = false;
		70
		71	switch (hpd) {
		72	case RADEON_HPD_1:
		73	if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
		74	connected = true;
		75	break;
		76	case RADEON_HPD_2:
		77	if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
		78	connected = true;
		79	break;
		80	default:
		81	break;
		82	}
		83	return connected;
		84	}
		85
		86	void r100_hpd_set_polarity(struct radeon_device *rdev,
		87	enum radeon_hpd_id hpd)
		88	{
		89	u32 tmp;
		90	bool connected = r100_hpd_sense(rdev, hpd);
		91
		92	switch (hpd) {
		93	case RADEON_HPD_1:
		94	tmp = RREG32(RADEON_FP_GEN_CNTL);
		95	if (connected)
		96	tmp &= ~RADEON_FP_DETECT_INT_POL;
		97	else
		98	tmp \|= RADEON_FP_DETECT_INT_POL;
		99	WREG32(RADEON_FP_GEN_CNTL, tmp);
		100	break;
		101	case RADEON_HPD_2:
		102	tmp = RREG32(RADEON_FP2_GEN_CNTL);
		103	if (connected)
		104	tmp &= ~RADEON_FP2_DETECT_INT_POL;
		105	else
		106	tmp \|= RADEON_FP2_DETECT_INT_POL;
		107	WREG32(RADEON_FP2_GEN_CNTL, tmp);
		108	break;
		109	default:
		110	break;
		111	}
		112	}
		113
		114	void r100_hpd_init(struct radeon_device *rdev)
		115	{
		116	struct drm_device *dev = rdev->ddev;
		117	struct drm_connector *connector;
		118
		119	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		120	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		121	switch (radeon_connector->hpd.hpd) {
		122	case RADEON_HPD_1:
1403	serge	123	// rdev->irq.hpd[0] = true;
1321	serge	124	break;
		125	case RADEON_HPD_2:
1403	serge	126	// rdev->irq.hpd[1] = true;
1321	serge	127	break;
		128	default:
		129	break;
		130	}
		131	}
1403	serge	132	// if (rdev->irq.installed)
		133	// r100_irq_set(rdev);
1321	serge	134	}
		135
		136	void r100_hpd_fini(struct radeon_device *rdev)
		137	{
		138	struct drm_device *dev = rdev->ddev;
		139	struct drm_connector *connector;
		140
		141	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		142	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		143	switch (radeon_connector->hpd.hpd) {
		144	case RADEON_HPD_1:
1403	serge	145	// rdev->irq.hpd[0] = false;
1321	serge	146	break;
		147	case RADEON_HPD_2:
1403	serge	148	// rdev->irq.hpd[1] = false;
1321	serge	149	break;
		150	default:
		151	break;
		152	}
		153	}
		154	}
		155
1117	serge	156	/*
		157	* PCI GART
		158	*/
		159	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		160	{
		161	/* TODO: can we do somethings here ? */
		162	/* It seems hw only cache one entry so we should discard this
		163	* entry otherwise if first GPU GART read hit this entry it
		164	* could end up in wrong address. */
		165	}
		166
1179	serge	167	int r100_pci_gart_init(struct radeon_device *rdev)
1117	serge	168	{
		169	int r;
		170
1179	serge	171	if (rdev->gart.table.ram.ptr) {
		172	WARN(1, "R100 PCI GART already initialized.\n");
		173	return 0;
		174	}
1117	serge	175	/* Initialize common gart structure */
		176	r = radeon_gart_init(rdev);
1179	serge	177	if (r)
1117	serge	178	return r;
1268	serge	179	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
1179	serge	180	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		181	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		182	return radeon_gart_table_ram_alloc(rdev);
		183	}
		184
1321	serge	185	/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
		186	void r100_enable_bm(struct radeon_device *rdev)
		187	{
		188	uint32_t tmp;
		189	/* Enable bus mastering */
		190	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		191	WREG32(RADEON_BUS_CNTL, tmp);
		192	}
		193
1179	serge	194	int r100_pci_gart_enable(struct radeon_device *rdev)
		195	{
		196	uint32_t tmp;
		197
1117	serge	198	/* discard memory request outside of configured range */
		199	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		200	WREG32(RADEON_AIC_CNTL, tmp);
		201	/* set address range for PCI address translate */
		202	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
		203	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		204	WREG32(RADEON_AIC_HI_ADDR, tmp);
		205	/* set PCI GART page-table base address */
		206	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		207	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		208	WREG32(RADEON_AIC_CNTL, tmp);
		209	r100_pci_gart_tlb_flush(rdev);
		210	rdev->gart.ready = true;
		211	return 0;
		212	}
		213
		214	void r100_pci_gart_disable(struct radeon_device *rdev)
		215	{
		216	uint32_t tmp;
		217
		218	/* discard memory request outside of configured range */
		219	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		220	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		221	WREG32(RADEON_AIC_LO_ADDR, 0);
		222	WREG32(RADEON_AIC_HI_ADDR, 0);
		223	}
		224
		225	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		226	{
		227	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		228	return -EINVAL;
		229	}
1179	serge	230	rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
1117	serge	231	return 0;
		232	}
		233
1179	serge	234	void r100_pci_gart_fini(struct radeon_device *rdev)
1117	serge	235	{
		236	r100_pci_gart_disable(rdev);
1179	serge	237	radeon_gart_table_ram_free(rdev);
		238	radeon_gart_fini(rdev);
1117	serge	239	}
		240
		241
1221	serge	242	void r100_irq_disable(struct radeon_device *rdev)
1117	serge	243	{
1221	serge	244	u32 tmp;
1117	serge	245
1221	serge	246	WREG32(R_000040_GEN_INT_CNTL, 0);
		247	/* Wait and acknowledge irq */
		248	mdelay(1);
		249	tmp = RREG32(R_000044_GEN_INT_STATUS);
		250	WREG32(R_000044_GEN_INT_STATUS, tmp);
1117	serge	251	}
		252
1221	serge	253	static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
1117	serge	254	{
1221	serge	255	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
1321	serge	256	uint32_t irq_mask = RADEON_SW_INT_TEST \|
		257	RADEON_CRTC_VBLANK_STAT \| RADEON_CRTC2_VBLANK_STAT \|
		258	RADEON_FP_DETECT_STAT \| RADEON_FP2_DETECT_STAT;
1117	serge	259
1221	serge	260	if (irqs) {
		261	WREG32(RADEON_GEN_INT_STATUS, irqs);
1129	serge	262	}
1221	serge	263	return irqs & irq_mask;
1117	serge	264	}
		265
		266
1403	serge	267	u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
		268	{
		269	if (crtc == 0)
		270	return RREG32(RADEON_CRTC_CRNT_FRAME);
		271	else
		272	return RREG32(RADEON_CRTC2_CRNT_FRAME);
		273	}
1117	serge	274
1404	serge	275	/* Who ever call radeon_fence_emit should call ring_lock and ask
		276	* for enough space (today caller are ib schedule and buffer move) */
1117	serge	277	void r100_fence_ring_emit(struct radeon_device *rdev,
		278	struct radeon_fence *fence)
		279	{
1404	serge	280	/* We have to make sure that caches are flushed before
		281	* CPU might read something from VRAM. */
		282	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
		283	radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
		284	radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
		285	radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
1117	serge	286	/* Wait until IDLE & CLEAN */
		287	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		288	radeon_ring_write(rdev, (1 << 16) \| (1 << 17));
1403	serge	289	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		290	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl \|
		291	RADEON_HDP_READ_BUFFER_INVALIDATE);
		292	radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
		293	radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
1117	serge	294	/* Emit fence sequence & fire IRQ */
		295	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		296	radeon_ring_write(rdev, fence->seq);
		297	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		298	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		299	}
		300
1128	serge	301	#if 0
1117	serge	302	/*
		303	* Writeback
		304	*/
		305	int r100_wb_init(struct radeon_device *rdev)
		306	{
		307	int r;
		308
		309	if (rdev->wb.wb_obj == NULL) {
1321	serge	310	r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1117	serge	311	RADEON_GEM_DOMAIN_GTT,
1321	serge	312	&rdev->wb.wb_obj);
1117	serge	313	if (r) {
1321	serge	314	dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
1117	serge	315	return r;
		316	}
1321	serge	317	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		318	if (unlikely(r != 0))
		319	return r;
		320	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1117	serge	321	&rdev->wb.gpu_addr);
		322	if (r) {
1321	serge	323	dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
		324	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	325	return r;
		326	}
1321	serge	327	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		328	radeon_bo_unreserve(rdev->wb.wb_obj);
1117	serge	329	if (r) {
1321	serge	330	dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
1117	serge	331	return r;
		332	}
		333	}
1179	serge	334	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
		335	WREG32(R_00070C_CP_RB_RPTR_ADDR,
		336	S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
		337	WREG32(R_000770_SCRATCH_UMSK, 0xff);
1117	serge	338	return 0;
		339	}
		340
1179	serge	341	void r100_wb_disable(struct radeon_device *rdev)
		342	{
		343	WREG32(R_000770_SCRATCH_UMSK, 0);
		344	}
		345
1117	serge	346	void r100_wb_fini(struct radeon_device *rdev)
		347	{
1321	serge	348	int r;
		349
1179	serge	350	r100_wb_disable(rdev);
1117	serge	351	if (rdev->wb.wb_obj) {
1404	serge	352	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		353	if (unlikely(r != 0)) {
		354	dev_err(rdev->dev, "(%d) can't finish WB\n", r);
		355	return;
		356	}
		357	radeon_bo_kunmap(rdev->wb.wb_obj);
		358	radeon_bo_unpin(rdev->wb.wb_obj);
		359	radeon_bo_unreserve(rdev->wb.wb_obj);
		360	radeon_bo_unref(&rdev->wb.wb_obj);
1117	serge	361	rdev->wb.wb = NULL;
		362	rdev->wb.wb_obj = NULL;
		363	}
		364	}
		365
		366	int r100_copy_blit(struct radeon_device *rdev,
		367	uint64_t src_offset,
		368	uint64_t dst_offset,
		369	unsigned num_pages,
		370	struct radeon_fence *fence)
		371	{
		372	uint32_t cur_pages;
		373	uint32_t stride_bytes = PAGE_SIZE;
		374	uint32_t pitch;
		375	uint32_t stride_pixels;
		376	unsigned ndw;
		377	int num_loops;
		378	int r = 0;
		379
		380	/* radeon limited to 16k stride */
		381	stride_bytes &= 0x3fff;
		382	/* radeon pitch is /64 */
		383	pitch = stride_bytes / 64;
		384	stride_pixels = stride_bytes / 4;
		385	num_loops = DIV_ROUND_UP(num_pages, 8191);
		386
		387	/* Ask for enough room for blit + flush + fence */
		388	ndw = 64 + (10 * num_loops);
		389	r = radeon_ring_lock(rdev, ndw);
		390	if (r) {
		391	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		392	return -EINVAL;
		393	}
		394	while (num_pages > 0) {
		395	cur_pages = num_pages;
		396	if (cur_pages > 8191) {
		397	cur_pages = 8191;
		398	}
		399	num_pages -= cur_pages;
		400
		401	/* pages are in Y direction - height
		402	page width in X direction - width */
		403	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		404	radeon_ring_write(rdev,
		405	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		406	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		407	RADEON_GMC_SRC_CLIPPING \|
		408	RADEON_GMC_DST_CLIPPING \|
		409	RADEON_GMC_BRUSH_NONE \|
		410	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		411	RADEON_GMC_SRC_DATATYPE_COLOR \|
		412	RADEON_ROP3_S \|
		413	RADEON_DP_SRC_SOURCE_MEMORY \|
		414	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		415	RADEON_GMC_WR_MSK_DIS);
		416	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		417	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		418	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		419	radeon_ring_write(rdev, 0);
		420	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		421	radeon_ring_write(rdev, num_pages);
		422	radeon_ring_write(rdev, num_pages);
		423	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		424	}
		425	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		426	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		427	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		428	radeon_ring_write(rdev,
		429	RADEON_WAIT_2D_IDLECLEAN \|
		430	RADEON_WAIT_HOST_IDLECLEAN \|
		431	RADEON_WAIT_DMA_GUI_IDLE);
		432	if (fence) {
		433	r = radeon_fence_emit(rdev, fence);
		434	}
		435	radeon_ring_unlock_commit(rdev);
		436	return r;
		437	}
		438
1128	serge	439	#endif
1117	serge	440
1221	serge	441
1179	serge	442	static int r100_cp_wait_for_idle(struct radeon_device *rdev)
		443	{
		444	unsigned i;
		445	u32 tmp;
		446
		447	for (i = 0; i < rdev->usec_timeout; i++) {
		448	tmp = RREG32(R_000E40_RBBM_STATUS);
		449	if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
		450	return 0;
		451	}
		452	udelay(1);
		453	}
		454	return -1;
		455	}
		456
1117	serge	457	void r100_ring_start(struct radeon_device *rdev)
		458	{
		459	int r;
		460
		461	r = radeon_ring_lock(rdev, 2);
		462	if (r) {
		463	return;
		464	}
		465	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		466	radeon_ring_write(rdev,
		467	RADEON_ISYNC_ANY2D_IDLE3D \|
		468	RADEON_ISYNC_ANY3D_IDLE2D \|
		469	RADEON_ISYNC_WAIT_IDLEGUI \|
		470	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		471	radeon_ring_unlock_commit(rdev);
		472	}
		473
1221	serge	474
		475	/* Load the microcode for the CP */
		476	static int r100_cp_init_microcode(struct radeon_device *rdev)
1117	serge	477	{
1221	serge	478	struct platform_device *pdev;
		479	const char *fw_name = NULL;
		480	int err;
1117	serge	481
1221	serge	482	DRM_DEBUG("\n");
1117	serge	483
1221	serge	484	// pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
		485	// err = IS_ERR(pdev);
		486	// if (err) {
		487	// printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
		488	// return -EINVAL;
		489	// }
1117	serge	490	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		491	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		492	(rdev->family == CHIP_RS200)) {
		493	DRM_INFO("Loading R100 Microcode\n");
1221	serge	494	fw_name = FIRMWARE_R100;
1117	serge	495	} else if ((rdev->family == CHIP_R200) \|\|
		496	(rdev->family == CHIP_RV250) \|\|
		497	(rdev->family == CHIP_RV280) \|\|
		498	(rdev->family == CHIP_RS300)) {
		499	DRM_INFO("Loading R200 Microcode\n");
1221	serge	500	fw_name = FIRMWARE_R200;
1117	serge	501	} else if ((rdev->family == CHIP_R300) \|\|
		502	(rdev->family == CHIP_R350) \|\|
		503	(rdev->family == CHIP_RV350) \|\|
		504	(rdev->family == CHIP_RV380) \|\|
		505	(rdev->family == CHIP_RS400) \|\|
		506	(rdev->family == CHIP_RS480)) {
		507	DRM_INFO("Loading R300 Microcode\n");
1221	serge	508	fw_name = FIRMWARE_R300;
1117	serge	509	} else if ((rdev->family == CHIP_R420) \|\|
		510	(rdev->family == CHIP_R423) \|\|
		511	(rdev->family == CHIP_RV410)) {
		512	DRM_INFO("Loading R400 Microcode\n");
1221	serge	513	fw_name = FIRMWARE_R420;
1117	serge	514	} else if ((rdev->family == CHIP_RS690) \|\|
		515	(rdev->family == CHIP_RS740)) {
		516	DRM_INFO("Loading RS690/RS740 Microcode\n");
1221	serge	517	fw_name = FIRMWARE_RS690;
1117	serge	518	} else if (rdev->family == CHIP_RS600) {
		519	DRM_INFO("Loading RS600 Microcode\n");
1221	serge	520	fw_name = FIRMWARE_RS600;
1117	serge	521	} else if ((rdev->family == CHIP_RV515) \|\|
		522	(rdev->family == CHIP_R520) \|\|
		523	(rdev->family == CHIP_RV530) \|\|
		524	(rdev->family == CHIP_R580) \|\|
		525	(rdev->family == CHIP_RV560) \|\|
		526	(rdev->family == CHIP_RV570)) {
		527	DRM_INFO("Loading R500 Microcode\n");
1221	serge	528	fw_name = FIRMWARE_R520;
1117	serge	529	}
1221	serge	530
		531	// err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
		532	// platform_device_unregister(pdev);
		533	if (err) {
		534	printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
		535	fw_name);
		536	} else if (rdev->me_fw->size % 8) {
		537	printk(KERN_ERR
		538	"radeon_cp: Bogus length %zu in firmware \"%s\"\n",
		539	rdev->me_fw->size, fw_name);
		540	err = -EINVAL;
		541	release_firmware(rdev->me_fw);
		542	rdev->me_fw = NULL;
1117	serge	543	}
1221	serge	544	return err;
1117	serge	545	}
		546
1221	serge	547	static void r100_cp_load_microcode(struct radeon_device *rdev)
		548	{
		549	const __be32 *fw_data;
		550	int i, size;
		551
		552	if (r100_gui_wait_for_idle(rdev)) {
		553	printk(KERN_WARNING "Failed to wait GUI idle while "
		554	"programming pipes. Bad things might happen.\n");
		555	}
		556
		557	if (rdev->me_fw) {
		558	size = rdev->me_fw->size / 4;
		559	fw_data = (const __be32 *)&rdev->me_fw->data[0];
		560	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		561	for (i = 0; i < size; i += 2) {
		562	WREG32(RADEON_CP_ME_RAM_DATAH,
		563	be32_to_cpup(&fw_data[i]));
		564	WREG32(RADEON_CP_ME_RAM_DATAL,
		565	be32_to_cpup(&fw_data[i + 1]));
		566	}
		567	}
		568	}
		569
1117	serge	570	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		571	{
		572	unsigned rb_bufsz;
		573	unsigned rb_blksz;
		574	unsigned max_fetch;
		575	unsigned pre_write_timer;
		576	unsigned pre_write_limit;
		577	unsigned indirect2_start;
		578	unsigned indirect1_start;
		579	uint32_t tmp;
		580	int r;
		581
1129	serge	582	if (r100_debugfs_cp_init(rdev)) {
		583	DRM_ERROR("Failed to register debugfs file for CP !\n");
		584	}
1117	serge	585	/* Reset CP */
		586	tmp = RREG32(RADEON_CP_CSQ_STAT);
		587	if ((tmp & (1 << 31))) {
		588	DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
		589	WREG32(RADEON_CP_CSQ_MODE, 0);
		590	WREG32(RADEON_CP_CSQ_CNTL, 0);
		591	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		592	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		593	mdelay(2);
		594	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		595	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		596	mdelay(2);
		597	tmp = RREG32(RADEON_CP_CSQ_STAT);
		598	if ((tmp & (1 << 31))) {
		599	DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
		600	}
		601	} else {
		602	DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
		603	}
1179	serge	604
		605	if (!rdev->me_fw) {
		606	r = r100_cp_init_microcode(rdev);
		607	if (r) {
		608	DRM_ERROR("Failed to load firmware!\n");
		609	return r;
		610	}
		611	}
		612
1117	serge	613	/* Align ring size */
		614	rb_bufsz = drm_order(ring_size / 8);
		615	ring_size = (1 << (rb_bufsz + 1)) * 4;
		616	r100_cp_load_microcode(rdev);
		617	r = radeon_ring_init(rdev, ring_size);
		618	if (r) {
		619	return r;
		620	}
		621	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		622	* the rptr copy in system ram */
		623	rb_blksz = 9;
		624	/* cp will read 128bytes at a time (4 dwords) */
		625	max_fetch = 1;
		626	rdev->cp.align_mask = 16 - 1;
		627	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		628	pre_write_timer = 64;
		629	/* Force CP_RB_WPTR write if written more than one time before the
		630	* delay expire
		631	*/
		632	pre_write_limit = 0;
		633	/* Setup the cp cache like this (cache size is 96 dwords) :
		634	* RING 0 to 15
		635	* INDIRECT1 16 to 79
		636	* INDIRECT2 80 to 95
		637	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		638	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		639	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		640	* Idea being that most of the gpu cmd will be through indirect1 buffer
		641	* so it gets the bigger cache.
		642	*/
		643	indirect2_start = 80;
		644	indirect1_start = 16;
		645	/* cp setup */
		646	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
1268	serge	647	tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
1117	serge	648	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
		649	REG_SET(RADEON_MAX_FETCH, max_fetch) \|
		650	RADEON_RB_NO_UPDATE);
1268	serge	651	#ifdef __BIG_ENDIAN
		652	tmp \|= RADEON_BUF_SWAP_32BIT;
		653	#endif
		654	WREG32(RADEON_CP_RB_CNTL, tmp);
		655
1117	serge	656	/* Set ring address */
		657	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		658	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		659	/* Force read & write ptr to 0 */
		660	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		661	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		662	WREG32(RADEON_CP_RB_WPTR, 0);
		663	WREG32(RADEON_CP_RB_CNTL, tmp);
		664	udelay(10);
		665	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		666	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
		667	/* Set cp mode to bus mastering & enable cp*/
		668	WREG32(RADEON_CP_CSQ_MODE,
		669	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		670	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
		671	WREG32(0x718, 0);
		672	WREG32(0x744, 0x00004D4D);
		673	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		674	radeon_ring_start(rdev);
		675	r = radeon_ring_test(rdev);
		676	if (r) {
		677	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		678	return r;
		679	}
		680	rdev->cp.ready = true;
		681	return 0;
		682	}
		683
		684	void r100_cp_fini(struct radeon_device *rdev)
		685	{
1179	serge	686	if (r100_cp_wait_for_idle(rdev)) {
		687	DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
		688	}
1117	serge	689	/* Disable ring */
1179	serge	690	r100_cp_disable(rdev);
1117	serge	691	radeon_ring_fini(rdev);
		692	DRM_INFO("radeon: cp finalized\n");
		693	}
		694
		695	void r100_cp_disable(struct radeon_device *rdev)
		696	{
		697	/* Disable ring */
		698	rdev->cp.ready = false;
		699	WREG32(RADEON_CP_CSQ_MODE, 0);
		700	WREG32(RADEON_CP_CSQ_CNTL, 0);
		701	if (r100_gui_wait_for_idle(rdev)) {
		702	printk(KERN_WARNING "Failed to wait GUI idle while "
		703	"programming pipes. Bad things might happen.\n");
		704	}
		705	}
		706
		707	int r100_cp_reset(struct radeon_device *rdev)
		708	{
		709	uint32_t tmp;
		710	bool reinit_cp;
		711	int i;
		712
1179	serge	713	ENTER();
1117	serge	714
		715	reinit_cp = rdev->cp.ready;
		716	rdev->cp.ready = false;
		717	WREG32(RADEON_CP_CSQ_MODE, 0);
		718	WREG32(RADEON_CP_CSQ_CNTL, 0);
		719	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		720	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		721	udelay(200);
		722	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		723	/* Wait to prevent race in RBBM_STATUS */
		724	mdelay(1);
		725	for (i = 0; i < rdev->usec_timeout; i++) {
		726	tmp = RREG32(RADEON_RBBM_STATUS);
		727	if (!(tmp & (1 << 16))) {
		728	DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
		729	tmp);
		730	if (reinit_cp) {
		731	return r100_cp_init(rdev, rdev->cp.ring_size);
		732	}
		733	return 0;
		734	}
		735	DRM_UDELAY(1);
		736	}
		737	tmp = RREG32(RADEON_RBBM_STATUS);
		738	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
		739	return -1;
		740	}
		741
1179	serge	742	void r100_cp_commit(struct radeon_device *rdev)
		743	{
		744	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
		745	(void)RREG32(RADEON_CP_RB_WPTR);
		746	}
		747
		748
1117	serge	749	#if 0
		750	/*
		751	* CS functions
		752	*/
		753	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		754	struct radeon_cs_packet *pkt,
		755	const unsigned *auth, unsigned n,
		756	radeon_packet0_check_t check)
		757	{
		758	unsigned reg;
		759	unsigned i, j, m;
		760	unsigned idx;
		761	int r;
		762
		763	idx = pkt->idx + 1;
		764	reg = pkt->reg;
		765	/* Check that register fall into register range
		766	* determined by the number of entry (n) in the
		767	* safe register bitmap.
		768	*/
		769	if (pkt->one_reg_wr) {
		770	if ((reg >> 7) > n) {
		771	return -EINVAL;
		772	}
		773	} else {
		774	if (((reg + (pkt->count << 2)) >> 7) > n) {
		775	return -EINVAL;
		776	}
		777	}
		778	for (i = 0; i <= pkt->count; i++, idx++) {
		779	j = (reg >> 7);
		780	m = 1 << ((reg >> 2) & 31);
		781	if (auth[j] & m) {
		782	r = check(p, pkt, idx, reg);
		783	if (r) {
		784	return r;
		785	}
		786	}
		787	if (pkt->one_reg_wr) {
		788	if (!(auth[j] & m)) {
		789	break;
		790	}
		791	} else {
		792	reg += 4;
		793	}
		794	}
		795	return 0;
		796	}
		797
		798	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		799	struct radeon_cs_packet *pkt)
		800	{
		801	volatile uint32_t *ib;
		802	unsigned i;
		803	unsigned idx;
		804
		805	ib = p->ib->ptr;
		806	idx = pkt->idx;
		807	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		808	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		809	}
		810	}
		811
		812	/**
		813	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		814	* @parser: parser structure holding parsing context.
		815	* @pkt: where to store packet informations
		816	*
		817	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		818	* if packet is bigger than remaining ib size. or if packets is unknown.
		819	**/
		820	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		821	struct radeon_cs_packet *pkt,
		822	unsigned idx)
		823	{
		824	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1179	serge	825	uint32_t header;
1117	serge	826
		827	if (idx >= ib_chunk->length_dw) {
		828	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		829	idx, ib_chunk->length_dw);
		830	return -EINVAL;
		831	}
1221	serge	832	header = radeon_get_ib_value(p, idx);
1117	serge	833	pkt->idx = idx;
		834	pkt->type = CP_PACKET_GET_TYPE(header);
		835	pkt->count = CP_PACKET_GET_COUNT(header);
		836	switch (pkt->type) {
		837	case PACKET_TYPE0:
		838	pkt->reg = CP_PACKET0_GET_REG(header);
		839	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		840	break;
		841	case PACKET_TYPE3:
		842	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		843	break;
		844	case PACKET_TYPE2:
		845	pkt->count = -1;
		846	break;
		847	default:
		848	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		849	return -EINVAL;
		850	}
		851	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		852	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		853	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		854	return -EINVAL;
		855	}
		856	return 0;
		857	}
		858
		859	/**
1179	serge	860	* r100_cs_packet_next_vline() - parse userspace VLINE packet
		861	* @parser: parser structure holding parsing context.
		862	*
		863	* Userspace sends a special sequence for VLINE waits.
		864	* PACKET0 - VLINE_START_END + value
		865	* PACKET0 - WAIT_UNTIL +_value
		866	* RELOC (P3) - crtc_id in reloc.
		867	*
		868	* This function parses this and relocates the VLINE START END
		869	* and WAIT UNTIL packets to the correct crtc.
		870	* It also detects a switched off crtc and nulls out the
		871	* wait in that case.
		872	*/
		873	int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
		874	{
		875	struct drm_mode_object *obj;
		876	struct drm_crtc *crtc;
		877	struct radeon_crtc *radeon_crtc;
		878	struct radeon_cs_packet p3reloc, waitreloc;
		879	int crtc_id;
		880	int r;
		881	uint32_t header, h_idx, reg;
1221	serge	882	volatile uint32_t *ib;
1179	serge	883
1221	serge	884	ib = p->ib->ptr;
1179	serge	885
		886	/* parse the wait until */
		887	r = r100_cs_packet_parse(p, &waitreloc, p->idx);
		888	if (r)
		889	return r;
		890
		891	/* check its a wait until and only 1 count */
		892	if (waitreloc.reg != RADEON_WAIT_UNTIL \|\|
		893	waitreloc.count != 0) {
		894	DRM_ERROR("vline wait had illegal wait until segment\n");
		895	r = -EINVAL;
		896	return r;
		897	}
		898
1221	serge	899	if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1179	serge	900	DRM_ERROR("vline wait had illegal wait until\n");
		901	r = -EINVAL;
		902	return r;
		903	}
		904
		905	/* jump over the NOP */
1221	serge	906	r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1179	serge	907	if (r)
		908	return r;
		909
		910	h_idx = p->idx - 2;
1221	serge	911	p->idx += waitreloc.count + 2;
		912	p->idx += p3reloc.count + 2;
1179	serge	913
1221	serge	914	header = radeon_get_ib_value(p, h_idx);
		915	crtc_id = radeon_get_ib_value(p, h_idx + 5);
		916	reg = CP_PACKET0_GET_REG(header);
1179	serge	917	mutex_lock(&p->rdev->ddev->mode_config.mutex);
		918	obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
		919	if (!obj) {
		920	DRM_ERROR("cannot find crtc %d\n", crtc_id);
		921	r = -EINVAL;
		922	goto out;
		923	}
		924	crtc = obj_to_crtc(obj);
		925	radeon_crtc = to_radeon_crtc(crtc);
		926	crtc_id = radeon_crtc->crtc_id;
		927
		928	if (!crtc->enabled) {
		929	/* if the CRTC isn't enabled - we need to nop out the wait until */
1221	serge	930	ib[h_idx + 2] = PACKET2(0);
		931	ib[h_idx + 3] = PACKET2(0);
1179	serge	932	} else if (crtc_id == 1) {
		933	switch (reg) {
		934	case AVIVO_D1MODE_VLINE_START_END:
1221	serge	935	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	936	header \|= AVIVO_D2MODE_VLINE_START_END >> 2;
		937	break;
		938	case RADEON_CRTC_GUI_TRIG_VLINE:
1221	serge	939	header &= ~R300_CP_PACKET0_REG_MASK;
1179	serge	940	header \|= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
		941	break;
		942	default:
		943	DRM_ERROR("unknown crtc reloc\n");
		944	r = -EINVAL;
		945	goto out;
		946	}
1221	serge	947	ib[h_idx] = header;
		948	ib[h_idx + 3] \|= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1179	serge	949	}
		950	out:
		951	mutex_unlock(&p->rdev->ddev->mode_config.mutex);
		952	return r;
		953	}
		954
		955	/**
1117	serge	956	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		957	* @parser: parser structure holding parsing context.
		958	* @data: pointer to relocation data
		959	* @offset_start: starting offset
		960	* @offset_mask: offset mask (to align start offset on)
		961	* @reloc: reloc informations
		962	*
		963	* Check next packet is relocation packet3, do bo validation and compute
		964	* GPU offset using the provided start.
		965	**/
		966	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		967	struct radeon_cs_reloc **cs_reloc)
		968	{
		969	struct radeon_cs_chunk *relocs_chunk;
		970	struct radeon_cs_packet p3reloc;
		971	unsigned idx;
		972	int r;
		973
		974	if (p->chunk_relocs_idx == -1) {
		975	DRM_ERROR("No relocation chunk !\n");
		976	return -EINVAL;
		977	}
		978	*cs_reloc = NULL;
		979	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		980	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		981	if (r) {
		982	return r;
		983	}
		984	p->idx += p3reloc.count + 2;
		985	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		986	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		987	p3reloc.idx);
		988	r100_cs_dump_packet(p, &p3reloc);
		989	return -EINVAL;
		990	}
1221	serge	991	idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1117	serge	992	if (idx >= relocs_chunk->length_dw) {
		993	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		994	idx, relocs_chunk->length_dw);
		995	r100_cs_dump_packet(p, &p3reloc);
		996	return -EINVAL;
		997	}
		998	/* FIXME: we assume reloc size is 4 dwords */
		999	*cs_reloc = p->relocs_ptr[(idx / 4)];
		1000	return 0;
		1001	}
		1002
1179	serge	1003	static int r100_get_vtx_size(uint32_t vtx_fmt)
		1004	{
		1005	int vtx_size;
		1006	vtx_size = 2;
		1007	/* ordered according to bits in spec */
		1008	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
		1009	vtx_size++;
		1010	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
		1011	vtx_size += 3;
		1012	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
		1013	vtx_size++;
		1014	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
		1015	vtx_size++;
		1016	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
		1017	vtx_size += 3;
		1018	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
		1019	vtx_size++;
		1020	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
		1021	vtx_size++;
		1022	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
		1023	vtx_size += 2;
		1024	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
		1025	vtx_size += 2;
		1026	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
		1027	vtx_size++;
		1028	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
		1029	vtx_size += 2;
		1030	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
		1031	vtx_size++;
		1032	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
		1033	vtx_size += 2;
		1034	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
		1035	vtx_size++;
		1036	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
		1037	vtx_size++;
		1038	/* blend weight */
		1039	if (vtx_fmt & (0x7 << 15))
		1040	vtx_size += (vtx_fmt >> 15) & 0x7;
		1041	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
		1042	vtx_size += 3;
		1043	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
		1044	vtx_size += 2;
		1045	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
		1046	vtx_size++;
		1047	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
		1048	vtx_size++;
		1049	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
		1050	vtx_size++;
		1051	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
		1052	vtx_size++;
		1053	return vtx_size;
		1054	}
		1055
1117	serge	1056	static int r100_packet0_check(struct radeon_cs_parser *p,
1179	serge	1057	struct radeon_cs_packet *pkt,
		1058	unsigned idx, unsigned reg)
1117	serge	1059	{
		1060	struct radeon_cs_reloc *reloc;
1179	serge	1061	struct r100_cs_track *track;
1117	serge	1062	volatile uint32_t *ib;
		1063	uint32_t tmp;
		1064	int r;
1179	serge	1065	int i, face;
		1066	u32 tile_flags = 0;
1221	serge	1067	u32 idx_value;
1117	serge	1068
		1069	ib = p->ib->ptr;
1179	serge	1070	track = (struct r100_cs_track *)p->track;
		1071
1221	serge	1072	idx_value = radeon_get_ib_value(p, idx);
		1073
1117	serge	1074	switch (reg) {
1179	serge	1075	case RADEON_CRTC_GUI_TRIG_VLINE:
		1076	r = r100_cs_packet_parse_vline(p);
		1077	if (r) {
		1078	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1079	idx, reg);
		1080	r100_cs_dump_packet(p, pkt);
		1081	return r;
		1082	}
		1083	break;
1117	serge	1084	/* FIXME: only allow PACKET3 blit? easier to check for out of
		1085	* range access */
		1086	case RADEON_DST_PITCH_OFFSET:
		1087	case RADEON_SRC_PITCH_OFFSET:
1179	serge	1088	r = r100_reloc_pitch_offset(p, pkt, idx, reg);
		1089	if (r)
		1090	return r;
		1091	break;
		1092	case RADEON_RB3D_DEPTHOFFSET:
1117	serge	1093	r = r100_cs_packet_next_reloc(p, &reloc);
		1094	if (r) {
		1095	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1096	idx, reg);
		1097	r100_cs_dump_packet(p, pkt);
		1098	return r;
		1099	}
1179	serge	1100	track->zb.robj = reloc->robj;
1221	serge	1101	track->zb.offset = idx_value;
		1102	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1117	serge	1103	break;
		1104	case RADEON_RB3D_COLOROFFSET:
1179	serge	1105	r = r100_cs_packet_next_reloc(p, &reloc);
		1106	if (r) {
		1107	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1108	idx, reg);
		1109	r100_cs_dump_packet(p, pkt);
		1110	return r;
		1111	}
		1112	track->cb[0].robj = reloc->robj;
1221	serge	1113	track->cb[0].offset = idx_value;
		1114	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1115	break;
1117	serge	1116	case RADEON_PP_TXOFFSET_0:
		1117	case RADEON_PP_TXOFFSET_1:
		1118	case RADEON_PP_TXOFFSET_2:
1179	serge	1119	i = (reg - RADEON_PP_TXOFFSET_0) / 24;
		1120	r = r100_cs_packet_next_reloc(p, &reloc);
		1121	if (r) {
		1122	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1123	idx, reg);
		1124	r100_cs_dump_packet(p, pkt);
		1125	return r;
		1126	}
1221	serge	1127	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1128	track->textures[i].robj = reloc->robj;
		1129	break;
		1130	case RADEON_PP_CUBIC_OFFSET_T0_0:
		1131	case RADEON_PP_CUBIC_OFFSET_T0_1:
		1132	case RADEON_PP_CUBIC_OFFSET_T0_2:
		1133	case RADEON_PP_CUBIC_OFFSET_T0_3:
		1134	case RADEON_PP_CUBIC_OFFSET_T0_4:
		1135	i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
		1136	r = r100_cs_packet_next_reloc(p, &reloc);
		1137	if (r) {
		1138	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1139	idx, reg);
		1140	r100_cs_dump_packet(p, pkt);
		1141	return r;
		1142	}
1221	serge	1143	track->textures[0].cube_info[i].offset = idx_value;
		1144	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1145	track->textures[0].cube_info[i].robj = reloc->robj;
		1146	break;
		1147	case RADEON_PP_CUBIC_OFFSET_T1_0:
		1148	case RADEON_PP_CUBIC_OFFSET_T1_1:
		1149	case RADEON_PP_CUBIC_OFFSET_T1_2:
		1150	case RADEON_PP_CUBIC_OFFSET_T1_3:
		1151	case RADEON_PP_CUBIC_OFFSET_T1_4:
		1152	i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
		1153	r = r100_cs_packet_next_reloc(p, &reloc);
		1154	if (r) {
		1155	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1156	idx, reg);
		1157	r100_cs_dump_packet(p, pkt);
		1158	return r;
		1159	}
1221	serge	1160	track->textures[1].cube_info[i].offset = idx_value;
		1161	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1162	track->textures[1].cube_info[i].robj = reloc->robj;
		1163	break;
		1164	case RADEON_PP_CUBIC_OFFSET_T2_0:
		1165	case RADEON_PP_CUBIC_OFFSET_T2_1:
		1166	case RADEON_PP_CUBIC_OFFSET_T2_2:
		1167	case RADEON_PP_CUBIC_OFFSET_T2_3:
		1168	case RADEON_PP_CUBIC_OFFSET_T2_4:
		1169	i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1117	serge	1170	r = r100_cs_packet_next_reloc(p, &reloc);
		1171	if (r) {
		1172	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1173	idx, reg);
		1174	r100_cs_dump_packet(p, pkt);
		1175	return r;
		1176	}
1221	serge	1177	track->textures[2].cube_info[i].offset = idx_value;
		1178	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1179	track->textures[2].cube_info[i].robj = reloc->robj;
		1180	break;
		1181	case RADEON_RE_WIDTH_HEIGHT:
1221	serge	1182	track->maxy = ((idx_value >> 16) & 0x7FF);
1117	serge	1183	break;
1179	serge	1184	case RADEON_RB3D_COLORPITCH:
		1185	r = r100_cs_packet_next_reloc(p, &reloc);
		1186	if (r) {
		1187	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1188	idx, reg);
		1189	r100_cs_dump_packet(p, pkt);
		1190	return r;
		1191	}
		1192
		1193	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
		1194	tile_flags \|= RADEON_COLOR_TILE_ENABLE;
		1195	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
		1196	tile_flags \|= RADEON_COLOR_MICROTILE_ENABLE;
		1197
1221	serge	1198	tmp = idx_value & ~(0x7 << 16);
1179	serge	1199	tmp \|= tile_flags;
		1200	ib[idx] = tmp;
		1201
1221	serge	1202	track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1179	serge	1203	break;
		1204	case RADEON_RB3D_DEPTHPITCH:
1221	serge	1205	track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1179	serge	1206	break;
		1207	case RADEON_RB3D_CNTL:
1221	serge	1208	switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1179	serge	1209	case 7:
		1210	case 8:
		1211	case 9:
		1212	case 11:
		1213	case 12:
		1214	track->cb[0].cpp = 1;
		1215	break;
		1216	case 3:
		1217	case 4:
		1218	case 15:
		1219	track->cb[0].cpp = 2;
		1220	break;
		1221	case 6:
		1222	track->cb[0].cpp = 4;
		1223	break;
1117	serge	1224	default:
1179	serge	1225	DRM_ERROR("Invalid color buffer format (%d) !\n",
1221	serge	1226	((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1179	serge	1227	return -EINVAL;
		1228	}
1221	serge	1229	track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1179	serge	1230	break;
		1231	case RADEON_RB3D_ZSTENCILCNTL:
1221	serge	1232	switch (idx_value & 0xf) {
1179	serge	1233	case 0:
		1234	track->zb.cpp = 2;
1117	serge	1235	break;
1179	serge	1236	case 2:
		1237	case 3:
		1238	case 4:
		1239	case 5:
		1240	case 9:
		1241	case 11:
		1242	track->zb.cpp = 4;
		1243	break;
		1244	default:
		1245	break;
1117	serge	1246	}
		1247	break;
1179	serge	1248	case RADEON_RB3D_ZPASS_ADDR:
		1249	r = r100_cs_packet_next_reloc(p, &reloc);
		1250	if (r) {
		1251	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		1252	idx, reg);
		1253	r100_cs_dump_packet(p, pkt);
		1254	return r;
		1255	}
1221	serge	1256	ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179	serge	1257	break;
		1258	case RADEON_PP_CNTL:
		1259	{
1221	serge	1260	uint32_t temp = idx_value >> 4;
1179	serge	1261	for (i = 0; i < track->num_texture; i++)
		1262	track->textures[i].enabled = !!(temp & (1 << i));
1117	serge	1263	}
1179	serge	1264	break;
		1265	case RADEON_SE_VF_CNTL:
1221	serge	1266	track->vap_vf_cntl = idx_value;
1179	serge	1267	break;
		1268	case RADEON_SE_VTX_FMT:
1221	serge	1269	track->vtx_size = r100_get_vtx_size(idx_value);
1179	serge	1270	break;
		1271	case RADEON_PP_TEX_SIZE_0:
		1272	case RADEON_PP_TEX_SIZE_1:
		1273	case RADEON_PP_TEX_SIZE_2:
		1274	i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1221	serge	1275	track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
		1276	track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1179	serge	1277	break;
		1278	case RADEON_PP_TEX_PITCH_0:
		1279	case RADEON_PP_TEX_PITCH_1:
		1280	case RADEON_PP_TEX_PITCH_2:
		1281	i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1221	serge	1282	track->textures[i].pitch = idx_value + 32;
1179	serge	1283	break;
		1284	case RADEON_PP_TXFILTER_0:
		1285	case RADEON_PP_TXFILTER_1:
		1286	case RADEON_PP_TXFILTER_2:
		1287	i = (reg - RADEON_PP_TXFILTER_0) / 24;
1221	serge	1288	track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1179	serge	1289	>> RADEON_MAX_MIP_LEVEL_SHIFT);
1221	serge	1290	tmp = (idx_value >> 23) & 0x7;
1179	serge	1291	if (tmp == 2 \|\| tmp == 6)
		1292	track->textures[i].roundup_w = false;
1221	serge	1293	tmp = (idx_value >> 27) & 0x7;
1179	serge	1294	if (tmp == 2 \|\| tmp == 6)
		1295	track->textures[i].roundup_h = false;
		1296	break;
		1297	case RADEON_PP_TXFORMAT_0:
		1298	case RADEON_PP_TXFORMAT_1:
		1299	case RADEON_PP_TXFORMAT_2:
		1300	i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1221	serge	1301	if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1179	serge	1302	track->textures[i].use_pitch = 1;
		1303	} else {
		1304	track->textures[i].use_pitch = 0;
1221	serge	1305	track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
		1306	track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1179	serge	1307	}
1221	serge	1308	if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1179	serge	1309	track->textures[i].tex_coord_type = 2;
1221	serge	1310	switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1179	serge	1311	case RADEON_TXFORMAT_I8:
		1312	case RADEON_TXFORMAT_RGB332:
		1313	case RADEON_TXFORMAT_Y8:
		1314	track->textures[i].cpp = 1;
		1315	break;
		1316	case RADEON_TXFORMAT_AI88:
		1317	case RADEON_TXFORMAT_ARGB1555:
		1318	case RADEON_TXFORMAT_RGB565:
		1319	case RADEON_TXFORMAT_ARGB4444:
		1320	case RADEON_TXFORMAT_VYUY422:
		1321	case RADEON_TXFORMAT_YVYU422:
		1322	case RADEON_TXFORMAT_SHADOW16:
		1323	case RADEON_TXFORMAT_LDUDV655:
		1324	case RADEON_TXFORMAT_DUDV88:
		1325	track->textures[i].cpp = 2;
		1326	break;
		1327	case RADEON_TXFORMAT_ARGB8888:
		1328	case RADEON_TXFORMAT_RGBA8888:
		1329	case RADEON_TXFORMAT_SHADOW32:
		1330	case RADEON_TXFORMAT_LDUDUV8888:
		1331	track->textures[i].cpp = 4;
		1332	break;
1403	serge	1333	case RADEON_TXFORMAT_DXT1:
		1334	track->textures[i].cpp = 1;
		1335	track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
		1336	break;
		1337	case RADEON_TXFORMAT_DXT23:
		1338	case RADEON_TXFORMAT_DXT45:
		1339	track->textures[i].cpp = 1;
		1340	track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
		1341	break;
1179	serge	1342	}
1221	serge	1343	track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
		1344	track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1179	serge	1345	break;
		1346	case RADEON_PP_CUBIC_FACES_0:
		1347	case RADEON_PP_CUBIC_FACES_1:
		1348	case RADEON_PP_CUBIC_FACES_2:
1221	serge	1349	tmp = idx_value;
1179	serge	1350	i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
		1351	for (face = 0; face < 4; face++) {
		1352	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
		1353	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
		1354	}
		1355	break;
		1356	default:
		1357	printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
		1358	reg, idx);
		1359	return -EINVAL;
1117	serge	1360	}
		1361	return 0;
		1362	}
		1363
		1364	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		1365	struct radeon_cs_packet *pkt,
1321	serge	1366	struct radeon_bo *robj)
1117	serge	1367	{
		1368	unsigned idx;
1221	serge	1369	u32 value;
1117	serge	1370	idx = pkt->idx + 1;
1221	serge	1371	value = radeon_get_ib_value(p, idx + 2);
1321	serge	1372	if ((value + 1) > radeon_bo_size(robj)) {
1117	serge	1373	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		1374	"(need %u have %lu) !\n",
1221	serge	1375	value + 1,
1321	serge	1376	radeon_bo_size(robj));
1117	serge	1377	return -EINVAL;
		1378	}
		1379	return 0;
		1380	}
		1381
		1382	static int r100_packet3_check(struct radeon_cs_parser *p,
		1383	struct radeon_cs_packet *pkt)
		1384	{
		1385	struct radeon_cs_reloc *reloc;
1179	serge	1386	struct r100_cs_track *track;
1117	serge	1387	unsigned idx;
		1388	volatile uint32_t *ib;
		1389	int r;
		1390
		1391	ib = p->ib->ptr;
		1392	idx = pkt->idx + 1;
1179	serge	1393	track = (struct r100_cs_track *)p->track;
1117	serge	1394	switch (pkt->opcode) {
		1395	case PACKET3_3D_LOAD_VBPNTR:
1221	serge	1396	r = r100_packet3_load_vbpntr(p, pkt, idx);
		1397	if (r)
1117	serge	1398	return r;
		1399	break;
		1400	case PACKET3_INDX_BUFFER:
		1401	r = r100_cs_packet_next_reloc(p, &reloc);
		1402	if (r) {
		1403	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1404	r100_cs_dump_packet(p, pkt);
		1405	return r;
		1406	}
1221	serge	1407	ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1117	serge	1408	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		1409	if (r) {
		1410	return r;
		1411	}
		1412	break;
		1413	case 0x23:
		1414	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		1415	r = r100_cs_packet_next_reloc(p, &reloc);
		1416	if (r) {
		1417	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		1418	r100_cs_dump_packet(p, pkt);
		1419	return r;
		1420	}
1221	serge	1421	ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1179	serge	1422	track->num_arrays = 1;
1221	serge	1423	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1179	serge	1424
		1425	track->arrays[0].robj = reloc->robj;
		1426	track->arrays[0].esize = track->vtx_size;
		1427
1221	serge	1428	track->max_indx = radeon_get_ib_value(p, idx+1);
1179	serge	1429
1221	serge	1430	track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1179	serge	1431	track->immd_dwords = pkt->count - 1;
		1432	r = r100_cs_track_check(p->rdev, track);
		1433	if (r)
		1434	return r;
1117	serge	1435	break;
		1436	case PACKET3_3D_DRAW_IMMD:
1221	serge	1437	if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1179	serge	1438	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1439	return -EINVAL;
		1440	}
1403	serge	1441	track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1221	serge	1442	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1443	track->immd_dwords = pkt->count - 1;
		1444	r = r100_cs_track_check(p->rdev, track);
		1445	if (r)
		1446	return r;
		1447	break;
1117	serge	1448	/* triggers drawing using in-packet vertex data */
		1449	case PACKET3_3D_DRAW_IMMD_2:
1221	serge	1450	if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1179	serge	1451	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
		1452	return -EINVAL;
		1453	}
1221	serge	1454	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1455	track->immd_dwords = pkt->count;
		1456	r = r100_cs_track_check(p->rdev, track);
		1457	if (r)
		1458	return r;
		1459	break;
1117	serge	1460	/* triggers drawing using in-packet vertex data */
		1461	case PACKET3_3D_DRAW_VBUF_2:
1221	serge	1462	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1463	r = r100_cs_track_check(p->rdev, track);
		1464	if (r)
		1465	return r;
		1466	break;
1117	serge	1467	/* triggers drawing of vertex buffers setup elsewhere */
		1468	case PACKET3_3D_DRAW_INDX_2:
1221	serge	1469	track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1179	serge	1470	r = r100_cs_track_check(p->rdev, track);
		1471	if (r)
		1472	return r;
		1473	break;
1117	serge	1474	/* triggers drawing using indices to vertex buffer */
		1475	case PACKET3_3D_DRAW_VBUF:
1221	serge	1476	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1477	r = r100_cs_track_check(p->rdev, track);
		1478	if (r)
		1479	return r;
		1480	break;
1117	serge	1481	/* triggers drawing of vertex buffers setup elsewhere */
		1482	case PACKET3_3D_DRAW_INDX:
1221	serge	1483	track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1179	serge	1484	r = r100_cs_track_check(p->rdev, track);
		1485	if (r)
		1486	return r;
		1487	break;
1117	serge	1488	/* triggers drawing using indices to vertex buffer */
		1489	case PACKET3_NOP:
		1490	break;
		1491	default:
		1492	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1493	return -EINVAL;
		1494	}
		1495	return 0;
		1496	}
		1497
		1498	int r100_cs_parse(struct radeon_cs_parser *p)
		1499	{
		1500	struct radeon_cs_packet pkt;
1179	serge	1501	struct r100_cs_track *track;
1117	serge	1502	int r;
		1503
1179	serge	1504	track = kzalloc(sizeof(*track), GFP_KERNEL);
		1505	r100_cs_track_clear(p->rdev, track);
		1506	p->track = track;
1117	serge	1507	do {
		1508	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1509	if (r) {
		1510	return r;
		1511	}
		1512	p->idx += pkt.count + 2;
		1513	switch (pkt.type) {
		1514	case PACKET_TYPE0:
1179	serge	1515	if (p->rdev->family >= CHIP_R200)
		1516	r = r100_cs_parse_packet0(p, &pkt,
		1517	p->rdev->config.r100.reg_safe_bm,
		1518	p->rdev->config.r100.reg_safe_bm_size,
		1519	&r200_packet0_check);
		1520	else
		1521	r = r100_cs_parse_packet0(p, &pkt,
		1522	p->rdev->config.r100.reg_safe_bm,
		1523	p->rdev->config.r100.reg_safe_bm_size,
		1524	&r100_packet0_check);
1117	serge	1525	break;
		1526	case PACKET_TYPE2:
		1527	break;
		1528	case PACKET_TYPE3:
		1529	r = r100_packet3_check(p, &pkt);
		1530	break;
		1531	default:
		1532	DRM_ERROR("Unknown packet type %d !\n",
		1533	pkt.type);
		1534	return -EINVAL;
		1535	}
		1536	if (r) {
		1537	return r;
		1538	}
		1539	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1540	return 0;
		1541	}
		1542
1128	serge	1543	#endif
1117	serge	1544
		1545	/*
		1546	* Global GPU functions
		1547	*/
		1548	void r100_errata(struct radeon_device *rdev)
		1549	{
		1550	rdev->pll_errata = 0;
		1551
		1552	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1553	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1554	}
		1555
		1556	if (rdev->family == CHIP_RV100 \|\|
		1557	rdev->family == CHIP_RS100 \|\|
		1558	rdev->family == CHIP_RS200) {
		1559	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1560	}
		1561	}
		1562
		1563	/* Wait for vertical sync on primary CRTC */
		1564	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1565	{
		1566	uint32_t crtc_gen_cntl, tmp;
		1567	int i;
		1568
		1569	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1570	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1571	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1572	return;
		1573	}
		1574	/* Clear the CRTC_VBLANK_SAVE bit */
		1575	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1576	for (i = 0; i < rdev->usec_timeout; i++) {
		1577	tmp = RREG32(RADEON_CRTC_STATUS);
		1578	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1579	return;
		1580	}
		1581	DRM_UDELAY(1);
		1582	}
		1583	}
		1584
		1585	/* Wait for vertical sync on secondary CRTC */
		1586	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1587	{
		1588	uint32_t crtc2_gen_cntl, tmp;
		1589	int i;
		1590
		1591	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1592	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1593	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1594	return;
		1595
		1596	/* Clear the CRTC_VBLANK_SAVE bit */
		1597	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1598	for (i = 0; i < rdev->usec_timeout; i++) {
		1599	tmp = RREG32(RADEON_CRTC2_STATUS);
		1600	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1601	return;
		1602	}
		1603	DRM_UDELAY(1);
		1604	}
		1605	}
		1606
		1607	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1608	{
		1609	unsigned i;
		1610	uint32_t tmp;
		1611
		1612	for (i = 0; i < rdev->usec_timeout; i++) {
		1613	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1614	if (tmp >= n) {
		1615	return 0;
		1616	}
		1617	DRM_UDELAY(1);
		1618	}
		1619	return -1;
		1620	}
		1621
		1622	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1623	{
		1624	unsigned i;
		1625	uint32_t tmp;
		1626
		1627	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1628	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1629	" Bad things might happen.\n");
		1630	}
		1631	for (i = 0; i < rdev->usec_timeout; i++) {
		1632	tmp = RREG32(RADEON_RBBM_STATUS);
		1633	if (!(tmp & (1 << 31))) {
		1634	return 0;
		1635	}
		1636	DRM_UDELAY(1);
		1637	}
		1638	return -1;
		1639	}
		1640
		1641	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1642	{
		1643	unsigned i;
		1644	uint32_t tmp;
		1645
		1646	for (i = 0; i < rdev->usec_timeout; i++) {
		1647	/* read MC_STATUS */
		1648	tmp = RREG32(0x0150);
		1649	if (tmp & (1 << 2)) {
		1650	return 0;
		1651	}
		1652	DRM_UDELAY(1);
		1653	}
		1654	return -1;
		1655	}
		1656
		1657	void r100_gpu_init(struct radeon_device *rdev)
		1658	{
		1659	/* TODO: anythings to do here ? pipes ? */
		1660	r100_hdp_reset(rdev);
		1661	}
		1662
		1663	void r100_hdp_reset(struct radeon_device *rdev)
		1664	{
		1665	uint32_t tmp;
		1666
1179	serge	1667	ENTER();
1117	serge	1668
		1669	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		1670	tmp \|= (7 << 28);
		1671	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		1672	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1673	udelay(200);
		1674	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1675	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		1676	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1677	}
		1678
		1679	int r100_rb2d_reset(struct radeon_device *rdev)
		1680	{
		1681	uint32_t tmp;
		1682	int i;
		1683
1179	serge	1684	ENTER();
1117	serge	1685
		1686	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
		1687	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		1688	udelay(200);
		1689	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1690	/* Wait to prevent race in RBBM_STATUS */
		1691	mdelay(1);
		1692	for (i = 0; i < rdev->usec_timeout; i++) {
		1693	tmp = RREG32(RADEON_RBBM_STATUS);
		1694	if (!(tmp & (1 << 26))) {
		1695	DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
		1696	tmp);
		1697	return 0;
		1698	}
		1699	DRM_UDELAY(1);
		1700	}
		1701	tmp = RREG32(RADEON_RBBM_STATUS);
		1702	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
		1703	return -1;
		1704	}
		1705
		1706	int r100_gpu_reset(struct radeon_device *rdev)
		1707	{
		1708	uint32_t status;
		1709
		1710	/* reset order likely matter */
		1711	status = RREG32(RADEON_RBBM_STATUS);
		1712	/* reset HDP */
		1713	r100_hdp_reset(rdev);
		1714	/* reset rb2d */
		1715	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		1716	r100_rb2d_reset(rdev);
		1717	}
		1718	/* TODO: reset 3D engine */
		1719	/* reset CP */
		1720	status = RREG32(RADEON_RBBM_STATUS);
		1721	if (status & (1 << 16)) {
		1722	r100_cp_reset(rdev);
		1723	}
		1724	/* Check if GPU is idle */
		1725	status = RREG32(RADEON_RBBM_STATUS);
		1726	if (status & (1 << 31)) {
		1727	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		1728	return -1;
		1729	}
		1730	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		1731	return 0;
		1732	}
		1733
1321	serge	1734	void r100_set_common_regs(struct radeon_device *rdev)
		1735	{
		1736	/* set these so they don't interfere with anything */
		1737	WREG32(RADEON_OV0_SCALE_CNTL, 0);
		1738	WREG32(RADEON_SUBPIC_CNTL, 0);
		1739	WREG32(RADEON_VIPH_CONTROL, 0);
		1740	WREG32(RADEON_I2C_CNTL_1, 0);
		1741	WREG32(RADEON_DVI_I2C_CNTL_1, 0);
		1742	WREG32(RADEON_CAP0_TRIG_CNTL, 0);
		1743	WREG32(RADEON_CAP1_TRIG_CNTL, 0);
		1744	}
1117	serge	1745
		1746	/*
		1747	* VRAM info
		1748	*/
		1749	static void r100_vram_get_type(struct radeon_device *rdev)
		1750	{
		1751	uint32_t tmp;
		1752
		1753	rdev->mc.vram_is_ddr = false;
		1754	if (rdev->flags & RADEON_IS_IGP)
		1755	rdev->mc.vram_is_ddr = true;
		1756	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1757	rdev->mc.vram_is_ddr = true;
		1758	if ((rdev->family == CHIP_RV100) \|\|
		1759	(rdev->family == CHIP_RS100) \|\|
		1760	(rdev->family == CHIP_RS200)) {
		1761	tmp = RREG32(RADEON_MEM_CNTL);
		1762	if (tmp & RV100_HALF_MODE) {
		1763	rdev->mc.vram_width = 32;
		1764	} else {
		1765	rdev->mc.vram_width = 64;
		1766	}
		1767	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1768	rdev->mc.vram_width /= 4;
		1769	rdev->mc.vram_is_ddr = true;
		1770	}
		1771	} else if (rdev->family <= CHIP_RV280) {
		1772	tmp = RREG32(RADEON_MEM_CNTL);
		1773	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1774	rdev->mc.vram_width = 128;
		1775	} else {
		1776	rdev->mc.vram_width = 64;
		1777	}
		1778	} else {
		1779	/* newer IGPs */
		1780	rdev->mc.vram_width = 128;
		1781	}
		1782	}
		1783
1179	serge	1784	static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1117	serge	1785	{
1179	serge	1786	u32 aper_size;
		1787	u8 byte;
1117	serge	1788
1179	serge	1789	aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1790
		1791	/* Set HDP_APER_CNTL only on cards that are known not to be broken,
		1792	* that is has the 2nd generation multifunction PCI interface
		1793	*/
		1794	if (rdev->family == CHIP_RV280 \|\|
		1795	rdev->family >= CHIP_RV350) {
		1796	WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
		1797	~RADEON_HDP_APER_CNTL);
		1798	DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
		1799	return aper_size * 2;
		1800	}
		1801
		1802	/* Older cards have all sorts of funny issues to deal with. First
		1803	* check if it's a multifunction card by reading the PCI config
		1804	* header type... Limit those to one aperture size
		1805	*/
		1806	// pci_read_config_byte(rdev->pdev, 0xe, &byte);
		1807	// if (byte & 0x80) {
		1808	// DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
		1809	// DRM_INFO("Limiting VRAM to one aperture\n");
		1810	// return aper_size;
		1811	// }
		1812
		1813	/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
		1814	* have set it up. We don't write this as it's broken on some ASICs but
		1815	* we expect the BIOS to have done the right thing (might be too optimistic...)
		1816	*/
		1817	if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
		1818	return aper_size * 2;
		1819	return aper_size;
		1820	}
		1821
		1822	void r100_vram_init_sizes(struct radeon_device *rdev)
		1823	{
		1824	u64 config_aper_size;
		1825	u32 accessible;
		1826
		1827	config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
		1828
1117	serge	1829	if (rdev->flags & RADEON_IS_IGP) {
		1830	uint32_t tom;
		1831	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1832	tom = RREG32(RADEON_NB_TOM);
1179	serge	1833	rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1834	/* for IGPs we need to keep VRAM where it was put by the BIOS */
		1835	rdev->mc.vram_location = (tom & 0xffff) << 16;
		1836	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
		1837	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1838	} else {
1179	serge	1839	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1117	serge	1840	/* Some production boards of m6 will report 0
		1841	* if it's 8 MB
		1842	*/
1179	serge	1843	if (rdev->mc.real_vram_size == 0) {
		1844	rdev->mc.real_vram_size = 8192 * 1024;
		1845	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1117	serge	1846	}
1179	serge	1847	/* let driver place VRAM */
		1848	rdev->mc.vram_location = 0xFFFFFFFFUL;
		1849	/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
		1850	* Novell bug 204882 + along with lots of ubuntu ones */
		1851	if (config_aper_size > rdev->mc.real_vram_size)
		1852	rdev->mc.mc_vram_size = config_aper_size;
		1853	else
		1854	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1117	serge	1855	}
		1856
1179	serge	1857	/* work out accessible VRAM */
		1858	accessible = r100_get_accessible_vram(rdev);
		1859
1117	serge	1860	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		1861	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1179	serge	1862
		1863	if (accessible > rdev->mc.aper_size)
		1864	accessible = rdev->mc.aper_size;
		1865
		1866	if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
		1867	rdev->mc.mc_vram_size = rdev->mc.aper_size;
		1868
		1869	if (rdev->mc.real_vram_size > rdev->mc.aper_size)
		1870	rdev->mc.real_vram_size = rdev->mc.aper_size;
1117	serge	1871	}
		1872
1179	serge	1873	void r100_vga_set_state(struct radeon_device *rdev, bool state)
		1874	{
		1875	uint32_t temp;
		1876
		1877	temp = RREG32(RADEON_CONFIG_CNTL);
		1878	if (state == false) {
		1879	temp &= ~(1<<8);
		1880	temp \|= (1<<9);
		1881	} else {
		1882	temp &= ~(1<<9);
		1883	}
		1884	WREG32(RADEON_CONFIG_CNTL, temp);
		1885	}
		1886
		1887	void r100_vram_info(struct radeon_device *rdev)
		1888	{
		1889	r100_vram_get_type(rdev);
		1890
		1891	r100_vram_init_sizes(rdev);
		1892	}
		1893
		1894
1117	serge	1895	/*
		1896	* Indirect registers accessor
		1897	*/
		1898	void r100_pll_errata_after_index(struct radeon_device *rdev)
		1899	{
		1900	if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
		1901	return;
		1902	}
		1903	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		1904	(void)RREG32(RADEON_CRTC_GEN_CNTL);
		1905	}
		1906
		1907	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		1908	{
		1909	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		1910	* or the chip could hang on a subsequent access
		1911	*/
		1912	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		1913	udelay(5000);
		1914	}
		1915
		1916	/* This function is required to workaround a hardware bug in some (all?)
		1917	* revisions of the R300. This workaround should be called after every
		1918	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1919	* may not be correct.
		1920	*/
		1921	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		1922	uint32_t save, tmp;
		1923
		1924	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		1925	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		1926	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		1927	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		1928	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		1929	}
		1930	}
		1931
		1932	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		1933	{
		1934	uint32_t data;
		1935
		1936	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		1937	r100_pll_errata_after_index(rdev);
		1938	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		1939	r100_pll_errata_after_data(rdev);
		1940	return data;
		1941	}
		1942
		1943	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		1944	{
		1945	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		1946	r100_pll_errata_after_index(rdev);
		1947	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		1948	r100_pll_errata_after_data(rdev);
		1949	}
		1950
1221	serge	1951	void r100_set_safe_registers(struct radeon_device *rdev)
1117	serge	1952	{
1179	serge	1953	if (ASIC_IS_RN50(rdev)) {
		1954	rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
		1955	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
		1956	} else if (rdev->family < CHIP_R200) {
		1957	rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
		1958	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
		1959	} else {
1221	serge	1960	r200_set_safe_registers(rdev);
1117	serge	1961	}
		1962	}
		1963
1129	serge	1964	/*
		1965	* Debugfs info
		1966	*/
		1967	#if defined(CONFIG_DEBUG_FS)
		1968	static int r100_debugfs_rbbm_info(struct seq_file m, void data)
		1969	{
		1970	struct drm_info_node node = (struct drm_info_node ) m->private;
		1971	struct drm_device *dev = node->minor->dev;
		1972	struct radeon_device *rdev = dev->dev_private;
		1973	uint32_t reg, value;
		1974	unsigned i;
		1975
		1976	seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
		1977	seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
		1978	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		1979	for (i = 0; i < 64; i++) {
		1980	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i \| 0x100);
		1981	reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
		1982	WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
		1983	value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
		1984	seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
		1985	}
		1986	return 0;
		1987	}
		1988
		1989	static int r100_debugfs_cp_ring_info(struct seq_file m, void data)
		1990	{
		1991	struct drm_info_node node = (struct drm_info_node ) m->private;
		1992	struct drm_device *dev = node->minor->dev;
		1993	struct radeon_device *rdev = dev->dev_private;
		1994	uint32_t rdp, wdp;
		1995	unsigned count, i, j;
		1996
		1997	radeon_ring_free_size(rdev);
		1998	rdp = RREG32(RADEON_CP_RB_RPTR);
		1999	wdp = RREG32(RADEON_CP_RB_WPTR);
		2000	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
		2001	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2002	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
		2003	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
		2004	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
		2005	seq_printf(m, "%u dwords in ring\n", count);
		2006	for (j = 0; j <= count; j++) {
		2007	i = (rdp + j) & rdev->cp.ptr_mask;
		2008	seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
		2009	}
		2010	return 0;
		2011	}
		2012
		2013
		2014	static int r100_debugfs_cp_csq_fifo(struct seq_file m, void data)
		2015	{
		2016	struct drm_info_node node = (struct drm_info_node ) m->private;
		2017	struct drm_device *dev = node->minor->dev;
		2018	struct radeon_device *rdev = dev->dev_private;
		2019	uint32_t csq_stat, csq2_stat, tmp;
		2020	unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
		2021	unsigned i;
		2022
		2023	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
		2024	seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
		2025	csq_stat = RREG32(RADEON_CP_CSQ_STAT);
		2026	csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
		2027	r_rptr = (csq_stat >> 0) & 0x3ff;
		2028	r_wptr = (csq_stat >> 10) & 0x3ff;
		2029	ib1_rptr = (csq_stat >> 20) & 0x3ff;
		2030	ib1_wptr = (csq2_stat >> 0) & 0x3ff;
		2031	ib2_rptr = (csq2_stat >> 10) & 0x3ff;
		2032	ib2_wptr = (csq2_stat >> 20) & 0x3ff;
		2033	seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
		2034	seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
		2035	seq_printf(m, "Ring rptr %u\n", r_rptr);
		2036	seq_printf(m, "Ring wptr %u\n", r_wptr);
		2037	seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
		2038	seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
		2039	seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
		2040	seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
		2041	/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
		2042	* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
		2043	seq_printf(m, "Ring fifo:\n");
		2044	for (i = 0; i < 256; i++) {
		2045	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2046	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2047	seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
		2048	}
		2049	seq_printf(m, "Indirect1 fifo:\n");
		2050	for (i = 256; i <= 512; i++) {
		2051	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2052	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2053	seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
		2054	}
		2055	seq_printf(m, "Indirect2 fifo:\n");
		2056	for (i = 640; i < ib1_wptr; i++) {
		2057	WREG32(RADEON_CP_CSQ_ADDR, i << 2);
		2058	tmp = RREG32(RADEON_CP_CSQ_DATA);
		2059	seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
		2060	}
		2061	return 0;
		2062	}
		2063
		2064	static int r100_debugfs_mc_info(struct seq_file m, void data)
		2065	{
		2066	struct drm_info_node node = (struct drm_info_node ) m->private;
		2067	struct drm_device *dev = node->minor->dev;
		2068	struct radeon_device *rdev = dev->dev_private;
		2069	uint32_t tmp;
		2070
		2071	tmp = RREG32(RADEON_CONFIG_MEMSIZE);
		2072	seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
		2073	tmp = RREG32(RADEON_MC_FB_LOCATION);
		2074	seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
		2075	tmp = RREG32(RADEON_BUS_CNTL);
		2076	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
		2077	tmp = RREG32(RADEON_MC_AGP_LOCATION);
		2078	seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
		2079	tmp = RREG32(RADEON_AGP_BASE);
		2080	seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
		2081	tmp = RREG32(RADEON_HOST_PATH_CNTL);
		2082	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
		2083	tmp = RREG32(0x01D0);
		2084	seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
		2085	tmp = RREG32(RADEON_AIC_LO_ADDR);
		2086	seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
		2087	tmp = RREG32(RADEON_AIC_HI_ADDR);
		2088	seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
		2089	tmp = RREG32(0x01E4);
		2090	seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
		2091	return 0;
		2092	}
		2093
		2094	static struct drm_info_list r100_debugfs_rbbm_list[] = {
		2095	{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
		2096	};
		2097
		2098	static struct drm_info_list r100_debugfs_cp_list[] = {
		2099	{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
		2100	{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
		2101	};
		2102
		2103	static struct drm_info_list r100_debugfs_mc_info_list[] = {
		2104	{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
		2105	};
		2106	#endif
		2107
		2108	int r100_debugfs_rbbm_init(struct radeon_device *rdev)
		2109	{
		2110	#if defined(CONFIG_DEBUG_FS)
		2111	return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
		2112	#else
		2113	return 0;
		2114	#endif
		2115	}
		2116
		2117	int r100_debugfs_cp_init(struct radeon_device *rdev)
		2118	{
		2119	#if defined(CONFIG_DEBUG_FS)
		2120	return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
		2121	#else
		2122	return 0;
		2123	#endif
		2124	}
		2125
		2126	int r100_debugfs_mc_info_init(struct radeon_device *rdev)
		2127	{
		2128	#if defined(CONFIG_DEBUG_FS)
		2129	return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
		2130	#else
		2131	return 0;
		2132	#endif
		2133	}
1179	serge	2134
		2135	int r100_set_surface_reg(struct radeon_device *rdev, int reg,
		2136	uint32_t tiling_flags, uint32_t pitch,
		2137	uint32_t offset, uint32_t obj_size)
		2138	{
		2139	int surf_index = reg * 16;
		2140	int flags = 0;
		2141
		2142	/* r100/r200 divide by 16 */
		2143	if (rdev->family < CHIP_R300)
		2144	flags = pitch / 16;
		2145	else
		2146	flags = pitch / 8;
		2147
		2148	if (rdev->family <= CHIP_RS200) {
		2149	if ((tiling_flags & (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2150	== (RADEON_TILING_MACRO\|RADEON_TILING_MICRO))
		2151	flags \|= RADEON_SURF_TILE_COLOR_BOTH;
		2152	if (tiling_flags & RADEON_TILING_MACRO)
		2153	flags \|= RADEON_SURF_TILE_COLOR_MACRO;
		2154	} else if (rdev->family <= CHIP_RV280) {
		2155	if (tiling_flags & (RADEON_TILING_MACRO))
		2156	flags \|= R200_SURF_TILE_COLOR_MACRO;
		2157	if (tiling_flags & RADEON_TILING_MICRO)
		2158	flags \|= R200_SURF_TILE_COLOR_MICRO;
		2159	} else {
		2160	if (tiling_flags & RADEON_TILING_MACRO)
		2161	flags \|= R300_SURF_TILE_MACRO;
		2162	if (tiling_flags & RADEON_TILING_MICRO)
		2163	flags \|= R300_SURF_TILE_MICRO;
		2164	}
		2165
		2166	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
		2167	flags \|= RADEON_SURF_AP0_SWP_16BPP \| RADEON_SURF_AP1_SWP_16BPP;
		2168	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
		2169	flags \|= RADEON_SURF_AP0_SWP_32BPP \| RADEON_SURF_AP1_SWP_32BPP;
		2170
		2171	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
		2172	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
		2173	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
		2174	WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
		2175	return 0;
		2176	}
		2177
		2178	void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
		2179	{
		2180	int surf_index = reg * 16;
		2181	WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
		2182	}
		2183
		2184	void r100_bandwidth_update(struct radeon_device *rdev)
		2185	{
		2186	fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
		2187	fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
		2188	fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
		2189	uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
		2190	fixed20_12 memtcas_ff[8] = {
		2191	fixed_init(1),
		2192	fixed_init(2),
		2193	fixed_init(3),
		2194	fixed_init(0),
		2195	fixed_init_half(1),
		2196	fixed_init_half(2),
		2197	fixed_init(0),
		2198	};
		2199	fixed20_12 memtcas_rs480_ff[8] = {
		2200	fixed_init(0),
		2201	fixed_init(1),
		2202	fixed_init(2),
		2203	fixed_init(3),
		2204	fixed_init(0),
		2205	fixed_init_half(1),
		2206	fixed_init_half(2),
		2207	fixed_init_half(3),
		2208	};
		2209	fixed20_12 memtcas2_ff[8] = {
		2210	fixed_init(0),
		2211	fixed_init(1),
		2212	fixed_init(2),
		2213	fixed_init(3),
		2214	fixed_init(4),
		2215	fixed_init(5),
		2216	fixed_init(6),
		2217	fixed_init(7),
		2218	};
		2219	fixed20_12 memtrbs[8] = {
		2220	fixed_init(1),
		2221	fixed_init_half(1),
		2222	fixed_init(2),
		2223	fixed_init_half(2),
		2224	fixed_init(3),
		2225	fixed_init_half(3),
		2226	fixed_init(4),
		2227	fixed_init_half(4)
		2228	};
		2229	fixed20_12 memtrbs_r4xx[8] = {
		2230	fixed_init(4),
		2231	fixed_init(5),
		2232	fixed_init(6),
		2233	fixed_init(7),
		2234	fixed_init(8),
		2235	fixed_init(9),
		2236	fixed_init(10),
		2237	fixed_init(11)
		2238	};
		2239	fixed20_12 min_mem_eff;
		2240	fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
		2241	fixed20_12 cur_latency_mclk, cur_latency_sclk;
		2242	fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
		2243	disp_drain_rate2, read_return_rate;
		2244	fixed20_12 time_disp1_drop_priority;
		2245	int c;
		2246	int cur_size = 16; /* in octawords */
		2247	int critical_point = 0, critical_point2;
		2248	/* uint32_t read_return_rate, time_disp1_drop_priority; */
		2249	int stop_req, max_stop_req;
		2250	struct drm_display_mode *mode1 = NULL;
		2251	struct drm_display_mode *mode2 = NULL;
		2252	uint32_t pixel_bytes1 = 0;
		2253	uint32_t pixel_bytes2 = 0;
		2254
		2255	if (rdev->mode_info.crtcs[0]->base.enabled) {
		2256	mode1 = &rdev->mode_info.crtcs[0]->base.mode;
		2257	pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
		2258	}
1221	serge	2259	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
1179	serge	2260	if (rdev->mode_info.crtcs[1]->base.enabled) {
		2261	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
		2262	pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
		2263	}
1221	serge	2264	}
1179	serge	2265
		2266	min_mem_eff.full = rfixed_const_8(0);
		2267	/* get modes */
		2268	if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
		2269	uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
		2270	mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2271	mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2272	/* check crtc enables */
		2273	if (mode2)
		2274	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
		2275	if (mode1)
		2276	mc_init_misc_lat_timer \|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
		2277	WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
		2278	}
		2279
		2280	/*
		2281	* determine is there is enough bw for current mode
		2282	*/
		2283	mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
		2284	temp_ff.full = rfixed_const(100);
		2285	mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
		2286	sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
		2287	sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
		2288
		2289	temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
		2290	temp_ff.full = rfixed_const(temp);
		2291	mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
		2292
		2293	pix_clk.full = 0;
		2294	pix_clk2.full = 0;
		2295	peak_disp_bw.full = 0;
		2296	if (mode1) {
		2297	temp_ff.full = rfixed_const(1000);
		2298	pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
		2299	pix_clk.full = rfixed_div(pix_clk, temp_ff);
		2300	temp_ff.full = rfixed_const(pixel_bytes1);
		2301	peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
		2302	}
		2303	if (mode2) {
		2304	temp_ff.full = rfixed_const(1000);
		2305	pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
		2306	pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
		2307	temp_ff.full = rfixed_const(pixel_bytes2);
		2308	peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
		2309	}
		2310
		2311	mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
		2312	if (peak_disp_bw.full >= mem_bw.full) {
		2313	DRM_ERROR("You may not have enough display bandwidth for current mode\n"
		2314	"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
		2315	}
		2316
		2317	/* Get values from the EXT_MEM_CNTL register...converting its contents. */
		2318	temp = RREG32(RADEON_MEM_TIMING_CNTL);
		2319	if ((rdev->family == CHIP_RV100) \|\| (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
		2320	mem_trcd = ((temp >> 2) & 0x3) + 1;
		2321	mem_trp = ((temp & 0x3)) + 1;
		2322	mem_tras = ((temp & 0x70) >> 4) + 1;
		2323	} else if (rdev->family == CHIP_R300 \|\|
		2324	rdev->family == CHIP_R350) { /* r300, r350 */
		2325	mem_trcd = (temp & 0x7) + 1;
		2326	mem_trp = ((temp >> 8) & 0x7) + 1;
		2327	mem_tras = ((temp >> 11) & 0xf) + 4;
		2328	} else if (rdev->family == CHIP_RV350 \|\|
		2329	rdev->family <= CHIP_RV380) {
		2330	/* rv3x0 */
		2331	mem_trcd = (temp & 0x7) + 3;
		2332	mem_trp = ((temp >> 8) & 0x7) + 3;
		2333	mem_tras = ((temp >> 11) & 0xf) + 6;
		2334	} else if (rdev->family == CHIP_R420 \|\|
		2335	rdev->family == CHIP_R423 \|\|
		2336	rdev->family == CHIP_RV410) {
		2337	/* r4xx */
		2338	mem_trcd = (temp & 0xf) + 3;
		2339	if (mem_trcd > 15)
		2340	mem_trcd = 15;
		2341	mem_trp = ((temp >> 8) & 0xf) + 3;
		2342	if (mem_trp > 15)
		2343	mem_trp = 15;
		2344	mem_tras = ((temp >> 12) & 0x1f) + 6;
		2345	if (mem_tras > 31)
		2346	mem_tras = 31;
		2347	} else { /* RV200, R200 */
		2348	mem_trcd = (temp & 0x7) + 1;
		2349	mem_trp = ((temp >> 8) & 0x7) + 1;
		2350	mem_tras = ((temp >> 12) & 0xf) + 4;
		2351	}
		2352	/* convert to FF */
		2353	trcd_ff.full = rfixed_const(mem_trcd);
		2354	trp_ff.full = rfixed_const(mem_trp);
		2355	tras_ff.full = rfixed_const(mem_tras);
		2356
		2357	/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
		2358	temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2359	data = (temp & (7 << 20)) >> 20;
		2360	if ((rdev->family == CHIP_RV100) \|\| rdev->flags & RADEON_IS_IGP) {
		2361	if (rdev->family == CHIP_RS480) /* don't think rs400 */
		2362	tcas_ff = memtcas_rs480_ff[data];
		2363	else
		2364	tcas_ff = memtcas_ff[data];
		2365	} else
		2366	tcas_ff = memtcas2_ff[data];
		2367
		2368	if (rdev->family == CHIP_RS400 \|\|
		2369	rdev->family == CHIP_RS480) {
		2370	/* extra cas latency stored in bits 23-25 0-4 clocks */
		2371	data = (temp >> 23) & 0x7;
		2372	if (data < 5)
		2373	tcas_ff.full += rfixed_const(data);
		2374	}
		2375
		2376	if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
		2377	/* on the R300, Tcas is included in Trbs.
		2378	*/
		2379	temp = RREG32(RADEON_MEM_CNTL);
		2380	data = (R300_MEM_NUM_CHANNELS_MASK & temp);
		2381	if (data == 1) {
		2382	if (R300_MEM_USE_CD_CH_ONLY & temp) {
		2383	temp = RREG32(R300_MC_IND_INDEX);
		2384	temp &= ~R300_MC_IND_ADDR_MASK;
		2385	temp \|= R300_MC_READ_CNTL_CD_mcind;
		2386	WREG32(R300_MC_IND_INDEX, temp);
		2387	temp = RREG32(R300_MC_IND_DATA);
		2388	data = (R300_MEM_RBS_POSITION_C_MASK & temp);
		2389	} else {
		2390	temp = RREG32(R300_MC_READ_CNTL_AB);
		2391	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2392	}
		2393	} else {
		2394	temp = RREG32(R300_MC_READ_CNTL_AB);
		2395	data = (R300_MEM_RBS_POSITION_A_MASK & temp);
		2396	}
		2397	if (rdev->family == CHIP_RV410 \|\|
		2398	rdev->family == CHIP_R420 \|\|
		2399	rdev->family == CHIP_R423)
		2400	trbs_ff = memtrbs_r4xx[data];
		2401	else
		2402	trbs_ff = memtrbs[data];
		2403	tcas_ff.full += trbs_ff.full;
		2404	}
		2405
		2406	sclk_eff_ff.full = sclk_ff.full;
		2407
		2408	if (rdev->flags & RADEON_IS_AGP) {
		2409	fixed20_12 agpmode_ff;
		2410	agpmode_ff.full = rfixed_const(radeon_agpmode);
		2411	temp_ff.full = rfixed_const_666(16);
		2412	sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
		2413	}
		2414	/* TODO PCIE lanes may affect this - agpmode == 16?? */
		2415
		2416	if (ASIC_IS_R300(rdev)) {
		2417	sclk_delay_ff.full = rfixed_const(250);
		2418	} else {
		2419	if ((rdev->family == CHIP_RV100) \|\|
		2420	rdev->flags & RADEON_IS_IGP) {
		2421	if (rdev->mc.vram_is_ddr)
		2422	sclk_delay_ff.full = rfixed_const(41);
		2423	else
		2424	sclk_delay_ff.full = rfixed_const(33);
		2425	} else {
		2426	if (rdev->mc.vram_width == 128)
		2427	sclk_delay_ff.full = rfixed_const(57);
		2428	else
		2429	sclk_delay_ff.full = rfixed_const(41);
		2430	}
		2431	}
		2432
		2433	mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
		2434
		2435	if (rdev->mc.vram_is_ddr) {
		2436	if (rdev->mc.vram_width == 32) {
		2437	k1.full = rfixed_const(40);
		2438	c = 3;
		2439	} else {
		2440	k1.full = rfixed_const(20);
		2441	c = 1;
		2442	}
		2443	} else {
		2444	k1.full = rfixed_const(40);
		2445	c = 3;
		2446	}
		2447
		2448	temp_ff.full = rfixed_const(2);
		2449	mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
		2450	temp_ff.full = rfixed_const(c);
		2451	mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
		2452	temp_ff.full = rfixed_const(4);
		2453	mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
		2454	mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
		2455	mc_latency_mclk.full += k1.full;
		2456
		2457	mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
		2458	mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
		2459
		2460	/*
		2461	HW cursor time assuming worst case of full size colour cursor.
		2462	*/
		2463	temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
		2464	temp_ff.full += trcd_ff.full;
		2465	if (temp_ff.full < tras_ff.full)
		2466	temp_ff.full = tras_ff.full;
		2467	cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
		2468
		2469	temp_ff.full = rfixed_const(cur_size);
		2470	cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
		2471	/*
		2472	Find the total latency for the display data.
		2473	*/
1268	serge	2474	disp_latency_overhead.full = rfixed_const(8);
1179	serge	2475	disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
		2476	mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
		2477	mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
		2478
		2479	if (mc_latency_mclk.full > mc_latency_sclk.full)
		2480	disp_latency.full = mc_latency_mclk.full;
		2481	else
		2482	disp_latency.full = mc_latency_sclk.full;
		2483
		2484	/* setup Max GRPH_STOP_REQ default value */
		2485	if (ASIC_IS_RV100(rdev))
		2486	max_stop_req = 0x5c;
		2487	else
		2488	max_stop_req = 0x7c;
		2489
		2490	if (mode1) {
		2491	/* CRTC1
		2492	Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
		2493	GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
		2494	*/
		2495	stop_req = mode1->hdisplay * pixel_bytes1 / 16;
		2496
		2497	if (stop_req > max_stop_req)
		2498	stop_req = max_stop_req;
		2499
		2500	/*
		2501	Find the drain rate of the display buffer.
		2502	*/
		2503	temp_ff.full = rfixed_const((16/pixel_bytes1));
		2504	disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
		2505
		2506	/*
		2507	Find the critical point of the display buffer.
		2508	*/
		2509	crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
		2510	crit_point_ff.full += rfixed_const_half(0);
		2511
		2512	critical_point = rfixed_trunc(crit_point_ff);
		2513
		2514	if (rdev->disp_priority == 2) {
		2515	critical_point = 0;
		2516	}
		2517
		2518	/*
		2519	The critical point should never be above max_stop_req-4. Setting
		2520	GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
		2521	*/
		2522	if (max_stop_req - critical_point < 4)
		2523	critical_point = 0;
		2524
		2525	if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
		2526	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
		2527	critical_point = 0x10;
		2528	}
		2529
		2530	temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
		2531	temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2532	temp \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2533	temp &= ~(RADEON_GRPH_START_REQ_MASK);
		2534	if ((rdev->family == CHIP_R350) &&
		2535	(stop_req > 0x15)) {
		2536	stop_req -= 0x10;
		2537	}
		2538	temp \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2539	temp \|= RADEON_GRPH_BUFFER_SIZE;
		2540	temp &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2541	RADEON_GRPH_CRITICAL_AT_SOF \|
		2542	RADEON_GRPH_STOP_CNTL);
		2543	/*
		2544	Write the result into the register.
		2545	*/
		2546	WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2547	(critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2548
		2549	#if 0
		2550	if ((rdev->family == CHIP_RS400) \|\|
		2551	(rdev->family == CHIP_RS480)) {
		2552	/* attempt to program RS400 disp regs correctly ??? */
		2553	temp = RREG32(RS400_DISP1_REG_CNTL);
		2554	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK \|
		2555	RS400_DISP1_STOP_REQ_LEVEL_MASK);
		2556	WREG32(RS400_DISP1_REQ_CNTL1, (temp \|
		2557	(critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2558	(critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2559	temp = RREG32(RS400_DMIF_MEM_CNTL1);
		2560	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK \|
		2561	RS400_DISP1_CRITICAL_POINT_STOP_MASK);
		2562	WREG32(RS400_DMIF_MEM_CNTL1, (temp \|
		2563	(critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) \|
		2564	(critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
		2565	}
		2566	#endif
		2567
		2568	DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
		2569	/* (unsigned int)info->SavedReg->grph_buffer_cntl, */
		2570	(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
		2571	}
		2572
		2573	if (mode2) {
		2574	u32 grph2_cntl;
		2575	stop_req = mode2->hdisplay * pixel_bytes2 / 16;
		2576
		2577	if (stop_req > max_stop_req)
		2578	stop_req = max_stop_req;
		2579
		2580	/*
		2581	Find the drain rate of the display buffer.
		2582	*/
		2583	temp_ff.full = rfixed_const((16/pixel_bytes2));
		2584	disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
		2585
		2586	grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
		2587	grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
		2588	grph2_cntl \|= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
		2589	grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
		2590	if ((rdev->family == CHIP_R350) &&
		2591	(stop_req > 0x15)) {
		2592	stop_req -= 0x10;
		2593	}
		2594	grph2_cntl \|= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
		2595	grph2_cntl \|= RADEON_GRPH_BUFFER_SIZE;
		2596	grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL \|
		2597	RADEON_GRPH_CRITICAL_AT_SOF \|
		2598	RADEON_GRPH_STOP_CNTL);
		2599
		2600	if ((rdev->family == CHIP_RS100) \|\|
		2601	(rdev->family == CHIP_RS200))
		2602	critical_point2 = 0;
		2603	else {
		2604	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
		2605	temp_ff.full = rfixed_const(temp);
		2606	temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
		2607	if (sclk_ff.full < temp_ff.full)
		2608	temp_ff.full = sclk_ff.full;
		2609
		2610	read_return_rate.full = temp_ff.full;
		2611
		2612	if (mode1) {
		2613	temp_ff.full = read_return_rate.full - disp_drain_rate.full;
		2614	time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
		2615	} else {
		2616	time_disp1_drop_priority.full = 0;
		2617	}
		2618	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
		2619	crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
		2620	crit_point_ff.full += rfixed_const_half(0);
		2621
		2622	critical_point2 = rfixed_trunc(crit_point_ff);
		2623
		2624	if (rdev->disp_priority == 2) {
		2625	critical_point2 = 0;
		2626	}
		2627
		2628	if (max_stop_req - critical_point2 < 4)
		2629	critical_point2 = 0;
		2630
		2631	}
		2632
		2633	if (critical_point2 == 0 && rdev->family == CHIP_R300) {
		2634	/* some R300 cards have problem with this set to 0 */
		2635	critical_point2 = 0x10;
		2636	}
		2637
		2638	WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) \|
		2639	(critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
		2640
		2641	if ((rdev->family == CHIP_RS400) \|\|
		2642	(rdev->family == CHIP_RS480)) {
		2643	#if 0
		2644	/* attempt to program RS400 disp2 regs correctly ??? */
		2645	temp = RREG32(RS400_DISP2_REQ_CNTL1);
		2646	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK \|
		2647	RS400_DISP2_STOP_REQ_LEVEL_MASK);
		2648	WREG32(RS400_DISP2_REQ_CNTL1, (temp \|
		2649	(critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) \|
		2650	(critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
		2651	temp = RREG32(RS400_DISP2_REQ_CNTL2);
		2652	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK \|
		2653	RS400_DISP2_CRITICAL_POINT_STOP_MASK);
		2654	WREG32(RS400_DISP2_REQ_CNTL2, (temp \|
		2655	(critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) \|
		2656	(critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
		2657	#endif
		2658	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
		2659	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
		2660	WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
		2661	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
		2662	}
		2663
		2664	DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
		2665	(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
		2666	}
		2667	}
		2668
		2669
		2670
		2671
		2672	void r100_mc_stop(struct radeon_device rdev, struct r100_mc_save save)
		2673	{
		2674	/* Shutdown CP we shouldn't need to do that but better be safe than
		2675	* sorry
		2676	*/
		2677	rdev->cp.ready = false;
		2678	WREG32(R_000740_CP_CSQ_CNTL, 0);
		2679
		2680	/* Save few CRTC registers */
1221	serge	2681	save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
1179	serge	2682	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
		2683	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
		2684	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
		2685	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2686	save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
		2687	save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
		2688	}
		2689
		2690	/* Disable VGA aperture access */
1221	serge	2691	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
1179	serge	2692	/* Disable cursor, overlay, crtc */
		2693	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET \| S_000260_CUR_LOCK(1));
		2694	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL \|
		2695	S_000054_CRTC_DISPLAY_DIS(1));
		2696	WREG32(R_000050_CRTC_GEN_CNTL,
		2697	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) \|
		2698	S_000050_CRTC_DISP_REQ_EN_B(1));
		2699	WREG32(R_000420_OV0_SCALE_CNTL,
		2700	C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
		2701	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
		2702	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2703	WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET \|
		2704	S_000360_CUR2_LOCK(1));
		2705	WREG32(R_0003F8_CRTC2_GEN_CNTL,
		2706	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) \|
		2707	S_0003F8_CRTC2_DISPLAY_DIS(1) \|
		2708	S_0003F8_CRTC2_DISP_REQ_EN_B(1));
		2709	WREG32(R_000360_CUR2_OFFSET,
		2710	C_000360_CUR2_LOCK & save->CUR2_OFFSET);
		2711	}
		2712	}
		2713
		2714	void r100_mc_resume(struct radeon_device rdev, struct r100_mc_save save)
		2715	{
		2716	/* Update base address for crtc */
		2717	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
		2718	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2719	WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
		2720	rdev->mc.vram_location);
		2721	}
		2722	/* Restore CRTC registers */
1221	serge	2723	WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
1179	serge	2724	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
		2725	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
		2726	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		2727	WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
		2728	}
		2729	}
		2730
1221	serge	2731	void r100_vga_render_disable(struct radeon_device *rdev)
		2732	{
		2733	u32 tmp;
		2734
		2735	tmp = RREG8(R_0003C2_GENMO_WT);
		2736	WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
		2737	}
		2738
		2739	static void r100_debugfs(struct radeon_device *rdev)
		2740	{
		2741	int r;
		2742
		2743	r = r100_debugfs_mc_info_init(rdev);
		2744	if (r)
		2745	dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
		2746	}
		2747
		2748
1179	serge	2749	int drm_order(unsigned long size)
		2750	{
		2751	int order;
		2752	unsigned long tmp;
		2753
		2754	for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
		2755
		2756	if (size & (size - 1))
		2757	++order;
		2758
		2759	return order;
		2760	}
		2761
1221	serge	2762	static void r100_mc_program(struct radeon_device *rdev)
		2763	{
		2764	struct r100_mc_save save;
		2765
		2766	/* Stops all mc clients */
		2767	r100_mc_stop(rdev, &save);
		2768	if (rdev->flags & RADEON_IS_AGP) {
		2769	WREG32(R_00014C_MC_AGP_LOCATION,
		2770	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
		2771	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		2772	WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		2773	if (rdev->family > CHIP_RV200)
		2774	WREG32(R_00015C_AGP_BASE_2,
		2775	upper_32_bits(rdev->mc.agp_base) & 0xff);
		2776	} else {
		2777	WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
		2778	WREG32(R_000170_AGP_BASE, 0);
		2779	if (rdev->family > CHIP_RV200)
		2780	WREG32(R_00015C_AGP_BASE_2, 0);
		2781	}
		2782	/* Wait for mc idle */
		2783	if (r100_mc_wait_for_idle(rdev))
		2784	dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
		2785	/* Program MC, should be a 32bits limited address space */
		2786	WREG32(R_000148_MC_FB_LOCATION,
		2787	S_000148_MC_FB_START(rdev->mc.vram_start >> 16) \|
		2788	S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
		2789	r100_mc_resume(rdev, &save);
		2790	}
		2791
		2792	void r100_clock_startup(struct radeon_device *rdev)
		2793	{
		2794	u32 tmp;
		2795
		2796	if (radeon_dynclks != -1 && radeon_dynclks)
		2797	radeon_legacy_set_clock_gating(rdev, 1);
		2798	/* We need to force on some of the block */
		2799	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
		2800	tmp \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
		2801	if ((rdev->family == CHIP_RV250) \|\| (rdev->family == CHIP_RV280))
		2802	tmp \|= S_00000D_FORCE_DISP1(1) \| S_00000D_FORCE_DISP2(1);
		2803	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
		2804	}
		2805
		2806	static int r100_startup(struct radeon_device *rdev)
		2807	{
		2808	int r;
		2809
1321	serge	2810	/* set common regs */
		2811	r100_set_common_regs(rdev);
		2812	/* program mc */
1221	serge	2813	r100_mc_program(rdev);
		2814	/* Resume clock */
		2815	r100_clock_startup(rdev);
		2816	/* Initialize GPU configuration (# pipes, ...) */
		2817	r100_gpu_init(rdev);
		2818	/* Initialize GART (initialize after TTM so we can allocate
		2819	* memory through TTM but finalize after TTM) */
1321	serge	2820	r100_enable_bm(rdev);
1221	serge	2821	if (rdev->flags & RADEON_IS_PCI) {
		2822	r = r100_pci_gart_enable(rdev);
		2823	if (r)
		2824	return r;
		2825	}
		2826	/* Enable IRQ */
		2827	// r100_irq_set(rdev);
1404	serge	2828	rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1221	serge	2829	/* 1M ring buffer */
		2830	// r = r100_cp_init(rdev, 1024 * 1024);
		2831	// if (r) {
		2832	// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		2833	// return r;
		2834	// }
		2835	// r = r100_wb_init(rdev);
		2836	// if (r)
		2837	// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
		2838	// r = r100_ib_init(rdev);
		2839	// if (r) {
		2840	// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		2841	// return r;
		2842	// }
		2843	return 0;
		2844	}
		2845
		2846
		2847	int r100_mc_init(struct radeon_device *rdev)
		2848	{
		2849	int r;
		2850	u32 tmp;
		2851
		2852	/* Setup GPU memory space */
		2853	rdev->mc.vram_location = 0xFFFFFFFFUL;
		2854	rdev->mc.gtt_location = 0xFFFFFFFFUL;
		2855	if (rdev->flags & RADEON_IS_IGP) {
		2856	tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
		2857	rdev->mc.vram_location = tmp << 16;
		2858	}
		2859	if (rdev->flags & RADEON_IS_AGP) {
		2860	r = radeon_agp_init(rdev);
		2861	if (r) {
1403	serge	2862	radeon_agp_disable(rdev);
1221	serge	2863	} else {
		2864	rdev->mc.gtt_location = rdev->mc.agp_base;
		2865	}
		2866	}
		2867	r = radeon_mc_setup(rdev);
		2868	if (r)
		2869	return r;
		2870	return 0;
		2871	}
		2872
		2873	int r100_init(struct radeon_device *rdev)
		2874	{
		2875	int r;
		2876
		2877	/* Register debugfs file specific to this group of asics */
		2878	r100_debugfs(rdev);
		2879	/* Disable VGA */
		2880	r100_vga_render_disable(rdev);
		2881	/* Initialize scratch registers */
		2882	radeon_scratch_init(rdev);
		2883	/* Initialize surface registers */
		2884	radeon_surface_init(rdev);
		2885	/* TODO: disable VGA need to use VGA request */
		2886	/* BIOS*/
		2887	if (!radeon_get_bios(rdev)) {
		2888	if (ASIC_IS_AVIVO(rdev))
		2889	return -EINVAL;
		2890	}
		2891	if (rdev->is_atom_bios) {
		2892	dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
		2893	return -EINVAL;
		2894	} else {
		2895	r = radeon_combios_init(rdev);
		2896	if (r)
		2897	return r;
		2898	}
		2899	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
		2900	if (radeon_gpu_reset(rdev)) {
		2901	dev_warn(rdev->dev,
		2902	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
		2903	RREG32(R_000E40_RBBM_STATUS),
		2904	RREG32(R_0007C0_CP_STAT));
		2905	}
		2906	/* check if cards are posted or not */
1321	serge	2907	if (radeon_boot_test_post_card(rdev) == false)
		2908	return -EINVAL;
1221	serge	2909	/* Set asic errata */
		2910	r100_errata(rdev);
		2911	/* Initialize clocks */
		2912	radeon_get_clock_info(rdev->ddev);
1403	serge	2913	/* Initialize power management */
		2914	radeon_pm_init(rdev);
1221	serge	2915	/* Get vram informations */
		2916	r100_vram_info(rdev);
		2917	/* Initialize memory controller (also test AGP) */
		2918	r = r100_mc_init(rdev);
1246	serge	2919	dbgprintf("mc vram location %x\n", rdev->mc.vram_location);
1221	serge	2920	if (r)
		2921	return r;
		2922	/* Fence driver */
		2923	// r = radeon_fence_driver_init(rdev);
		2924	// if (r)
		2925	// return r;
		2926	// r = radeon_irq_kms_init(rdev);
		2927	// if (r)
		2928	// return r;
		2929	/* Memory manager */
1321	serge	2930	r = radeon_bo_init(rdev);
1221	serge	2931	if (r)
		2932	return r;
		2933	if (rdev->flags & RADEON_IS_PCI) {
		2934	r = r100_pci_gart_init(rdev);
		2935	if (r)
		2936	return r;
		2937	}
		2938	r100_set_safe_registers(rdev);
		2939	rdev->accel_working = true;
		2940	r = r100_startup(rdev);
		2941	if (r) {
		2942	/* Somethings want wront with the accel init stop accel */
		2943	dev_err(rdev->dev, "Disabling GPU acceleration\n");
		2944	// r100_suspend(rdev);
		2945	// r100_cp_fini(rdev);
		2946	// r100_wb_fini(rdev);
		2947	// r100_ib_fini(rdev);
		2948	if (rdev->flags & RADEON_IS_PCI)
		2949	r100_pci_gart_fini(rdev);
		2950	// radeon_irq_kms_fini(rdev);
		2951	rdev->accel_working = false;
		2952	}
		2953	return 0;
		2954	}

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(root)/drivers/video/drm/radeon/r100.c – Rev 1404