WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/r100.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
		29	//#include "drmP.h"
		30	//#include "drm.h"
		31	#include "radeon_drm.h"
		32	#include "radeon_microcode.h"
		33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35
		36	/* This files gather functions specifics to:
		37	* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		38	*
		39	* Some of these functions might be used by newer ASICs.
		40	*/
		41	void r100_hdp_reset(struct radeon_device *rdev);
		42	void r100_gpu_init(struct radeon_device *rdev);
		43	int r100_gui_wait_for_idle(struct radeon_device *rdev);
		44	int r100_mc_wait_for_idle(struct radeon_device *rdev);
		45	void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
		46	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
		47	int r100_debugfs_mc_info_init(struct radeon_device *rdev);
		48
		49	#if 0
		50	/*
		51	* PCI GART
		52	*/
		53	void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
		54	{
		55	/* TODO: can we do somethings here ? */
		56	/* It seems hw only cache one entry so we should discard this
		57	* entry otherwise if first GPU GART read hit this entry it
		58	* could end up in wrong address. */
		59	}
		60
		61	int r100_pci_gart_enable(struct radeon_device *rdev)
		62	{
		63	uint32_t tmp;
		64	int r;
		65
		66	/* Initialize common gart structure */
		67	r = radeon_gart_init(rdev);
		68	if (r) {
		69	return r;
		70	}
		71	if (rdev->gart.table.ram.ptr == NULL) {
		72	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
		73	r = radeon_gart_table_ram_alloc(rdev);
		74	if (r) {
		75	return r;
		76	}
		77	}
		78	/* discard memory request outside of configured range */
		79	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		80	WREG32(RADEON_AIC_CNTL, tmp);
		81	/* set address range for PCI address translate */
		82	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
		83	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		84	WREG32(RADEON_AIC_HI_ADDR, tmp);
		85	/* Enable bus mastering */
		86	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		87	WREG32(RADEON_BUS_CNTL, tmp);
		88	/* set PCI GART page-table base address */
		89	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
		90	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_PCIGART_TRANSLATE_EN;
		91	WREG32(RADEON_AIC_CNTL, tmp);
		92	r100_pci_gart_tlb_flush(rdev);
		93	rdev->gart.ready = true;
		94	return 0;
		95	}
		96
		97	void r100_pci_gart_disable(struct radeon_device *rdev)
		98	{
		99	uint32_t tmp;
		100
		101	/* discard memory request outside of configured range */
		102	tmp = RREG32(RADEON_AIC_CNTL) \| RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
		103	WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
		104	WREG32(RADEON_AIC_LO_ADDR, 0);
		105	WREG32(RADEON_AIC_HI_ADDR, 0);
		106	}
		107
		108	int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
		109	{
		110	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
		111	return -EINVAL;
		112	}
		113	rdev->gart.table.ram.ptr[i] = cpu_to_le32((uint32_t)addr);
		114	return 0;
		115	}
		116
		117	int r100_gart_enable(struct radeon_device *rdev)
		118	{
		119	if (rdev->flags & RADEON_IS_AGP) {
		120	r100_pci_gart_disable(rdev);
		121	return 0;
		122	}
		123	return r100_pci_gart_enable(rdev);
		124	}
		125
		126
		127	/*
		128	* MC
		129	*/
		130	void r100_mc_disable_clients(struct radeon_device *rdev)
		131	{
		132	uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
		133
		134	/* FIXME: is this function correct for rs100,rs200,rs300 ? */
		135	// if (r100_gui_wait_for_idle(rdev)) {
		136	// printk(KERN_WARNING "Failed to wait GUI idle while "
		137	// "programming pipes. Bad things might happen.\n");
		138	// }
		139
		140	/* stop display and memory access */
		141	ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
		142	WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
		143	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		144	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl \| RADEON_CRTC_DISPLAY_DIS);
		145	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		146
		147	r100_gpu_wait_for_vsync(rdev);
		148
		149	WREG32(RADEON_CRTC_GEN_CNTL,
		150	(crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN \| RADEON_CRTC_ICON_EN)) \|
		151	RADEON_CRTC_DISP_REQ_EN_B \| RADEON_CRTC_EXT_DISP_EN);
		152
		153	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
		154	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		155
		156	r100_gpu_wait_for_vsync2(rdev);
		157	WREG32(RADEON_CRTC2_GEN_CNTL,
		158	(crtc2_gen_cntl &
		159	~(RADEON_CRTC2_CUR_EN \| RADEON_CRTC2_ICON_EN)) \|
		160	RADEON_CRTC2_DISP_REQ_EN_B);
		161	}
		162
		163	udelay(500);
		164	}
		165
		166	void r100_mc_setup(struct radeon_device *rdev)
		167	{
		168	uint32_t tmp;
		169	int r;
		170
		171	r = r100_debugfs_mc_info_init(rdev);
		172	if (r) {
		173	DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
		174	}
		175	/* Write VRAM size in case we are limiting it */
		176	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
		177	tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
		178	tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
		179	tmp \|= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
		180	WREG32(RADEON_MC_FB_LOCATION, tmp);
		181
		182	/* Enable bus mastering */
		183	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
		184	WREG32(RADEON_BUS_CNTL, tmp);
		185
		186	if (rdev->flags & RADEON_IS_AGP) {
		187	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		188	tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
		189	tmp \|= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
		190	WREG32(RADEON_MC_AGP_LOCATION, tmp);
		191	WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
		192	} else {
		193	WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
		194	WREG32(RADEON_AGP_BASE, 0);
		195	}
		196
		197	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		198	tmp \|= (7 << 28);
		199	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		200	(void)RREG32(RADEON_HOST_PATH_CNTL);
		201	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		202	(void)RREG32(RADEON_HOST_PATH_CNTL);
		203	}
		204
		205	int r100_mc_init(struct radeon_device *rdev)
		206	{
		207	int r;
		208
		209	if (r100_debugfs_rbbm_init(rdev)) {
		210	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
		211	}
		212
		213	r100_gpu_init(rdev);
		214	/* Disable gart which also disable out of gart access */
		215	r100_pci_gart_disable(rdev);
		216
		217	/* Setup GPU memory space */
		218	rdev->mc.vram_location = 0xFFFFFFFFUL;
		219	rdev->mc.gtt_location = 0xFFFFFFFFUL;
		220	if (rdev->flags & RADEON_IS_AGP) {
		221	r = radeon_agp_init(rdev);
		222	if (r) {
		223	printk(KERN_WARNING "[drm] Disabling AGP\n");
		224	rdev->flags &= ~RADEON_IS_AGP;
		225	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		226	} else {
		227	rdev->mc.gtt_location = rdev->mc.agp_base;
		228	}
		229	}
		230	r = radeon_mc_setup(rdev);
		231	if (r) {
		232	return r;
		233	}
		234
		235	r100_mc_disable_clients(rdev);
		236	if (r100_mc_wait_for_idle(rdev)) {
		237	printk(KERN_WARNING "Failed to wait MC idle while "
		238	"programming pipes. Bad things might happen.\n");
		239	}
		240
		241	r100_mc_setup(rdev);
		242	return 0;
		243	}
		244
		245	void r100_mc_fini(struct radeon_device *rdev)
		246	{
		247	r100_pci_gart_disable(rdev);
		248	radeon_gart_table_ram_free(rdev);
		249	radeon_gart_fini(rdev);
		250	}
		251
		252
		253	/*
		254	* Fence emission
		255	*/
		256	void r100_fence_ring_emit(struct radeon_device *rdev,
		257	struct radeon_fence *fence)
		258	{
		259	/* Who ever call radeon_fence_emit should call ring_lock and ask
		260	* for enough space (today caller are ib schedule and buffer move) */
		261	/* Wait until IDLE & CLEAN */
		262	radeon_ring_write(rdev, PACKET0(0x1720, 0));
		263	radeon_ring_write(rdev, (1 << 16) \| (1 << 17));
		264	/* Emit fence sequence & fire IRQ */
		265	radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
		266	radeon_ring_write(rdev, fence->seq);
		267	radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
		268	radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
		269	}
		270
		271
		272	/*
		273	* Writeback
		274	*/
		275	int r100_wb_init(struct radeon_device *rdev)
		276	{
		277	int r;
		278
		279	if (rdev->wb.wb_obj == NULL) {
		280	r = radeon_object_create(rdev, NULL, 4096,
		281	true,
		282	RADEON_GEM_DOMAIN_GTT,
		283	false, &rdev->wb.wb_obj);
		284	if (r) {
		285	DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
		286	return r;
		287	}
		288	r = radeon_object_pin(rdev->wb.wb_obj,
		289	RADEON_GEM_DOMAIN_GTT,
		290	&rdev->wb.gpu_addr);
		291	if (r) {
		292	DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
		293	return r;
		294	}
		295	r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
		296	if (r) {
		297	DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
		298	return r;
		299	}
		300	}
		301	WREG32(0x774, rdev->wb.gpu_addr);
		302	WREG32(0x70C, rdev->wb.gpu_addr + 1024);
		303	WREG32(0x770, 0xff);
		304	return 0;
		305	}
		306
		307	void r100_wb_fini(struct radeon_device *rdev)
		308	{
		309	if (rdev->wb.wb_obj) {
		310	radeon_object_kunmap(rdev->wb.wb_obj);
		311	radeon_object_unpin(rdev->wb.wb_obj);
		312	radeon_object_unref(&rdev->wb.wb_obj);
		313	rdev->wb.wb = NULL;
		314	rdev->wb.wb_obj = NULL;
		315	}
		316	}
		317
		318	int r100_copy_blit(struct radeon_device *rdev,
		319	uint64_t src_offset,
		320	uint64_t dst_offset,
		321	unsigned num_pages,
		322	struct radeon_fence *fence)
		323	{
		324	uint32_t cur_pages;
		325	uint32_t stride_bytes = PAGE_SIZE;
		326	uint32_t pitch;
		327	uint32_t stride_pixels;
		328	unsigned ndw;
		329	int num_loops;
		330	int r = 0;
		331
		332	/* radeon limited to 16k stride */
		333	stride_bytes &= 0x3fff;
		334	/* radeon pitch is /64 */
		335	pitch = stride_bytes / 64;
		336	stride_pixels = stride_bytes / 4;
		337	num_loops = DIV_ROUND_UP(num_pages, 8191);
		338
		339	/* Ask for enough room for blit + flush + fence */
		340	ndw = 64 + (10 * num_loops);
		341	r = radeon_ring_lock(rdev, ndw);
		342	if (r) {
		343	DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
		344	return -EINVAL;
		345	}
		346	while (num_pages > 0) {
		347	cur_pages = num_pages;
		348	if (cur_pages > 8191) {
		349	cur_pages = 8191;
		350	}
		351	num_pages -= cur_pages;
		352
		353	/* pages are in Y direction - height
		354	page width in X direction - width */
		355	radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
		356	radeon_ring_write(rdev,
		357	RADEON_GMC_SRC_PITCH_OFFSET_CNTL \|
		358	RADEON_GMC_DST_PITCH_OFFSET_CNTL \|
		359	RADEON_GMC_SRC_CLIPPING \|
		360	RADEON_GMC_DST_CLIPPING \|
		361	RADEON_GMC_BRUSH_NONE \|
		362	(RADEON_COLOR_FORMAT_ARGB8888 << 8) \|
		363	RADEON_GMC_SRC_DATATYPE_COLOR \|
		364	RADEON_ROP3_S \|
		365	RADEON_DP_SRC_SOURCE_MEMORY \|
		366	RADEON_GMC_CLR_CMP_CNTL_DIS \|
		367	RADEON_GMC_WR_MSK_DIS);
		368	radeon_ring_write(rdev, (pitch << 22) \| (src_offset >> 10));
		369	radeon_ring_write(rdev, (pitch << 22) \| (dst_offset >> 10));
		370	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		371	radeon_ring_write(rdev, 0);
		372	radeon_ring_write(rdev, (0x1fff) \| (0x1fff << 16));
		373	radeon_ring_write(rdev, num_pages);
		374	radeon_ring_write(rdev, num_pages);
		375	radeon_ring_write(rdev, cur_pages \| (stride_pixels << 16));
		376	}
		377	radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
		378	radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
		379	radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
		380	radeon_ring_write(rdev,
		381	RADEON_WAIT_2D_IDLECLEAN \|
		382	RADEON_WAIT_HOST_IDLECLEAN \|
		383	RADEON_WAIT_DMA_GUI_IDLE);
		384	if (fence) {
		385	r = radeon_fence_emit(rdev, fence);
		386	}
		387	radeon_ring_unlock_commit(rdev);
		388	return r;
		389	}
		390
		391
		392	/*
		393	* CP
		394	*/
		395	void r100_ring_start(struct radeon_device *rdev)
		396	{
		397	int r;
		398
		399	r = radeon_ring_lock(rdev, 2);
		400	if (r) {
		401	return;
		402	}
		403	radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
		404	radeon_ring_write(rdev,
		405	RADEON_ISYNC_ANY2D_IDLE3D \|
		406	RADEON_ISYNC_ANY3D_IDLE2D \|
		407	RADEON_ISYNC_WAIT_IDLEGUI \|
		408	RADEON_ISYNC_CPSCRATCH_IDLEGUI);
		409	radeon_ring_unlock_commit(rdev);
		410	}
		411
		412	#endif
		413
		414	static void r100_cp_load_microcode(struct radeon_device *rdev)
		415	{
		416	int i;
		417
		418	dbgprintf("%s\n\r",__FUNCTION__);
		419
		420	if (r100_gui_wait_for_idle(rdev)) {
		421	printk(KERN_WARNING "Failed to wait GUI idle while "
		422	"programming pipes. Bad things might happen.\n");
		423	}
		424
		425	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
		426	if ((rdev->family == CHIP_R100) \|\| (rdev->family == CHIP_RV100) \|\|
		427	(rdev->family == CHIP_RV200) \|\| (rdev->family == CHIP_RS100) \|\|
		428	(rdev->family == CHIP_RS200)) {
		429	DRM_INFO("Loading R100 Microcode\n");
		430	for (i = 0; i < 256; i++) {
		431	WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
		432	WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
		433	}
		434	} else if ((rdev->family == CHIP_R200) \|\|
		435	(rdev->family == CHIP_RV250) \|\|
		436	(rdev->family == CHIP_RV280) \|\|
		437	(rdev->family == CHIP_RS300)) {
		438	DRM_INFO("Loading R200 Microcode\n");
		439	for (i = 0; i < 256; i++) {
		440	WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
		441	WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
		442	}
		443	} else if ((rdev->family == CHIP_R300) \|\|
		444	(rdev->family == CHIP_R350) \|\|
		445	(rdev->family == CHIP_RV350) \|\|
		446	(rdev->family == CHIP_RV380) \|\|
		447	(rdev->family == CHIP_RS400) \|\|
		448	(rdev->family == CHIP_RS480)) {
		449	DRM_INFO("Loading R300 Microcode\n");
		450	for (i = 0; i < 256; i++) {
		451	WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
		452	WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
		453	}
		454	} else if ((rdev->family == CHIP_R420) \|\|
		455	(rdev->family == CHIP_R423) \|\|
		456	(rdev->family == CHIP_RV410)) {
		457	DRM_INFO("Loading R400 Microcode\n");
		458	for (i = 0; i < 256; i++) {
		459	WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
		460	WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
		461	}
		462	} else if ((rdev->family == CHIP_RS690) \|\|
		463	(rdev->family == CHIP_RS740)) {
		464	DRM_INFO("Loading RS690/RS740 Microcode\n");
		465	for (i = 0; i < 256; i++) {
		466	WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
		467	WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
		468	}
		469	} else if (rdev->family == CHIP_RS600) {
		470	DRM_INFO("Loading RS600 Microcode\n");
		471	for (i = 0; i < 256; i++) {
		472	WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
		473	WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
		474	}
		475	} else if ((rdev->family == CHIP_RV515) \|\|
		476	(rdev->family == CHIP_R520) \|\|
		477	(rdev->family == CHIP_RV530) \|\|
		478	(rdev->family == CHIP_R580) \|\|
		479	(rdev->family == CHIP_RV560) \|\|
		480	(rdev->family == CHIP_RV570)) {
		481	DRM_INFO("Loading R500 Microcode\n");
		482	for (i = 0; i < 256; i++) {
		483	WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
		484	WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
		485	}
		486	}
		487	}
		488
		489	int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		490	{
		491	unsigned rb_bufsz;
		492	unsigned rb_blksz;
		493	unsigned max_fetch;
		494	unsigned pre_write_timer;
		495	unsigned pre_write_limit;
		496	unsigned indirect2_start;
		497	unsigned indirect1_start;
		498	uint32_t tmp;
		499	int r;
		500
		501	dbgprintf("%s\n\r",__FUNCTION__);
		502
		503	// if (r100_debugfs_cp_init(rdev)) {
		504	// DRM_ERROR("Failed to register debugfs file for CP !\n");
		505	// }
		506	/* Reset CP */
		507	tmp = RREG32(RADEON_CP_CSQ_STAT);
		508	if ((tmp & (1 << 31))) {
		509	DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
		510	WREG32(RADEON_CP_CSQ_MODE, 0);
		511	WREG32(RADEON_CP_CSQ_CNTL, 0);
		512	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		513	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		514	mdelay(2);
		515	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		516	tmp = RREG32(RADEON_RBBM_SOFT_RESET);
		517	mdelay(2);
		518	tmp = RREG32(RADEON_CP_CSQ_STAT);
		519	if ((tmp & (1 << 31))) {
		520	DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
		521	}
		522	} else {
		523	DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
		524	}
		525	/* Align ring size */
		526	rb_bufsz = drm_order(ring_size / 8);
		527	ring_size = (1 << (rb_bufsz + 1)) * 4;
		528	r100_cp_load_microcode(rdev);
		529	r = radeon_ring_init(rdev, ring_size);
		530	if (r) {
		531	return r;
		532	}
		533	/* Each time the cp read 1024 bytes (16 dword/quadword) update
		534	* the rptr copy in system ram */
		535	rb_blksz = 9;
		536	/* cp will read 128bytes at a time (4 dwords) */
		537	max_fetch = 1;
		538	rdev->cp.align_mask = 16 - 1;
		539	/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
		540	pre_write_timer = 64;
		541	/* Force CP_RB_WPTR write if written more than one time before the
		542	* delay expire
		543	*/
		544	pre_write_limit = 0;
		545	/* Setup the cp cache like this (cache size is 96 dwords) :
		546	* RING 0 to 15
		547	* INDIRECT1 16 to 79
		548	* INDIRECT2 80 to 95
		549	* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		550	* indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
		551	* indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
		552	* Idea being that most of the gpu cmd will be through indirect1 buffer
		553	* so it gets the bigger cache.
		554	*/
		555	indirect2_start = 80;
		556	indirect1_start = 16;
		557	/* cp setup */
		558	WREG32(0x718, pre_write_timer \| (pre_write_limit << 28));
		559	WREG32(RADEON_CP_RB_CNTL,
		560	#ifdef __BIG_ENDIAN
		561	RADEON_BUF_SWAP_32BIT \|
		562	#endif
		563	REG_SET(RADEON_RB_BUFSZ, rb_bufsz) \|
		564	REG_SET(RADEON_RB_BLKSZ, rb_blksz) \|
		565	REG_SET(RADEON_MAX_FETCH, max_fetch) \|
		566	RADEON_RB_NO_UPDATE);
		567	/* Set ring address */
		568	DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
		569	WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
		570	/* Force read & write ptr to 0 */
		571	tmp = RREG32(RADEON_CP_RB_CNTL);
		572	WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA);
		573	WREG32(RADEON_CP_RB_RPTR_WR, 0);
		574	WREG32(RADEON_CP_RB_WPTR, 0);
		575	WREG32(RADEON_CP_RB_CNTL, tmp);
		576	udelay(10);
		577	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
		578	rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
		579	/* Set cp mode to bus mastering & enable cp*/
		580	WREG32(RADEON_CP_CSQ_MODE,
		581	REG_SET(RADEON_INDIRECT2_START, indirect2_start) \|
		582	REG_SET(RADEON_INDIRECT1_START, indirect1_start));
		583	WREG32(0x718, 0);
		584	WREG32(0x744, 0x00004D4D);
		585	WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
		586	radeon_ring_start(rdev);
		587	r = radeon_ring_test(rdev);
		588	if (r) {
		589	DRM_ERROR("radeon: cp isn't working (%d).\n", r);
		590	return r;
		591	}
		592	rdev->cp.ready = true;
		593	return 0;
		594	}
		595
		596	#if 0
		597
		598	void r100_cp_fini(struct radeon_device *rdev)
		599	{
		600	/* Disable ring */
		601	rdev->cp.ready = false;
		602	WREG32(RADEON_CP_CSQ_CNTL, 0);
		603	radeon_ring_fini(rdev);
		604	DRM_INFO("radeon: cp finalized\n");
		605	}
		606
		607	void r100_cp_disable(struct radeon_device *rdev)
		608	{
		609	/* Disable ring */
		610	rdev->cp.ready = false;
		611	WREG32(RADEON_CP_CSQ_MODE, 0);
		612	WREG32(RADEON_CP_CSQ_CNTL, 0);
		613	if (r100_gui_wait_for_idle(rdev)) {
		614	printk(KERN_WARNING "Failed to wait GUI idle while "
		615	"programming pipes. Bad things might happen.\n");
		616	}
		617	}
		618
		619	#endif
		620
		621	int r100_cp_reset(struct radeon_device *rdev)
		622	{
		623	uint32_t tmp;
		624	bool reinit_cp;
		625	int i;
		626
		627	dbgprintf("%s\n\r",__FUNCTION__);
		628
		629
		630	reinit_cp = rdev->cp.ready;
		631	rdev->cp.ready = false;
		632	WREG32(RADEON_CP_CSQ_MODE, 0);
		633	WREG32(RADEON_CP_CSQ_CNTL, 0);
		634	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
		635	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		636	udelay(200);
		637	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		638	/* Wait to prevent race in RBBM_STATUS */
		639	mdelay(1);
		640	for (i = 0; i < rdev->usec_timeout; i++) {
		641	tmp = RREG32(RADEON_RBBM_STATUS);
		642	if (!(tmp & (1 << 16))) {
		643	DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
		644	tmp);
		645	if (reinit_cp) {
		646	return r100_cp_init(rdev, rdev->cp.ring_size);
		647	}
		648	return 0;
		649	}
		650	DRM_UDELAY(1);
		651	}
		652	tmp = RREG32(RADEON_RBBM_STATUS);
		653	DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
		654	return -1;
		655	}
		656
		657	#if 0
		658	/*
		659	* CS functions
		660	*/
		661	int r100_cs_parse_packet0(struct radeon_cs_parser *p,
		662	struct radeon_cs_packet *pkt,
		663	const unsigned *auth, unsigned n,
		664	radeon_packet0_check_t check)
		665	{
		666	unsigned reg;
		667	unsigned i, j, m;
		668	unsigned idx;
		669	int r;
		670
		671	idx = pkt->idx + 1;
		672	reg = pkt->reg;
		673	/* Check that register fall into register range
		674	* determined by the number of entry (n) in the
		675	* safe register bitmap.
		676	*/
		677	if (pkt->one_reg_wr) {
		678	if ((reg >> 7) > n) {
		679	return -EINVAL;
		680	}
		681	} else {
		682	if (((reg + (pkt->count << 2)) >> 7) > n) {
		683	return -EINVAL;
		684	}
		685	}
		686	for (i = 0; i <= pkt->count; i++, idx++) {
		687	j = (reg >> 7);
		688	m = 1 << ((reg >> 2) & 31);
		689	if (auth[j] & m) {
		690	r = check(p, pkt, idx, reg);
		691	if (r) {
		692	return r;
		693	}
		694	}
		695	if (pkt->one_reg_wr) {
		696	if (!(auth[j] & m)) {
		697	break;
		698	}
		699	} else {
		700	reg += 4;
		701	}
		702	}
		703	return 0;
		704	}
		705
		706	void r100_cs_dump_packet(struct radeon_cs_parser *p,
		707	struct radeon_cs_packet *pkt)
		708	{
		709	struct radeon_cs_chunk *ib_chunk;
		710	volatile uint32_t *ib;
		711	unsigned i;
		712	unsigned idx;
		713
		714	ib = p->ib->ptr;
		715	ib_chunk = &p->chunks[p->chunk_ib_idx];
		716	idx = pkt->idx;
		717	for (i = 0; i <= (pkt->count + 1); i++, idx++) {
		718	DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
		719	}
		720	}
		721
		722	/**
		723	* r100_cs_packet_parse() - parse cp packet and point ib index to next packet
		724	* @parser: parser structure holding parsing context.
		725	* @pkt: where to store packet informations
		726	*
		727	* Assume that chunk_ib_index is properly set. Will return -EINVAL
		728	* if packet is bigger than remaining ib size. or if packets is unknown.
		729	**/
		730	int r100_cs_packet_parse(struct radeon_cs_parser *p,
		731	struct radeon_cs_packet *pkt,
		732	unsigned idx)
		733	{
		734	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
		735	uint32_t header = ib_chunk->kdata[idx];
		736
		737	if (idx >= ib_chunk->length_dw) {
		738	DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
		739	idx, ib_chunk->length_dw);
		740	return -EINVAL;
		741	}
		742	pkt->idx = idx;
		743	pkt->type = CP_PACKET_GET_TYPE(header);
		744	pkt->count = CP_PACKET_GET_COUNT(header);
		745	switch (pkt->type) {
		746	case PACKET_TYPE0:
		747	pkt->reg = CP_PACKET0_GET_REG(header);
		748	pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
		749	break;
		750	case PACKET_TYPE3:
		751	pkt->opcode = CP_PACKET3_GET_OPCODE(header);
		752	break;
		753	case PACKET_TYPE2:
		754	pkt->count = -1;
		755	break;
		756	default:
		757	DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
		758	return -EINVAL;
		759	}
		760	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
		761	DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
		762	pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
		763	return -EINVAL;
		764	}
		765	return 0;
		766	}
		767
		768	/**
		769	* r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
		770	* @parser: parser structure holding parsing context.
		771	* @data: pointer to relocation data
		772	* @offset_start: starting offset
		773	* @offset_mask: offset mask (to align start offset on)
		774	* @reloc: reloc informations
		775	*
		776	* Check next packet is relocation packet3, do bo validation and compute
		777	* GPU offset using the provided start.
		778	**/
		779	int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
		780	struct radeon_cs_reloc **cs_reloc)
		781	{
		782	struct radeon_cs_chunk *ib_chunk;
		783	struct radeon_cs_chunk *relocs_chunk;
		784	struct radeon_cs_packet p3reloc;
		785	unsigned idx;
		786	int r;
		787
		788	if (p->chunk_relocs_idx == -1) {
		789	DRM_ERROR("No relocation chunk !\n");
		790	return -EINVAL;
		791	}
		792	*cs_reloc = NULL;
		793	ib_chunk = &p->chunks[p->chunk_ib_idx];
		794	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
		795	r = r100_cs_packet_parse(p, &p3reloc, p->idx);
		796	if (r) {
		797	return r;
		798	}
		799	p->idx += p3reloc.count + 2;
		800	if (p3reloc.type != PACKET_TYPE3 \|\| p3reloc.opcode != PACKET3_NOP) {
		801	DRM_ERROR("No packet3 for relocation for packet at %d.\n",
		802	p3reloc.idx);
		803	r100_cs_dump_packet(p, &p3reloc);
		804	return -EINVAL;
		805	}
		806	idx = ib_chunk->kdata[p3reloc.idx + 1];
		807	if (idx >= relocs_chunk->length_dw) {
		808	DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
		809	idx, relocs_chunk->length_dw);
		810	r100_cs_dump_packet(p, &p3reloc);
		811	return -EINVAL;
		812	}
		813	/* FIXME: we assume reloc size is 4 dwords */
		814	*cs_reloc = p->relocs_ptr[(idx / 4)];
		815	return 0;
		816	}
		817
		818	static int r100_packet0_check(struct radeon_cs_parser *p,
		819	struct radeon_cs_packet *pkt)
		820	{
		821	struct radeon_cs_chunk *ib_chunk;
		822	struct radeon_cs_reloc *reloc;
		823	volatile uint32_t *ib;
		824	uint32_t tmp;
		825	unsigned reg;
		826	unsigned i;
		827	unsigned idx;
		828	bool onereg;
		829	int r;
		830
		831	ib = p->ib->ptr;
		832	ib_chunk = &p->chunks[p->chunk_ib_idx];
		833	idx = pkt->idx + 1;
		834	reg = pkt->reg;
		835	onereg = false;
		836	if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
		837	onereg = true;
		838	}
		839	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
		840	switch (reg) {
		841	/* FIXME: only allow PACKET3 blit? easier to check for out of
		842	* range access */
		843	case RADEON_DST_PITCH_OFFSET:
		844	case RADEON_SRC_PITCH_OFFSET:
		845	r = r100_cs_packet_next_reloc(p, &reloc);
		846	if (r) {
		847	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		848	idx, reg);
		849	r100_cs_dump_packet(p, pkt);
		850	return r;
		851	}
		852	tmp = ib_chunk->kdata[idx] & 0x003fffff;
		853	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
		854	ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) \| tmp;
		855	break;
		856	case RADEON_RB3D_DEPTHOFFSET:
		857	case RADEON_RB3D_COLOROFFSET:
		858	case R300_RB3D_COLOROFFSET0:
		859	case R300_ZB_DEPTHOFFSET:
		860	case R200_PP_TXOFFSET_0:
		861	case R200_PP_TXOFFSET_1:
		862	case R200_PP_TXOFFSET_2:
		863	case R200_PP_TXOFFSET_3:
		864	case R200_PP_TXOFFSET_4:
		865	case R200_PP_TXOFFSET_5:
		866	case RADEON_PP_TXOFFSET_0:
		867	case RADEON_PP_TXOFFSET_1:
		868	case RADEON_PP_TXOFFSET_2:
		869	case R300_TX_OFFSET_0:
		870	case R300_TX_OFFSET_0+4:
		871	case R300_TX_OFFSET_0+8:
		872	case R300_TX_OFFSET_0+12:
		873	case R300_TX_OFFSET_0+16:
		874	case R300_TX_OFFSET_0+20:
		875	case R300_TX_OFFSET_0+24:
		876	case R300_TX_OFFSET_0+28:
		877	case R300_TX_OFFSET_0+32:
		878	case R300_TX_OFFSET_0+36:
		879	case R300_TX_OFFSET_0+40:
		880	case R300_TX_OFFSET_0+44:
		881	case R300_TX_OFFSET_0+48:
		882	case R300_TX_OFFSET_0+52:
		883	case R300_TX_OFFSET_0+56:
		884	case R300_TX_OFFSET_0+60:
		885	r = r100_cs_packet_next_reloc(p, &reloc);
		886	if (r) {
		887	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
		888	idx, reg);
		889	r100_cs_dump_packet(p, pkt);
		890	return r;
		891	}
		892	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
		893	break;
		894	default:
		895	/* FIXME: we don't want to allow anyothers packet */
		896	break;
		897	}
		898	if (onereg) {
		899	/* FIXME: forbid onereg write to register on relocate */
		900	break;
		901	}
		902	}
		903	return 0;
		904	}
		905
		906	int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
		907	struct radeon_cs_packet *pkt,
		908	struct radeon_object *robj)
		909	{
		910	struct radeon_cs_chunk *ib_chunk;
		911	unsigned idx;
		912
		913	ib_chunk = &p->chunks[p->chunk_ib_idx];
		914	idx = pkt->idx + 1;
		915	if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
		916	DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
		917	"(need %u have %lu) !\n",
		918	ib_chunk->kdata[idx+2] + 1,
		919	radeon_object_size(robj));
		920	return -EINVAL;
		921	}
		922	return 0;
		923	}
		924
		925	static int r100_packet3_check(struct radeon_cs_parser *p,
		926	struct radeon_cs_packet *pkt)
		927	{
		928	struct radeon_cs_chunk *ib_chunk;
		929	struct radeon_cs_reloc *reloc;
		930	unsigned idx;
		931	unsigned i, c;
		932	volatile uint32_t *ib;
		933	int r;
		934
		935	ib = p->ib->ptr;
		936	ib_chunk = &p->chunks[p->chunk_ib_idx];
		937	idx = pkt->idx + 1;
		938	switch (pkt->opcode) {
		939	case PACKET3_3D_LOAD_VBPNTR:
		940	c = ib_chunk->kdata[idx++];
		941	for (i = 0; i < (c - 1); i += 2, idx += 3) {
		942	r = r100_cs_packet_next_reloc(p, &reloc);
		943	if (r) {
		944	DRM_ERROR("No reloc for packet3 %d\n",
		945	pkt->opcode);
		946	r100_cs_dump_packet(p, pkt);
		947	return r;
		948	}
		949	ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
		950	r = r100_cs_packet_next_reloc(p, &reloc);
		951	if (r) {
		952	DRM_ERROR("No reloc for packet3 %d\n",
		953	pkt->opcode);
		954	r100_cs_dump_packet(p, pkt);
		955	return r;
		956	}
		957	ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
		958	}
		959	if (c & 1) {
		960	r = r100_cs_packet_next_reloc(p, &reloc);
		961	if (r) {
		962	DRM_ERROR("No reloc for packet3 %d\n",
		963	pkt->opcode);
		964	r100_cs_dump_packet(p, pkt);
		965	return r;
		966	}
		967	ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
		968	}
		969	break;
		970	case PACKET3_INDX_BUFFER:
		971	r = r100_cs_packet_next_reloc(p, &reloc);
		972	if (r) {
		973	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		974	r100_cs_dump_packet(p, pkt);
		975	return r;
		976	}
		977	ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
		978	r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
		979	if (r) {
		980	return r;
		981	}
		982	break;
		983	case 0x23:
		984	/* FIXME: cleanup */
		985	/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
		986	r = r100_cs_packet_next_reloc(p, &reloc);
		987	if (r) {
		988	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
		989	r100_cs_dump_packet(p, pkt);
		990	return r;
		991	}
		992	ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
		993	break;
		994	case PACKET3_3D_DRAW_IMMD:
		995	/* triggers drawing using in-packet vertex data */
		996	case PACKET3_3D_DRAW_IMMD_2:
		997	/* triggers drawing using in-packet vertex data */
		998	case PACKET3_3D_DRAW_VBUF_2:
		999	/* triggers drawing of vertex buffers setup elsewhere */
		1000	case PACKET3_3D_DRAW_INDX_2:
		1001	/* triggers drawing using indices to vertex buffer */
		1002	case PACKET3_3D_DRAW_VBUF:
		1003	/* triggers drawing of vertex buffers setup elsewhere */
		1004	case PACKET3_3D_DRAW_INDX:
		1005	/* triggers drawing using indices to vertex buffer */
		1006	case PACKET3_NOP:
		1007	break;
		1008	default:
		1009	DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
		1010	return -EINVAL;
		1011	}
		1012	return 0;
		1013	}
		1014
		1015	int r100_cs_parse(struct radeon_cs_parser *p)
		1016	{
		1017	struct radeon_cs_packet pkt;
		1018	int r;
		1019
		1020	do {
		1021	r = r100_cs_packet_parse(p, &pkt, p->idx);
		1022	if (r) {
		1023	return r;
		1024	}
		1025	p->idx += pkt.count + 2;
		1026	switch (pkt.type) {
		1027	case PACKET_TYPE0:
		1028	r = r100_packet0_check(p, &pkt);
		1029	break;
		1030	case PACKET_TYPE2:
		1031	break;
		1032	case PACKET_TYPE3:
		1033	r = r100_packet3_check(p, &pkt);
		1034	break;
		1035	default:
		1036	DRM_ERROR("Unknown packet type %d !\n",
		1037	pkt.type);
		1038	return -EINVAL;
		1039	}
		1040	if (r) {
		1041	return r;
		1042	}
		1043	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
		1044	return 0;
		1045	}
		1046
		1047
		1048	/*
		1049	* Global GPU functions
		1050	*/
		1051	void r100_errata(struct radeon_device *rdev)
		1052	{
		1053	rdev->pll_errata = 0;
		1054
		1055	if (rdev->family == CHIP_RV200 \|\| rdev->family == CHIP_RS200) {
		1056	rdev->pll_errata \|= CHIP_ERRATA_PLL_DUMMYREADS;
		1057	}
		1058
		1059	if (rdev->family == CHIP_RV100 \|\|
		1060	rdev->family == CHIP_RS100 \|\|
		1061	rdev->family == CHIP_RS200) {
		1062	rdev->pll_errata \|= CHIP_ERRATA_PLL_DELAY;
		1063	}
		1064	}
		1065
		1066	#endif
		1067
		1068
		1069	/* Wait for vertical sync on primary CRTC */
		1070	void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
		1071	{
		1072	uint32_t crtc_gen_cntl, tmp;
		1073	int i;
		1074
		1075	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
		1076	if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) \|\|
		1077	!(crtc_gen_cntl & RADEON_CRTC_EN)) {
		1078	return;
		1079	}
		1080	/* Clear the CRTC_VBLANK_SAVE bit */
		1081	WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
		1082	for (i = 0; i < rdev->usec_timeout; i++) {
		1083	tmp = RREG32(RADEON_CRTC_STATUS);
		1084	if (tmp & RADEON_CRTC_VBLANK_SAVE) {
		1085	return;
		1086	}
		1087	DRM_UDELAY(1);
		1088	}
		1089	}
		1090
		1091	/* Wait for vertical sync on secondary CRTC */
		1092	void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
		1093	{
		1094	uint32_t crtc2_gen_cntl, tmp;
		1095	int i;
		1096
		1097	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1098	if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) \|\|
		1099	!(crtc2_gen_cntl & RADEON_CRTC2_EN))
		1100	return;
		1101
		1102	/* Clear the CRTC_VBLANK_SAVE bit */
		1103	WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
		1104	for (i = 0; i < rdev->usec_timeout; i++) {
		1105	tmp = RREG32(RADEON_CRTC2_STATUS);
		1106	if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
		1107	return;
		1108	}
		1109	DRM_UDELAY(1);
		1110	}
		1111	}
		1112
		1113	int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
		1114	{
		1115	unsigned i;
		1116	uint32_t tmp;
		1117
		1118	for (i = 0; i < rdev->usec_timeout; i++) {
		1119	tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
		1120	if (tmp >= n) {
		1121	return 0;
		1122	}
		1123	DRM_UDELAY(1);
		1124	}
		1125	return -1;
		1126	}
		1127
		1128	int r100_gui_wait_for_idle(struct radeon_device *rdev)
		1129	{
		1130	unsigned i;
		1131	uint32_t tmp;
		1132
		1133	if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
		1134	printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
		1135	" Bad things might happen.\n");
		1136	}
		1137	for (i = 0; i < rdev->usec_timeout; i++) {
		1138	tmp = RREG32(RADEON_RBBM_STATUS);
		1139	if (!(tmp & (1 << 31))) {
		1140	return 0;
		1141	}
		1142	DRM_UDELAY(1);
		1143	}
		1144	return -1;
		1145	}
		1146
		1147	int r100_mc_wait_for_idle(struct radeon_device *rdev)
		1148	{
		1149	unsigned i;
		1150	uint32_t tmp;
		1151
		1152	for (i = 0; i < rdev->usec_timeout; i++) {
		1153	/* read MC_STATUS */
		1154	tmp = RREG32(0x0150);
		1155	if (tmp & (1 << 2)) {
		1156	return 0;
		1157	}
		1158	DRM_UDELAY(1);
		1159	}
		1160	return -1;
		1161	}
		1162
		1163	void r100_gpu_init(struct radeon_device *rdev)
		1164	{
		1165	/* TODO: anythings to do here ? pipes ? */
		1166	r100_hdp_reset(rdev);
		1167	}
		1168
		1169	void r100_hdp_reset(struct radeon_device *rdev)
		1170	{
		1171	uint32_t tmp;
		1172
		1173	dbgprintf("%s\n\r",__FUNCTION__);
		1174
		1175	tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
		1176	tmp \|= (7 << 28);
		1177	WREG32(RADEON_HOST_PATH_CNTL, tmp \| RADEON_HDP_SOFT_RESET \| RADEON_HDP_READ_BUFFER_INVALIDATE);
		1178	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1179	udelay(200);
		1180	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1181	WREG32(RADEON_HOST_PATH_CNTL, tmp);
		1182	(void)RREG32(RADEON_HOST_PATH_CNTL);
		1183	}
		1184
		1185	int r100_rb2d_reset(struct radeon_device *rdev)
		1186	{
		1187	uint32_t tmp;
		1188	int i;
		1189
		1190	dbgprintf("%s\n\r",__FUNCTION__);
		1191
		1192	WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
		1193	(void)RREG32(RADEON_RBBM_SOFT_RESET);
		1194	udelay(200);
		1195	WREG32(RADEON_RBBM_SOFT_RESET, 0);
		1196	/* Wait to prevent race in RBBM_STATUS */
		1197	mdelay(1);
		1198	for (i = 0; i < rdev->usec_timeout; i++) {
		1199	tmp = RREG32(RADEON_RBBM_STATUS);
		1200	if (!(tmp & (1 << 26))) {
		1201	DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
		1202	tmp);
		1203	return 0;
		1204	}
		1205	DRM_UDELAY(1);
		1206	}
		1207	tmp = RREG32(RADEON_RBBM_STATUS);
		1208	DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
		1209	return -1;
		1210	}
		1211
		1212	#if 0
		1213
		1214	int r100_gpu_reset(struct radeon_device *rdev)
		1215	{
		1216	uint32_t status;
		1217
		1218	/* reset order likely matter */
		1219	status = RREG32(RADEON_RBBM_STATUS);
		1220	/* reset HDP */
		1221	r100_hdp_reset(rdev);
		1222	/* reset rb2d */
		1223	if (status & ((1 << 17) \| (1 << 18) \| (1 << 27))) {
		1224	r100_rb2d_reset(rdev);
		1225	}
		1226	/* TODO: reset 3D engine */
		1227	/* reset CP */
		1228	status = RREG32(RADEON_RBBM_STATUS);
		1229	if (status & (1 << 16)) {
		1230	r100_cp_reset(rdev);
		1231	}
		1232	/* Check if GPU is idle */
		1233	status = RREG32(RADEON_RBBM_STATUS);
		1234	if (status & (1 << 31)) {
		1235	DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
		1236	return -1;
		1237	}
		1238	DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
		1239	return 0;
		1240	}
		1241
		1242
		1243	/*
		1244	* VRAM info
		1245	*/
		1246	static void r100_vram_get_type(struct radeon_device *rdev)
		1247	{
		1248	uint32_t tmp;
		1249
		1250	rdev->mc.vram_is_ddr = false;
		1251	if (rdev->flags & RADEON_IS_IGP)
		1252	rdev->mc.vram_is_ddr = true;
		1253	else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
		1254	rdev->mc.vram_is_ddr = true;
		1255	if ((rdev->family == CHIP_RV100) \|\|
		1256	(rdev->family == CHIP_RS100) \|\|
		1257	(rdev->family == CHIP_RS200)) {
		1258	tmp = RREG32(RADEON_MEM_CNTL);
		1259	if (tmp & RV100_HALF_MODE) {
		1260	rdev->mc.vram_width = 32;
		1261	} else {
		1262	rdev->mc.vram_width = 64;
		1263	}
		1264	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1265	rdev->mc.vram_width /= 4;
		1266	rdev->mc.vram_is_ddr = true;
		1267	}
		1268	} else if (rdev->family <= CHIP_RV280) {
		1269	tmp = RREG32(RADEON_MEM_CNTL);
		1270	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
		1271	rdev->mc.vram_width = 128;
		1272	} else {
		1273	rdev->mc.vram_width = 64;
		1274	}
		1275	} else {
		1276	/* newer IGPs */
		1277	rdev->mc.vram_width = 128;
		1278	}
		1279	}
		1280
		1281	void r100_vram_info(struct radeon_device *rdev)
		1282	{
		1283	r100_vram_get_type(rdev);
		1284
		1285	if (rdev->flags & RADEON_IS_IGP) {
		1286	uint32_t tom;
		1287	/* read NB_TOM to get the amount of ram stolen for the GPU */
		1288	tom = RREG32(RADEON_NB_TOM);
		1289	rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
		1290	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
		1291	} else {
		1292	rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
		1293	/* Some production boards of m6 will report 0
		1294	* if it's 8 MB
		1295	*/
		1296	if (rdev->mc.vram_size == 0) {
		1297	rdev->mc.vram_size = 8192 * 1024;
		1298	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
		1299	}
		1300	}
		1301
		1302	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
		1303	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
		1304	}
		1305
1119	serge	1306	#endif
1117	serge	1307
		1308	/*
		1309	* Indirect registers accessor
		1310	*/
		1311	void r100_pll_errata_after_index(struct radeon_device *rdev)
		1312	{
		1313	if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
		1314	return;
		1315	}
		1316	(void)RREG32(RADEON_CLOCK_CNTL_DATA);
		1317	(void)RREG32(RADEON_CRTC_GEN_CNTL);
		1318	}
		1319
		1320	static void r100_pll_errata_after_data(struct radeon_device *rdev)
		1321	{
		1322	/* This workarounds is necessary on RV100, RS100 and RS200 chips
		1323	* or the chip could hang on a subsequent access
		1324	*/
		1325	if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
		1326	udelay(5000);
		1327	}
		1328
		1329	/* This function is required to workaround a hardware bug in some (all?)
		1330	* revisions of the R300. This workaround should be called after every
		1331	* CLOCK_CNTL_INDEX register access. If not, register reads afterward
		1332	* may not be correct.
		1333	*/
		1334	if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
		1335	uint32_t save, tmp;
		1336
		1337	save = RREG32(RADEON_CLOCK_CNTL_INDEX);
		1338	tmp = save & ~(0x3f \| RADEON_PLL_WR_EN);
		1339	WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
		1340	tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
		1341	WREG32(RADEON_CLOCK_CNTL_INDEX, save);
		1342	}
		1343	}
		1344
		1345	uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
		1346	{
		1347	uint32_t data;
		1348
		1349	WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
		1350	r100_pll_errata_after_index(rdev);
		1351	data = RREG32(RADEON_CLOCK_CNTL_DATA);
		1352	r100_pll_errata_after_data(rdev);
		1353	return data;
		1354	}
		1355
		1356	void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		1357	{
		1358	WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) \| RADEON_PLL_WR_EN));
		1359	r100_pll_errata_after_index(rdev);
		1360	WREG32(RADEON_CLOCK_CNTL_DATA, v);
		1361	r100_pll_errata_after_data(rdev);
		1362	}
		1363
		1364	uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
		1365	{
		1366	if (reg < 0x10000)
		1367	return readl(((void __iomem *)rdev->rmmio) + reg);
		1368	else {
		1369	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		1370	return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		1371	}
		1372	}
		1373
		1374	void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		1375	{
		1376	if (reg < 0x10000)
		1377	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		1378	else {
		1379	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		1380	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		1381	}
		1382	}
		1383
		1384	int r100_init(struct radeon_device *rdev)
		1385	{
		1386	return 0;
		1387	}
		1388

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/r100.c – Rev 1119