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Rev | Author | Line No. | Line |
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6104 | serge | 1 | #include |
2 | |||
1403 | serge | 3 | #include |
1630 | serge | 4 | #include |
1963 | serge | 5 | #include |
5271 | serge | 6 | #include |
6104 | serge | 7 | #include |
8 | |||
5271 | serge | 9 | #include |
1117 | serge | 10 | |
5271 | serge | 11 | extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn); |
5078 | serge | 12 | |
1120 | serge | 13 | static LIST_HEAD(devices); |
1117 | serge | 14 | |
15 | /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
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16 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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17 | |||
18 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
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19 | |||
20 | /* |
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21 | * Translate the low bits of the PCI base |
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22 | * to the resource type |
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23 | */ |
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24 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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25 | { |
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26 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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27 | return IORESOURCE_IO; |
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28 | |||
29 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
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30 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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31 | |||
32 | return IORESOURCE_MEM; |
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33 | } |
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34 | |||
35 | |||
5271 | serge | 36 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) |
1117 | serge | 37 | { |
5271 | serge | 38 | u32 size = mask & maxbase; /* Find the significant bits */ |
1117 | serge | 39 | |
40 | if (!size) |
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41 | return 0; |
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42 | |||
43 | /* Get the lowest of them to find the decode size, and |
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44 | from that the extent. */ |
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45 | size = (size & ~(size-1)) - 1; |
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46 | |||
47 | /* base == maxbase can be valid only if the BAR has |
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48 | already been programmed with all 1s. */ |
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49 | if (base == maxbase && ((base | size) & mask) != mask) |
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50 | return 0; |
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51 | |||
52 | return size; |
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53 | } |
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54 | |||
5271 | serge | 55 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) |
1117 | serge | 56 | { |
5271 | serge | 57 | u64 size = mask & maxbase; /* Find the significant bits */ |
1117 | serge | 58 | |
59 | if (!size) |
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60 | return 0; |
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61 | |||
62 | /* Get the lowest of them to find the decode size, and |
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63 | from that the extent. */ |
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64 | size = (size & ~(size-1)) - 1; |
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65 | |||
66 | /* base == maxbase can be valid only if the BAR has |
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67 | already been programmed with all 1s. */ |
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68 | if (base == maxbase && ((base | size) & mask) != mask) |
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69 | return 0; |
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70 | |||
71 | return size; |
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72 | } |
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73 | |||
5271 | serge | 74 | static inline int is_64bit_memory(u32 mask) |
1117 | serge | 75 | { |
76 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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77 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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78 | return 1; |
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79 | return 0; |
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80 | } |
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81 | |||
82 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
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83 | { |
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5271 | serge | 84 | u32 pos, reg, next; |
85 | u32 l, sz; |
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1117 | serge | 86 | struct resource *res; |
87 | |||
88 | for(pos=0; pos < howmany; pos = next) |
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89 | { |
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5271 | serge | 90 | u64 l64; |
91 | u64 sz64; |
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92 | u32 raw_sz; |
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1117 | serge | 93 | |
94 | next = pos + 1; |
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95 | |||
96 | res = &dev->resource[pos]; |
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97 | |||
98 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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2160 | serge | 99 | l = PciRead32(dev->busnr, dev->devfn, reg); |
100 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
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101 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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102 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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1117 | serge | 103 | |
104 | if (!sz || sz == 0xffffffff) |
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105 | continue; |
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106 | |||
107 | if (l == 0xffffffff) |
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108 | l = 0; |
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109 | |||
110 | raw_sz = sz; |
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111 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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112 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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113 | { |
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5271 | serge | 114 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 115 | /* |
116 | * For 64bit prefetchable memory sz could be 0, if the |
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117 | * real size is bigger than 4G, so we need to check |
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118 | * szhi for that. |
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119 | */ |
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120 | if (!is_64bit_memory(l) && !sz) |
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121 | continue; |
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122 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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123 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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124 | } |
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125 | else { |
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126 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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127 | if (!sz) |
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128 | continue; |
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129 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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130 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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131 | } |
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132 | res->end = res->start + (unsigned long) sz; |
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133 | res->flags |= pci_calc_resource_flags(l); |
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134 | if (is_64bit_memory(l)) |
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135 | { |
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5271 | serge | 136 | u32 szhi, lhi; |
1117 | serge | 137 | |
2160 | serge | 138 | lhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
139 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
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140 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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141 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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5271 | serge | 142 | sz64 = ((u64)szhi << 32) | raw_sz; |
143 | l64 = ((u64)lhi << 32) | l; |
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1117 | serge | 144 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
145 | next++; |
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146 | |||
147 | #if BITS_PER_LONG == 64 |
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148 | if (!sz64) { |
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149 | res->start = 0; |
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150 | res->end = 0; |
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151 | res->flags = 0; |
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152 | continue; |
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153 | } |
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154 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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155 | res->end = res->start + sz64; |
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156 | #else |
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157 | if (sz64 > 0x100000000ULL) { |
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158 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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159 | "BAR for device %s\n", pci_name(dev)); |
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160 | res->start = 0; |
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161 | res->flags = 0; |
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162 | } |
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163 | else if (lhi) |
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164 | { |
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165 | /* 64-bit wide address, treat as disabled */ |
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2160 | serge | 166 | PciWrite32(dev->busnr, dev->devfn, reg, |
5271 | serge | 167 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); |
2160 | serge | 168 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
1117 | serge | 169 | res->start = 0; |
170 | res->end = sz; |
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171 | } |
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172 | #endif |
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173 | } |
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174 | } |
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175 | |||
176 | if ( rom ) |
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177 | { |
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178 | dev->rom_base_reg = rom; |
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179 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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180 | |||
2160 | serge | 181 | l = PciRead32(dev->busnr, dev->devfn, rom); |
182 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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183 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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184 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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1117 | serge | 185 | |
186 | if (l == 0xffffffff) |
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187 | l = 0; |
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188 | |||
189 | if (sz && sz != 0xffffffff) |
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190 | { |
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5271 | serge | 191 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); |
1117 | serge | 192 | |
193 | if (sz) |
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194 | { |
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195 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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196 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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197 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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198 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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199 | res->end = res->start + (unsigned long) sz; |
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200 | } |
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201 | } |
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202 | } |
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203 | } |
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204 | |||
205 | static void pci_read_irq(struct pci_dev *dev) |
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206 | { |
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5271 | serge | 207 | u8 irq; |
1117 | serge | 208 | |
2160 | serge | 209 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN); |
1117 | serge | 210 | dev->pin = irq; |
211 | if (irq) |
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2160 | serge | 212 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
1117 | serge | 213 | dev->irq = irq; |
214 | }; |
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215 | |||
216 | |||
2160 | serge | 217 | int pci_setup_device(struct pci_dev *dev) |
1117 | serge | 218 | { |
5271 | serge | 219 | u32 class; |
1117 | serge | 220 | |
2160 | serge | 221 | class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION); |
1117 | serge | 222 | dev->revision = class & 0xff; |
223 | class >>= 8; /* upper 3 bytes */ |
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224 | dev->class = class; |
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225 | |||
226 | /* "Unknown power state" */ |
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227 | // dev->current_state = PCI_UNKNOWN; |
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228 | |||
229 | /* Early fixups, before probing the BARs */ |
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230 | // pci_fixup_device(pci_fixup_early, dev); |
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231 | class = dev->class >> 8; |
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232 | |||
233 | switch (dev->hdr_type) |
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234 | { |
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235 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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236 | if (class == PCI_CLASS_BRIDGE_PCI) |
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237 | goto bad; |
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238 | pci_read_irq(dev); |
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239 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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2160 | serge | 240 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
241 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
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1117 | serge | 242 | |
243 | /* |
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244 | * Do the ugly legacy mode stuff here rather than broken chip |
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245 | * quirk code. Legacy mode ATA controllers have fixed |
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246 | * addresses. These are not always echoed in BAR0-3, and |
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247 | * BAR0-3 in a few cases contain junk! |
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248 | */ |
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249 | if (class == PCI_CLASS_STORAGE_IDE) |
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250 | { |
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5271 | serge | 251 | u8 progif; |
1117 | serge | 252 | |
2160 | serge | 253 | progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG); |
1117 | serge | 254 | if ((progif & 1) == 0) |
255 | { |
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256 | dev->resource[0].start = 0x1F0; |
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257 | dev->resource[0].end = 0x1F7; |
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258 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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259 | dev->resource[1].start = 0x3F6; |
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260 | dev->resource[1].end = 0x3F6; |
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261 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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262 | } |
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263 | if ((progif & 4) == 0) |
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264 | { |
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265 | dev->resource[2].start = 0x170; |
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266 | dev->resource[2].end = 0x177; |
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267 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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268 | dev->resource[3].start = 0x376; |
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269 | dev->resource[3].end = 0x376; |
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270 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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271 | }; |
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272 | } |
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273 | break; |
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274 | |||
275 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
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276 | if (class != PCI_CLASS_BRIDGE_PCI) |
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277 | goto bad; |
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278 | /* The PCI-to-PCI bridge spec requires that subtractive |
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279 | decoding (i.e. transparent) bridge must have programming |
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280 | interface code of 0x01. */ |
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281 | pci_read_irq(dev); |
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282 | dev->transparent = ((dev->class & 0xff) == 1); |
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283 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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284 | break; |
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285 | |||
286 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
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287 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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288 | goto bad; |
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289 | pci_read_irq(dev); |
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290 | pci_read_bases(dev, 1, 0); |
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2160 | serge | 291 | dev->subsystem_vendor = PciRead16(dev->busnr, |
1117 | serge | 292 | dev->devfn, |
293 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
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294 | |||
2160 | serge | 295 | dev->subsystem_device = PciRead16(dev->busnr, |
1117 | serge | 296 | dev->devfn, |
297 | PCI_CB_SUBSYSTEM_ID); |
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298 | break; |
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299 | |||
300 | default: /* unknown header */ |
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301 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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302 | pci_name(dev), dev->hdr_type); |
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303 | return -1; |
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304 | |||
305 | bad: |
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306 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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307 | pci_name(dev), class, dev->hdr_type); |
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308 | dev->class = PCI_CLASS_NOT_DEFINED; |
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309 | } |
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310 | |||
311 | /* We found a fine healthy device, go go go... */ |
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312 | |||
313 | return 0; |
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314 | }; |
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315 | |||
5271 | serge | 316 | static pci_dev_t* pci_scan_device(u32 busnr, int devfn) |
1117 | serge | 317 | { |
1403 | serge | 318 | pci_dev_t *dev; |
1117 | serge | 319 | |
5271 | serge | 320 | u32 id; |
321 | u8 hdr; |
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1117 | serge | 322 | |
323 | int timeout = 10; |
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324 | |||
2160 | serge | 325 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
1117 | serge | 326 | |
327 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
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328 | if (id == 0xffffffff || id == 0x00000000 || |
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329 | id == 0x0000ffff || id == 0xffff0000) |
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330 | return NULL; |
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331 | |||
332 | while (id == 0xffff0001) |
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333 | { |
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334 | |||
335 | delay(timeout/10); |
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336 | timeout *= 2; |
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337 | |||
2160 | serge | 338 | id = PciRead32(busnr, devfn, PCI_VENDOR_ID); |
1117 | serge | 339 | |
340 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
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341 | if (timeout > 60 * 100) |
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342 | { |
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343 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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2160 | serge | 344 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
1117 | serge | 345 | return NULL; |
346 | } |
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347 | }; |
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348 | |||
2997 | Serge | 349 | if( pci_scan_filter(id, busnr, devfn) == 0) |
350 | return NULL; |
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351 | |||
2160 | serge | 352 | hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE); |
1117 | serge | 353 | |
1404 | serge | 354 | dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0); |
2997 | Serge | 355 | if(unlikely(dev == NULL)) |
356 | return NULL; |
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1117 | serge | 357 | |
1120 | serge | 358 | INIT_LIST_HEAD(&dev->link); |
1117 | serge | 359 | |
360 | |||
2160 | serge | 361 | dev->pci_dev.busnr = busnr; |
1117 | serge | 362 | dev->pci_dev.devfn = devfn; |
363 | dev->pci_dev.hdr_type = hdr & 0x7f; |
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364 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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365 | dev->pci_dev.vendor = id & 0xffff; |
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366 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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367 | |||
368 | pci_setup_device(&dev->pci_dev); |
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369 | |||
370 | return dev; |
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371 | |||
372 | }; |
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373 | |||
2997 | Serge | 374 | |
375 | |||
376 | |||
6104 | serge | 377 | int _pci_scan_slot(u32 bus, int devfn) |
1117 | serge | 378 | { |
379 | int func, nr = 0; |
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380 | |||
381 | for (func = 0; func < 8; func++, devfn++) |
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382 | { |
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1403 | serge | 383 | pci_dev_t *dev; |
1117 | serge | 384 | |
385 | dev = pci_scan_device(bus, devfn); |
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386 | if( dev ) |
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387 | { |
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1120 | serge | 388 | list_add(&dev->link, &devices); |
1117 | serge | 389 | |
390 | nr++; |
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391 | |||
392 | /* |
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393 | * If this is a single function device, |
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394 | * don't scan past the first function. |
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395 | */ |
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396 | if (!dev->pci_dev.multifunction) |
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397 | { |
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398 | if (func > 0) { |
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399 | dev->pci_dev.multifunction = 1; |
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400 | } |
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401 | else { |
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402 | break; |
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403 | } |
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404 | } |
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405 | } |
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406 | else { |
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407 | if (func == 0) |
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408 | break; |
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409 | } |
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410 | }; |
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411 | |||
412 | return nr; |
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413 | }; |
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414 | |||
1239 | serge | 415 | #define PCI_FIND_CAP_TTL 48 |
416 | |||
417 | static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn, |
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418 | u8 pos, int cap, int *ttl) |
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419 | { |
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420 | u8 id; |
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421 | |||
422 | while ((*ttl)--) { |
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423 | pos = PciRead8(bus, devfn, pos); |
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424 | if (pos < 0x40) |
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425 | break; |
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426 | pos &= ~3; |
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427 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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428 | if (id == 0xff) |
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429 | break; |
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430 | if (id == cap) |
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431 | return pos; |
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432 | pos += PCI_CAP_LIST_NEXT; |
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433 | } |
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434 | return 0; |
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435 | } |
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436 | |||
437 | static int __pci_find_next_cap(unsigned int bus, unsigned int devfn, |
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438 | u8 pos, int cap) |
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439 | { |
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440 | int ttl = PCI_FIND_CAP_TTL; |
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441 | |||
442 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); |
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443 | } |
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444 | |||
445 | static int __pci_bus_find_cap_start(unsigned int bus, |
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446 | unsigned int devfn, u8 hdr_type) |
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447 | { |
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448 | u16 status; |
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449 | |||
450 | status = PciRead16(bus, devfn, PCI_STATUS); |
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451 | if (!(status & PCI_STATUS_CAP_LIST)) |
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452 | return 0; |
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453 | |||
454 | switch (hdr_type) { |
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455 | case PCI_HEADER_TYPE_NORMAL: |
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456 | case PCI_HEADER_TYPE_BRIDGE: |
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457 | return PCI_CAPABILITY_LIST; |
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458 | case PCI_HEADER_TYPE_CARDBUS: |
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459 | return PCI_CB_CAPABILITY_LIST; |
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460 | default: |
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461 | return 0; |
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462 | } |
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463 | |||
464 | return 0; |
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465 | } |
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466 | |||
467 | |||
468 | int pci_find_capability(struct pci_dev *dev, int cap) |
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469 | { |
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470 | int pos; |
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471 | |||
2160 | serge | 472 | pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type); |
1239 | serge | 473 | if (pos) |
2160 | serge | 474 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
1239 | serge | 475 | |
476 | return pos; |
||
477 | } |
||
478 | |||
479 | |||
2997 | Serge | 480 | |
481 | |||
482 | int enum_pci_devices() |
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1963 | serge | 483 | { |
2997 | Serge | 484 | pci_dev_t *dev; |
5271 | serge | 485 | u32 last_bus; |
486 | u32 bus = 0 , devfn = 0; |
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1117 | serge | 487 | |
1963 | serge | 488 | |
2997 | Serge | 489 | last_bus = PciApi(1); |
1963 | serge | 490 | |
491 | |||
2997 | Serge | 492 | if( unlikely(last_bus == -1)) |
493 | return -1; |
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1963 | serge | 494 | |
2997 | Serge | 495 | for(;bus <= last_bus; bus++) |
496 | { |
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497 | for (devfn = 0; devfn < 0x100; devfn += 8) |
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6104 | serge | 498 | _pci_scan_slot(bus, devfn); |
1963 | serge | 499 | |
500 | |||
2997 | Serge | 501 | } |
502 | for(dev = (pci_dev_t*)devices.next; |
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503 | &dev->link != &devices; |
||
504 | dev = (pci_dev_t*)dev->link.next) |
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505 | { |
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506 | dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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507 | dev->pci_dev.vendor, |
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508 | dev->pci_dev.device, |
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509 | dev->pci_dev.busnr, |
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510 | dev->pci_dev.devfn); |
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1963 | serge | 511 | |
2997 | Serge | 512 | } |
513 | return 0; |
||
514 | } |
||
1963 | serge | 515 | |
2997 | Serge | 516 | const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist) |
517 | { |
||
518 | pci_dev_t *dev; |
||
519 | const struct pci_device_id *ent; |
||
1963 | serge | 520 | |
2997 | Serge | 521 | for(dev = (pci_dev_t*)devices.next; |
522 | &dev->link != &devices; |
||
523 | dev = (pci_dev_t*)dev->link.next) |
||
524 | { |
||
525 | if( dev->pci_dev.vendor != idlist->vendor ) |
||
526 | continue; |
||
527 | |||
528 | for(ent = idlist; ent->vendor != 0; ent++) |
||
529 | { |
||
530 | if(unlikely(ent->device == dev->pci_dev.device)) |
||
531 | { |
||
532 | pdev->pci_dev = dev->pci_dev; |
||
533 | return ent; |
||
534 | } |
||
535 | }; |
||
536 | } |
||
537 | |||
538 | return NULL; |
||
539 | }; |
||
540 | |||
541 | struct pci_dev * |
||
542 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
||
543 | { |
||
544 | pci_dev_t *dev; |
||
545 | |||
546 | dev = (pci_dev_t*)devices.next; |
||
547 | |||
548 | if(from != NULL) |
||
549 | { |
||
550 | for(; &dev->link != &devices; |
||
551 | dev = (pci_dev_t*)dev->link.next) |
||
552 | { |
||
553 | if( &dev->pci_dev == from) |
||
554 | { |
||
555 | dev = (pci_dev_t*)dev->link.next; |
||
1963 | serge | 556 | break; |
2997 | Serge | 557 | }; |
1963 | serge | 558 | } |
2997 | Serge | 559 | }; |
1963 | serge | 560 | |
2997 | Serge | 561 | for(; &dev->link != &devices; |
562 | dev = (pci_dev_t*)dev->link.next) |
||
563 | { |
||
564 | if( dev->pci_dev.vendor != vendor ) |
||
565 | continue; |
||
1963 | serge | 566 | |
2997 | Serge | 567 | if(dev->pci_dev.device == device) |
568 | { |
||
569 | return &dev->pci_dev; |
||
570 | } |
||
571 | } |
||
572 | return NULL; |
||
573 | }; |
||
1963 | serge | 574 | |
575 | |||
6104 | serge | 576 | struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn) |
2997 | Serge | 577 | { |
578 | pci_dev_t *dev; |
||
1963 | serge | 579 | |
2997 | Serge | 580 | for(dev = (pci_dev_t*)devices.next; |
581 | &dev->link != &devices; |
||
582 | dev = (pci_dev_t*)dev->link.next) |
||
583 | { |
||
584 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
||
585 | return &dev->pci_dev; |
||
586 | } |
||
587 | return NULL; |
||
1963 | serge | 588 | } |
589 | |||
2997 | Serge | 590 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) |
1117 | serge | 591 | { |
2997 | Serge | 592 | pci_dev_t *dev; |
1117 | serge | 593 | |
2997 | Serge | 594 | dev = (pci_dev_t*)devices.next; |
595 | |||
596 | if(from != NULL) |
||
1117 | serge | 597 | { |
2997 | Serge | 598 | for(; &dev->link != &devices; |
599 | dev = (pci_dev_t*)dev->link.next) |
||
600 | { |
||
601 | if( &dev->pci_dev == from) |
||
602 | { |
||
603 | dev = (pci_dev_t*)dev->link.next; |
||
604 | break; |
||
605 | }; |
||
606 | } |
||
607 | }; |
||
1117 | serge | 608 | |
2997 | Serge | 609 | for(; &dev->link != &devices; |
610 | dev = (pci_dev_t*)dev->link.next) |
||
611 | { |
||
612 | if( dev->pci_dev.class == class) |
||
613 | { |
||
614 | return &dev->pci_dev; |
||
1117 | serge | 615 | } |
616 | } |
||
2997 | Serge | 617 | |
618 | return NULL; |
||
1117 | serge | 619 | } |
620 | |||
621 | |||
2997 | Serge | 622 | #define PIO_OFFSET 0x10000UL |
623 | #define PIO_MASK 0x0ffffUL |
||
624 | #define PIO_RESERVED 0x40000UL |
||
625 | |||
626 | #define IO_COND(addr, is_pio, is_mmio) do { \ |
||
627 | unsigned long port = (unsigned long __force)addr; \ |
||
628 | if (port >= PIO_RESERVED) { \ |
||
629 | is_mmio; \ |
||
630 | } else if (port > PIO_OFFSET) { \ |
||
631 | port &= PIO_MASK; \ |
||
632 | is_pio; \ |
||
633 | }; \ |
||
634 | } while (0) |
||
635 | |||
636 | /* Create a virtual mapping cookie for an IO port range */ |
||
637 | void __iomem *ioport_map(unsigned long port, unsigned int nr) |
||
1117 | serge | 638 | { |
3764 | Serge | 639 | if (port > PIO_MASK) |
640 | return NULL; |
||
641 | return (void __iomem *) (unsigned long) (port + PIO_OFFSET); |
||
2997 | Serge | 642 | } |
1117 | serge | 643 | |
2997 | Serge | 644 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) |
645 | { |
||
646 | resource_size_t start = pci_resource_start(dev, bar); |
||
647 | resource_size_t len = pci_resource_len(dev, bar); |
||
648 | unsigned long flags = pci_resource_flags(dev, bar); |
||
1117 | serge | 649 | |
2997 | Serge | 650 | if (!len || !start) |
651 | return NULL; |
||
652 | if (maxlen && len > maxlen) |
||
653 | len = maxlen; |
||
654 | if (flags & IORESOURCE_IO) |
||
655 | return ioport_map(start, len); |
||
656 | if (flags & IORESOURCE_MEM) { |
||
657 | return ioremap(start, len); |
||
658 | } |
||
659 | /* What? */ |
||
660 | return NULL; |
||
1117 | serge | 661 | } |
662 | |||
2997 | Serge | 663 | void pci_iounmap(struct pci_dev *dev, void __iomem * addr) |
664 | { |
||
665 | IO_COND(addr, /* nothing */, iounmap(addr)); |
||
666 | } |
||
1117 | serge | 667 | |
2997 | Serge | 668 | |
1117 | serge | 669 | |
670 | |||
2997 | Serge | 671 | int pci_enable_rom(struct pci_dev *pdev) |
672 | { |
||
673 | struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
||
674 | struct pci_bus_region region; |
||
675 | u32 rom_addr; |
||
1117 | serge | 676 | |
2997 | Serge | 677 | if (!res->flags) |
678 | return -1; |
||
679 | |||
6104 | serge | 680 | _pcibios_resource_to_bus(pdev, ®ion, res); |
2997 | Serge | 681 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
682 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
||
683 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
||
684 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
685 | return 0; |
||
1117 | serge | 686 | } |
687 | |||
2997 | Serge | 688 | void pci_disable_rom(struct pci_dev *pdev) |
689 | { |
||
690 | u32 rom_addr; |
||
691 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
692 | rom_addr &= ~PCI_ROM_ADDRESS_ENABLE; |
||
693 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
694 | } |
||
1117 | serge | 695 | |
696 | /** |
||
2997 | Serge | 697 | * pci_get_rom_size - obtain the actual size of the ROM image |
698 | * @pdev: target PCI device |
||
699 | * @rom: kernel virtual pointer to image of ROM |
||
700 | * @size: size of PCI window |
||
701 | * return: size of actual ROM image |
||
1117 | serge | 702 | * |
2997 | Serge | 703 | * Determine the actual length of the ROM image. |
704 | * The PCI window size could be much larger than the |
||
705 | * actual image size. |
||
1117 | serge | 706 | */ |
2997 | Serge | 707 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) |
1117 | serge | 708 | { |
2997 | Serge | 709 | void __iomem *image; |
710 | int last_image; |
||
1117 | serge | 711 | |
2997 | Serge | 712 | image = rom; |
713 | do { |
||
714 | void __iomem *pds; |
||
715 | /* Standard PCI ROMs start out with these bytes 55 AA */ |
||
716 | if (readb(image) != 0x55) { |
||
717 | dev_err(&pdev->dev, "Invalid ROM contents\n"); |
||
718 | break; |
||
1117 | serge | 719 | } |
2997 | Serge | 720 | if (readb(image + 1) != 0xAA) |
721 | break; |
||
722 | /* get the PCI data structure and check its signature */ |
||
723 | pds = image + readw(image + 24); |
||
724 | if (readb(pds) != 'P') |
||
725 | break; |
||
726 | if (readb(pds + 1) != 'C') |
||
727 | break; |
||
728 | if (readb(pds + 2) != 'I') |
||
729 | break; |
||
730 | if (readb(pds + 3) != 'R') |
||
731 | break; |
||
732 | last_image = readb(pds + 21) & 0x80; |
||
733 | /* this length is reliable */ |
||
734 | image += readw(pds + 16) * 512; |
||
735 | } while (!last_image); |
||
1963 | serge | 736 | |
2997 | Serge | 737 | /* never return a size larger than the PCI resource window */ |
738 | /* there are known ROMs that get the size wrong */ |
||
739 | return min((size_t)(image - rom), size); |
||
740 | } |
||
1117 | serge | 741 | |
742 | |||
743 | /** |
||
744 | * pci_map_rom - map a PCI ROM to kernel space |
||
745 | * @pdev: pointer to pci device struct |
||
746 | * @size: pointer to receive size of pci window over ROM |
||
747 | * |
||
2997 | Serge | 748 | * Return: kernel virtual pointer to image of ROM |
749 | * |
||
1117 | serge | 750 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
751 | * the shadow BIOS copy will be returned instead of the |
||
752 | * actual ROM. |
||
753 | */ |
||
2997 | Serge | 754 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) |
1117 | serge | 755 | { |
756 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
2997 | Serge | 757 | loff_t start; |
758 | void __iomem *rom; |
||
1117 | serge | 759 | |
1963 | serge | 760 | /* |
761 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
||
762 | * memory map if the VGA enable bit of the Bridge Control register is |
||
763 | * set for embedded VGA. |
||
764 | */ |
||
765 | if (res->flags & IORESOURCE_ROM_SHADOW) { |
||
766 | /* primary video rom always starts here */ |
||
2997 | Serge | 767 | start = (loff_t)0xC0000; |
1963 | serge | 768 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
769 | } else { |
||
3764 | Serge | 770 | if (res->flags & |
771 | (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
||
1963 | serge | 772 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
2997 | Serge | 773 | return (void __iomem *)(unsigned long) |
774 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
1963 | serge | 775 | } else { |
5271 | serge | 776 | start = (loff_t)0xC0000; |
777 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
1963 | serge | 778 | |
779 | } |
||
780 | } |
||
781 | |||
782 | rom = ioremap(start, *size); |
||
783 | if (!rom) { |
||
784 | /* restore enable if ioremap fails */ |
||
785 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
786 | IORESOURCE_ROM_SHADOW | |
||
787 | IORESOURCE_ROM_COPY))) |
||
788 | pci_disable_rom(pdev); |
||
789 | return NULL; |
||
790 | } |
||
791 | |||
792 | /* |
||
793 | * Try to find the true size of the ROM since sometimes the PCI window |
||
794 | * size is much larger than the actual size of the ROM. |
||
795 | * True size is important if the ROM is going to be copied. |
||
796 | */ |
||
2997 | Serge | 797 | *size = pci_get_rom_size(pdev, rom, *size); |
798 | return rom; |
||
799 | } |
||
1963 | serge | 800 | |
2997 | Serge | 801 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) |
802 | { |
||
803 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
1117 | serge | 804 | |
2997 | Serge | 805 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) |
806 | return; |
||
1117 | serge | 807 | |
2997 | Serge | 808 | iounmap(rom); |
809 | |||
810 | /* Disable again before continuing, leave enabled if pci=rom */ |
||
811 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
||
812 | pci_disable_rom(pdev); |
||
813 | } |
||
814 | |||
815 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
||
816 | { |
||
817 | u16 old_cmd, cmd; |
||
818 | |||
819 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); |
||
820 | if (enable) |
||
821 | cmd = old_cmd | PCI_COMMAND_MASTER; |
||
1117 | serge | 822 | else |
2997 | Serge | 823 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
824 | if (cmd != old_cmd) { |
||
5271 | serge | 825 | dbgprintf("%s bus mastering\n", |
826 | enable ? "enabling" : "disabling"); |
||
2997 | Serge | 827 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
828 | } |
||
829 | dev->is_busmaster = enable; |
||
830 | } |
||
1117 | serge | 831 | |
2997 | Serge | 832 | |
833 | /* pci_set_master - enables bus-mastering for device dev |
||
834 | * @dev: the PCI device to enable |
||
835 | * |
||
836 | * Enables bus-mastering on the device and calls pcibios_set_master() |
||
837 | * to do the needed arch specific settings. |
||
838 | */ |
||
839 | void pci_set_master(struct pci_dev *dev) |
||
840 | { |
||
841 | __pci_set_master(dev, true); |
||
842 | // pcibios_set_master(dev); |
||
1117 | serge | 843 | } |
844 | |||
2997 | Serge | 845 | /** |
846 | * pci_clear_master - disables bus-mastering for device dev |
||
847 | * @dev: the PCI device to disable |
||
848 | */ |
||
849 | void pci_clear_master(struct pci_dev *dev) |
||
850 | { |
||
851 | __pci_set_master(dev, false); |
||
852 | } |
||
1119 | serge | 853 | |
2997 | Serge | 854 | |
855 | static inline int pcie_cap_version(const struct pci_dev *dev) |
||
1119 | serge | 856 | { |
2997 | Serge | 857 | return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS; |
858 | } |
||
1119 | serge | 859 | |
2997 | Serge | 860 | static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) |
861 | { |
||
862 | return true; |
||
863 | } |
||
1119 | serge | 864 | |
2997 | Serge | 865 | static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
866 | { |
||
867 | int type = pci_pcie_type(dev); |
||
868 | |||
869 | return pcie_cap_version(dev) > 1 || |
||
870 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
871 | type == PCI_EXP_TYPE_ENDPOINT || |
||
872 | type == PCI_EXP_TYPE_LEG_END; |
||
873 | } |
||
874 | |||
875 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) |
||
876 | { |
||
877 | int type = pci_pcie_type(dev); |
||
878 | |||
879 | return pcie_cap_version(dev) > 1 || |
||
880 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
881 | (type == PCI_EXP_TYPE_DOWNSTREAM && |
||
882 | dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT); |
||
883 | } |
||
884 | |||
885 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) |
||
886 | { |
||
887 | int type = pci_pcie_type(dev); |
||
888 | |||
889 | return pcie_cap_version(dev) > 1 || |
||
890 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
891 | type == PCI_EXP_TYPE_RC_EC; |
||
892 | } |
||
893 | |||
894 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) |
||
895 | { |
||
896 | if (!pci_is_pcie(dev)) |
||
897 | return false; |
||
898 | |||
899 | switch (pos) { |
||
900 | case PCI_EXP_FLAGS_TYPE: |
||
901 | return true; |
||
902 | case PCI_EXP_DEVCAP: |
||
903 | case PCI_EXP_DEVCTL: |
||
904 | case PCI_EXP_DEVSTA: |
||
905 | return pcie_cap_has_devctl(dev); |
||
906 | case PCI_EXP_LNKCAP: |
||
907 | case PCI_EXP_LNKCTL: |
||
908 | case PCI_EXP_LNKSTA: |
||
909 | return pcie_cap_has_lnkctl(dev); |
||
910 | case PCI_EXP_SLTCAP: |
||
911 | case PCI_EXP_SLTCTL: |
||
912 | case PCI_EXP_SLTSTA: |
||
913 | return pcie_cap_has_sltctl(dev); |
||
914 | case PCI_EXP_RTCTL: |
||
915 | case PCI_EXP_RTCAP: |
||
916 | case PCI_EXP_RTSTA: |
||
917 | return pcie_cap_has_rtctl(dev); |
||
918 | case PCI_EXP_DEVCAP2: |
||
919 | case PCI_EXP_DEVCTL2: |
||
920 | case PCI_EXP_LNKCAP2: |
||
921 | case PCI_EXP_LNKCTL2: |
||
922 | case PCI_EXP_LNKSTA2: |
||
923 | return pcie_cap_version(dev) > 1; |
||
924 | default: |
||
925 | return false; |
||
926 | } |
||
927 | } |
||
928 | |||
929 | /* |
||
930 | * Note that these accessor functions are only for the "PCI Express |
||
931 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
||
932 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
||
933 | */ |
||
934 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
||
935 | { |
||
936 | int ret; |
||
937 | |||
938 | *val = 0; |
||
939 | if (pos & 1) |
||
940 | return -EINVAL; |
||
941 | |||
942 | if (pcie_capability_reg_implemented(dev, pos)) { |
||
943 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
||
944 | /* |
||
945 | * Reset *val to 0 if pci_read_config_word() fails, it may |
||
946 | * have been written as 0xFFFF if hardware error happens |
||
947 | * during pci_read_config_word(). |
||
948 | */ |
||
949 | if (ret) |
||
950 | *val = 0; |
||
951 | return ret; |
||
952 | } |
||
953 | |||
954 | /* |
||
955 | * For Functions that do not implement the Slot Capabilities, |
||
956 | * Slot Status, and Slot Control registers, these spaces must |
||
957 | * be hardwired to 0b, with the exception of the Presence Detect |
||
958 | * State bit in the Slot Status register of Downstream Ports, |
||
959 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
||
960 | */ |
||
961 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && |
||
962 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
963 | *val = PCI_EXP_SLTSTA_PDS; |
||
964 | } |
||
965 | |||
966 | return 0; |
||
967 | } |
||
968 | EXPORT_SYMBOL(pcie_capability_read_word); |
||
969 | |||
970 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) |
||
971 | { |
||
972 | int ret; |
||
973 | |||
974 | *val = 0; |
||
975 | if (pos & 3) |
||
976 | return -EINVAL; |
||
977 | |||
978 | if (pcie_capability_reg_implemented(dev, pos)) { |
||
979 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
||
980 | /* |
||
981 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
||
982 | * have been written as 0xFFFFFFFF if hardware error happens |
||
983 | * during pci_read_config_dword(). |
||
984 | */ |
||
985 | if (ret) |
||
986 | *val = 0; |
||
987 | return ret; |
||
988 | } |
||
989 | |||
990 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL && |
||
991 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
992 | *val = PCI_EXP_SLTSTA_PDS; |
||
993 | } |
||
994 | |||
995 | return 0; |
||
996 | } |
||
997 | EXPORT_SYMBOL(pcie_capability_read_dword); |
||
998 | |||
999 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) |
||
1000 | { |
||
1001 | if (pos & 1) |
||
1002 | return -EINVAL; |
||
1003 | |||
1004 | if (!pcie_capability_reg_implemented(dev, pos)) |
||
1119 | serge | 1005 | return 0; |
2997 | Serge | 1006 | |
1007 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); |
||
1119 | serge | 1008 | } |
2997 | Serge | 1009 | EXPORT_SYMBOL(pcie_capability_write_word); |
1119 | serge | 1010 | |
2997 | Serge | 1011 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) |
1012 | { |
||
1013 | if (pos & 3) |
||
1014 | return -EINVAL; |
||
1963 | serge | 1015 | |
2997 | Serge | 1016 | if (!pcie_capability_reg_implemented(dev, pos)) |
1017 | return 0; |
||
1018 | |||
1019 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
||
1020 | } |
||
1021 | EXPORT_SYMBOL(pcie_capability_write_dword); |
||
1022 | |||
5078 | serge | 1023 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
1024 | u16 clear, u16 set) |
||
1025 | { |
||
1026 | int ret; |
||
1027 | u16 val; |
||
1028 | |||
1029 | ret = pcie_capability_read_word(dev, pos, &val); |
||
1030 | if (!ret) { |
||
1031 | val &= ~clear; |
||
1032 | val |= set; |
||
1033 | ret = pcie_capability_write_word(dev, pos, val); |
||
1034 | } |
||
1035 | |||
1036 | return ret; |
||
1037 | } |
||
1038 | |||
1039 | |||
1040 | |||
1041 | int pcie_get_readrq(struct pci_dev *dev) |
||
1042 | { |
||
1043 | u16 ctl; |
||
1044 | |||
1045 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
||
1046 | |||
1047 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
||
1048 | } |
||
1049 | EXPORT_SYMBOL(pcie_get_readrq); |
||
1050 | |||
1051 | /** |
||
1052 | * pcie_set_readrq - set PCI Express maximum memory read request |
||
1053 | * @dev: PCI device to query |
||
1054 | * @rq: maximum memory read count in bytes |
||
1055 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
||
1056 | * |
||
1057 | * If possible sets maximum memory read request in bytes |
||
1058 | */ |
||
1059 | int pcie_set_readrq(struct pci_dev *dev, int rq) |
||
1060 | { |
||
1061 | u16 v; |
||
1062 | |||
1063 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
||
1064 | return -EINVAL; |
||
1065 | |||
1066 | v = (ffs(rq) - 8) << 12; |
||
1067 | |||
1068 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
||
1069 | PCI_EXP_DEVCTL_READRQ, v); |
||
1070 | }><>>><>>=>>>><>><>><>>4)><4)> |
||
1071 |