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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
1403 | serge | 2 | #include |
3764 | Serge | 3 | #include |
2997 | Serge | 4 | #include |
1630 | serge | 5 | #include |
1963 | serge | 6 | #include |
2160 | serge | 7 | #include |
1117 | serge | 8 | #include |
9 | |||
10 | |||
2997 | Serge | 11 | |
12 | |||
1120 | serge | 13 | |
1117 | serge | 14 | |
15 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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16 | |||
17 | |||
18 | |||
19 | |||
20 | * Translate the low bits of the PCI base |
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21 | * to the resource type |
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22 | */ |
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23 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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24 | { |
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25 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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26 | return IORESOURCE_IO; |
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27 | |||
28 | |||
29 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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30 | |||
31 | |||
32 | } |
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33 | |||
34 | |||
35 | |||
36 | { |
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37 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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38 | |||
39 | |||
40 | return 0; |
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41 | |||
42 | |||
43 | from that the extent. */ |
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44 | size = (size & ~(size-1)) - 1; |
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45 | |||
46 | |||
47 | already been programmed with all 1s. */ |
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48 | if (base == maxbase && ((base | size) & mask) != mask) |
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49 | return 0; |
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50 | |||
51 | |||
52 | } |
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53 | |||
54 | |||
55 | { |
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56 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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57 | |||
58 | |||
59 | return 0; |
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60 | |||
61 | |||
62 | from that the extent. */ |
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63 | size = (size & ~(size-1)) - 1; |
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64 | |||
65 | |||
66 | already been programmed with all 1s. */ |
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67 | if (base == maxbase && ((base | size) & mask) != mask) |
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68 | return 0; |
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69 | |||
70 | |||
71 | } |
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72 | |||
73 | |||
74 | { |
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75 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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76 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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77 | return 1; |
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78 | return 0; |
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79 | } |
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80 | |||
81 | |||
82 | { |
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83 | u32_t pos, reg, next; |
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84 | u32_t l, sz; |
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85 | struct resource *res; |
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86 | |||
87 | |||
88 | { |
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89 | u64_t l64; |
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90 | u64_t sz64; |
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91 | u32_t raw_sz; |
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92 | |||
93 | |||
94 | |||
95 | |||
96 | |||
97 | |||
98 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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2160 | serge | 99 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
100 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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101 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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102 | |||
1117 | serge | 103 | |
104 | continue; |
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105 | |||
106 | |||
107 | l = 0; |
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108 | |||
109 | |||
110 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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111 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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112 | { |
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113 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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114 | /* |
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115 | * For 64bit prefetchable memory sz could be 0, if the |
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116 | * real size is bigger than 4G, so we need to check |
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117 | * szhi for that. |
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118 | */ |
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119 | if (!is_64bit_memory(l) && !sz) |
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120 | continue; |
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121 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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122 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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123 | } |
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124 | else { |
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125 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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126 | if (!sz) |
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127 | continue; |
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128 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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129 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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130 | } |
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131 | res->end = res->start + (unsigned long) sz; |
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132 | res->flags |= pci_calc_resource_flags(l); |
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133 | if (is_64bit_memory(l)) |
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134 | { |
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135 | u32_t szhi, lhi; |
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136 | |||
137 | |||
2160 | serge | 138 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
139 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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140 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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141 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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1117 | serge | 142 | l64 = ((u64_t)lhi << 32) | l; |
143 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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144 | next++; |
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145 | |||
146 | |||
147 | if (!sz64) { |
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148 | res->start = 0; |
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149 | res->end = 0; |
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150 | res->flags = 0; |
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151 | continue; |
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152 | } |
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153 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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154 | res->end = res->start + sz64; |
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155 | #else |
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156 | if (sz64 > 0x100000000ULL) { |
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157 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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158 | "BAR for device %s\n", pci_name(dev)); |
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159 | res->start = 0; |
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160 | res->flags = 0; |
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161 | } |
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162 | else if (lhi) |
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163 | { |
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164 | /* 64-bit wide address, treat as disabled */ |
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165 | PciWrite32(dev->busnr, dev->devfn, reg, |
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2160 | serge | 166 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 167 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
2160 | serge | 168 | res->start = 0; |
1117 | serge | 169 | res->end = sz; |
170 | } |
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171 | #endif |
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172 | } |
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173 | } |
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174 | |||
175 | |||
176 | { |
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177 | dev->rom_base_reg = rom; |
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178 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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179 | |||
180 | |||
2160 | serge | 181 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
182 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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183 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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184 | |||
1117 | serge | 185 | |
186 | l = 0; |
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187 | |||
188 | |||
189 | { |
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190 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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191 | |||
192 | |||
193 | { |
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194 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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195 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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196 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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197 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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198 | res->end = res->start + (unsigned long) sz; |
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199 | } |
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200 | } |
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201 | } |
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202 | } |
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203 | |||
204 | |||
205 | { |
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206 | u8_t irq; |
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207 | |||
208 | |||
2160 | serge | 209 | dev->pin = irq; |
1117 | serge | 210 | if (irq) |
211 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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2160 | serge | 212 | dev->irq = irq; |
1117 | serge | 213 | }; |
214 | |||
215 | |||
216 | |||
2160 | serge | 217 | { |
1117 | serge | 218 | u32_t class; |
219 | |||
220 | |||
2160 | serge | 221 | dev->revision = class & 0xff; |
1117 | serge | 222 | class >>= 8; /* upper 3 bytes */ |
223 | dev->class = class; |
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224 | |||
225 | |||
226 | // dev->current_state = PCI_UNKNOWN; |
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227 | |||
228 | |||
229 | // pci_fixup_device(pci_fixup_early, dev); |
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230 | class = dev->class >> 8; |
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231 | |||
232 | |||
233 | { |
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234 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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235 | if (class == PCI_CLASS_BRIDGE_PCI) |
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236 | goto bad; |
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237 | pci_read_irq(dev); |
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238 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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239 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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2160 | serge | 240 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
241 | |||
1117 | serge | 242 | |
243 | * Do the ugly legacy mode stuff here rather than broken chip |
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244 | * quirk code. Legacy mode ATA controllers have fixed |
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245 | * addresses. These are not always echoed in BAR0-3, and |
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246 | * BAR0-3 in a few cases contain junk! |
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247 | */ |
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248 | if (class == PCI_CLASS_STORAGE_IDE) |
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249 | { |
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250 | u8_t progif; |
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251 | |||
252 | |||
2160 | serge | 253 | if ((progif & 1) == 0) |
1117 | serge | 254 | { |
255 | dev->resource[0].start = 0x1F0; |
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256 | dev->resource[0].end = 0x1F7; |
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257 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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258 | dev->resource[1].start = 0x3F6; |
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259 | dev->resource[1].end = 0x3F6; |
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260 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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261 | } |
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262 | if ((progif & 4) == 0) |
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263 | { |
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264 | dev->resource[2].start = 0x170; |
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265 | dev->resource[2].end = 0x177; |
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266 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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267 | dev->resource[3].start = 0x376; |
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268 | dev->resource[3].end = 0x376; |
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269 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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270 | }; |
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271 | } |
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272 | break; |
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273 | |||
274 | |||
275 | if (class != PCI_CLASS_BRIDGE_PCI) |
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276 | goto bad; |
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277 | /* The PCI-to-PCI bridge spec requires that subtractive |
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278 | decoding (i.e. transparent) bridge must have programming |
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279 | interface code of 0x01. */ |
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280 | pci_read_irq(dev); |
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281 | dev->transparent = ((dev->class & 0xff) == 1); |
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282 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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283 | break; |
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284 | |||
285 | |||
286 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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287 | goto bad; |
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288 | pci_read_irq(dev); |
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289 | pci_read_bases(dev, 1, 0); |
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290 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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2160 | serge | 291 | dev->devfn, |
1117 | serge | 292 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
293 | |||
294 | |||
2160 | serge | 295 | dev->devfn, |
1117 | serge | 296 | PCI_CB_SUBSYSTEM_ID); |
297 | break; |
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298 | |||
299 | |||
300 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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301 | pci_name(dev), dev->hdr_type); |
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302 | return -1; |
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303 | |||
304 | |||
305 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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306 | pci_name(dev), class, dev->hdr_type); |
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307 | dev->class = PCI_CLASS_NOT_DEFINED; |
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308 | } |
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309 | |||
310 | |||
311 | |||
312 | |||
313 | }; |
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314 | |||
315 | |||
2160 | serge | 316 | { |
1117 | serge | 317 | pci_dev_t *dev; |
1403 | serge | 318 | |
1117 | serge | 319 | |
320 | u8_t hdr; |
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321 | |||
322 | |||
323 | |||
324 | |||
2160 | serge | 325 | |
1117 | serge | 326 | |
327 | if (id == 0xffffffff || id == 0x00000000 || |
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328 | id == 0x0000ffff || id == 0xffff0000) |
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329 | return NULL; |
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330 | |||
331 | |||
332 | { |
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333 | |||
334 | |||
335 | timeout *= 2; |
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336 | |||
337 | |||
2160 | serge | 338 | |
1117 | serge | 339 | |
340 | if (timeout > 60 * 100) |
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341 | { |
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342 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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343 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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2160 | serge | 344 | return NULL; |
1117 | serge | 345 | } |
346 | }; |
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347 | |||
348 | |||
2997 | Serge | 349 | return NULL; |
350 | |||
351 | |||
2160 | serge | 352 | |
1117 | serge | 353 | |
1404 | serge | 354 | if(unlikely(dev == NULL)) |
2997 | Serge | 355 | return NULL; |
356 | |||
1117 | serge | 357 | |
1120 | serge | 358 | |
1117 | serge | 359 | |
360 | |||
2160 | serge | 361 | dev->pci_dev.devfn = devfn; |
1117 | serge | 362 | dev->pci_dev.hdr_type = hdr & 0x7f; |
363 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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364 | dev->pci_dev.vendor = id & 0xffff; |
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365 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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366 | |||
367 | |||
368 | |||
369 | |||
370 | |||
371 | |||
372 | |||
373 | |||
2997 | Serge | 374 | |
375 | |||
376 | |||
1117 | serge | 377 | { |
378 | int func, nr = 0; |
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379 | |||
380 | |||
381 | { |
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382 | pci_dev_t *dev; |
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1403 | serge | 383 | |
1117 | serge | 384 | |
385 | if( dev ) |
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386 | { |
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387 | list_add(&dev->link, &devices); |
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1120 | serge | 388 | |
1117 | serge | 389 | |
390 | |||
391 | |||
392 | * If this is a single function device, |
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393 | * don't scan past the first function. |
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394 | */ |
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395 | if (!dev->pci_dev.multifunction) |
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396 | { |
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397 | if (func > 0) { |
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398 | dev->pci_dev.multifunction = 1; |
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399 | } |
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400 | else { |
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401 | break; |
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402 | } |
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403 | } |
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404 | } |
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405 | else { |
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406 | if (func == 0) |
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407 | break; |
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408 | } |
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409 | }; |
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410 | |||
411 | |||
412 | }; |
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413 | |||
414 | |||
1239 | serge | 415 | |
416 | |||
417 | u8 pos, int cap, int *ttl) |
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418 | { |
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419 | u8 id; |
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420 | |||
421 | |||
422 | pos = PciRead8(bus, devfn, pos); |
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423 | if (pos < 0x40) |
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424 | break; |
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425 | pos &= ~3; |
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426 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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427 | if (id == 0xff) |
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428 | break; |
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429 | if (id == cap) |
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430 | return pos; |
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431 | pos += PCI_CAP_LIST_NEXT; |
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432 | } |
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433 | return 0; |
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434 | } |
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435 | |||
436 | |||
437 | u8 pos, int cap) |
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438 | { |
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439 | int ttl = PCI_FIND_CAP_TTL; |
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440 | |||
441 | |||
442 | } |
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443 | |||
444 | |||
445 | unsigned int devfn, u8 hdr_type) |
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446 | { |
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447 | u16 status; |
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448 | |||
449 | |||
450 | if (!(status & PCI_STATUS_CAP_LIST)) |
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451 | return 0; |
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452 | |||
453 | |||
454 | case PCI_HEADER_TYPE_NORMAL: |
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455 | case PCI_HEADER_TYPE_BRIDGE: |
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456 | return PCI_CAPABILITY_LIST; |
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457 | case PCI_HEADER_TYPE_CARDBUS: |
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458 | return PCI_CB_CAPABILITY_LIST; |
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459 | default: |
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460 | return 0; |
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461 | } |
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462 | |||
463 | |||
464 | } |
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465 | |||
466 | |||
467 | |||
468 | { |
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469 | int pos; |
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470 | |||
471 | |||
2160 | serge | 472 | if (pos) |
1239 | serge | 473 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
2160 | serge | 474 | |
1239 | serge | 475 | |
476 | } |
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477 | |||
478 | |||
479 | |||
2997 | Serge | 480 | |
481 | |||
482 | { |
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1963 | serge | 483 | pci_dev_t *dev; |
2997 | Serge | 484 | u32_t last_bus; |
485 | u32_t bus = 0 , devfn = 0; |
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486 | |||
1117 | serge | 487 | |
1963 | serge | 488 | |
2997 | Serge | 489 | |
1963 | serge | 490 | |
491 | |||
2997 | Serge | 492 | return -1; |
493 | |||
1963 | serge | 494 | |
2997 | Serge | 495 | { |
496 | for (devfn = 0; devfn < 0x100; devfn += 8) |
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497 | pci_scan_slot(bus, devfn); |
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498 | |||
1963 | serge | 499 | |
500 | |||
2997 | Serge | 501 | for(dev = (pci_dev_t*)devices.next; |
502 | &dev->link != &devices; |
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503 | dev = (pci_dev_t*)dev->link.next) |
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504 | { |
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505 | dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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506 | dev->pci_dev.vendor, |
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507 | dev->pci_dev.device, |
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508 | dev->pci_dev.busnr, |
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509 | dev->pci_dev.devfn); |
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510 | |||
1963 | serge | 511 | |
2997 | Serge | 512 | return 0; |
513 | } |
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514 | |||
1963 | serge | 515 | |
2997 | Serge | 516 | { |
517 | pci_dev_t *dev; |
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518 | const struct pci_device_id *ent; |
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519 | |||
1963 | serge | 520 | |
2997 | Serge | 521 | &dev->link != &devices; |
522 | dev = (pci_dev_t*)dev->link.next) |
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523 | { |
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524 | if( dev->pci_dev.vendor != idlist->vendor ) |
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525 | continue; |
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526 | |||
527 | |||
528 | { |
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529 | if(unlikely(ent->device == dev->pci_dev.device)) |
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530 | { |
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531 | pdev->pci_dev = dev->pci_dev; |
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532 | return ent; |
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533 | } |
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534 | }; |
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535 | } |
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536 | |||
537 | |||
538 | }; |
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539 | |||
540 | |||
541 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
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542 | { |
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543 | pci_dev_t *dev; |
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544 | |||
545 | |||
546 | |||
547 | |||
548 | { |
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549 | for(; &dev->link != &devices; |
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550 | dev = (pci_dev_t*)dev->link.next) |
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551 | { |
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552 | if( &dev->pci_dev == from) |
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553 | { |
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554 | dev = (pci_dev_t*)dev->link.next; |
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555 | break; |
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1963 | serge | 556 | }; |
2997 | Serge | 557 | } |
1963 | serge | 558 | }; |
2997 | Serge | 559 | |
1963 | serge | 560 | |
2997 | Serge | 561 | dev = (pci_dev_t*)dev->link.next) |
562 | { |
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563 | if( dev->pci_dev.vendor != vendor ) |
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564 | continue; |
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565 | |||
1963 | serge | 566 | |
2997 | Serge | 567 | { |
568 | return &dev->pci_dev; |
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569 | } |
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570 | } |
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571 | return NULL; |
||
572 | }; |
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573 | |||
1963 | serge | 574 | |
575 | |||
2997 | Serge | 576 | { |
577 | pci_dev_t *dev; |
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578 | |||
1963 | serge | 579 | |
2997 | Serge | 580 | &dev->link != &devices; |
581 | dev = (pci_dev_t*)dev->link.next) |
||
582 | { |
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583 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
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584 | return &dev->pci_dev; |
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585 | } |
||
586 | return NULL; |
||
587 | } |
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1963 | serge | 588 | |
589 | |||
2997 | Serge | 590 | { |
1117 | serge | 591 | pci_dev_t *dev; |
2997 | Serge | 592 | |
1117 | serge | 593 | |
2997 | Serge | 594 | |
595 | |||
596 | { |
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1117 | serge | 597 | for(; &dev->link != &devices; |
2997 | Serge | 598 | dev = (pci_dev_t*)dev->link.next) |
599 | { |
||
600 | if( &dev->pci_dev == from) |
||
601 | { |
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602 | dev = (pci_dev_t*)dev->link.next; |
||
603 | break; |
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604 | }; |
||
605 | } |
||
606 | }; |
||
607 | |||
1117 | serge | 608 | |
2997 | Serge | 609 | dev = (pci_dev_t*)dev->link.next) |
610 | { |
||
611 | if( dev->pci_dev.class == class) |
||
612 | { |
||
613 | return &dev->pci_dev; |
||
614 | } |
||
1117 | serge | 615 | } |
616 | |||
2997 | Serge | 617 | |
618 | } |
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1117 | serge | 619 | |
620 | |||
621 | |||
2997 | Serge | 622 | #define PIO_MASK 0x0ffffUL |
623 | #define PIO_RESERVED 0x40000UL |
||
624 | |||
625 | |||
626 | unsigned long port = (unsigned long __force)addr; \ |
||
627 | if (port >= PIO_RESERVED) { \ |
||
628 | is_mmio; \ |
||
629 | } else if (port > PIO_OFFSET) { \ |
||
630 | port &= PIO_MASK; \ |
||
631 | is_pio; \ |
||
632 | }; \ |
||
633 | } while (0) |
||
634 | |||
635 | |||
636 | void __iomem *ioport_map(unsigned long port, unsigned int nr) |
||
637 | { |
||
1117 | serge | 638 | if (port > PIO_MASK) |
3764 | Serge | 639 | return NULL; |
640 | return (void __iomem *) (unsigned long) (port + PIO_OFFSET); |
||
641 | } |
||
2997 | Serge | 642 | |
1117 | serge | 643 | |
2997 | Serge | 644 | { |
645 | resource_size_t start = pci_resource_start(dev, bar); |
||
646 | resource_size_t len = pci_resource_len(dev, bar); |
||
647 | unsigned long flags = pci_resource_flags(dev, bar); |
||
648 | |||
1117 | serge | 649 | |
2997 | Serge | 650 | return NULL; |
651 | if (maxlen && len > maxlen) |
||
652 | len = maxlen; |
||
653 | if (flags & IORESOURCE_IO) |
||
654 | return ioport_map(start, len); |
||
655 | if (flags & IORESOURCE_MEM) { |
||
656 | return ioremap(start, len); |
||
657 | } |
||
658 | /* What? */ |
||
659 | return NULL; |
||
660 | } |
||
1117 | serge | 661 | |
662 | |||
2997 | Serge | 663 | { |
664 | IO_COND(addr, /* nothing */, iounmap(addr)); |
||
665 | } |
||
666 | |||
1117 | serge | 667 | |
2997 | Serge | 668 | |
669 | resource_size_t start; |
||
670 | resource_size_t end; |
||
671 | }; |
||
672 | |||
673 | |||
674 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
||
675 | struct resource *res) |
||
676 | { |
||
1117 | serge | 677 | region->start = res->start; |
2997 | Serge | 678 | region->end = res->end; |
679 | } |
||
680 | |||
1117 | serge | 681 | |
682 | |||
2997 | Serge | 683 | { |
684 | struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
||
685 | struct pci_bus_region region; |
||
686 | u32 rom_addr; |
||
687 | |||
1117 | serge | 688 | |
2997 | Serge | 689 | return -1; |
690 | |||
691 | |||
692 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
693 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
||
694 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
||
695 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
696 | return 0; |
||
697 | } |
||
1117 | serge | 698 | |
699 | |||
2997 | Serge | 700 | { |
701 | u32 rom_addr; |
||
702 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
703 | rom_addr &= ~PCI_ROM_ADDRESS_ENABLE; |
||
704 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
705 | } |
||
706 | |||
1117 | serge | 707 | |
708 | * pci_get_rom_size - obtain the actual size of the ROM image |
||
2997 | Serge | 709 | * @pdev: target PCI device |
710 | * @rom: kernel virtual pointer to image of ROM |
||
711 | * @size: size of PCI window |
||
712 | * return: size of actual ROM image |
||
713 | * |
||
1117 | serge | 714 | * Determine the actual length of the ROM image. |
2997 | Serge | 715 | * The PCI window size could be much larger than the |
716 | * actual image size. |
||
717 | */ |
||
1117 | serge | 718 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) |
2997 | Serge | 719 | { |
1117 | serge | 720 | void __iomem *image; |
2997 | Serge | 721 | int last_image; |
722 | |||
1117 | serge | 723 | |
2997 | Serge | 724 | do { |
725 | void __iomem *pds; |
||
726 | /* Standard PCI ROMs start out with these bytes 55 AA */ |
||
727 | if (readb(image) != 0x55) { |
||
728 | dev_err(&pdev->dev, "Invalid ROM contents\n"); |
||
729 | break; |
||
730 | } |
||
1117 | serge | 731 | if (readb(image + 1) != 0xAA) |
2997 | Serge | 732 | break; |
733 | /* get the PCI data structure and check its signature */ |
||
734 | pds = image + readw(image + 24); |
||
735 | if (readb(pds) != 'P') |
||
736 | break; |
||
737 | if (readb(pds + 1) != 'C') |
||
738 | break; |
||
739 | if (readb(pds + 2) != 'I') |
||
740 | break; |
||
741 | if (readb(pds + 3) != 'R') |
||
742 | break; |
||
743 | last_image = readb(pds + 21) & 0x80; |
||
744 | /* this length is reliable */ |
||
745 | image += readw(pds + 16) * 512; |
||
746 | } while (!last_image); |
||
747 | |||
1963 | serge | 748 | |
2997 | Serge | 749 | /* there are known ROMs that get the size wrong */ |
750 | return min((size_t)(image - rom), size); |
||
751 | } |
||
752 | |||
1117 | serge | 753 | |
754 | |||
755 | * pci_map_rom - map a PCI ROM to kernel space |
||
756 | * @pdev: pointer to pci device struct |
||
757 | * @size: pointer to receive size of pci window over ROM |
||
758 | * |
||
759 | * Return: kernel virtual pointer to image of ROM |
||
2997 | Serge | 760 | * |
761 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
1117 | serge | 762 | * the shadow BIOS copy will be returned instead of the |
763 | * actual ROM. |
||
764 | */ |
||
765 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) |
||
2997 | Serge | 766 | { |
1117 | serge | 767 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
768 | loff_t start; |
||
2997 | Serge | 769 | void __iomem *rom; |
770 | |||
1117 | serge | 771 | |
2997 | Serge | 772 | |
773 | |||
774 | // res->start, res->end, res->flags); |
||
775 | /* |
||
1963 | serge | 776 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
777 | * memory map if the VGA enable bit of the Bridge Control register is |
||
778 | * set for embedded VGA. |
||
779 | */ |
||
780 | |||
2997 | Serge | 781 | |
782 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
783 | |||
784 | |||
785 | |||
786 | |||
1963 | serge | 787 | /* primary video rom always starts here */ |
788 | start = (loff_t)0xC0000; |
||
2997 | Serge | 789 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
1963 | serge | 790 | } else { |
791 | if (res->flags & |
||
3764 | Serge | 792 | (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
793 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
1963 | serge | 794 | return (void __iomem *)(unsigned long) |
2997 | Serge | 795 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
796 | } else { |
||
1963 | serge | 797 | /* assign the ROM an address if it doesn't have one */ |
798 | // if (res->parent == NULL && |
||
2997 | Serge | 799 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
800 | return NULL; |
||
1963 | serge | 801 | // start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
2997 | Serge | 802 | // *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
803 | // if (*size == 0) |
||
804 | // return NULL; |
||
805 | |||
1963 | serge | 806 | |
807 | // if (pci_enable_rom(pdev)) |
||
2997 | Serge | 808 | // return NULL; |
809 | } |
||
1963 | serge | 810 | } |
811 | #endif |
||
2997 | Serge | 812 | |
1963 | serge | 813 | |
814 | if (!rom) { |
||
815 | /* restore enable if ioremap fails */ |
||
816 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
817 | IORESOURCE_ROM_SHADOW | |
||
818 | IORESOURCE_ROM_COPY))) |
||
819 | pci_disable_rom(pdev); |
||
820 | return NULL; |
||
821 | } |
||
822 | |||
823 | |||
824 | * Try to find the true size of the ROM since sometimes the PCI window |
||
825 | * size is much larger than the actual size of the ROM. |
||
826 | * True size is important if the ROM is going to be copied. |
||
827 | */ |
||
828 | *size = pci_get_rom_size(pdev, rom, *size); |
||
2997 | Serge | 829 | // LEAVE(); |
830 | return rom; |
||
831 | } |
||
832 | |||
1963 | serge | 833 | |
2997 | Serge | 834 | { |
835 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
836 | |||
1117 | serge | 837 | |
2997 | Serge | 838 | return; |
839 | |||
1117 | serge | 840 | |
2997 | Serge | 841 | |
842 | |||
843 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
||
844 | pci_disable_rom(pdev); |
||
845 | } |
||
846 | |||
847 | |||
848 | { |
||
849 | u16 old_cmd, cmd; |
||
850 | |||
851 | |||
852 | if (enable) |
||
853 | cmd = old_cmd | PCI_COMMAND_MASTER; |
||
854 | else |
||
1117 | serge | 855 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
2997 | Serge | 856 | if (cmd != old_cmd) { |
857 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
858 | } |
||
859 | dev->is_busmaster = enable; |
||
860 | } |
||
861 | |||
1117 | serge | 862 | |
2997 | Serge | 863 | |
864 | * @dev: the PCI device to enable |
||
865 | * |
||
866 | * Enables bus-mastering on the device and calls pcibios_set_master() |
||
867 | * to do the needed arch specific settings. |
||
868 | */ |
||
869 | void pci_set_master(struct pci_dev *dev) |
||
870 | { |
||
871 | __pci_set_master(dev, true); |
||
872 | // pcibios_set_master(dev); |
||
873 | } |
||
1117 | serge | 874 | |
875 | |||
2997 | Serge | 876 | * pci_clear_master - disables bus-mastering for device dev |
877 | * @dev: the PCI device to disable |
||
878 | */ |
||
879 | void pci_clear_master(struct pci_dev *dev) |
||
880 | { |
||
881 | __pci_set_master(dev, false); |
||
882 | } |
||
883 | |||
1119 | serge | 884 | |
2997 | Serge | 885 | |
886 | { |
||
1119 | serge | 887 | return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS; |
2997 | Serge | 888 | } |
889 | |||
1119 | serge | 890 | |
2997 | Serge | 891 | { |
892 | return true; |
||
893 | } |
||
894 | |||
1119 | serge | 895 | |
2997 | Serge | 896 | { |
897 | int type = pci_pcie_type(dev); |
||
898 | |||
899 | |||
900 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
901 | type == PCI_EXP_TYPE_ENDPOINT || |
||
902 | type == PCI_EXP_TYPE_LEG_END; |
||
903 | } |
||
904 | |||
905 | |||
906 | { |
||
907 | int type = pci_pcie_type(dev); |
||
908 | |||
909 | |||
910 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
911 | (type == PCI_EXP_TYPE_DOWNSTREAM && |
||
912 | dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT); |
||
913 | } |
||
914 | |||
915 | |||
916 | { |
||
917 | int type = pci_pcie_type(dev); |
||
918 | |||
919 | |||
920 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
921 | type == PCI_EXP_TYPE_RC_EC; |
||
922 | } |
||
923 | |||
924 | |||
925 | { |
||
926 | if (!pci_is_pcie(dev)) |
||
927 | return false; |
||
928 | |||
929 | |||
930 | case PCI_EXP_FLAGS_TYPE: |
||
931 | return true; |
||
932 | case PCI_EXP_DEVCAP: |
||
933 | case PCI_EXP_DEVCTL: |
||
934 | case PCI_EXP_DEVSTA: |
||
935 | return pcie_cap_has_devctl(dev); |
||
936 | case PCI_EXP_LNKCAP: |
||
937 | case PCI_EXP_LNKCTL: |
||
938 | case PCI_EXP_LNKSTA: |
||
939 | return pcie_cap_has_lnkctl(dev); |
||
940 | case PCI_EXP_SLTCAP: |
||
941 | case PCI_EXP_SLTCTL: |
||
942 | case PCI_EXP_SLTSTA: |
||
943 | return pcie_cap_has_sltctl(dev); |
||
944 | case PCI_EXP_RTCTL: |
||
945 | case PCI_EXP_RTCAP: |
||
946 | case PCI_EXP_RTSTA: |
||
947 | return pcie_cap_has_rtctl(dev); |
||
948 | case PCI_EXP_DEVCAP2: |
||
949 | case PCI_EXP_DEVCTL2: |
||
950 | case PCI_EXP_LNKCAP2: |
||
951 | case PCI_EXP_LNKCTL2: |
||
952 | case PCI_EXP_LNKSTA2: |
||
953 | return pcie_cap_version(dev) > 1; |
||
954 | default: |
||
955 | return false; |
||
956 | } |
||
957 | } |
||
958 | |||
959 | |||
960 | * Note that these accessor functions are only for the "PCI Express |
||
961 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
||
962 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
||
963 | */ |
||
964 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
||
965 | { |
||
966 | int ret; |
||
967 | |||
968 | |||
969 | if (pos & 1) |
||
970 | return -EINVAL; |
||
971 | |||
972 | |||
973 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
||
974 | /* |
||
975 | * Reset *val to 0 if pci_read_config_word() fails, it may |
||
976 | * have been written as 0xFFFF if hardware error happens |
||
977 | * during pci_read_config_word(). |
||
978 | */ |
||
979 | if (ret) |
||
980 | *val = 0; |
||
981 | return ret; |
||
982 | } |
||
983 | |||
984 | |||
985 | * For Functions that do not implement the Slot Capabilities, |
||
986 | * Slot Status, and Slot Control registers, these spaces must |
||
987 | * be hardwired to 0b, with the exception of the Presence Detect |
||
988 | * State bit in the Slot Status register of Downstream Ports, |
||
989 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
||
990 | */ |
||
991 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && |
||
992 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
993 | *val = PCI_EXP_SLTSTA_PDS; |
||
994 | } |
||
995 | |||
996 | |||
997 | } |
||
998 | EXPORT_SYMBOL(pcie_capability_read_word); |
||
999 | |||
1000 | |||
1001 | { |
||
1002 | int ret; |
||
1003 | |||
1004 | |||
1005 | if (pos & 3) |
||
1006 | return -EINVAL; |
||
1007 | |||
1008 | |||
1009 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
||
1010 | /* |
||
1011 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
||
1012 | * have been written as 0xFFFFFFFF if hardware error happens |
||
1013 | * during pci_read_config_dword(). |
||
1014 | */ |
||
1015 | if (ret) |
||
1016 | *val = 0; |
||
1017 | return ret; |
||
1018 | } |
||
1019 | |||
1020 | |||
1021 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
1022 | *val = PCI_EXP_SLTSTA_PDS; |
||
1023 | } |
||
1024 | |||
1025 | |||
1026 | } |
||
1027 | EXPORT_SYMBOL(pcie_capability_read_dword); |
||
1028 | |||
1029 | |||
1030 | { |
||
1031 | if (pos & 1) |
||
1032 | return -EINVAL; |
||
1033 | |||
1034 | |||
1035 | return 0; |
||
1119 | serge | 1036 | |
2997 | Serge | 1037 | |
1038 | } |
||
1119 | serge | 1039 | EXPORT_SYMBOL(pcie_capability_write_word); |
2997 | Serge | 1040 | |
1119 | serge | 1041 | |
2997 | Serge | 1042 | { |
1043 | if (pos & 3) |
||
1044 | return -EINVAL; |
||
1045 | |||
1963 | serge | 1046 | |
2997 | Serge | 1047 | return 0; |
1048 | |||
1049 | |||
1050 | } |
||
1051 | EXPORT_SYMBOL(pcie_capability_write_dword);>=>>>><>><>><>>4)><4)> |
||
1052 |