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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
1403 | serge | 2 | #include |
2997 | Serge | 3 | #include |
1630 | serge | 4 | #include |
1963 | serge | 5 | #include |
2160 | serge | 6 | #include |
1117 | serge | 7 | #include |
8 | |||
9 | |||
2997 | Serge | 10 | |
11 | |||
1120 | serge | 12 | |
1117 | serge | 13 | |
14 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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15 | |||
16 | |||
17 | |||
18 | |||
19 | * Translate the low bits of the PCI base |
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20 | * to the resource type |
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21 | */ |
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22 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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23 | { |
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24 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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25 | return IORESOURCE_IO; |
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26 | |||
27 | |||
28 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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29 | |||
30 | |||
31 | } |
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32 | |||
33 | |||
34 | |||
35 | { |
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36 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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37 | |||
38 | |||
39 | return 0; |
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40 | |||
41 | |||
42 | from that the extent. */ |
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43 | size = (size & ~(size-1)) - 1; |
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44 | |||
45 | |||
46 | already been programmed with all 1s. */ |
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47 | if (base == maxbase && ((base | size) & mask) != mask) |
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48 | return 0; |
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49 | |||
50 | |||
51 | } |
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52 | |||
53 | |||
54 | { |
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55 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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56 | |||
57 | |||
58 | return 0; |
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59 | |||
60 | |||
61 | from that the extent. */ |
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62 | size = (size & ~(size-1)) - 1; |
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63 | |||
64 | |||
65 | already been programmed with all 1s. */ |
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66 | if (base == maxbase && ((base | size) & mask) != mask) |
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67 | return 0; |
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68 | |||
69 | |||
70 | } |
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71 | |||
72 | |||
73 | { |
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74 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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75 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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76 | return 1; |
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77 | return 0; |
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78 | } |
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79 | |||
80 | |||
81 | { |
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82 | u32_t pos, reg, next; |
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83 | u32_t l, sz; |
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84 | struct resource *res; |
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85 | |||
86 | |||
87 | { |
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88 | u64_t l64; |
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89 | u64_t sz64; |
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90 | u32_t raw_sz; |
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91 | |||
92 | |||
93 | |||
94 | |||
95 | |||
96 | |||
97 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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2160 | serge | 98 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
99 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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100 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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101 | |||
1117 | serge | 102 | |
103 | continue; |
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104 | |||
105 | |||
106 | l = 0; |
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107 | |||
108 | |||
109 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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110 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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111 | { |
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112 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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113 | /* |
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114 | * For 64bit prefetchable memory sz could be 0, if the |
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115 | * real size is bigger than 4G, so we need to check |
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116 | * szhi for that. |
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117 | */ |
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118 | if (!is_64bit_memory(l) && !sz) |
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119 | continue; |
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120 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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121 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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122 | } |
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123 | else { |
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124 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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125 | if (!sz) |
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126 | continue; |
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127 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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128 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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129 | } |
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130 | res->end = res->start + (unsigned long) sz; |
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131 | res->flags |= pci_calc_resource_flags(l); |
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132 | if (is_64bit_memory(l)) |
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133 | { |
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134 | u32_t szhi, lhi; |
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135 | |||
136 | |||
2160 | serge | 137 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
138 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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139 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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140 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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1117 | serge | 141 | l64 = ((u64_t)lhi << 32) | l; |
142 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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143 | next++; |
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144 | |||
145 | |||
146 | if (!sz64) { |
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147 | res->start = 0; |
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148 | res->end = 0; |
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149 | res->flags = 0; |
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150 | continue; |
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151 | } |
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152 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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153 | res->end = res->start + sz64; |
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154 | #else |
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155 | if (sz64 > 0x100000000ULL) { |
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156 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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157 | "BAR for device %s\n", pci_name(dev)); |
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158 | res->start = 0; |
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159 | res->flags = 0; |
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160 | } |
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161 | else if (lhi) |
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162 | { |
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163 | /* 64-bit wide address, treat as disabled */ |
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164 | PciWrite32(dev->busnr, dev->devfn, reg, |
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2160 | serge | 165 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 166 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
2160 | serge | 167 | res->start = 0; |
1117 | serge | 168 | res->end = sz; |
169 | } |
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170 | #endif |
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171 | } |
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172 | } |
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173 | |||
174 | |||
175 | { |
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176 | dev->rom_base_reg = rom; |
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177 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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178 | |||
179 | |||
2160 | serge | 180 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
181 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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182 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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183 | |||
1117 | serge | 184 | |
185 | l = 0; |
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186 | |||
187 | |||
188 | { |
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189 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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190 | |||
191 | |||
192 | { |
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193 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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194 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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195 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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196 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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197 | res->end = res->start + (unsigned long) sz; |
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198 | } |
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199 | } |
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200 | } |
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201 | } |
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202 | |||
203 | |||
204 | { |
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205 | u8_t irq; |
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206 | |||
207 | |||
2160 | serge | 208 | dev->pin = irq; |
1117 | serge | 209 | if (irq) |
210 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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2160 | serge | 211 | dev->irq = irq; |
1117 | serge | 212 | }; |
213 | |||
214 | |||
215 | |||
2160 | serge | 216 | { |
1117 | serge | 217 | u32_t class; |
218 | |||
219 | |||
2160 | serge | 220 | dev->revision = class & 0xff; |
1117 | serge | 221 | class >>= 8; /* upper 3 bytes */ |
222 | dev->class = class; |
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223 | |||
224 | |||
225 | // dev->current_state = PCI_UNKNOWN; |
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226 | |||
227 | |||
228 | // pci_fixup_device(pci_fixup_early, dev); |
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229 | class = dev->class >> 8; |
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230 | |||
231 | |||
232 | { |
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233 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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234 | if (class == PCI_CLASS_BRIDGE_PCI) |
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235 | goto bad; |
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236 | pci_read_irq(dev); |
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237 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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238 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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2160 | serge | 239 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
240 | |||
1117 | serge | 241 | |
242 | * Do the ugly legacy mode stuff here rather than broken chip |
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243 | * quirk code. Legacy mode ATA controllers have fixed |
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244 | * addresses. These are not always echoed in BAR0-3, and |
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245 | * BAR0-3 in a few cases contain junk! |
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246 | */ |
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247 | if (class == PCI_CLASS_STORAGE_IDE) |
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248 | { |
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249 | u8_t progif; |
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250 | |||
251 | |||
2160 | serge | 252 | if ((progif & 1) == 0) |
1117 | serge | 253 | { |
254 | dev->resource[0].start = 0x1F0; |
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255 | dev->resource[0].end = 0x1F7; |
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256 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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257 | dev->resource[1].start = 0x3F6; |
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258 | dev->resource[1].end = 0x3F6; |
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259 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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260 | } |
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261 | if ((progif & 4) == 0) |
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262 | { |
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263 | dev->resource[2].start = 0x170; |
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264 | dev->resource[2].end = 0x177; |
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265 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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266 | dev->resource[3].start = 0x376; |
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267 | dev->resource[3].end = 0x376; |
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268 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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269 | }; |
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270 | } |
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271 | break; |
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272 | |||
273 | |||
274 | if (class != PCI_CLASS_BRIDGE_PCI) |
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275 | goto bad; |
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276 | /* The PCI-to-PCI bridge spec requires that subtractive |
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277 | decoding (i.e. transparent) bridge must have programming |
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278 | interface code of 0x01. */ |
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279 | pci_read_irq(dev); |
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280 | dev->transparent = ((dev->class & 0xff) == 1); |
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281 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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282 | break; |
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283 | |||
284 | |||
285 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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286 | goto bad; |
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287 | pci_read_irq(dev); |
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288 | pci_read_bases(dev, 1, 0); |
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289 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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2160 | serge | 290 | dev->devfn, |
1117 | serge | 291 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
292 | |||
293 | |||
2160 | serge | 294 | dev->devfn, |
1117 | serge | 295 | PCI_CB_SUBSYSTEM_ID); |
296 | break; |
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297 | |||
298 | |||
299 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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300 | pci_name(dev), dev->hdr_type); |
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301 | return -1; |
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302 | |||
303 | |||
304 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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305 | pci_name(dev), class, dev->hdr_type); |
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306 | dev->class = PCI_CLASS_NOT_DEFINED; |
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307 | } |
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308 | |||
309 | |||
310 | |||
311 | |||
312 | }; |
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313 | |||
314 | |||
2160 | serge | 315 | { |
1117 | serge | 316 | pci_dev_t *dev; |
1403 | serge | 317 | |
1117 | serge | 318 | |
319 | u8_t hdr; |
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320 | |||
321 | |||
322 | |||
323 | |||
2160 | serge | 324 | |
1117 | serge | 325 | |
326 | if (id == 0xffffffff || id == 0x00000000 || |
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327 | id == 0x0000ffff || id == 0xffff0000) |
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328 | return NULL; |
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329 | |||
330 | |||
331 | { |
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332 | |||
333 | |||
334 | timeout *= 2; |
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335 | |||
336 | |||
2160 | serge | 337 | |
1117 | serge | 338 | |
339 | if (timeout > 60 * 100) |
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340 | { |
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341 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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342 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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2160 | serge | 343 | return NULL; |
1117 | serge | 344 | } |
345 | }; |
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346 | |||
347 | |||
2997 | Serge | 348 | return NULL; |
349 | |||
350 | |||
2160 | serge | 351 | |
1117 | serge | 352 | |
1404 | serge | 353 | if(unlikely(dev == NULL)) |
2997 | Serge | 354 | return NULL; |
355 | |||
1117 | serge | 356 | |
1120 | serge | 357 | |
1117 | serge | 358 | |
359 | |||
2160 | serge | 360 | dev->pci_dev.devfn = devfn; |
1117 | serge | 361 | dev->pci_dev.hdr_type = hdr & 0x7f; |
362 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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363 | dev->pci_dev.vendor = id & 0xffff; |
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364 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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365 | |||
366 | |||
367 | |||
368 | |||
369 | |||
370 | |||
371 | |||
372 | |||
2997 | Serge | 373 | |
374 | |||
375 | |||
1117 | serge | 376 | { |
377 | int func, nr = 0; |
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378 | |||
379 | |||
380 | { |
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381 | pci_dev_t *dev; |
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1403 | serge | 382 | |
1117 | serge | 383 | |
384 | if( dev ) |
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385 | { |
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386 | list_add(&dev->link, &devices); |
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1120 | serge | 387 | |
1117 | serge | 388 | |
389 | |||
390 | |||
391 | * If this is a single function device, |
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392 | * don't scan past the first function. |
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393 | */ |
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394 | if (!dev->pci_dev.multifunction) |
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395 | { |
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396 | if (func > 0) { |
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397 | dev->pci_dev.multifunction = 1; |
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398 | } |
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399 | else { |
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400 | break; |
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401 | } |
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402 | } |
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403 | } |
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404 | else { |
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405 | if (func == 0) |
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406 | break; |
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407 | } |
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408 | }; |
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409 | |||
410 | |||
411 | }; |
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412 | |||
413 | |||
1239 | serge | 414 | |
415 | |||
416 | u8 pos, int cap, int *ttl) |
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417 | { |
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418 | u8 id; |
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419 | |||
420 | |||
421 | pos = PciRead8(bus, devfn, pos); |
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422 | if (pos < 0x40) |
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423 | break; |
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424 | pos &= ~3; |
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425 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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426 | if (id == 0xff) |
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427 | break; |
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428 | if (id == cap) |
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429 | return pos; |
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430 | pos += PCI_CAP_LIST_NEXT; |
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431 | } |
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432 | return 0; |
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433 | } |
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434 | |||
435 | |||
436 | u8 pos, int cap) |
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437 | { |
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438 | int ttl = PCI_FIND_CAP_TTL; |
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439 | |||
440 | |||
441 | } |
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442 | |||
443 | |||
444 | unsigned int devfn, u8 hdr_type) |
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445 | { |
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446 | u16 status; |
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447 | |||
448 | |||
449 | if (!(status & PCI_STATUS_CAP_LIST)) |
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450 | return 0; |
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451 | |||
452 | |||
453 | case PCI_HEADER_TYPE_NORMAL: |
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454 | case PCI_HEADER_TYPE_BRIDGE: |
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455 | return PCI_CAPABILITY_LIST; |
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456 | case PCI_HEADER_TYPE_CARDBUS: |
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457 | return PCI_CB_CAPABILITY_LIST; |
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458 | default: |
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459 | return 0; |
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460 | } |
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461 | |||
462 | |||
463 | } |
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464 | |||
465 | |||
466 | |||
467 | { |
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468 | int pos; |
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469 | |||
470 | |||
2160 | serge | 471 | if (pos) |
1239 | serge | 472 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
2160 | serge | 473 | |
1239 | serge | 474 | |
475 | } |
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476 | |||
477 | |||
478 | |||
2997 | Serge | 479 | |
480 | |||
481 | { |
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1963 | serge | 482 | pci_dev_t *dev; |
2997 | Serge | 483 | u32_t last_bus; |
484 | u32_t bus = 0 , devfn = 0; |
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485 | |||
1117 | serge | 486 | |
1963 | serge | 487 | |
2997 | Serge | 488 | |
1963 | serge | 489 | |
490 | |||
2997 | Serge | 491 | return -1; |
492 | |||
1963 | serge | 493 | |
2997 | Serge | 494 | { |
495 | for (devfn = 0; devfn < 0x100; devfn += 8) |
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496 | pci_scan_slot(bus, devfn); |
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497 | |||
1963 | serge | 498 | |
499 | |||
2997 | Serge | 500 | for(dev = (pci_dev_t*)devices.next; |
501 | &dev->link != &devices; |
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502 | dev = (pci_dev_t*)dev->link.next) |
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503 | { |
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504 | dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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505 | dev->pci_dev.vendor, |
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506 | dev->pci_dev.device, |
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507 | dev->pci_dev.busnr, |
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508 | dev->pci_dev.devfn); |
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509 | |||
1963 | serge | 510 | |
2997 | Serge | 511 | return 0; |
512 | } |
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513 | |||
1963 | serge | 514 | |
2997 | Serge | 515 | { |
516 | pci_dev_t *dev; |
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517 | const struct pci_device_id *ent; |
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518 | |||
1963 | serge | 519 | |
2997 | Serge | 520 | &dev->link != &devices; |
521 | dev = (pci_dev_t*)dev->link.next) |
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522 | { |
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523 | if( dev->pci_dev.vendor != idlist->vendor ) |
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524 | continue; |
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525 | |||
526 | |||
527 | { |
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528 | if(unlikely(ent->device == dev->pci_dev.device)) |
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529 | { |
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530 | pdev->pci_dev = dev->pci_dev; |
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531 | return ent; |
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532 | } |
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533 | }; |
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534 | } |
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535 | |||
536 | |||
537 | }; |
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538 | |||
539 | |||
540 | pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from) |
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541 | { |
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542 | pci_dev_t *dev; |
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543 | |||
544 | |||
545 | |||
546 | |||
547 | { |
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548 | for(; &dev->link != &devices; |
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549 | dev = (pci_dev_t*)dev->link.next) |
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550 | { |
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551 | if( &dev->pci_dev == from) |
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552 | { |
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553 | dev = (pci_dev_t*)dev->link.next; |
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554 | break; |
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1963 | serge | 555 | }; |
2997 | Serge | 556 | } |
1963 | serge | 557 | }; |
2997 | Serge | 558 | |
1963 | serge | 559 | |
2997 | Serge | 560 | dev = (pci_dev_t*)dev->link.next) |
561 | { |
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562 | if( dev->pci_dev.vendor != vendor ) |
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563 | continue; |
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564 | |||
1963 | serge | 565 | |
2997 | Serge | 566 | { |
567 | return &dev->pci_dev; |
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568 | } |
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569 | } |
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570 | return NULL; |
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571 | }; |
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572 | |||
1963 | serge | 573 | |
574 | |||
2997 | Serge | 575 | { |
576 | pci_dev_t *dev; |
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577 | |||
1963 | serge | 578 | |
2997 | Serge | 579 | &dev->link != &devices; |
580 | dev = (pci_dev_t*)dev->link.next) |
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581 | { |
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582 | if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn) |
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583 | return &dev->pci_dev; |
||
584 | } |
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585 | return NULL; |
||
586 | } |
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1963 | serge | 587 | |
588 | |||
2997 | Serge | 589 | { |
1117 | serge | 590 | pci_dev_t *dev; |
2997 | Serge | 591 | |
1117 | serge | 592 | |
2997 | Serge | 593 | |
594 | |||
595 | { |
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1117 | serge | 596 | for(; &dev->link != &devices; |
2997 | Serge | 597 | dev = (pci_dev_t*)dev->link.next) |
598 | { |
||
599 | if( &dev->pci_dev == from) |
||
600 | { |
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601 | dev = (pci_dev_t*)dev->link.next; |
||
602 | break; |
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603 | }; |
||
604 | } |
||
605 | }; |
||
606 | |||
1117 | serge | 607 | |
2997 | Serge | 608 | dev = (pci_dev_t*)dev->link.next) |
609 | { |
||
610 | if( dev->pci_dev.class == class) |
||
611 | { |
||
612 | return &dev->pci_dev; |
||
613 | } |
||
1117 | serge | 614 | } |
615 | |||
2997 | Serge | 616 | |
617 | } |
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1117 | serge | 618 | |
619 | |||
620 | |||
2997 | Serge | 621 | #define PIO_MASK 0x0ffffUL |
622 | #define PIO_RESERVED 0x40000UL |
||
623 | |||
624 | |||
625 | unsigned long port = (unsigned long __force)addr; \ |
||
626 | if (port >= PIO_RESERVED) { \ |
||
627 | is_mmio; \ |
||
628 | } else if (port > PIO_OFFSET) { \ |
||
629 | port &= PIO_MASK; \ |
||
630 | is_pio; \ |
||
631 | }; \ |
||
632 | } while (0) |
||
633 | |||
634 | |||
635 | void __iomem *ioport_map(unsigned long port, unsigned int nr) |
||
636 | { |
||
1117 | serge | 637 | return (void __iomem *) port; |
2997 | Serge | 638 | } |
639 | |||
1117 | serge | 640 | |
2997 | Serge | 641 | { |
642 | resource_size_t start = pci_resource_start(dev, bar); |
||
643 | resource_size_t len = pci_resource_len(dev, bar); |
||
644 | unsigned long flags = pci_resource_flags(dev, bar); |
||
645 | |||
1117 | serge | 646 | |
2997 | Serge | 647 | return NULL; |
648 | if (maxlen && len > maxlen) |
||
649 | len = maxlen; |
||
650 | if (flags & IORESOURCE_IO) |
||
651 | return ioport_map(start, len); |
||
652 | if (flags & IORESOURCE_MEM) { |
||
653 | return ioremap(start, len); |
||
654 | } |
||
655 | /* What? */ |
||
656 | return NULL; |
||
657 | } |
||
1117 | serge | 658 | |
659 | |||
2997 | Serge | 660 | { |
661 | IO_COND(addr, /* nothing */, iounmap(addr)); |
||
662 | } |
||
663 | |||
1117 | serge | 664 | |
2997 | Serge | 665 | |
666 | resource_size_t start; |
||
667 | resource_size_t end; |
||
668 | }; |
||
669 | |||
670 | |||
671 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
||
672 | struct resource *res) |
||
673 | { |
||
1117 | serge | 674 | region->start = res->start; |
2997 | Serge | 675 | region->end = res->end; |
676 | } |
||
677 | |||
1117 | serge | 678 | |
2997 | Serge | 679 | u32 *val) |
680 | { |
||
681 | *val = PciRead32(dev->busnr, dev->devfn, where); |
||
682 | return 1; |
||
683 | } |
||
684 | |||
1117 | serge | 685 | |
2997 | Serge | 686 | u32 val) |
687 | { |
||
688 | PciWrite32(dev->busnr, dev->devfn, where, val); |
||
689 | return 1; |
||
690 | } |
||
1117 | serge | 691 | |
692 | |||
2997 | Serge | 693 | u16 *val) |
694 | { |
||
695 | *val = PciRead16(dev->busnr, dev->devfn, where); |
||
696 | return 1; |
||
697 | } |
||
698 | |||
1117 | serge | 699 | |
2997 | Serge | 700 | u16 val) |
701 | { |
||
1117 | serge | 702 | PciWrite16(dev->busnr, dev->devfn, where, val); |
2997 | Serge | 703 | return 1; |
704 | } |
||
705 | |||
1117 | serge | 706 | |
707 | |||
2997 | Serge | 708 | { |
709 | struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
||
710 | struct pci_bus_region region; |
||
711 | u32 rom_addr; |
||
712 | |||
1117 | serge | 713 | |
2997 | Serge | 714 | return -1; |
715 | |||
716 | |||
717 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
718 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
||
719 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; |
||
720 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
721 | return 0; |
||
722 | } |
||
1117 | serge | 723 | |
724 | |||
2997 | Serge | 725 | { |
726 | u32 rom_addr; |
||
727 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
||
728 | rom_addr &= ~PCI_ROM_ADDRESS_ENABLE; |
||
729 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
||
730 | } |
||
731 | |||
1117 | serge | 732 | |
733 | * pci_get_rom_size - obtain the actual size of the ROM image |
||
2997 | Serge | 734 | * @pdev: target PCI device |
735 | * @rom: kernel virtual pointer to image of ROM |
||
736 | * @size: size of PCI window |
||
737 | * return: size of actual ROM image |
||
738 | * |
||
1117 | serge | 739 | * Determine the actual length of the ROM image. |
2997 | Serge | 740 | * The PCI window size could be much larger than the |
741 | * actual image size. |
||
742 | */ |
||
1117 | serge | 743 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) |
2997 | Serge | 744 | { |
1117 | serge | 745 | void __iomem *image; |
2997 | Serge | 746 | int last_image; |
747 | |||
1117 | serge | 748 | |
2997 | Serge | 749 | do { |
750 | void __iomem *pds; |
||
751 | /* Standard PCI ROMs start out with these bytes 55 AA */ |
||
752 | if (readb(image) != 0x55) { |
||
753 | dev_err(&pdev->dev, "Invalid ROM contents\n"); |
||
754 | break; |
||
755 | } |
||
1117 | serge | 756 | if (readb(image + 1) != 0xAA) |
2997 | Serge | 757 | break; |
758 | /* get the PCI data structure and check its signature */ |
||
759 | pds = image + readw(image + 24); |
||
760 | if (readb(pds) != 'P') |
||
761 | break; |
||
762 | if (readb(pds + 1) != 'C') |
||
763 | break; |
||
764 | if (readb(pds + 2) != 'I') |
||
765 | break; |
||
766 | if (readb(pds + 3) != 'R') |
||
767 | break; |
||
768 | last_image = readb(pds + 21) & 0x80; |
||
769 | /* this length is reliable */ |
||
770 | image += readw(pds + 16) * 512; |
||
771 | } while (!last_image); |
||
772 | |||
1963 | serge | 773 | |
2997 | Serge | 774 | /* there are known ROMs that get the size wrong */ |
775 | return min((size_t)(image - rom), size); |
||
776 | } |
||
777 | |||
1117 | serge | 778 | |
779 | |||
780 | * pci_map_rom - map a PCI ROM to kernel space |
||
781 | * @pdev: pointer to pci device struct |
||
782 | * @size: pointer to receive size of pci window over ROM |
||
783 | * |
||
784 | * Return: kernel virtual pointer to image of ROM |
||
2997 | Serge | 785 | * |
786 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
1117 | serge | 787 | * the shadow BIOS copy will be returned instead of the |
788 | * actual ROM. |
||
789 | */ |
||
790 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) |
||
2997 | Serge | 791 | { |
1117 | serge | 792 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
793 | loff_t start; |
||
2997 | Serge | 794 | void __iomem *rom; |
795 | |||
1117 | serge | 796 | |
2997 | Serge | 797 | |
798 | |||
799 | // res->start, res->end, res->flags); |
||
800 | /* |
||
1963 | serge | 801 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
802 | * memory map if the VGA enable bit of the Bridge Control register is |
||
803 | * set for embedded VGA. |
||
804 | */ |
||
805 | |||
2997 | Serge | 806 | |
807 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
808 | |||
809 | |||
810 | |||
811 | |||
1963 | serge | 812 | /* primary video rom always starts here */ |
813 | start = (loff_t)0xC0000; |
||
2997 | Serge | 814 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
1963 | serge | 815 | } else { |
816 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
||
817 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
818 | return (void __iomem *)(unsigned long) |
||
2997 | Serge | 819 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
820 | } else { |
||
1963 | serge | 821 | /* assign the ROM an address if it doesn't have one */ |
822 | // if (res->parent == NULL && |
||
2997 | Serge | 823 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
824 | return NULL; |
||
1963 | serge | 825 | // start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
2997 | Serge | 826 | // *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
827 | // if (*size == 0) |
||
828 | // return NULL; |
||
829 | |||
1963 | serge | 830 | |
831 | // if (pci_enable_rom(pdev)) |
||
2997 | Serge | 832 | // return NULL; |
833 | } |
||
1963 | serge | 834 | } |
835 | #endif |
||
2997 | Serge | 836 | |
1963 | serge | 837 | |
838 | if (!rom) { |
||
839 | /* restore enable if ioremap fails */ |
||
840 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
841 | IORESOURCE_ROM_SHADOW | |
||
842 | IORESOURCE_ROM_COPY))) |
||
843 | pci_disable_rom(pdev); |
||
844 | return NULL; |
||
845 | } |
||
846 | |||
847 | |||
848 | * Try to find the true size of the ROM since sometimes the PCI window |
||
849 | * size is much larger than the actual size of the ROM. |
||
850 | * True size is important if the ROM is going to be copied. |
||
851 | */ |
||
852 | *size = pci_get_rom_size(pdev, rom, *size); |
||
2997 | Serge | 853 | // LEAVE(); |
854 | return rom; |
||
855 | } |
||
856 | |||
1963 | serge | 857 | |
2997 | Serge | 858 | { |
859 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
860 | |||
1117 | serge | 861 | |
2997 | Serge | 862 | return; |
863 | |||
1117 | serge | 864 | |
2997 | Serge | 865 | |
866 | |||
867 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) |
||
868 | pci_disable_rom(pdev); |
||
869 | } |
||
870 | |||
871 | |||
872 | { |
||
873 | dev->dma_mask = mask; |
||
874 | |||
875 | |||
876 | } |
||
877 | |||
878 | |||
879 | |||
880 | |||
881 | { |
||
882 | u16 old_cmd, cmd; |
||
883 | |||
884 | |||
885 | if (enable) |
||
886 | cmd = old_cmd | PCI_COMMAND_MASTER; |
||
887 | else |
||
1117 | serge | 888 | cmd = old_cmd & ~PCI_COMMAND_MASTER; |
2997 | Serge | 889 | if (cmd != old_cmd) { |
890 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
891 | } |
||
892 | dev->is_busmaster = enable; |
||
893 | } |
||
894 | |||
1117 | serge | 895 | |
2997 | Serge | 896 | |
897 | * @dev: the PCI device to enable |
||
898 | * |
||
899 | * Enables bus-mastering on the device and calls pcibios_set_master() |
||
900 | * to do the needed arch specific settings. |
||
901 | */ |
||
902 | void pci_set_master(struct pci_dev *dev) |
||
903 | { |
||
904 | __pci_set_master(dev, true); |
||
905 | // pcibios_set_master(dev); |
||
906 | } |
||
1117 | serge | 907 | |
908 | |||
2997 | Serge | 909 | * pci_clear_master - disables bus-mastering for device dev |
910 | * @dev: the PCI device to disable |
||
911 | */ |
||
912 | void pci_clear_master(struct pci_dev *dev) |
||
913 | { |
||
914 | __pci_set_master(dev, false); |
||
915 | } |
||
916 | |||
1119 | serge | 917 | |
2997 | Serge | 918 | |
919 | { |
||
1119 | serge | 920 | return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS; |
2997 | Serge | 921 | } |
922 | |||
1119 | serge | 923 | |
2997 | Serge | 924 | { |
925 | return true; |
||
926 | } |
||
927 | |||
1119 | serge | 928 | |
2997 | Serge | 929 | { |
930 | int type = pci_pcie_type(dev); |
||
931 | |||
932 | |||
933 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
934 | type == PCI_EXP_TYPE_ENDPOINT || |
||
935 | type == PCI_EXP_TYPE_LEG_END; |
||
936 | } |
||
937 | |||
938 | |||
939 | { |
||
940 | int type = pci_pcie_type(dev); |
||
941 | |||
942 | |||
943 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
944 | (type == PCI_EXP_TYPE_DOWNSTREAM && |
||
945 | dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT); |
||
946 | } |
||
947 | |||
948 | |||
949 | { |
||
950 | int type = pci_pcie_type(dev); |
||
951 | |||
952 | |||
953 | type == PCI_EXP_TYPE_ROOT_PORT || |
||
954 | type == PCI_EXP_TYPE_RC_EC; |
||
955 | } |
||
956 | |||
957 | |||
958 | { |
||
959 | if (!pci_is_pcie(dev)) |
||
960 | return false; |
||
961 | |||
962 | |||
963 | case PCI_EXP_FLAGS_TYPE: |
||
964 | return true; |
||
965 | case PCI_EXP_DEVCAP: |
||
966 | case PCI_EXP_DEVCTL: |
||
967 | case PCI_EXP_DEVSTA: |
||
968 | return pcie_cap_has_devctl(dev); |
||
969 | case PCI_EXP_LNKCAP: |
||
970 | case PCI_EXP_LNKCTL: |
||
971 | case PCI_EXP_LNKSTA: |
||
972 | return pcie_cap_has_lnkctl(dev); |
||
973 | case PCI_EXP_SLTCAP: |
||
974 | case PCI_EXP_SLTCTL: |
||
975 | case PCI_EXP_SLTSTA: |
||
976 | return pcie_cap_has_sltctl(dev); |
||
977 | case PCI_EXP_RTCTL: |
||
978 | case PCI_EXP_RTCAP: |
||
979 | case PCI_EXP_RTSTA: |
||
980 | return pcie_cap_has_rtctl(dev); |
||
981 | case PCI_EXP_DEVCAP2: |
||
982 | case PCI_EXP_DEVCTL2: |
||
983 | case PCI_EXP_LNKCAP2: |
||
984 | case PCI_EXP_LNKCTL2: |
||
985 | case PCI_EXP_LNKSTA2: |
||
986 | return pcie_cap_version(dev) > 1; |
||
987 | default: |
||
988 | return false; |
||
989 | } |
||
990 | } |
||
991 | |||
992 | |||
993 | * Note that these accessor functions are only for the "PCI Express |
||
994 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the |
||
995 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) |
||
996 | */ |
||
997 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) |
||
998 | { |
||
999 | int ret; |
||
1000 | |||
1001 | |||
1002 | if (pos & 1) |
||
1003 | return -EINVAL; |
||
1004 | |||
1005 | |||
1006 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); |
||
1007 | /* |
||
1008 | * Reset *val to 0 if pci_read_config_word() fails, it may |
||
1009 | * have been written as 0xFFFF if hardware error happens |
||
1010 | * during pci_read_config_word(). |
||
1011 | */ |
||
1012 | if (ret) |
||
1013 | *val = 0; |
||
1014 | return ret; |
||
1015 | } |
||
1016 | |||
1017 | |||
1018 | * For Functions that do not implement the Slot Capabilities, |
||
1019 | * Slot Status, and Slot Control registers, these spaces must |
||
1020 | * be hardwired to 0b, with the exception of the Presence Detect |
||
1021 | * State bit in the Slot Status register of Downstream Ports, |
||
1022 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) |
||
1023 | */ |
||
1024 | if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA && |
||
1025 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
1026 | *val = PCI_EXP_SLTSTA_PDS; |
||
1027 | } |
||
1028 | |||
1029 | |||
1030 | } |
||
1031 | EXPORT_SYMBOL(pcie_capability_read_word); |
||
1032 | |||
1033 | |||
1034 | { |
||
1035 | int ret; |
||
1036 | |||
1037 | |||
1038 | if (pos & 3) |
||
1039 | return -EINVAL; |
||
1040 | |||
1041 | |||
1042 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); |
||
1043 | /* |
||
1044 | * Reset *val to 0 if pci_read_config_dword() fails, it may |
||
1045 | * have been written as 0xFFFFFFFF if hardware error happens |
||
1046 | * during pci_read_config_dword(). |
||
1047 | */ |
||
1048 | if (ret) |
||
1049 | *val = 0; |
||
1050 | return ret; |
||
1051 | } |
||
1052 | |||
1053 | |||
1054 | pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) { |
||
1055 | *val = PCI_EXP_SLTSTA_PDS; |
||
1056 | } |
||
1057 | |||
1058 | |||
1059 | } |
||
1060 | EXPORT_SYMBOL(pcie_capability_read_dword); |
||
1061 | |||
1062 | |||
1063 | { |
||
1064 | if (pos & 1) |
||
1065 | return -EINVAL; |
||
1066 | |||
1067 | |||
1068 | return 0; |
||
1119 | serge | 1069 | |
2997 | Serge | 1070 | |
1071 | } |
||
1119 | serge | 1072 | EXPORT_SYMBOL(pcie_capability_write_word); |
2997 | Serge | 1073 | |
1119 | serge | 1074 | |
2997 | Serge | 1075 | { |
1076 | if (pos & 3) |
||
1077 | return -EINVAL; |
||
1078 | |||
1963 | serge | 1079 | |
2997 | Serge | 1080 | return 0; |
1081 | |||
1082 | |||
1083 | } |
||
1084 | EXPORT_SYMBOL(pcie_capability_write_dword);>=>>>><>><>><>>4)><4)> |
||
1085 |