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Rev | Author | Line No. | Line |
---|---|---|---|
1117 | serge | 1 | |
1403 | serge | 2 | #include |
1630 | serge | 3 | #include |
1963 | serge | 4 | #include |
2160 | serge | 5 | #include |
1117 | serge | 6 | #include |
7 | |||
8 | |||
1120 | serge | 9 | |
1117 | serge | 10 | |
1403 | serge | 11 | |
1117 | serge | 12 | |
13 | |||
14 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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15 | |||
16 | |||
17 | |||
18 | |||
19 | * Translate the low bits of the PCI base |
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20 | * to the resource type |
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21 | */ |
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22 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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23 | { |
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24 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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25 | return IORESOURCE_IO; |
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26 | |||
27 | |||
28 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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29 | |||
30 | |||
31 | } |
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32 | |||
33 | |||
34 | |||
35 | { |
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36 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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37 | |||
38 | |||
39 | return 0; |
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40 | |||
41 | |||
42 | from that the extent. */ |
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43 | size = (size & ~(size-1)) - 1; |
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44 | |||
45 | |||
46 | already been programmed with all 1s. */ |
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47 | if (base == maxbase && ((base | size) & mask) != mask) |
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48 | return 0; |
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49 | |||
50 | |||
51 | } |
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52 | |||
53 | |||
54 | { |
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55 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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56 | |||
57 | |||
58 | return 0; |
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59 | |||
60 | |||
61 | from that the extent. */ |
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62 | size = (size & ~(size-1)) - 1; |
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63 | |||
64 | |||
65 | already been programmed with all 1s. */ |
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66 | if (base == maxbase && ((base | size) & mask) != mask) |
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67 | return 0; |
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68 | |||
69 | |||
70 | } |
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71 | |||
72 | |||
73 | { |
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74 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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75 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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76 | return 1; |
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77 | return 0; |
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78 | } |
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79 | |||
80 | |||
81 | { |
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82 | u32_t pos, reg, next; |
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83 | u32_t l, sz; |
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84 | struct resource *res; |
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85 | |||
86 | |||
87 | { |
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88 | u64_t l64; |
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89 | u64_t sz64; |
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90 | u32_t raw_sz; |
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91 | |||
92 | |||
93 | |||
94 | |||
95 | |||
96 | |||
97 | l = PciRead32(dev->busnr, dev->devfn, reg); |
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2160 | serge | 98 | PciWrite32(dev->busnr, dev->devfn, reg, ~0); |
99 | sz = PciRead32(dev->busnr, dev->devfn, reg); |
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100 | PciWrite32(dev->busnr, dev->devfn, reg, l); |
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101 | |||
1117 | serge | 102 | |
103 | continue; |
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104 | |||
105 | |||
106 | l = 0; |
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107 | |||
108 | |||
109 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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110 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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111 | { |
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112 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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113 | /* |
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114 | * For 64bit prefetchable memory sz could be 0, if the |
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115 | * real size is bigger than 4G, so we need to check |
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116 | * szhi for that. |
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117 | */ |
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118 | if (!is_64bit_memory(l) && !sz) |
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119 | continue; |
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120 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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121 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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122 | } |
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123 | else { |
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124 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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125 | if (!sz) |
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126 | continue; |
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127 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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128 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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129 | } |
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130 | res->end = res->start + (unsigned long) sz; |
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131 | res->flags |= pci_calc_resource_flags(l); |
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132 | if (is_64bit_memory(l)) |
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133 | { |
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134 | u32_t szhi, lhi; |
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135 | |||
136 | |||
2160 | serge | 137 | PciWrite32(dev->busnr, dev->devfn, reg+4, ~0); |
138 | szhi = PciRead32(dev->busnr, dev->devfn, reg+4); |
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139 | PciWrite32(dev->busnr, dev->devfn, reg+4, lhi); |
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140 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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1117 | serge | 141 | l64 = ((u64_t)lhi << 32) | l; |
142 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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143 | next++; |
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144 | |||
145 | |||
146 | if (!sz64) { |
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147 | res->start = 0; |
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148 | res->end = 0; |
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149 | res->flags = 0; |
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150 | continue; |
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151 | } |
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152 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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153 | res->end = res->start + sz64; |
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154 | #else |
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155 | if (sz64 > 0x100000000ULL) { |
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156 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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157 | "BAR for device %s\n", pci_name(dev)); |
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158 | res->start = 0; |
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159 | res->flags = 0; |
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160 | } |
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161 | else if (lhi) |
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162 | { |
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163 | /* 64-bit wide address, treat as disabled */ |
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164 | PciWrite32(dev->busnr, dev->devfn, reg, |
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2160 | serge | 165 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
1117 | serge | 166 | PciWrite32(dev->busnr, dev->devfn, reg+4, 0); |
2160 | serge | 167 | res->start = 0; |
1117 | serge | 168 | res->end = sz; |
169 | } |
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170 | #endif |
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171 | } |
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172 | } |
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173 | |||
174 | |||
175 | { |
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176 | dev->rom_base_reg = rom; |
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177 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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178 | |||
179 | |||
2160 | serge | 180 | PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
181 | sz = PciRead32(dev->busnr, dev->devfn, rom); |
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182 | PciWrite32(dev->busnr, dev->devfn, rom, l); |
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183 | |||
1117 | serge | 184 | |
185 | l = 0; |
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186 | |||
187 | |||
188 | { |
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189 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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190 | |||
191 | |||
192 | { |
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193 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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194 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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195 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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196 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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197 | res->end = res->start + (unsigned long) sz; |
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198 | } |
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199 | } |
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200 | } |
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201 | } |
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202 | |||
203 | |||
204 | { |
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205 | u8_t irq; |
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206 | |||
207 | |||
2160 | serge | 208 | dev->pin = irq; |
1117 | serge | 209 | if (irq) |
210 | irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE); |
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2160 | serge | 211 | dev->irq = irq; |
1117 | serge | 212 | }; |
213 | |||
214 | |||
215 | |||
2160 | serge | 216 | { |
1117 | serge | 217 | u32_t class; |
218 | |||
219 | |||
2160 | serge | 220 | dev->revision = class & 0xff; |
1117 | serge | 221 | class >>= 8; /* upper 3 bytes */ |
222 | dev->class = class; |
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223 | |||
224 | |||
225 | // dev->current_state = PCI_UNKNOWN; |
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226 | |||
227 | |||
228 | // pci_fixup_device(pci_fixup_early, dev); |
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229 | class = dev->class >> 8; |
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230 | |||
231 | |||
232 | { |
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233 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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234 | if (class == PCI_CLASS_BRIDGE_PCI) |
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235 | goto bad; |
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236 | pci_read_irq(dev); |
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237 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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238 | dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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2160 | serge | 239 | dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID); |
240 | |||
1117 | serge | 241 | |
242 | * Do the ugly legacy mode stuff here rather than broken chip |
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243 | * quirk code. Legacy mode ATA controllers have fixed |
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244 | * addresses. These are not always echoed in BAR0-3, and |
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245 | * BAR0-3 in a few cases contain junk! |
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246 | */ |
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247 | if (class == PCI_CLASS_STORAGE_IDE) |
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248 | { |
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249 | u8_t progif; |
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250 | |||
251 | |||
2160 | serge | 252 | if ((progif & 1) == 0) |
1117 | serge | 253 | { |
254 | dev->resource[0].start = 0x1F0; |
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255 | dev->resource[0].end = 0x1F7; |
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256 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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257 | dev->resource[1].start = 0x3F6; |
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258 | dev->resource[1].end = 0x3F6; |
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259 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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260 | } |
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261 | if ((progif & 4) == 0) |
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262 | { |
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263 | dev->resource[2].start = 0x170; |
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264 | dev->resource[2].end = 0x177; |
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265 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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266 | dev->resource[3].start = 0x376; |
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267 | dev->resource[3].end = 0x376; |
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268 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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269 | }; |
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270 | } |
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271 | break; |
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272 | |||
273 | |||
274 | if (class != PCI_CLASS_BRIDGE_PCI) |
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275 | goto bad; |
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276 | /* The PCI-to-PCI bridge spec requires that subtractive |
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277 | decoding (i.e. transparent) bridge must have programming |
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278 | interface code of 0x01. */ |
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279 | pci_read_irq(dev); |
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280 | dev->transparent = ((dev->class & 0xff) == 1); |
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281 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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282 | break; |
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283 | |||
284 | |||
285 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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286 | goto bad; |
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287 | pci_read_irq(dev); |
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288 | pci_read_bases(dev, 1, 0); |
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289 | dev->subsystem_vendor = PciRead16(dev->busnr, |
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2160 | serge | 290 | dev->devfn, |
1117 | serge | 291 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
292 | |||
293 | |||
2160 | serge | 294 | dev->devfn, |
1117 | serge | 295 | PCI_CB_SUBSYSTEM_ID); |
296 | break; |
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297 | |||
298 | |||
299 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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300 | pci_name(dev), dev->hdr_type); |
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301 | return -1; |
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302 | |||
303 | |||
304 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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305 | pci_name(dev), class, dev->hdr_type); |
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306 | dev->class = PCI_CLASS_NOT_DEFINED; |
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307 | } |
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308 | |||
309 | |||
310 | |||
311 | |||
312 | }; |
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313 | |||
314 | |||
2160 | serge | 315 | { |
1117 | serge | 316 | pci_dev_t *dev; |
1403 | serge | 317 | |
1117 | serge | 318 | |
319 | u8_t hdr; |
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320 | |||
321 | |||
322 | |||
323 | |||
2160 | serge | 324 | |
1117 | serge | 325 | |
326 | if (id == 0xffffffff || id == 0x00000000 || |
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327 | id == 0x0000ffff || id == 0xffff0000) |
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328 | return NULL; |
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329 | |||
330 | |||
331 | { |
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332 | |||
333 | |||
334 | timeout *= 2; |
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335 | |||
336 | |||
2160 | serge | 337 | |
1117 | serge | 338 | |
339 | if (timeout > 60 * 100) |
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340 | { |
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341 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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342 | "responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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2160 | serge | 343 | return NULL; |
1117 | serge | 344 | } |
345 | }; |
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346 | |||
347 | |||
2160 | serge | 348 | |
1117 | serge | 349 | |
1404 | serge | 350 | |
1117 | serge | 351 | |
1120 | serge | 352 | |
1117 | serge | 353 | |
354 | return NULL; |
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355 | |||
356 | |||
2160 | serge | 357 | dev->pci_dev.devfn = devfn; |
1117 | serge | 358 | dev->pci_dev.hdr_type = hdr & 0x7f; |
359 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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360 | dev->pci_dev.vendor = id & 0xffff; |
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361 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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362 | |||
363 | |||
364 | |||
365 | |||
366 | |||
367 | |||
368 | |||
369 | |||
370 | { |
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371 | int func, nr = 0; |
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372 | |||
373 | |||
374 | { |
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375 | pci_dev_t *dev; |
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1403 | serge | 376 | |
1117 | serge | 377 | |
378 | if( dev ) |
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379 | { |
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380 | list_add(&dev->link, &devices); |
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1120 | serge | 381 | |
1117 | serge | 382 | |
383 | |||
384 | |||
385 | * If this is a single function device, |
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386 | * don't scan past the first function. |
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387 | */ |
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388 | if (!dev->pci_dev.multifunction) |
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389 | { |
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390 | if (func > 0) { |
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391 | dev->pci_dev.multifunction = 1; |
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392 | } |
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393 | else { |
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394 | break; |
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395 | } |
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396 | } |
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397 | } |
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398 | else { |
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399 | if (func == 0) |
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400 | break; |
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401 | } |
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402 | }; |
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403 | |||
404 | |||
405 | }; |
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406 | |||
407 | |||
408 | |||
409 | { |
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410 | u32_t devfn; |
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411 | pci_dev_t *dev; |
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1404 | serge | 412 | |
1117 | serge | 413 | |
414 | |||
415 | pci_scan_slot(bus, devfn); |
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416 | |||
417 | |||
418 | |||
419 | |||
420 | { |
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421 | pci_dev_t *dev; |
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1403 | serge | 422 | u32_t last_bus; |
423 | u32_t bus = 0 , devfn = 0; |
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424 | |||
1117 | serge | 425 | |
1120 | serge | 426 | |
1117 | serge | 427 | |
428 | |||
429 | |||
430 | |||
431 | return -1; |
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432 | |||
433 | |||
434 | pci_scan_bus(bus); |
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435 | |||
436 | |||
437 | // &dev->link != &devices; |
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438 | // dev = (dev_t*)dev->link.next) |
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439 | // { |
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440 | // dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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441 | // dev->pci_dev.vendor, |
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442 | // dev->pci_dev.device, |
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443 | // dev->pci_dev.bus, |
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444 | // dev->pci_dev.devfn); |
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445 | // |
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446 | // } |
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447 | return 0; |
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448 | } |
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449 | |||
450 | |||
1239 | serge | 451 | |
452 | |||
453 | u8 pos, int cap, int *ttl) |
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454 | { |
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455 | u8 id; |
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456 | |||
457 | |||
458 | pos = PciRead8(bus, devfn, pos); |
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459 | if (pos < 0x40) |
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460 | break; |
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461 | pos &= ~3; |
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462 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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463 | if (id == 0xff) |
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464 | break; |
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465 | if (id == cap) |
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466 | return pos; |
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467 | pos += PCI_CAP_LIST_NEXT; |
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468 | } |
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469 | return 0; |
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470 | } |
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471 | |||
472 | |||
473 | u8 pos, int cap) |
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474 | { |
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475 | int ttl = PCI_FIND_CAP_TTL; |
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476 | |||
477 | |||
478 | } |
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479 | |||
480 | |||
481 | unsigned int devfn, u8 hdr_type) |
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482 | { |
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483 | u16 status; |
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484 | |||
485 | |||
486 | if (!(status & PCI_STATUS_CAP_LIST)) |
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487 | return 0; |
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488 | |||
489 | |||
490 | case PCI_HEADER_TYPE_NORMAL: |
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491 | case PCI_HEADER_TYPE_BRIDGE: |
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492 | return PCI_CAPABILITY_LIST; |
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493 | case PCI_HEADER_TYPE_CARDBUS: |
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494 | return PCI_CB_CAPABILITY_LIST; |
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495 | default: |
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496 | return 0; |
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497 | } |
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498 | |||
499 | |||
500 | } |
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501 | |||
502 | |||
503 | |||
504 | { |
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505 | int pos; |
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506 | |||
507 | |||
2160 | serge | 508 | if (pos) |
1239 | serge | 509 | pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap); |
2160 | serge | 510 | |
1239 | serge | 511 | |
512 | } |
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513 | |||
514 | |||
515 | |||
1963 | serge | 516 | /** |
517 | * pci_set_power_state - Set the power state of a PCI device |
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518 | * @dev: PCI device to be suspended |
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519 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering |
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520 | * |
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521 | * Transition a device to a new power state, using the Power Management |
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522 | * Capabilities in the device's config space. |
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523 | * |
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524 | * RETURN VALUE: |
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525 | * -EINVAL if trying to enter a lower state than we're already in. |
||
526 | * 0 if we're already in the requested state. |
||
527 | * -EIO if device does not support PCI PM. |
||
528 | * 0 if we can successfully change the power state. |
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529 | */ |
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530 | int |
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531 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
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532 | { |
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533 | int pm, need_restore = 0; |
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534 | u16 pmcsr, pmc; |
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535 | |||
1117 | serge | 536 | |
1963 | serge | 537 | if (state > PCI_D3hot) |
538 | state = PCI_D3hot; |
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539 | |||
540 | |||
541 | * If the device or the parent bridge can't support PCI PM, ignore |
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542 | * the request if we're doing anything besides putting it into D0 |
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543 | * (which would only happen on boot). |
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544 | */ |
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545 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
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546 | return 0; |
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547 | |||
548 | |||
549 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
||
550 | |||
551 | |||
552 | if (!pm) |
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553 | return -EIO; |
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554 | |||
555 | |||
556 | * Can enter D0 from any state, but if we can only go deeper |
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557 | * to sleep if we're already in a low power state |
||
558 | */ |
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559 | if (state != PCI_D0 && dev->current_state > state) { |
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560 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", |
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561 | __FUNCTION__, pci_name(dev), state, dev->current_state); |
||
562 | return -EINVAL; |
||
563 | } else if (dev->current_state == state) |
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564 | return 0; /* we're already there */ |
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565 | |||
566 | |||
567 | |||
568 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
||
569 | printk(KERN_DEBUG |
||
570 | "PCI: %s has unsupported PM cap regs version (%u)\n", |
||
571 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); |
||
572 | return -EIO; |
||
573 | } |
||
574 | |||
575 | |||
576 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
||
577 | return -EIO; |
||
578 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) |
||
579 | return -EIO; |
||
580 | |||
581 | |||
582 | |||
583 | |||
584 | * This doesn't affect PME_Status, disables PME_En, and |
||
585 | * sets PowerState to 0. |
||
586 | */ |
||
587 | switch (dev->current_state) { |
||
588 | case PCI_D0: |
||
589 | case PCI_D1: |
||
590 | case PCI_D2: |
||
591 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
||
592 | pmcsr |= state; |
||
593 | break; |
||
594 | case PCI_UNKNOWN: /* Boot-up */ |
||
595 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
||
596 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
||
597 | need_restore = 1; |
||
598 | /* Fall-through: force to D0 */ |
||
599 | default: |
||
600 | pmcsr = 0; |
||
601 | break; |
||
602 | } |
||
603 | |||
604 | |||
605 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); |
||
606 | |||
607 | |||
608 | /* see PCI PM 1.1 5.6.1 table 18 */ |
||
609 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
||
610 | msleep(pci_pm_d3_delay); |
||
611 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
||
612 | udelay(200); |
||
613 | |||
614 | |||
615 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx |
||
616 | * Firmware method after native method ? |
||
617 | */ |
||
618 | if (platform_pci_set_power_state) |
||
619 | platform_pci_set_power_state(dev, state); |
||
620 | |||
621 | |||
622 | |||
623 | |||
624 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
||
625 | * from D3hot to D0 _may_ perform an internal reset, thereby |
||
626 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
||
627 | * For example, at least some versions of the 3c905B and the |
||
628 | * 3c556B exhibit this behaviour. |
||
629 | * |
||
630 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
||
631 | * devices in a D3hot state at boot. Consequently, we need to |
||
632 | * restore at least the BARs so that the device will be |
||
633 | * accessible to its driver. |
||
634 | */ |
||
635 | if (need_restore) |
||
636 | pci_restore_bars(dev); |
||
637 | |||
638 | |||
639 | } |
||
640 | #endif |
||
641 | |||
642 | |||
1117 | serge | 643 | { |
644 | u16_t cmd, old_cmd; |
||
645 | int idx; |
||
646 | struct resource *r; |
||
647 | |||
648 | |||
2160 | serge | 649 | old_cmd = cmd; |
1117 | serge | 650 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
651 | { |
||
652 | /* Only set up the requested stuff */ |
||
653 | if (!(mask & (1 << idx))) |
||
654 | continue; |
||
655 | |||
656 | |||
657 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
||
658 | continue; |
||
659 | if ((idx == PCI_ROM_RESOURCE) && |
||
660 | (!(r->flags & IORESOURCE_ROM_ENABLE))) |
||
661 | continue; |
||
662 | if (!r->start && r->end) { |
||
663 | printk(KERN_ERR "PCI: Device %s not available " |
||
664 | "because of resource %d collisions\n", |
||
665 | pci_name(dev), idx); |
||
666 | return -EINVAL; |
||
667 | } |
||
668 | if (r->flags & IORESOURCE_IO) |
||
669 | cmd |= PCI_COMMAND_IO; |
||
670 | if (r->flags & IORESOURCE_MEM) |
||
671 | cmd |= PCI_COMMAND_MEMORY; |
||
672 | } |
||
673 | if (cmd != old_cmd) { |
||
674 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
||
675 | pci_name(dev), old_cmd, cmd); |
||
676 | PciWrite16(dev->busnr, dev->devfn, PCI_COMMAND, cmd); |
||
2160 | serge | 677 | } |
1117 | serge | 678 | return 0; |
679 | } |
||
680 | |||
681 | |||
682 | |||
683 | { |
||
684 | int err; |
||
685 | |||
686 | |||
687 | return err; |
||
688 | |||
689 | |||
690 | // return pcibios_enable_irq(dev); |
||
691 | return 0; |
||
692 | } |
||
693 | |||
694 | |||
695 | |||
696 | { |
||
697 | int err; |
||
698 | |||
699 | |||
700 | // if (err < 0 && err != -EIO) |
||
701 | // return err; |
||
702 | err = pcibios_enable_device(dev, bars); |
||
703 | // if (err < 0) |
||
704 | // return err; |
||
705 | // pci_fixup_device(pci_fixup_enable, dev); |
||
706 | |||
707 | |||
708 | } |
||
709 | |||
710 | |||
711 | |||
712 | resource_size_t flags) |
||
713 | { |
||
714 | int err; |
||
715 | int i, bars = 0; |
||
716 | |||
717 | |||
718 | // return 0; /* already enabled */ |
||
719 | |||
720 | |||
721 | if (dev->resource[i].flags & flags) |
||
722 | bars |= (1 << i); |
||
723 | |||
724 | |||
725 | // if (err < 0) |
||
726 | // atomic_dec(&dev->enable_cnt); |
||
727 | return err; |
||
728 | } |
||
729 | |||
730 | |||
731 | |||
732 | * pci_enable_device - Initialize device before it's used by a driver. |
||
733 | * @dev: PCI device to be initialized |
||
734 | * |
||
735 | * Initialize device before it's used by a driver. Ask low-level code |
||
736 | * to enable I/O and memory. Wake up the device if it was suspended. |
||
737 | * Beware, this function can fail. |
||
738 | * |
||
739 | * Note we don't actually enable the device many times if we call |
||
740 | * this function repeatedly (we just increment the count). |
||
741 | */ |
||
742 | int pci_enable_device(struct pci_dev *dev) |
||
743 | { |
||
744 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
||
745 | } |
||
746 | |||
747 | |||
748 | |||
749 | |||
1403 | serge | 750 | { |
1117 | serge | 751 | pci_dev_t *dev; |
1403 | serge | 752 | struct pci_device_id *ent; |
1117 | serge | 753 | |
754 | |||
1403 | serge | 755 | &dev->link != &devices; |
1117 | serge | 756 | dev = (pci_dev_t*)dev->link.next) |
1403 | serge | 757 | { |
1117 | serge | 758 | if( dev->pci_dev.vendor != idlist->vendor ) |
759 | continue; |
||
760 | |||
761 | |||
762 | { |
||
763 | if(unlikely(ent->device == dev->pci_dev.device)) |
||
764 | { |
||
765 | pdev->pci_dev = dev->pci_dev; |
||
766 | return ent; |
||
767 | } |
||
768 | }; |
||
769 | } |
||
770 | |||
1963 | serge | 771 | |
1117 | serge | 772 | }; |
773 | |||
774 | |||
775 | |||
776 | |||
777 | * pci_map_rom - map a PCI ROM to kernel space |
||
778 | * @pdev: pointer to pci device struct |
||
779 | * @size: pointer to receive size of pci window over ROM |
||
780 | * @return: kernel virtual pointer to image of ROM |
||
781 | * |
||
782 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
783 | * the shadow BIOS copy will be returned instead of the |
||
784 | * actual ROM. |
||
785 | */ |
||
786 | |||
787 | |||
788 | #define OS_BASE 0x80000000 |
||
789 | |||
790 | |||
791 | { |
||
792 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
793 | u32_t start; |
||
794 | void *rom; |
||
795 | |||
796 | |||
797 | /* |
||
1963 | serge | 798 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
799 | * memory map if the VGA enable bit of the Bridge Control register is |
||
800 | * set for embedded VGA. |
||
801 | */ |
||
802 | if (res->flags & IORESOURCE_ROM_SHADOW) { |
||
803 | /* primary video rom always starts here */ |
||
804 | start = (u32_t)0xC0000; |
||
805 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
806 | } else { |
||
807 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
||
808 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
809 | return (void *)(unsigned long) |
||
810 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
811 | } else { |
||
812 | /* assign the ROM an address if it doesn't have one */ |
||
813 | //if (res->parent == NULL && |
||
814 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
||
815 | // return NULL; |
||
816 | start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
817 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
818 | if (*size == 0) |
||
819 | return NULL; |
||
820 | |||
821 | |||
822 | if (pci_enable_rom(pdev)) |
||
823 | return NULL; |
||
824 | } |
||
825 | } |
||
826 | |||
827 | |||
828 | if (!rom) { |
||
829 | /* restore enable if ioremap fails */ |
||
830 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
831 | IORESOURCE_ROM_SHADOW | |
||
832 | IORESOURCE_ROM_COPY))) |
||
833 | pci_disable_rom(pdev); |
||
834 | return NULL; |
||
835 | } |
||
836 | |||
837 | |||
838 | * Try to find the true size of the ROM since sometimes the PCI window |
||
839 | * size is much larger than the actual size of the ROM. |
||
840 | * True size is important if the ROM is going to be copied. |
||
841 | */ |
||
842 | *size = pci_get_rom_size(rom, *size); |
||
843 | |||
844 | |||
1117 | serge | 845 | |
846 | |||
847 | rom = NULL; |
||
848 | |||
849 | |||
850 | memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32); |
||
851 | *size = tmp[2] * 512; |
||
852 | if (*size > 0x10000 ) |
||
853 | { |
||
854 | *size = 0; |
||
855 | dbgprintf("Invalid BIOS length field\n"); |
||
856 | } |
||
857 | else |
||
858 | rom = (void*)( OS_BASE+legacyBIOSLocation); |
||
859 | |||
860 | |||
861 | } |
||
862 | |||
863 | |||
1119 | serge | 864 | |
865 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
||
866 | { |
||
867 | // if (!pci_dma_supported(dev, mask)) |
||
868 | // return -EIO; |
||
869 | |||
870 | |||
871 | |||
872 | |||
873 | }>><>>>>>><>>>=>>>><>><>><>>4)><4)> |
||
874 |