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Rev | Author | Line No. | Line |
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1117 | serge | 1 | |
1403 | serge | 2 | #include |
1117 | serge | 3 | #include |
4 | #include |
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5 | |||
6 | |||
1120 | serge | 7 | |
1117 | serge | 8 | |
1403 | serge | 9 | |
1117 | serge | 10 | |
11 | |||
12 | #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
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13 | |||
14 | |||
15 | |||
16 | |||
17 | * Translate the low bits of the PCI base |
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18 | * to the resource type |
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19 | */ |
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20 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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21 | { |
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22 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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23 | return IORESOURCE_IO; |
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24 | |||
25 | |||
26 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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27 | |||
28 | |||
29 | } |
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30 | |||
31 | |||
32 | |||
33 | { |
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34 | u32_t size = mask & maxbase; /* Find the significant bits */ |
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35 | |||
36 | |||
37 | return 0; |
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38 | |||
39 | |||
40 | from that the extent. */ |
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41 | size = (size & ~(size-1)) - 1; |
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42 | |||
43 | |||
44 | already been programmed with all 1s. */ |
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45 | if (base == maxbase && ((base | size) & mask) != mask) |
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46 | return 0; |
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47 | |||
48 | |||
49 | } |
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50 | |||
51 | |||
52 | { |
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53 | u64_t size = mask & maxbase; /* Find the significant bits */ |
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54 | |||
55 | |||
56 | return 0; |
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57 | |||
58 | |||
59 | from that the extent. */ |
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60 | size = (size & ~(size-1)) - 1; |
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61 | |||
62 | |||
63 | already been programmed with all 1s. */ |
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64 | if (base == maxbase && ((base | size) & mask) != mask) |
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65 | return 0; |
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66 | |||
67 | |||
68 | } |
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69 | |||
70 | |||
71 | { |
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72 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
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73 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
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74 | return 1; |
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75 | return 0; |
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76 | } |
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77 | |||
78 | |||
79 | { |
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80 | u32_t pos, reg, next; |
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81 | u32_t l, sz; |
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82 | struct resource *res; |
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83 | |||
84 | |||
85 | { |
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86 | u64_t l64; |
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87 | u64_t sz64; |
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88 | u32_t raw_sz; |
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89 | |||
90 | |||
91 | |||
92 | |||
93 | |||
94 | |||
95 | l = PciRead32(dev->bus, dev->devfn, reg); |
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96 | PciWrite32(dev->bus, dev->devfn, reg, ~0); |
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97 | sz = PciRead32(dev->bus, dev->devfn, reg); |
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98 | PciWrite32(dev->bus, dev->devfn, reg, l); |
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99 | |||
100 | |||
101 | continue; |
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102 | |||
103 | |||
104 | l = 0; |
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105 | |||
106 | |||
107 | if ((l & PCI_BASE_ADDRESS_SPACE) == |
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108 | PCI_BASE_ADDRESS_SPACE_MEMORY) |
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109 | { |
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110 | sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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111 | /* |
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112 | * For 64bit prefetchable memory sz could be 0, if the |
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113 | * real size is bigger than 4G, so we need to check |
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114 | * szhi for that. |
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115 | */ |
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116 | if (!is_64bit_memory(l) && !sz) |
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117 | continue; |
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118 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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119 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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120 | } |
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121 | else { |
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122 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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123 | if (!sz) |
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124 | continue; |
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125 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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126 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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127 | } |
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128 | res->end = res->start + (unsigned long) sz; |
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129 | res->flags |= pci_calc_resource_flags(l); |
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130 | if (is_64bit_memory(l)) |
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131 | { |
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132 | u32_t szhi, lhi; |
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133 | |||
134 | |||
135 | PciWrite32(dev->bus, dev->devfn, reg+4, ~0); |
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136 | szhi = PciRead32(dev->bus, dev->devfn, reg+4); |
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137 | PciWrite32(dev->bus, dev->devfn, reg+4, lhi); |
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138 | sz64 = ((u64_t)szhi << 32) | raw_sz; |
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139 | l64 = ((u64_t)lhi << 32) | l; |
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140 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
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141 | next++; |
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142 | |||
143 | |||
144 | if (!sz64) { |
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145 | res->start = 0; |
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146 | res->end = 0; |
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147 | res->flags = 0; |
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148 | continue; |
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149 | } |
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150 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
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151 | res->end = res->start + sz64; |
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152 | #else |
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153 | if (sz64 > 0x100000000ULL) { |
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154 | printk(KERN_ERR "PCI: Unable to handle 64-bit " |
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155 | "BAR for device %s\n", pci_name(dev)); |
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156 | res->start = 0; |
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157 | res->flags = 0; |
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158 | } |
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159 | else if (lhi) |
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160 | { |
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161 | /* 64-bit wide address, treat as disabled */ |
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162 | PciWrite32(dev->bus, dev->devfn, reg, |
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163 | l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
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164 | PciWrite32(dev->bus, dev->devfn, reg+4, 0); |
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165 | res->start = 0; |
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166 | res->end = sz; |
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167 | } |
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168 | #endif |
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169 | } |
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170 | } |
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171 | |||
172 | |||
173 | { |
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174 | dev->rom_base_reg = rom; |
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175 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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176 | |||
177 | |||
178 | PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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179 | sz = PciRead32(dev->bus, dev->devfn, rom); |
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180 | PciWrite32(dev->bus, dev->devfn, rom, l); |
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181 | |||
182 | |||
183 | l = 0; |
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184 | |||
185 | |||
186 | { |
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187 | sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
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188 | |||
189 | |||
190 | { |
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191 | res->flags = (l & IORESOURCE_ROM_ENABLE) | |
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192 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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193 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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194 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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195 | res->end = res->start + (unsigned long) sz; |
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196 | } |
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197 | } |
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198 | } |
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199 | } |
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200 | |||
201 | |||
202 | { |
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203 | u8_t irq; |
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204 | |||
205 | |||
206 | dev->pin = irq; |
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207 | if (irq) |
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208 | PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE); |
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209 | dev->irq = irq; |
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210 | }; |
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211 | |||
212 | |||
213 | |||
214 | { |
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215 | u32_t class; |
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216 | |||
217 | |||
218 | dev->revision = class & 0xff; |
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219 | class >>= 8; /* upper 3 bytes */ |
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220 | dev->class = class; |
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221 | |||
222 | |||
223 | // dev->current_state = PCI_UNKNOWN; |
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224 | |||
225 | |||
226 | // pci_fixup_device(pci_fixup_early, dev); |
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227 | class = dev->class >> 8; |
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228 | |||
229 | |||
230 | { |
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231 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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232 | if (class == PCI_CLASS_BRIDGE_PCI) |
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233 | goto bad; |
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234 | pci_read_irq(dev); |
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235 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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236 | dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
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237 | dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID); |
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238 | |||
239 | |||
240 | * Do the ugly legacy mode stuff here rather than broken chip |
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241 | * quirk code. Legacy mode ATA controllers have fixed |
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242 | * addresses. These are not always echoed in BAR0-3, and |
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243 | * BAR0-3 in a few cases contain junk! |
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244 | */ |
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245 | if (class == PCI_CLASS_STORAGE_IDE) |
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246 | { |
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247 | u8_t progif; |
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248 | |||
249 | |||
250 | if ((progif & 1) == 0) |
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251 | { |
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252 | dev->resource[0].start = 0x1F0; |
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253 | dev->resource[0].end = 0x1F7; |
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254 | dev->resource[0].flags = LEGACY_IO_RESOURCE; |
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255 | dev->resource[1].start = 0x3F6; |
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256 | dev->resource[1].end = 0x3F6; |
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257 | dev->resource[1].flags = LEGACY_IO_RESOURCE; |
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258 | } |
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259 | if ((progif & 4) == 0) |
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260 | { |
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261 | dev->resource[2].start = 0x170; |
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262 | dev->resource[2].end = 0x177; |
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263 | dev->resource[2].flags = LEGACY_IO_RESOURCE; |
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264 | dev->resource[3].start = 0x376; |
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265 | dev->resource[3].end = 0x376; |
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266 | dev->resource[3].flags = LEGACY_IO_RESOURCE; |
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267 | }; |
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268 | } |
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269 | break; |
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270 | |||
271 | |||
272 | if (class != PCI_CLASS_BRIDGE_PCI) |
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273 | goto bad; |
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274 | /* The PCI-to-PCI bridge spec requires that subtractive |
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275 | decoding (i.e. transparent) bridge must have programming |
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276 | interface code of 0x01. */ |
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277 | pci_read_irq(dev); |
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278 | dev->transparent = ((dev->class & 0xff) == 1); |
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279 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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280 | break; |
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281 | |||
282 | |||
283 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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284 | goto bad; |
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285 | pci_read_irq(dev); |
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286 | pci_read_bases(dev, 1, 0); |
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287 | dev->subsystem_vendor = PciRead16(dev->bus, |
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288 | dev->devfn, |
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289 | PCI_CB_SUBSYSTEM_VENDOR_ID); |
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290 | |||
291 | |||
292 | dev->devfn, |
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293 | PCI_CB_SUBSYSTEM_ID); |
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294 | break; |
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295 | |||
296 | |||
297 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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298 | pci_name(dev), dev->hdr_type); |
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299 | return -1; |
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300 | |||
301 | |||
302 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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303 | pci_name(dev), class, dev->hdr_type); |
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304 | dev->class = PCI_CLASS_NOT_DEFINED; |
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305 | } |
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306 | |||
307 | |||
308 | |||
309 | |||
310 | }; |
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311 | |||
312 | |||
1403 | serge | 313 | { |
1117 | serge | 314 | pci_dev_t *dev; |
1403 | serge | 315 | |
1117 | serge | 316 | |
317 | u8_t hdr; |
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318 | |||
319 | |||
320 | |||
321 | |||
322 | |||
323 | |||
324 | if (id == 0xffffffff || id == 0x00000000 || |
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325 | id == 0x0000ffff || id == 0xffff0000) |
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326 | return NULL; |
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327 | |||
328 | |||
329 | { |
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330 | |||
331 | |||
332 | timeout *= 2; |
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333 | |||
334 | |||
335 | |||
336 | |||
337 | if (timeout > 60 * 100) |
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338 | { |
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339 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
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340 | "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
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341 | return NULL; |
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342 | } |
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343 | }; |
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344 | |||
345 | |||
346 | |||
347 | |||
1403 | serge | 348 | |
1117 | serge | 349 | |
1120 | serge | 350 | |
1117 | serge | 351 | |
352 | return NULL; |
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353 | |||
354 | |||
355 | dev->pci_dev.devfn = devfn; |
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356 | dev->pci_dev.hdr_type = hdr & 0x7f; |
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357 | dev->pci_dev.multifunction = !!(hdr & 0x80); |
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358 | dev->pci_dev.vendor = id & 0xffff; |
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359 | dev->pci_dev.device = (id >> 16) & 0xffff; |
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360 | |||
361 | |||
362 | |||
363 | |||
364 | |||
365 | |||
366 | |||
367 | |||
368 | { |
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369 | int func, nr = 0; |
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370 | |||
371 | |||
372 | { |
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373 | pci_dev_t *dev; |
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1403 | serge | 374 | |
1117 | serge | 375 | |
376 | if( dev ) |
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377 | { |
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378 | list_add(&dev->link, &devices); |
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1120 | serge | 379 | |
1117 | serge | 380 | |
381 | |||
382 | |||
383 | * If this is a single function device, |
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384 | * don't scan past the first function. |
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385 | */ |
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386 | if (!dev->pci_dev.multifunction) |
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387 | { |
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388 | if (func > 0) { |
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389 | dev->pci_dev.multifunction = 1; |
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390 | } |
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391 | else { |
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392 | break; |
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393 | } |
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394 | } |
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395 | } |
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396 | else { |
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397 | if (func == 0) |
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398 | break; |
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399 | } |
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400 | }; |
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401 | |||
402 | |||
403 | }; |
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404 | |||
405 | |||
406 | |||
407 | { |
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408 | u32_t devfn; |
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409 | dev_t *dev; |
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410 | |||
411 | |||
412 | |||
413 | pci_scan_slot(bus, devfn); |
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414 | |||
415 | |||
416 | |||
417 | |||
418 | { |
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419 | pci_dev_t *dev; |
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1403 | serge | 420 | u32_t last_bus; |
421 | u32_t bus = 0 , devfn = 0; |
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422 | |||
1117 | serge | 423 | |
1120 | serge | 424 | |
1117 | serge | 425 | |
426 | |||
427 | |||
428 | |||
429 | return -1; |
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430 | |||
431 | |||
432 | pci_scan_bus(bus); |
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433 | |||
434 | |||
435 | // &dev->link != &devices; |
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436 | // dev = (dev_t*)dev->link.next) |
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437 | // { |
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438 | // dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
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439 | // dev->pci_dev.vendor, |
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440 | // dev->pci_dev.device, |
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441 | // dev->pci_dev.bus, |
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442 | // dev->pci_dev.devfn); |
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443 | // |
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444 | // } |
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445 | return 0; |
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446 | } |
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447 | |||
448 | |||
1239 | serge | 449 | |
450 | |||
451 | u8 pos, int cap, int *ttl) |
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452 | { |
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453 | u8 id; |
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454 | |||
455 | |||
456 | pos = PciRead8(bus, devfn, pos); |
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457 | if (pos < 0x40) |
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458 | break; |
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459 | pos &= ~3; |
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460 | id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID); |
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461 | if (id == 0xff) |
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462 | break; |
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463 | if (id == cap) |
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464 | return pos; |
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465 | pos += PCI_CAP_LIST_NEXT; |
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466 | } |
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467 | return 0; |
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468 | } |
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469 | |||
470 | |||
471 | u8 pos, int cap) |
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472 | { |
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473 | int ttl = PCI_FIND_CAP_TTL; |
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474 | |||
475 | |||
476 | } |
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477 | |||
478 | |||
479 | unsigned int devfn, u8 hdr_type) |
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480 | { |
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481 | u16 status; |
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482 | |||
483 | |||
484 | if (!(status & PCI_STATUS_CAP_LIST)) |
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485 | return 0; |
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486 | |||
487 | |||
488 | case PCI_HEADER_TYPE_NORMAL: |
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489 | case PCI_HEADER_TYPE_BRIDGE: |
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490 | return PCI_CAPABILITY_LIST; |
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491 | case PCI_HEADER_TYPE_CARDBUS: |
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492 | return PCI_CB_CAPABILITY_LIST; |
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493 | default: |
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494 | return 0; |
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495 | } |
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496 | |||
497 | |||
498 | } |
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499 | |||
500 | |||
501 | |||
502 | { |
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503 | int pos; |
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504 | |||
505 | |||
506 | if (pos) |
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507 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); |
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508 | |||
509 | |||
510 | } |
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511 | |||
512 | |||
513 | |||
1117 | serge | 514 | /** |
515 | * pci_set_power_state - Set the power state of a PCI device |
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516 | * @dev: PCI device to be suspended |
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517 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering |
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518 | * |
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519 | * Transition a device to a new power state, using the Power Management |
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520 | * Capabilities in the device's config space. |
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521 | * |
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522 | * RETURN VALUE: |
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523 | * -EINVAL if trying to enter a lower state than we're already in. |
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524 | * 0 if we're already in the requested state. |
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525 | * -EIO if device does not support PCI PM. |
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526 | * 0 if we can successfully change the power state. |
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527 | */ |
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528 | int |
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529 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
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530 | { |
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531 | int pm, need_restore = 0; |
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532 | u16 pmcsr, pmc; |
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533 | |||
534 | |||
535 | if (state > PCI_D3hot) |
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536 | state = PCI_D3hot; |
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537 | |||
538 | |||
539 | * If the device or the parent bridge can't support PCI PM, ignore |
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540 | * the request if we're doing anything besides putting it into D0 |
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541 | * (which would only happen on boot). |
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542 | */ |
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543 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
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544 | return 0; |
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545 | |||
546 | |||
547 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
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548 | |||
549 | |||
550 | if (!pm) |
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551 | return -EIO; |
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552 | |||
553 | |||
554 | * Can enter D0 from any state, but if we can only go deeper |
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555 | * to sleep if we're already in a low power state |
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556 | */ |
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557 | if (state != PCI_D0 && dev->current_state > state) { |
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558 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", |
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559 | __FUNCTION__, pci_name(dev), state, dev->current_state); |
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560 | return -EINVAL; |
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561 | } else if (dev->current_state == state) |
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562 | return 0; /* we're already there */ |
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563 | |||
564 | |||
565 | |||
566 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
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567 | printk(KERN_DEBUG |
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568 | "PCI: %s has unsupported PM cap regs version (%u)\n", |
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569 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); |
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570 | return -EIO; |
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571 | } |
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572 | |||
573 | |||
574 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
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575 | return -EIO; |
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576 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) |
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577 | return -EIO; |
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578 | |||
579 | |||
580 | |||
581 | |||
582 | * This doesn't affect PME_Status, disables PME_En, and |
||
583 | * sets PowerState to 0. |
||
584 | */ |
||
585 | switch (dev->current_state) { |
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586 | case PCI_D0: |
||
587 | case PCI_D1: |
||
588 | case PCI_D2: |
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589 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
||
590 | pmcsr |= state; |
||
591 | break; |
||
592 | case PCI_UNKNOWN: /* Boot-up */ |
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593 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
||
594 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
||
595 | need_restore = 1; |
||
596 | /* Fall-through: force to D0 */ |
||
597 | default: |
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598 | pmcsr = 0; |
||
599 | break; |
||
600 | } |
||
601 | |||
602 | |||
603 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); |
||
604 | |||
605 | |||
606 | /* see PCI PM 1.1 5.6.1 table 18 */ |
||
607 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
||
608 | msleep(pci_pm_d3_delay); |
||
609 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
||
610 | udelay(200); |
||
611 | |||
612 | |||
613 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx |
||
614 | * Firmware method after native method ? |
||
615 | */ |
||
616 | if (platform_pci_set_power_state) |
||
617 | platform_pci_set_power_state(dev, state); |
||
618 | |||
619 | |||
620 | |||
621 | |||
622 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
||
623 | * from D3hot to D0 _may_ perform an internal reset, thereby |
||
624 | * going to "D0 Uninitialized" rather than "D0 Initialized". |
||
625 | * For example, at least some versions of the 3c905B and the |
||
626 | * 3c556B exhibit this behaviour. |
||
627 | * |
||
628 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
||
629 | * devices in a D3hot state at boot. Consequently, we need to |
||
630 | * restore at least the BARs so that the device will be |
||
631 | * accessible to its driver. |
||
632 | */ |
||
633 | if (need_restore) |
||
634 | pci_restore_bars(dev); |
||
635 | |||
636 | |||
637 | } |
||
638 | #endif |
||
639 | |||
640 | |||
641 | { |
||
642 | u16_t cmd, old_cmd; |
||
643 | int idx; |
||
644 | struct resource *r; |
||
645 | |||
646 | |||
647 | old_cmd = cmd; |
||
648 | for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
||
649 | { |
||
650 | /* Only set up the requested stuff */ |
||
651 | if (!(mask & (1 << idx))) |
||
652 | continue; |
||
653 | |||
654 | |||
655 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
||
656 | continue; |
||
657 | if ((idx == PCI_ROM_RESOURCE) && |
||
658 | (!(r->flags & IORESOURCE_ROM_ENABLE))) |
||
659 | continue; |
||
660 | if (!r->start && r->end) { |
||
661 | printk(KERN_ERR "PCI: Device %s not available " |
||
662 | "because of resource %d collisions\n", |
||
663 | pci_name(dev), idx); |
||
664 | return -EINVAL; |
||
665 | } |
||
666 | if (r->flags & IORESOURCE_IO) |
||
667 | cmd |= PCI_COMMAND_IO; |
||
668 | if (r->flags & IORESOURCE_MEM) |
||
669 | cmd |= PCI_COMMAND_MEMORY; |
||
670 | } |
||
671 | if (cmd != old_cmd) { |
||
672 | printk("PCI: Enabling device %s (%04x -> %04x)\n", |
||
673 | pci_name(dev), old_cmd, cmd); |
||
674 | PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd); |
||
675 | } |
||
676 | return 0; |
||
677 | } |
||
678 | |||
679 | |||
680 | |||
681 | { |
||
682 | int err; |
||
683 | |||
684 | |||
685 | return err; |
||
686 | |||
687 | |||
688 | // return pcibios_enable_irq(dev); |
||
689 | return 0; |
||
690 | } |
||
691 | |||
692 | |||
693 | |||
694 | { |
||
695 | int err; |
||
696 | |||
697 | |||
698 | // if (err < 0 && err != -EIO) |
||
699 | // return err; |
||
700 | err = pcibios_enable_device(dev, bars); |
||
701 | // if (err < 0) |
||
702 | // return err; |
||
703 | // pci_fixup_device(pci_fixup_enable, dev); |
||
704 | |||
705 | |||
706 | } |
||
707 | |||
708 | |||
709 | |||
710 | resource_size_t flags) |
||
711 | { |
||
712 | int err; |
||
713 | int i, bars = 0; |
||
714 | |||
715 | |||
716 | // return 0; /* already enabled */ |
||
717 | |||
718 | |||
719 | if (dev->resource[i].flags & flags) |
||
720 | bars |= (1 << i); |
||
721 | |||
722 | |||
723 | // if (err < 0) |
||
724 | // atomic_dec(&dev->enable_cnt); |
||
725 | return err; |
||
726 | } |
||
727 | |||
728 | |||
729 | |||
730 | * pci_enable_device - Initialize device before it's used by a driver. |
||
731 | * @dev: PCI device to be initialized |
||
732 | * |
||
733 | * Initialize device before it's used by a driver. Ask low-level code |
||
734 | * to enable I/O and memory. Wake up the device if it was suspended. |
||
735 | * Beware, this function can fail. |
||
736 | * |
||
737 | * Note we don't actually enable the device many times if we call |
||
738 | * this function repeatedly (we just increment the count). |
||
739 | */ |
||
740 | int pci_enable_device(struct pci_dev *dev) |
||
741 | { |
||
742 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
||
743 | } |
||
744 | |||
745 | |||
746 | |||
747 | |||
1403 | serge | 748 | { |
1117 | serge | 749 | pci_dev_t *dev; |
1403 | serge | 750 | struct pci_device_id *ent; |
1117 | serge | 751 | |
752 | |||
1403 | serge | 753 | &dev->link != &devices; |
1117 | serge | 754 | dev = (pci_dev_t*)dev->link.next) |
1403 | serge | 755 | { |
1117 | serge | 756 | if( dev->pci_dev.vendor != idlist->vendor ) |
757 | continue; |
||
758 | |||
759 | |||
760 | { |
||
761 | if(unlikely(ent->device == dev->pci_dev.device)) |
||
762 | { |
||
763 | pdev->pci_dev = dev->pci_dev; |
||
764 | return ent; |
||
765 | } |
||
766 | }; |
||
767 | } |
||
768 | |||
769 | |||
770 | }; |
||
771 | |||
772 | |||
773 | |||
774 | |||
775 | * pci_map_rom - map a PCI ROM to kernel space |
||
776 | * @pdev: pointer to pci device struct |
||
777 | * @size: pointer to receive size of pci window over ROM |
||
778 | * @return: kernel virtual pointer to image of ROM |
||
779 | * |
||
780 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
||
781 | * the shadow BIOS copy will be returned instead of the |
||
782 | * actual ROM. |
||
783 | */ |
||
784 | |||
785 | |||
786 | #define OS_BASE 0x80000000 |
||
787 | |||
788 | |||
789 | { |
||
790 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
||
791 | u32_t start; |
||
792 | void *rom; |
||
793 | |||
794 | |||
795 | /* |
||
796 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
||
797 | * memory map if the VGA enable bit of the Bridge Control register is |
||
798 | * set for embedded VGA. |
||
799 | */ |
||
800 | if (res->flags & IORESOURCE_ROM_SHADOW) { |
||
801 | /* primary video rom always starts here */ |
||
802 | start = (u32_t)0xC0000; |
||
803 | *size = 0x20000; /* cover C000:0 through E000:0 */ |
||
804 | } else { |
||
805 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
||
806 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
807 | return (void *)(unsigned long) |
||
808 | pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
809 | } else { |
||
810 | /* assign the ROM an address if it doesn't have one */ |
||
811 | //if (res->parent == NULL && |
||
812 | // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
||
813 | // return NULL; |
||
814 | start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
||
815 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
||
816 | if (*size == 0) |
||
817 | return NULL; |
||
818 | |||
819 | |||
820 | if (pci_enable_rom(pdev)) |
||
821 | return NULL; |
||
822 | } |
||
823 | } |
||
824 | |||
825 | |||
826 | if (!rom) { |
||
827 | /* restore enable if ioremap fails */ |
||
828 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
||
829 | IORESOURCE_ROM_SHADOW | |
||
830 | IORESOURCE_ROM_COPY))) |
||
831 | pci_disable_rom(pdev); |
||
832 | return NULL; |
||
833 | } |
||
834 | |||
835 | |||
836 | * Try to find the true size of the ROM since sometimes the PCI window |
||
837 | * size is much larger than the actual size of the ROM. |
||
838 | * True size is important if the ROM is going to be copied. |
||
839 | */ |
||
840 | *size = pci_get_rom_size(rom, *size); |
||
841 | |||
842 | |||
843 | |||
844 | |||
845 | rom = NULL; |
||
846 | |||
847 | |||
848 | memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32); |
||
849 | *size = tmp[2] * 512; |
||
850 | if (*size > 0x10000 ) |
||
851 | { |
||
852 | *size = 0; |
||
853 | dbgprintf("Invalid BIOS length field\n"); |
||
854 | } |
||
855 | else |
||
856 | rom = (void*)( OS_BASE+legacyBIOSLocation); |
||
857 | |||
858 | |||
859 | } |
||
860 | |||
861 | |||
1119 | serge | 862 | |
863 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
||
864 | { |
||
865 | // if (!pci_dma_supported(dev, mask)) |
||
866 | // return -EIO; |
||
867 | |||
868 | |||
869 | |||
870 | |||
871 | }>><>>>>>><>>>=>>>><>><>><>>4)><4)> |
||
872 |