Subversion Repositories Kolibri OS

/*

 * Copyright 2010 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Alex Deucher

 */

#ifndef EVERGREEND_H

#define EVERGREEND_H

#define EVERGREEN_MAX_SH_GPRS           256

#define EVERGREEN_MAX_TEMP_GPRS         16

#define EVERGREEN_MAX_SH_THREADS        256

#define EVERGREEN_MAX_SH_STACK_ENTRIES  4096

#define EVERGREEN_MAX_FRC_EOV_CNT       16384

#define EVERGREEN_MAX_BACKENDS          8

#define EVERGREEN_MAX_BACKENDS_MASK     0xFF

#define EVERGREEN_MAX_SIMDS             16

#define EVERGREEN_MAX_SIMDS_MASK        0xFFFF

#define EVERGREEN_MAX_PIPES             8

#define EVERGREEN_MAX_PIPES_MASK        0xFF

#define EVERGREEN_MAX_LDS_NUM           0xFFFF

#define CYPRESS_GB_ADDR_CONFIG_GOLDEN        0x02011003

#define BARTS_GB_ADDR_CONFIG_GOLDEN          0x02011003

#define CAYMAN_GB_ADDR_CONFIG_GOLDEN         0x02011003

#define JUNIPER_GB_ADDR_CONFIG_GOLDEN        0x02010002

#define REDWOOD_GB_ADDR_CONFIG_GOLDEN        0x02010002

#define TURKS_GB_ADDR_CONFIG_GOLDEN          0x02010002

#define CEDAR_GB_ADDR_CONFIG_GOLDEN          0x02010001

#define CAICOS_GB_ADDR_CONFIG_GOLDEN         0x02010001

#define SUMO_GB_ADDR_CONFIG_GOLDEN           0x02010002

#define SUMO2_GB_ADDR_CONFIG_GOLDEN          0x02010002

/* pm registers */

#define	SMC_MSG						0x20c

#define		HOST_SMC_MSG(x)				((x) << 0)

#define		HOST_SMC_MSG_MASK			(0xff << 0)

#define		HOST_SMC_MSG_SHIFT			0

#define		HOST_SMC_RESP(x)			((x) << 8)

#define		HOST_SMC_RESP_MASK			(0xff << 8)

#define		HOST_SMC_RESP_SHIFT			8

#define		SMC_HOST_MSG(x)				((x) << 16)

#define		SMC_HOST_MSG_MASK			(0xff << 16)

#define		SMC_HOST_MSG_SHIFT			16

#define		SMC_HOST_RESP(x)			((x) << 24)

#define		SMC_HOST_RESP_MASK			(0xff << 24)

#define		SMC_HOST_RESP_SHIFT			24

#define DCCG_DISP_SLOW_SELECT_REG                       0x4fc

#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)

#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)

#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0

#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)

#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)

#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4

#define	CG_SPLL_FUNC_CNTL				0x600

#define		SPLL_RESET				(1 << 0)

#define		SPLL_SLEEP				(1 << 1)

#define		SPLL_BYPASS_EN				(1 << 3)

#define		SPLL_REF_DIV(x)				((x) << 4)

#define		SPLL_REF_DIV_MASK			(0x3f << 4)

#define		SPLL_PDIV_A(x)				((x) << 20)

#define		SPLL_PDIV_A_MASK			(0x7f << 20)

#define	CG_SPLL_FUNC_CNTL_2				0x604

#define		SCLK_MUX_SEL(x)				((x) << 0)

#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)

#define		SCLK_MUX_UPDATE				(1 << 26)

#define	CG_SPLL_FUNC_CNTL_3				0x608

#define		SPLL_FB_DIV(x)				((x) << 0)

#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)

#define		SPLL_DITHEN				(1 << 28)

#define	CG_SPLL_STATUS					0x60c

#define		SPLL_CHG_STATUS				(1 << 1)

#define MPLL_CNTL_MODE                                  0x61c

#       define MPLL_MCLK_SEL                            (1 << 11)

#       define SS_SSEN                                  (1 << 24)

#       define SS_DSMODE_EN                             (1 << 25)

#define	MPLL_AD_FUNC_CNTL				0x624

#define		CLKF(x)					((x) << 0)

#define		CLKF_MASK				(0x7f << 0)

#define		CLKR(x)					((x) << 7)

#define		CLKR_MASK				(0x1f << 7)

#define		CLKFRAC(x)				((x) << 12)

#define		CLKFRAC_MASK				(0x1f << 12)

#define		YCLK_POST_DIV(x)			((x) << 17)

#define		YCLK_POST_DIV_MASK			(3 << 17)

#define		IBIAS(x)				((x) << 20)

#define		IBIAS_MASK				(0x3ff << 20)

#define		RESET					(1 << 30)

#define		PDNB					(1 << 31)

#define	MPLL_AD_FUNC_CNTL_2				0x628

#define		BYPASS					(1 << 19)

#define		BIAS_GEN_PDNB				(1 << 24)

#define		RESET_EN				(1 << 25)

#define		VCO_MODE				(1 << 29)

#define	MPLL_DQ_FUNC_CNTL				0x62c

#define	MPLL_DQ_FUNC_CNTL_2				0x630

#define GENERAL_PWRMGT                                  0x63c

#       define GLOBAL_PWRMGT_EN                         (1 << 0)

#       define STATIC_PM_EN                             (1 << 1)

#       define THERMAL_PROTECTION_DIS                   (1 << 2)

#       define THERMAL_PROTECTION_TYPE                  (1 << 3)

#       define ENABLE_GEN2PCIE                          (1 << 4)

#       define ENABLE_GEN2XSP                           (1 << 5)

#       define SW_SMIO_INDEX(x)                         ((x) << 6)

#       define SW_SMIO_INDEX_MASK                       (3 << 6)

#       define SW_SMIO_INDEX_SHIFT                      6

#       define LOW_VOLT_D2_ACPI                         (1 << 8)

#       define LOW_VOLT_D3_ACPI                         (1 << 9)

#       define VOLT_PWRMGT_EN                           (1 << 10)

#       define BACKBIAS_PAD_EN                          (1 << 18)

#       define BACKBIAS_VALUE                           (1 << 19)

#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)

#       define AC_DC_SW                                 (1 << 24)

#define SCLK_PWRMGT_CNTL                                  0x644

#       define SCLK_PWRMGT_OFF                            (1 << 0)

#       define SCLK_LOW_D1                                (1 << 1)

#       define FIR_RESET                                  (1 << 4)

#       define FIR_FORCE_TREND_SEL                        (1 << 5)

#       define FIR_TREND_MODE                             (1 << 6)

#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)

#       define GFX_CLK_FORCE_ON                           (1 << 8)

#       define GFX_CLK_REQUEST_OFF                        (1 << 9)

#       define GFX_CLK_FORCE_OFF                          (1 << 10)

#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)

#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)

#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)

#       define DYN_LIGHT_SLEEP_EN                         (1 << 14)

#define	MCLK_PWRMGT_CNTL				0x648

#       define DLL_SPEED(x)				((x) << 0)

#       define DLL_SPEED_MASK				(0x1f << 0)

#       define MPLL_PWRMGT_OFF                          (1 << 5)

#       define DLL_READY                                (1 << 6)

#       define MC_INT_CNTL                              (1 << 7)

#       define MRDCKA0_PDNB                             (1 << 8)

#       define MRDCKA1_PDNB                             (1 << 9)

#       define MRDCKB0_PDNB                             (1 << 10)

#       define MRDCKB1_PDNB                             (1 << 11)

#       define MRDCKC0_PDNB                             (1 << 12)

#       define MRDCKC1_PDNB                             (1 << 13)

#       define MRDCKD0_PDNB                             (1 << 14)

#       define MRDCKD1_PDNB                             (1 << 15)

#       define MRDCKA0_RESET                            (1 << 16)

#       define MRDCKA1_RESET                            (1 << 17)

#       define MRDCKB0_RESET                            (1 << 18)

#       define MRDCKB1_RESET                            (1 << 19)

#       define MRDCKC0_RESET                            (1 << 20)

#       define MRDCKC1_RESET                            (1 << 21)

#       define MRDCKD0_RESET                            (1 << 22)

#       define MRDCKD1_RESET                            (1 << 23)

#       define DLL_READY_READ                           (1 << 24)

#       define USE_DISPLAY_GAP                          (1 << 25)

#       define USE_DISPLAY_URGENT_NORMAL                (1 << 26)

#       define MPLL_TURNOFF_D2                          (1 << 28)

#define	DLL_CNTL					0x64c

#       define MRDCKA0_BYPASS                           (1 << 24)

#       define MRDCKA1_BYPASS                           (1 << 25)

#       define MRDCKB0_BYPASS                           (1 << 26)

#       define MRDCKB1_BYPASS                           (1 << 27)

#       define MRDCKC0_BYPASS                           (1 << 28)

#       define MRDCKC1_BYPASS                           (1 << 29)

#       define MRDCKD0_BYPASS                           (1 << 30)

#       define MRDCKD1_BYPASS                           (1 << 31)

#define CG_AT                                           0x6d4

#       define CG_R(x)					((x) << 0)

#       define CG_R_MASK				(0xffff << 0)

#       define CG_L(x)					((x) << 16)

#       define CG_L_MASK				(0xffff << 16)

#define CG_DISPLAY_GAP_CNTL                               0x714

#       define DISP1_GAP(x)                               ((x) << 0)

#       define DISP1_GAP_MASK                             (3 << 0)

#       define DISP2_GAP(x)                               ((x) << 2)

#       define DISP2_GAP_MASK                             (3 << 2)

#       define VBI_TIMER_COUNT(x)                         ((x) << 4)

#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)

#       define VBI_TIMER_UNIT(x)                          ((x) << 20)

#       define VBI_TIMER_UNIT_MASK                        (7 << 20)

#       define DISP1_GAP_MCHG(x)                          ((x) << 24)

#       define DISP1_GAP_MCHG_MASK                        (3 << 24)

#       define DISP2_GAP_MCHG(x)                          ((x) << 26)

#       define DISP2_GAP_MCHG_MASK                        (3 << 26)

#define	CG_BIF_REQ_AND_RSP				0x7f4

#define		CG_CLIENT_REQ(x)			((x) << 0)

#define		CG_CLIENT_REQ_MASK			(0xff << 0)

#define		CG_CLIENT_REQ_SHIFT			0

#define		CG_CLIENT_RESP(x)			((x) << 8)

#define		CG_CLIENT_RESP_MASK			(0xff << 8)

#define		CG_CLIENT_RESP_SHIFT			8

#define		CLIENT_CG_REQ(x)			((x) << 16)

#define		CLIENT_CG_REQ_MASK			(0xff << 16)

#define		CLIENT_CG_REQ_SHIFT			16

#define		CLIENT_CG_RESP(x)			((x) << 24)

#define		CLIENT_CG_RESP_MASK			(0xff << 24)

#define		CLIENT_CG_RESP_SHIFT			24

#define	CG_SPLL_SPREAD_SPECTRUM				0x790

#define		SSEN					(1 << 0)

#define	CG_SPLL_SPREAD_SPECTRUM_2			0x794

#define	MPLL_SS1					0x85c

#define		CLKV(x)					((x) << 0)

#define		CLKV_MASK				(0x3ffffff << 0)

#define	MPLL_SS2					0x860

#define		CLKS(x)					((x) << 0)

#define		CLKS_MASK				(0xfff << 0)

#define	CG_IND_ADDR					0x8f8

#define	CG_IND_DATA					0x8fc

/* CGIND regs */

#define	CG_CGTT_LOCAL_0					0x00

#define	CG_CGTT_LOCAL_1					0x01

#define	CG_CGTT_LOCAL_2					0x02

#define	CG_CGTT_LOCAL_3					0x03

#define	CG_CGLS_TILE_0					0x20

#define	CG_CGLS_TILE_1					0x21

#define	CG_CGLS_TILE_2					0x22

#define	CG_CGLS_TILE_3					0x23

#define	CG_CGLS_TILE_4					0x24

#define	CG_CGLS_TILE_5					0x25

#define	CG_CGLS_TILE_6					0x26

#define	CG_CGLS_TILE_7					0x27

#define	CG_CGLS_TILE_8					0x28

#define	CG_CGLS_TILE_9					0x29

#define	CG_CGLS_TILE_10					0x2a

#define	CG_CGLS_TILE_11					0x2b

#define VM_L2_CG                                        0x15c0

#define MC_CONFIG                                       0x2000

#define MC_CONFIG_MCD                                   0x20a0

#define MC_CG_CONFIG_MCD                                0x20a4

#define		MC_RD_ENABLE_MCD(x)			((x) << 8)

#define		MC_RD_ENABLE_MCD_MASK			(7 << 8)

#define MC_HUB_MISC_HUB_CG                              0x20b8

#define MC_HUB_MISC_VM_CG                               0x20bc

#define MC_HUB_MISC_SIP_CG                              0x20c0

#define MC_XPB_CLK_GAT                                  0x2478

#define MC_CG_CONFIG                                    0x25bc

#define		MC_RD_ENABLE(x)				((x) << 4)

#define		MC_RD_ENABLE_MASK			(3 << 4)

#define MC_CITF_MISC_RD_CG                              0x2648

#define MC_CITF_MISC_WR_CG                              0x264c

#define MC_CITF_MISC_VM_CG                              0x2650

#       define MEM_LS_ENABLE                            (1 << 19)

#define MC_ARB_BURST_TIME                               0x2808

#define		STATE0(x)				((x) << 0)

#define		STATE0_MASK				(0x1f << 0)

#define		STATE1(x)				((x) << 5)

#define		STATE1_MASK				(0x1f << 5)

#define		STATE2(x)				((x) << 10)

#define		STATE2_MASK				(0x1f << 10)

#define		STATE3(x)				((x) << 15)

#define		STATE3_MASK				(0x1f << 15)

#define MC_SEQ_RAS_TIMING                               0x28a0

#define MC_SEQ_CAS_TIMING                               0x28a4

#define MC_SEQ_MISC_TIMING                              0x28a8

#define MC_SEQ_MISC_TIMING2                             0x28ac

#define MC_SEQ_RD_CTL_D0                                0x28b4

#define MC_SEQ_RD_CTL_D1                                0x28b8

#define MC_SEQ_WR_CTL_D0                                0x28bc

#define MC_SEQ_WR_CTL_D1                                0x28c0

#define MC_SEQ_STATUS_M                                 0x29f4

#       define PMG_PWRSTATE                             (1 << 16)

#define MC_SEQ_MISC1                                    0x2a04

#define MC_SEQ_RESERVE_M                                0x2a08

#define MC_PMG_CMD_EMRS                                 0x2a0c

#define MC_SEQ_MISC3                                    0x2a2c

#define MC_SEQ_MISC5                                    0x2a54

#define MC_SEQ_MISC6                                    0x2a58

#define MC_SEQ_MISC7                                    0x2a64

#define MC_SEQ_CG                                       0x2a68

#define		CG_SEQ_REQ(x)				((x) << 0)

#define		CG_SEQ_REQ_MASK				(0xff << 0)

#define		CG_SEQ_REQ_SHIFT			0

#define		CG_SEQ_RESP(x)				((x) << 8)

#define		CG_SEQ_RESP_MASK			(0xff << 8)

#define		CG_SEQ_RESP_SHIFT			8

#define		SEQ_CG_REQ(x)				((x) << 16)

#define		SEQ_CG_REQ_MASK				(0xff << 16)

#define		SEQ_CG_REQ_SHIFT			16

#define		SEQ_CG_RESP(x)				((x) << 24)

#define		SEQ_CG_RESP_MASK			(0xff << 24)

#define		SEQ_CG_RESP_SHIFT			24

#define MC_SEQ_RAS_TIMING_LP                            0x2a6c

#define MC_SEQ_CAS_TIMING_LP                            0x2a70

#define MC_SEQ_MISC_TIMING_LP                           0x2a74

#define MC_SEQ_MISC_TIMING2_LP                          0x2a78

#define MC_SEQ_WR_CTL_D0_LP                             0x2a7c

#define MC_SEQ_WR_CTL_D1_LP                             0x2a80

#define MC_SEQ_PMG_CMD_EMRS_LP                          0x2a84

#define MC_SEQ_PMG_CMD_MRS_LP                           0x2a88

#define MC_PMG_CMD_MRS                                  0x2aac

#define MC_SEQ_RD_CTL_D0_LP                             0x2b1c

#define MC_SEQ_RD_CTL_D1_LP                             0x2b20

#define MC_PMG_CMD_MRS1                                 0x2b44

#define MC_SEQ_PMG_CMD_MRS1_LP                          0x2b48

#define CGTS_SM_CTRL_REG                                0x9150

/* Registers */

#define RCU_IND_INDEX           			0x100

#define RCU_IND_DATA            			0x104

/* discrete uvd clocks */

#define CG_UPLL_FUNC_CNTL				0x718

#	define UPLL_RESET_MASK				0x00000001

#	define UPLL_SLEEP_MASK				0x00000002

#	define UPLL_BYPASS_EN_MASK			0x00000004

#	define UPLL_CTLREQ_MASK				0x00000008

#	define UPLL_REF_DIV_MASK			0x003F0000

#	define UPLL_VCO_MODE_MASK			0x00000200

#	define UPLL_CTLACK_MASK				0x40000000

#	define UPLL_CTLACK2_MASK			0x80000000

#define CG_UPLL_FUNC_CNTL_2				0x71c

#	define UPLL_PDIV_A(x)				((x) << 0)

#	define UPLL_PDIV_A_MASK				0x0000007F

#	define UPLL_PDIV_B(x)				((x) << 8)

#	define UPLL_PDIV_B_MASK				0x00007F00

#	define VCLK_SRC_SEL(x)				((x) << 20)

#	define VCLK_SRC_SEL_MASK			0x01F00000

#	define DCLK_SRC_SEL(x)				((x) << 25)

#	define DCLK_SRC_SEL_MASK			0x3E000000

#define CG_UPLL_FUNC_CNTL_3				0x720

#	define UPLL_FB_DIV(x)				((x) << 0)

#	define UPLL_FB_DIV_MASK				0x01FFFFFF

#define CG_UPLL_FUNC_CNTL_4				0x854

#	define UPLL_SPARE_ISPARE9			0x00020000

#define CG_UPLL_SPREAD_SPECTRUM				0x79c

#	define SSEN_MASK				0x00000001

/* fusion uvd clocks */

#define CG_DCLK_CNTL                                    0x610

#       define DCLK_DIVIDER_MASK                        0x7f

#       define DCLK_DIR_CNTL_EN                         (1 << 8)

#define CG_DCLK_STATUS                                  0x614

#       define DCLK_STATUS                              (1 << 0)

#define CG_VCLK_CNTL                                    0x618

#define CG_VCLK_STATUS                                  0x61c

#define	CG_SCRATCH1					0x820

#define RLC_CNTL                                        0x3f00

#       define RLC_ENABLE                               (1 << 0)

#       define GFX_POWER_GATING_ENABLE                  (1 << 7)

#       define GFX_POWER_GATING_SRC                     (1 << 8)

#       define DYN_PER_SIMD_PG_ENABLE                   (1 << 27)

#       define LB_CNT_SPIM_ACTIVE                       (1 << 30)

#       define LOAD_BALANCE_ENABLE                      (1 << 31)

#define RLC_HB_BASE                                       0x3f10

#define RLC_HB_CNTL                                       0x3f0c

#define RLC_HB_RPTR                                       0x3f20

#define RLC_HB_WPTR                                       0x3f1c

#define RLC_HB_WPTR_LSB_ADDR                              0x3f14

#define RLC_HB_WPTR_MSB_ADDR                              0x3f18

#define RLC_MC_CNTL                                       0x3f44

#define RLC_UCODE_CNTL                                    0x3f48

#define RLC_UCODE_ADDR                                    0x3f2c

#define RLC_UCODE_DATA                                    0x3f30

/* new for TN */

#define TN_RLC_SAVE_AND_RESTORE_BASE                      0x3f10

#define TN_RLC_LB_CNTR_MAX                                0x3f14

#define TN_RLC_LB_CNTR_INIT                               0x3f18

#define TN_RLC_CLEAR_STATE_RESTORE_BASE                   0x3f20

#define TN_RLC_LB_INIT_SIMD_MASK                          0x3fe4

#define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK                 0x3fe8

#define TN_RLC_LB_PARAMS                                  0x3fec

#define GRBM_GFX_INDEX          			0x802C

#define		INSTANCE_INDEX(x)			((x) << 0)

#define		SE_INDEX(x)     			((x) << 16)

#define		INSTANCE_BROADCAST_WRITES      		(1 << 30)

#define		SE_BROADCAST_WRITES      		(1 << 31)

#define RLC_GFX_INDEX           			0x3fC4

#define CC_GC_SHADER_PIPE_CONFIG			0x8950

#define		WRITE_DIS      				(1 << 0)

#define CC_RB_BACKEND_DISABLE				0x98F4

#define		BACKEND_DISABLE(x)     			((x) << 16)

#define GB_ADDR_CONFIG  				0x98F8

#define		NUM_PIPES(x)				((x) << 0)

#define		NUM_PIPES_MASK				0x0000000f

#define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)

#define		BANK_INTERLEAVE_SIZE(x)			((x) << 8)

#define		NUM_SHADER_ENGINES(x)			((x) << 12)

#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)

#define		NUM_GPUS(x)     			((x) << 20)

#define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)

#define		ROW_SIZE(x)             		((x) << 28)

#define GB_BACKEND_MAP  				0x98FC

#define DMIF_ADDR_CONFIG  				0xBD4

#define HDP_ADDR_CONFIG  				0x2F48

#define HDP_MISC_CNTL  					0x2F4C

#define		HDP_FLUSH_INVALIDATE_CACHE      	(1 << 0)

#define	CC_SYS_RB_BACKEND_DISABLE			0x3F88

#define	GC_USER_RB_BACKEND_DISABLE			0x9B7C

#define	CGTS_SYS_TCC_DISABLE				0x3F90

#define	CGTS_TCC_DISABLE				0x9148

#define	CGTS_USER_SYS_TCC_DISABLE			0x3F94

#define	CGTS_USER_TCC_DISABLE				0x914C

#define	CONFIG_MEMSIZE					0x5428

#define	BIF_FB_EN						0x5490

#define		FB_READ_EN					(1 << 0)

#define		FB_WRITE_EN					(1 << 1)

#define	CP_STRMOUT_CNTL					0x84FC

#define	CP_COHER_CNTL					0x85F0

#define	CP_COHER_SIZE					0x85F4

#define	CP_COHER_BASE					0x85F8

#define	CP_STALLED_STAT1			0x8674

#define	CP_STALLED_STAT2			0x8678

#define	CP_BUSY_STAT				0x867C

#define	CP_STAT						0x8680

#define CP_ME_CNTL					0x86D8

#define		CP_ME_HALT					(1 << 28)

#define		CP_PFP_HALT					(1 << 26)

#define	CP_ME_RAM_DATA					0xC160

#define	CP_ME_RAM_RADDR					0xC158

#define	CP_ME_RAM_WADDR					0xC15C

#define CP_MEQ_THRESHOLDS				0x8764

#define		STQ_SPLIT(x)					((x) << 0)

#define	CP_PERFMON_CNTL					0x87FC

#define	CP_PFP_UCODE_ADDR				0xC150

#define	CP_PFP_UCODE_DATA				0xC154

#define	CP_QUEUE_THRESHOLDS				0x8760

#define		ROQ_IB1_START(x)				((x) << 0)

#define		ROQ_IB2_START(x)				((x) << 8)

#define	CP_RB_BASE					0xC100

#define	CP_RB_CNTL					0xC104

#define		RB_BUFSZ(x)					((x) << 0)

#define		RB_BLKSZ(x)					((x) << 8)

#define		RB_NO_UPDATE					(1 << 27)

#define		RB_RPTR_WR_ENA					(1 << 31)

#define		BUF_SWAP_32BIT					(2 << 16)

#define	CP_RB_RPTR					0x8700

#define	CP_RB_RPTR_ADDR					0xC10C

#define		RB_RPTR_SWAP(x)					((x) << 0)

#define	CP_RB_RPTR_ADDR_HI				0xC110

#define	CP_RB_RPTR_WR					0xC108

#define	CP_RB_WPTR					0xC114

#define	CP_RB_WPTR_ADDR					0xC118

#define	CP_RB_WPTR_ADDR_HI				0xC11C

#define	CP_RB_WPTR_DELAY				0x8704

#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8

#define	CP_DEBUG					0xC1FC

/* Audio clocks */

#define DCCG_AUDIO_DTO_SOURCE             0x05ac

#       define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */

#       define DCCG_AUDIO_DTO_SEL         (1 << 4) /* 0=dto0 1=dto1 */

#define DCCG_AUDIO_DTO0_PHASE             0x05b0

#define DCCG_AUDIO_DTO0_MODULE            0x05b4

#define DCCG_AUDIO_DTO0_LOAD              0x05b8

#define DCCG_AUDIO_DTO0_CNTL              0x05bc

#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)

#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7

#       define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0

#define DCCG_AUDIO_DTO1_PHASE             0x05c0

#define DCCG_AUDIO_DTO1_MODULE            0x05c4

#define DCCG_AUDIO_DTO1_LOAD              0x05c8

#define DCCG_AUDIO_DTO1_CNTL              0x05cc

#       define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3)

/* DCE 4.0 AFMT */

#define HDMI_CONTROL                         0x7030

#       define HDMI_KEEPOUT_MODE             (1 << 0)

#       define HDMI_PACKET_GEN_VERSION       (1 << 4) /* 0 = r6xx compat */

#       define HDMI_ERROR_ACK                (1 << 8)

#       define HDMI_ERROR_MASK               (1 << 9)

#       define HDMI_DEEP_COLOR_ENABLE        (1 << 24)

#       define HDMI_DEEP_COLOR_DEPTH(x)      (((x) & 3) << 28)

#       define HDMI_24BIT_DEEP_COLOR         0

#       define HDMI_30BIT_DEEP_COLOR         1

#       define HDMI_36BIT_DEEP_COLOR         2

#       define HDMI_DEEP_COLOR_DEPTH_MASK    (3 << 28)

#define HDMI_STATUS                          0x7034

#       define HDMI_ACTIVE_AVMUTE            (1 << 0)

#       define HDMI_AUDIO_PACKET_ERROR       (1 << 16)

#       define HDMI_VBI_PACKET_ERROR         (1 << 20)

#define HDMI_AUDIO_PACKET_CONTROL            0x7038

#       define HDMI_AUDIO_DELAY_EN(x)        (((x) & 3) << 4)

#       define HDMI_AUDIO_PACKETS_PER_LINE(x)  (((x) & 0x1f) << 16)

#define HDMI_ACR_PACKET_CONTROL              0x703c

#       define HDMI_ACR_SEND                 (1 << 0)

#       define HDMI_ACR_CONT                 (1 << 1)

#       define HDMI_ACR_SELECT(x)            (((x) & 3) << 4)

#       define HDMI_ACR_HW                   0

#       define HDMI_ACR_32                   1

#       define HDMI_ACR_44                   2

#       define HDMI_ACR_48                   3

#       define HDMI_ACR_SOURCE               (1 << 8) /* 0 - hw; 1 - cts value */

#       define HDMI_ACR_AUTO_SEND            (1 << 12)

#       define HDMI_ACR_N_MULTIPLE(x)        (((x) & 7) << 16)

#       define HDMI_ACR_X1                   1

#       define HDMI_ACR_X2                   2

#       define HDMI_ACR_X4                   4

#       define HDMI_ACR_AUDIO_PRIORITY       (1 << 31)

#define HDMI_VBI_PACKET_CONTROL              0x7040

#       define HDMI_NULL_SEND                (1 << 0)

#       define HDMI_GC_SEND                  (1 << 4)

#       define HDMI_GC_CONT                  (1 << 5) /* 0 - once; 1 - every frame */

#define HDMI_INFOFRAME_CONTROL0              0x7044

#       define HDMI_AVI_INFO_SEND            (1 << 0)

#       define HDMI_AVI_INFO_CONT            (1 << 1)

#       define HDMI_AUDIO_INFO_SEND          (1 << 4)

#       define HDMI_AUDIO_INFO_CONT          (1 << 5)

#       define HDMI_MPEG_INFO_SEND           (1 << 8)

#       define HDMI_MPEG_INFO_CONT           (1 << 9)

#define HDMI_INFOFRAME_CONTROL1              0x7048

#       define HDMI_AVI_INFO_LINE(x)         (((x) & 0x3f) << 0)

#       define HDMI_AVI_INFO_LINE_MASK       (0x3f << 0)

#       define HDMI_AUDIO_INFO_LINE(x)       (((x) & 0x3f) << 8)

#       define HDMI_MPEG_INFO_LINE(x)        (((x) & 0x3f) << 16)

#define HDMI_GENERIC_PACKET_CONTROL          0x704c

#       define HDMI_GENERIC0_SEND            (1 << 0)

#       define HDMI_GENERIC0_CONT            (1 << 1)

#       define HDMI_GENERIC1_SEND            (1 << 4)

#       define HDMI_GENERIC1_CONT            (1 << 5)

#       define HDMI_GENERIC0_LINE(x)         (((x) & 0x3f) << 16)

#       define HDMI_GENERIC1_LINE(x)         (((x) & 0x3f) << 24)

#define HDMI_GC                              0x7058

#       define HDMI_GC_AVMUTE                (1 << 0)

#       define HDMI_GC_AVMUTE_CONT           (1 << 2)

#define AFMT_AUDIO_PACKET_CONTROL2           0x705c

#       define AFMT_AUDIO_LAYOUT_OVRD        (1 << 0)

#       define AFMT_AUDIO_LAYOUT_SELECT      (1 << 1)

#       define AFMT_60958_CS_SOURCE          (1 << 4)

#       define AFMT_AUDIO_CHANNEL_ENABLE(x)  (((x) & 0xff) << 8)

#       define AFMT_DP_AUDIO_STREAM_ID(x)    (((x) & 0xff) << 16)

#define AFMT_AVI_INFO0                       0x7084

#       define AFMT_AVI_INFO_CHECKSUM(x)     (((x) & 0xff) << 0)

#       define AFMT_AVI_INFO_S(x)            (((x) & 3) << 8)

#       define AFMT_AVI_INFO_B(x)            (((x) & 3) << 10)

#       define AFMT_AVI_INFO_A(x)            (((x) & 1) << 12)

#       define AFMT_AVI_INFO_Y(x)            (((x) & 3) << 13)

#       define AFMT_AVI_INFO_Y_RGB           0

#       define AFMT_AVI_INFO_Y_YCBCR422      1

#       define AFMT_AVI_INFO_Y_YCBCR444      2

#       define AFMT_AVI_INFO_Y_A_B_S(x)      (((x) & 0xff) << 8)

#       define AFMT_AVI_INFO_R(x)            (((x) & 0xf) << 16)

#       define AFMT_AVI_INFO_M(x)            (((x) & 0x3) << 20)

#       define AFMT_AVI_INFO_C(x)            (((x) & 0x3) << 22)

#       define AFMT_AVI_INFO_C_M_R(x)        (((x) & 0xff) << 16)

#       define AFMT_AVI_INFO_SC(x)           (((x) & 0x3) << 24)

#       define AFMT_AVI_INFO_Q(x)            (((x) & 0x3) << 26)

#       define AFMT_AVI_INFO_EC(x)           (((x) & 0x3) << 28)

#       define AFMT_AVI_INFO_ITC(x)          (((x) & 0x1) << 31)

#       define AFMT_AVI_INFO_ITC_EC_Q_SC(x)  (((x) & 0xff) << 24)

#define AFMT_AVI_INFO1                       0x7088

#       define AFMT_AVI_INFO_VIC(x)          (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

#       define AFMT_AVI_INFO_PR(x)           (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

#       define AFMT_AVI_INFO_CN(x)           (((x) & 0x3) << 12)

#       define AFMT_AVI_INFO_YQ(x)           (((x) & 0x3) << 14)

#       define AFMT_AVI_INFO_TOP(x)          (((x) & 0xffff) << 16)

#define AFMT_AVI_INFO2                       0x708c

#       define AFMT_AVI_INFO_BOTTOM(x)       (((x) & 0xffff) << 0)

#       define AFMT_AVI_INFO_LEFT(x)         (((x) & 0xffff) << 16)

#define AFMT_AVI_INFO3                       0x7090

#       define AFMT_AVI_INFO_RIGHT(x)        (((x) & 0xffff) << 0)

#       define AFMT_AVI_INFO_VERSION(x)      (((x) & 3) << 24)

#define AFMT_MPEG_INFO0                      0x7094

#       define AFMT_MPEG_INFO_CHECKSUM(x)    (((x) & 0xff) << 0)

#       define AFMT_MPEG_INFO_MB0(x)         (((x) & 0xff) << 8)

#       define AFMT_MPEG_INFO_MB1(x)         (((x) & 0xff) << 16)

#       define AFMT_MPEG_INFO_MB2(x)         (((x) & 0xff) << 24)

#define AFMT_MPEG_INFO1                      0x7098

#       define AFMT_MPEG_INFO_MB3(x)         (((x) & 0xff) << 0)

#       define AFMT_MPEG_INFO_MF(x)          (((x) & 3) << 8)

#       define AFMT_MPEG_INFO_FR(x)          (((x) & 1) << 12)

#define AFMT_GENERIC0_HDR                    0x709c

#define AFMT_GENERIC0_0                      0x70a0

#define AFMT_GENERIC0_1                      0x70a4

#define AFMT_GENERIC0_2                      0x70a8

#define AFMT_GENERIC0_3                      0x70ac

#define AFMT_GENERIC0_4                      0x70b0

#define AFMT_GENERIC0_5                      0x70b4

#define AFMT_GENERIC0_6                      0x70b8

#define AFMT_GENERIC1_HDR                    0x70bc

#define AFMT_GENERIC1_0                      0x70c0

#define AFMT_GENERIC1_1                      0x70c4

#define AFMT_GENERIC1_2                      0x70c8

#define AFMT_GENERIC1_3                      0x70cc

#define AFMT_GENERIC1_4                      0x70d0

#define AFMT_GENERIC1_5                      0x70d4

#define AFMT_GENERIC1_6                      0x70d8

#define HDMI_ACR_32_0                        0x70dc

#       define HDMI_ACR_CTS_32(x)            (((x) & 0xfffff) << 12)

#define HDMI_ACR_32_1                        0x70e0

#       define HDMI_ACR_N_32(x)              (((x) & 0xfffff) << 0)

#define HDMI_ACR_44_0                        0x70e4

#       define HDMI_ACR_CTS_44(x)            (((x) & 0xfffff) << 12)

#define HDMI_ACR_44_1                        0x70e8

#       define HDMI_ACR_N_44(x)              (((x) & 0xfffff) << 0)

#define HDMI_ACR_48_0                        0x70ec

#       define HDMI_ACR_CTS_48(x)            (((x) & 0xfffff) << 12)

#define HDMI_ACR_48_1                        0x70f0

#       define HDMI_ACR_N_48(x)              (((x) & 0xfffff) << 0)

#define HDMI_ACR_STATUS_0                    0x70f4

#define HDMI_ACR_STATUS_1                    0x70f8

#define AFMT_AUDIO_INFO0                     0x70fc

#       define AFMT_AUDIO_INFO_CHECKSUM(x)   (((x) & 0xff) << 0)

#       define AFMT_AUDIO_INFO_CC(x)         (((x) & 7) << 8)

#       define AFMT_AUDIO_INFO_CT(x)         (((x) & 0xf) << 11)

#       define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x)   (((x) & 0xff) << 16)

#       define AFMT_AUDIO_INFO_CXT(x)        (((x) & 0x1f) << 24)

#define AFMT_AUDIO_INFO1                     0x7100

#       define AFMT_AUDIO_INFO_CA(x)         (((x) & 0xff) << 0)

#       define AFMT_AUDIO_INFO_LSV(x)        (((x) & 0xf) << 11)

#       define AFMT_AUDIO_INFO_DM_INH(x)     (((x) & 1) << 15)

#       define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

#       define AFMT_AUDIO_INFO_LFEBPL(x)     (((x) & 3) << 16)

#define AFMT_60958_0                         0x7104

#       define AFMT_60958_CS_A(x)            (((x) & 1) << 0)

#       define AFMT_60958_CS_B(x)            (((x) & 1) << 1)

#       define AFMT_60958_CS_C(x)            (((x) & 1) << 2)

#       define AFMT_60958_CS_D(x)            (((x) & 3) << 3)

#       define AFMT_60958_CS_MODE(x)         (((x) & 3) << 6)

#       define AFMT_60958_CS_CATEGORY_CODE(x)      (((x) & 0xff) << 8)

#       define AFMT_60958_CS_SOURCE_NUMBER(x)      (((x) & 0xf) << 16)

#       define AFMT_60958_CS_CHANNEL_NUMBER_L(x)   (((x) & 0xf) << 20)

#       define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

#       define AFMT_60958_CS_CLOCK_ACCURACY(x)     (((x) & 3) << 28)

#define AFMT_60958_1                         0x7108

#       define AFMT_60958_CS_WORD_LENGTH(x)  (((x) & 0xf) << 0)

#       define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x)   (((x) & 0xf) << 4)

#       define AFMT_60958_CS_VALID_L(x)      (((x) & 1) << 16)

#       define AFMT_60958_CS_VALID_R(x)      (((x) & 1) << 18)

#       define AFMT_60958_CS_CHANNEL_NUMBER_R(x)   (((x) & 0xf) << 20)

#define AFMT_AUDIO_CRC_CONTROL               0x710c

#       define AFMT_AUDIO_CRC_EN             (1 << 0)

#define AFMT_RAMP_CONTROL0                   0x7110

#       define AFMT_RAMP_MAX_COUNT(x)        (((x) & 0xffffff) << 0)

#       define AFMT_RAMP_DATA_SIGN           (1 << 31)

#define AFMT_RAMP_CONTROL1                   0x7114

#       define AFMT_RAMP_MIN_COUNT(x)        (((x) & 0xffffff) << 0)

#       define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)

#define AFMT_RAMP_CONTROL2                   0x7118

#       define AFMT_RAMP_INC_COUNT(x)        (((x) & 0xffffff) << 0)

#define AFMT_RAMP_CONTROL3                   0x711c

#       define AFMT_RAMP_DEC_COUNT(x)        (((x) & 0xffffff) << 0)

#define AFMT_60958_2                         0x7120

#       define AFMT_60958_CS_CHANNEL_NUMBER_2(x)   (((x) & 0xf) << 0)

#       define AFMT_60958_CS_CHANNEL_NUMBER_3(x)   (((x) & 0xf) << 4)

#       define AFMT_60958_CS_CHANNEL_NUMBER_4(x)   (((x) & 0xf) << 8)

#       define AFMT_60958_CS_CHANNEL_NUMBER_5(x)   (((x) & 0xf) << 12)

#       define AFMT_60958_CS_CHANNEL_NUMBER_6(x)   (((x) & 0xf) << 16)

#       define AFMT_60958_CS_CHANNEL_NUMBER_7(x)   (((x) & 0xf) << 20)

#define AFMT_STATUS                          0x7128

#       define AFMT_AUDIO_ENABLE             (1 << 4)

#       define AFMT_AUDIO_HBR_ENABLE         (1 << 8)

#       define AFMT_AZ_FORMAT_WTRIG          (1 << 28)

#       define AFMT_AZ_FORMAT_WTRIG_INT      (1 << 29)

#       define AFMT_AZ_AUDIO_ENABLE_CHG      (1 << 30)

#define AFMT_AUDIO_PACKET_CONTROL            0x712c

#       define AFMT_AUDIO_SAMPLE_SEND        (1 << 0)

#       define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */

#       define AFMT_AUDIO_TEST_EN            (1 << 12)

#       define AFMT_AUDIO_CHANNEL_SWAP       (1 << 24)

#       define AFMT_60958_CS_UPDATE          (1 << 26)

#       define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

#       define AFMT_AZ_FORMAT_WTRIG_MASK     (1 << 28)

#       define AFMT_AZ_FORMAT_WTRIG_ACK      (1 << 29)

#       define AFMT_AZ_AUDIO_ENABLE_CHG_ACK  (1 << 30)

#define AFMT_VBI_PACKET_CONTROL              0x7130

#       define AFMT_GENERIC0_UPDATE          (1 << 2)

#define AFMT_INFOFRAME_CONTROL0              0x7134

#       define AFMT_AUDIO_INFO_SOURCE        (1 << 6) /* 0 - sound block; 1 - afmt regs */

#       define AFMT_AUDIO_INFO_UPDATE        (1 << 7)

#       define AFMT_MPEG_INFO_UPDATE         (1 << 10)

#define AFMT_GENERIC0_7                      0x7138

/* DCE4/5 ELD audio interface */

#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER          0x5f78

#define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)

#define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)

#define		SPEAKER_ALLOCATION_SHIFT		0

#define		HDMI_CONNECTION				(1 << 16)

#define		DP_CONNECTION				(1 << 17)

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0        0x5f84 /* LPCM */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1        0x5f88 /* AC3 */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2        0x5f8c /* MPEG1 */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3        0x5f90 /* MP3 */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4        0x5f94 /* MPEG2 */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5        0x5f98 /* AAC */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6        0x5f9c /* DTS */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7        0x5fa0 /* ATRAC */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8        0x5fa4 /* one bit audio - leave at 0 (default) */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9        0x5fa8 /* Dolby Digital */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10       0x5fac /* DTS-HD */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11       0x5fb0 /* MAT-MLP */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12       0x5fb4 /* DTS */

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13       0x5fb8 /* WMA Pro */

#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)

/* max channels minus one.  7 = 8 channels */

#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)

#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)

#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */

/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO

 * bit0 = 32 kHz

 * bit1 = 44.1 kHz

 * bit2 = 48 kHz

 * bit3 = 88.2 kHz

 * bit4 = 96 kHz

 * bit5 = 176.4 kHz

 * bit6 = 192 kHz

 */

#define AZ_CHANNEL_COUNT_CONTROL                          0x5fe4

#       define HBR_CHANNEL_COUNT(x)                       (((x) & 0x7) << 0)

#       define COMPRESSED_CHANNEL_COUNT(x)                (((x) & 0x7) << 4)

/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT

 * 0   = use stream header

 * 1-7 = channel count - 1

 */

#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC         0x5fe8

#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)

#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)

/* VIDEO_LIPSYNC, AUDIO_LIPSYNC

 * 0   = invalid

 * x   = legal delay value

 * 255 = sync not supported

 */

#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR             0x5fec

#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */

#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4

#       define DISPLAY0_TYPE(x)                           (((x) & 0x3) << 0)

#       define DISPLAY_TYPE_NONE                   0

#       define DISPLAY_TYPE_HDMI                   1

#       define DISPLAY_TYPE_DP                     2

#       define DISPLAY0_ID(x)                             (((x) & 0x3f) << 2)

#       define DISPLAY1_TYPE(x)                           (((x) & 0x3) << 8)

#       define DISPLAY1_ID(x)                             (((x) & 0x3f) << 10)

#       define DISPLAY2_TYPE(x)                           (((x) & 0x3) << 16)

#       define DISPLAY2_ID(x)                             (((x) & 0x3f) << 18)

#       define DISPLAY3_TYPE(x)                           (((x) & 0x3) << 24)

#       define DISPLAY3_ID(x)                             (((x) & 0x3f) << 26)

#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8

#       define DISPLAY4_TYPE(x)                           (((x) & 0x3) << 0)

#       define DISPLAY4_ID(x)                             (((x) & 0x3f) << 2)

#       define DISPLAY5_TYPE(x)                           (((x) & 0x3) << 8)

#       define DISPLAY5_ID(x)                             (((x) & 0x3f) << 10)

#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER       0x5ffc

#       define NUMBER_OF_DISPLAY_ID(x)                    (((x) & 0x7) << 0)

#define AZ_HOT_PLUG_CONTROL                               0x5e78

#       define AZ_FORCE_CODEC_WAKE                        (1 << 0)

#       define PIN0_JACK_DETECTION_ENABLE                 (1 << 4)

#       define PIN1_JACK_DETECTION_ENABLE                 (1 << 5)

#       define PIN2_JACK_DETECTION_ENABLE                 (1 << 6)

#       define PIN3_JACK_DETECTION_ENABLE                 (1 << 7)

#       define PIN0_UNSOLICITED_RESPONSE_ENABLE           (1 << 8)

#       define PIN1_UNSOLICITED_RESPONSE_ENABLE           (1 << 9)

#       define PIN2_UNSOLICITED_RESPONSE_ENABLE           (1 << 10)

#       define PIN3_UNSOLICITED_RESPONSE_ENABLE           (1 << 11)

#       define CODEC_HOT_PLUG_ENABLE                      (1 << 12)

#       define PIN0_AUDIO_ENABLED                         (1 << 24)

#       define PIN1_AUDIO_ENABLED                         (1 << 25)

#       define PIN2_AUDIO_ENABLED                         (1 << 26)

#       define PIN3_AUDIO_ENABLED                         (1 << 27)

#       define AUDIO_ENABLED                              (1 << 31)

#define	GC_USER_SHADER_PIPE_CONFIG			0x8954

#define		INACTIVE_QD_PIPES(x)				((x) << 8)

#define		INACTIVE_QD_PIPES_MASK				0x0000FF00

#define		INACTIVE_SIMDS(x)				((x) << 16)

#define		INACTIVE_SIMDS_MASK				0x00FF0000

#define	GRBM_CNTL					0x8000

#define		GRBM_READ_TIMEOUT(x)				((x) << 0)

#define	GRBM_SOFT_RESET					0x8020

#define		SOFT_RESET_CP					(1 << 0)

#define		SOFT_RESET_CB					(1 << 1)

#define		SOFT_RESET_DB					(1 << 3)

#define		SOFT_RESET_PA					(1 << 5)

#define		SOFT_RESET_SC					(1 << 6)

#define		SOFT_RESET_SPI					(1 << 8)

#define		SOFT_RESET_SH					(1 << 9)

#define		SOFT_RESET_SX					(1 << 10)

#define		SOFT_RESET_TC					(1 << 11)

#define		SOFT_RESET_TA					(1 << 12)

#define		SOFT_RESET_VC					(1 << 13)

#define		SOFT_RESET_VGT					(1 << 14)

#define	GRBM_STATUS					0x8010

#define		CMDFIFO_AVAIL_MASK				0x0000000F

#define		SRBM_RQ_PENDING					(1 << 5)

#define		CF_RQ_PENDING					(1 << 7)

#define		PF_RQ_PENDING					(1 << 8)

#define		GRBM_EE_BUSY					(1 << 10)

#define		SX_CLEAN					(1 << 11)

#define		DB_CLEAN					(1 << 12)

#define		CB_CLEAN					(1 << 13)

#define		TA_BUSY 					(1 << 14)

#define		VGT_BUSY_NO_DMA					(1 << 16)

#define		VGT_BUSY					(1 << 17)

#define		SX_BUSY 					(1 << 20)

#define		SH_BUSY 					(1 << 21)

#define		SPI_BUSY					(1 << 22)

#define		SC_BUSY 					(1 << 24)

#define		PA_BUSY 					(1 << 25)

#define		DB_BUSY 					(1 << 26)

#define		CP_COHERENCY_BUSY      				(1 << 28)

#define		CP_BUSY 					(1 << 29)

#define		CB_BUSY 					(1 << 30)

#define		GUI_ACTIVE					(1 << 31)

#define	GRBM_STATUS_SE0					0x8014

#define	GRBM_STATUS_SE1					0x8018

#define		SE_SX_CLEAN					(1 << 0)

#define		SE_DB_CLEAN					(1 << 1)

#define		SE_CB_CLEAN					(1 << 2)

#define		SE_TA_BUSY					(1 << 25)

#define		SE_SX_BUSY					(1 << 26)

#define		SE_SPI_BUSY					(1 << 27)

#define		SE_SH_BUSY					(1 << 28)

#define		SE_SC_BUSY					(1 << 29)

#define		SE_DB_BUSY					(1 << 30)

#define		SE_CB_BUSY					(1 << 31)

/* evergreen */

#define	CG_THERMAL_CTRL					0x72c

#define		TOFFSET_MASK			        0x00003FE0

#define		TOFFSET_SHIFT			        5

#define		DIG_THERM_DPM(x)			((x) << 14)

#define		DIG_THERM_DPM_MASK			0x003FC000

#define		DIG_THERM_DPM_SHIFT			14

#define	CG_THERMAL_INT					0x734

#define		DIG_THERM_INTH(x)			((x) << 8)

#define		DIG_THERM_INTH_MASK			0x0000FF00

#define		DIG_THERM_INTH_SHIFT			8

#define		DIG_THERM_INTL(x)			((x) << 16)

#define		DIG_THERM_INTL_MASK			0x00FF0000

#define		DIG_THERM_INTL_SHIFT			16

#define 	THERM_INT_MASK_HIGH			(1 << 24)

#define 	THERM_INT_MASK_LOW			(1 << 25)

#define	TN_CG_THERMAL_INT_CTRL				0x738

#define		TN_DIG_THERM_INTH(x)			((x) << 0)

#define		TN_DIG_THERM_INTH_MASK			0x000000FF

#define		TN_DIG_THERM_INTH_SHIFT			0

#define		TN_DIG_THERM_INTL(x)			((x) << 8)

#define		TN_DIG_THERM_INTL_MASK			0x0000FF00

#define		TN_DIG_THERM_INTL_SHIFT			8

#define 	TN_THERM_INT_MASK_HIGH			(1 << 24)

#define 	TN_THERM_INT_MASK_LOW			(1 << 25)

#define	CG_MULT_THERMAL_STATUS				0x740

#define		ASIC_T(x)			        ((x) << 16)

#define		ASIC_T_MASK			        0x07FF0000

#define		ASIC_T_SHIFT			        16

#define	CG_TS0_STATUS					0x760

#define		TS0_ADC_DOUT_MASK			0x000003FF

#define		TS0_ADC_DOUT_SHIFT			0

/* APU */

#define	CG_THERMAL_STATUS			        0x678

#define	HDP_HOST_PATH_CNTL				0x2C00

#define	HDP_NONSURFACE_BASE				0x2C04

#define	HDP_NONSURFACE_INFO				0x2C08

#define	HDP_NONSURFACE_SIZE				0x2C0C

#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480

#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0

#define	HDP_TILING_CONFIG				0x2F3C

#define MC_SHARED_CHMAP						0x2004

#define		NOOFCHAN_SHIFT					12

#define		NOOFCHAN_MASK					0x00003000

#define MC_SHARED_CHREMAP					0x2008

#define MC_SHARED_BLACKOUT_CNTL           		0x20ac

#define		BLACKOUT_MODE_MASK			0x00000007

#define	MC_ARB_RAMCFG					0x2760

#define		NOOFBANK_SHIFT					0

#define		NOOFBANK_MASK					0x00000003

#define		NOOFRANK_SHIFT					2

#define		NOOFRANK_MASK					0x00000004

#define		NOOFROWS_SHIFT					3

#define		NOOFROWS_MASK					0x00000038

#define		NOOFCOLS_SHIFT					6

#define		NOOFCOLS_MASK					0x000000C0

#define		CHANSIZE_SHIFT					8

#define		CHANSIZE_MASK					0x00000100

#define		BURSTLENGTH_SHIFT				9

#define		BURSTLENGTH_MASK				0x00000200

#define		CHANSIZE_OVERRIDE				(1 << 11)

#define	FUS_MC_ARB_RAMCFG				0x2768

#define	MC_VM_AGP_TOP					0x2028

#define	MC_VM_AGP_BOT					0x202C

#define	MC_VM_AGP_BASE					0x2030

#define	MC_VM_FB_LOCATION				0x2024

#define	MC_FUS_VM_FB_OFFSET				0x2898

#define	MC_VM_MB_L1_TLB0_CNTL				0x2234

#define	MC_VM_MB_L1_TLB1_CNTL				0x2238

#define	MC_VM_MB_L1_TLB2_CNTL				0x223C

#define	MC_VM_MB_L1_TLB3_CNTL				0x2240

#define		ENABLE_L1_TLB					(1 << 0)

#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)

#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)

#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)

#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)

#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)

#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)

#define		EFFECTIVE_L1_TLB_SIZE(x)			((x)<<15)

#define		EFFECTIVE_L1_QUEUE_SIZE(x)			((x)<<18)

#define	MC_VM_MD_L1_TLB0_CNTL				0x2654

#define	MC_VM_MD_L1_TLB1_CNTL				0x2658

#define	MC_VM_MD_L1_TLB2_CNTL				0x265C

#define	MC_VM_MD_L1_TLB3_CNTL				0x2698

#define	FUS_MC_VM_MD_L1_TLB0_CNTL			0x265C

#define	FUS_MC_VM_MD_L1_TLB1_CNTL			0x2660

#define	FUS_MC_VM_MD_L1_TLB2_CNTL			0x2664

#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C

#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038

#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034

#define	PA_CL_ENHANCE					0x8A14

#define		CLIP_VTX_REORDER_ENA				(1 << 0)

#define		NUM_CLIP_SEQ(x)					((x) << 1)

#define	PA_SC_ENHANCE					0x8BF0

#define PA_SC_AA_CONFIG					0x28C04

#define         MSAA_NUM_SAMPLES_SHIFT                  0

#define         MSAA_NUM_SAMPLES_MASK                   0x3

#define PA_SC_CLIPRECT_RULE				0x2820C

#define	PA_SC_EDGERULE					0x28230

#define	PA_SC_FIFO_SIZE					0x8BCC

#define		SC_PRIM_FIFO_SIZE(x)				((x) << 0)

#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 12)

#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 20)

#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24

#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)

#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)

#define PA_SC_LINE_STIPPLE				0x28A0C

#define	PA_SU_LINE_STIPPLE_VALUE			0x8A60

#define	PA_SC_LINE_STIPPLE_STATE			0x8B10

#define	SCRATCH_REG0					0x8500

#define	SCRATCH_REG1					0x8504

#define	SCRATCH_REG2					0x8508

#define	SCRATCH_REG3					0x850C

#define	SCRATCH_REG4					0x8510

#define	SCRATCH_REG5					0x8514

#define	SCRATCH_REG6					0x8518

#define	SCRATCH_REG7					0x851C

#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_ADDR					0x8544

#define	SMX_SAR_CTL0					0xA008

#define	SMX_DC_CTL0					0xA020

#define		USE_HASH_FUNCTION				(1 << 0)

#define		NUMBER_OF_SETS(x)				((x) << 1)

#define		FLUSH_ALL_ON_EVENT				(1 << 10)

#define		STALL_ON_EVENT					(1 << 11)

#define	SMX_EVENT_CTL					0xA02C

#define		ES_FLUSH_CTL(x)					((x) << 0)

#define		GS_FLUSH_CTL(x)					((x) << 3)

#define		ACK_FLUSH_CTL(x)				((x) << 6)

#define		SYNC_FLUSH_CTL					(1 << 8)

#define	SPI_CONFIG_CNTL					0x9100

#define		GPR_WRITE_PRIORITY(x)				((x) << 0)

#define	SPI_CONFIG_CNTL_1				0x913C

#define		VTX_DONE_DELAY(x)				((x) << 0)

#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)

#define	SPI_INPUT_Z					0x286D8

#define	SPI_PS_IN_CONTROL_0				0x286CC

#define		NUM_INTERP(x)					((x)<<0)

#define		POSITION_ENA					(1<<8)

#define		POSITION_CENTROID				(1<<9)

#define		POSITION_ADDR(x)				((x)<<10)

#define		PARAM_GEN(x)					((x)<<15)

#define		PARAM_GEN_ADDR(x)				((x)<<19)

#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)

#define		PERSP_GRADIENT_ENA				(1<<28)

#define		LINEAR_GRADIENT_ENA				(1<<29)

#define		POSITION_SAMPLE					(1<<30)

#define		BARYC_AT_SAMPLE_ENA				(1<<31)

#define	SQ_CONFIG					0x8C00

#define		VC_ENABLE					(1 << 0)

#define		EXPORT_SRC_C					(1 << 1)

#define		CS_PRIO(x)					((x) << 18)

#define		LS_PRIO(x)					((x) << 20)

#define		HS_PRIO(x)					((x) << 22)

#define		PS_PRIO(x)					((x) << 24)

#define		VS_PRIO(x)					((x) << 26)

#define		GS_PRIO(x)					((x) << 28)

#define		ES_PRIO(x)					((x) << 30)

#define	SQ_GPR_RESOURCE_MGMT_1				0x8C04

#define		NUM_PS_GPRS(x)					((x) << 0)

#define		NUM_VS_GPRS(x)					((x) << 16)

#define		NUM_CLAUSE_TEMP_GPRS(x)				((x) << 28)

#define	SQ_GPR_RESOURCE_MGMT_2				0x8C08

#define		NUM_GS_GPRS(x)					((x) << 0)

#define		NUM_ES_GPRS(x)					((x) << 16)

#define	SQ_GPR_RESOURCE_MGMT_3				0x8C0C

#define		NUM_HS_GPRS(x)					((x) << 0)

#define		NUM_LS_GPRS(x)					((x) << 16)

#define	SQ_GLOBAL_GPR_RESOURCE_MGMT_1			0x8C10

#define	SQ_GLOBAL_GPR_RESOURCE_MGMT_2			0x8C14

#define	SQ_THREAD_RESOURCE_MGMT				0x8C18

#define		NUM_PS_THREADS(x)				((x) << 0)

#define		NUM_VS_THREADS(x)				((x) << 8)

#define		NUM_GS_THREADS(x)				((x) << 16)

#define		NUM_ES_THREADS(x)				((x) << 24)

#define	SQ_THREAD_RESOURCE_MGMT_2			0x8C1C

#define		NUM_HS_THREADS(x)				((x) << 0)

#define		NUM_LS_THREADS(x)				((x) << 8)

#define	SQ_STACK_RESOURCE_MGMT_1			0x8C20

#define		NUM_PS_STACK_ENTRIES(x)				((x) << 0)

#define		NUM_VS_STACK_ENTRIES(x)				((x) << 16)

#define	SQ_STACK_RESOURCE_MGMT_2			0x8C24

#define		NUM_GS_STACK_ENTRIES(x)				((x) << 0)

#define		NUM_ES_STACK_ENTRIES(x)				((x) << 16)

#define	SQ_STACK_RESOURCE_MGMT_3			0x8C28

#define		NUM_HS_STACK_ENTRIES(x)				((x) << 0)

#define		NUM_LS_STACK_ENTRIES(x)				((x) << 16)

#define	SQ_DYN_GPR_CNTL_PS_FLUSH_REQ    		0x8D8C

#define	SQ_DYN_GPR_SIMD_LOCK_EN    			0x8D94

#define	SQ_STATIC_THREAD_MGMT_1    			0x8E20

#define	SQ_STATIC_THREAD_MGMT_2    			0x8E24

#define	SQ_STATIC_THREAD_MGMT_3    			0x8E28

#define	SQ_LDS_RESOURCE_MGMT    			0x8E2C

#define	SQ_MS_FIFO_SIZES				0x8CF0

#define		CACHE_FIFO_SIZE(x)				((x) << 0)

#define		FETCH_FIFO_HIWATER(x)				((x) << 8)

#define		DONE_FIFO_HIWATER(x)				((x) << 16)

#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)

#define	SX_DEBUG_1					0x9058

#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)

#define	SX_EXPORT_BUFFER_SIZES				0x900C

#define		COLOR_BUFFER_SIZE(x)				((x) << 0)

#define		POSITION_BUFFER_SIZE(x)				((x) << 8)

#define		SMX_BUFFER_SIZE(x)				((x) << 16)

#define	SX_MEMORY_EXPORT_BASE				0x9010

#define	SX_MISC						0x28350

#define CB_PERF_CTR0_SEL_0				0x9A20

#define CB_PERF_CTR0_SEL_1				0x9A24

#define CB_PERF_CTR1_SEL_0				0x9A28

#define CB_PERF_CTR1_SEL_1				0x9A2C

#define CB_PERF_CTR2_SEL_0				0x9A30

#define CB_PERF_CTR2_SEL_1				0x9A34

#define CB_PERF_CTR3_SEL_0				0x9A38

#define CB_PERF_CTR3_SEL_1				0x9A3C

#define	TA_CNTL_AUX					0x9508

#define		DISABLE_CUBE_WRAP				(1 << 0)

#define		DISABLE_CUBE_ANISO				(1 << 1)

#define		SYNC_GRADIENT					(1 << 24)

#define		SYNC_WALKER					(1 << 25)

#define		SYNC_ALIGNER					(1 << 26)

#define	TCP_CHAN_STEER_LO				0x960c

#define	TCP_CHAN_STEER_HI				0x9610

#define	VGT_CACHE_INVALIDATION				0x88C4

#define		CACHE_INVALIDATION(x)				((x) << 0)

#define			VC_ONLY						0

#define			TC_ONLY						1

#define			VC_AND_TC					2

#define		AUTO_INVLD_EN(x)				((x) << 6)

#define			NO_AUTO						0

#define			ES_AUTO						1

#define			GS_AUTO						2

#define			ES_AND_GS_AUTO					3

#define	VGT_GS_VERTEX_REUSE				0x88D4

#define	VGT_NUM_INSTANCES				0x8974

#define	VGT_OUT_DEALLOC_CNTL				0x28C5C

#define		DEALLOC_DIST_MASK				0x0000007F

#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58

#define		VTX_REUSE_DEPTH_MASK				0x000000FF