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Rev | Author | Line No. | Line |
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2997 | Serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | * Rafał Miłecki |
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26 | */ |
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3764 | Serge | 27 | #include |
2997 | Serge | 28 | #include |
29 | #include |
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30 | #include "radeon.h" |
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31 | #include "radeon_asic.h" |
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6104 | serge | 32 | #include "radeon_audio.h" |
2997 | Serge | 33 | #include "evergreend.h" |
34 | #include "atom.h" |
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35 | |||
5271 | serge | 36 | /* enable the audio stream */ |
6104 | serge | 37 | void dce4_audio_enable(struct radeon_device *rdev, |
5271 | serge | 38 | struct r600_audio_pin *pin, |
39 | u8 enable_mask) |
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40 | { |
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41 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
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42 | |||
43 | if (!pin) |
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44 | return; |
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45 | |||
46 | if (enable_mask) { |
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47 | tmp |= AUDIO_ENABLED; |
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48 | if (enable_mask & 1) |
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49 | tmp |= PIN0_AUDIO_ENABLED; |
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50 | if (enable_mask & 2) |
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51 | tmp |= PIN1_AUDIO_ENABLED; |
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52 | if (enable_mask & 4) |
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53 | tmp |= PIN2_AUDIO_ENABLED; |
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54 | if (enable_mask & 8) |
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55 | tmp |= PIN3_AUDIO_ENABLED; |
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56 | } else { |
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57 | tmp &= ~(AUDIO_ENABLED | |
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58 | PIN0_AUDIO_ENABLED | |
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59 | PIN1_AUDIO_ENABLED | |
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60 | PIN2_AUDIO_ENABLED | |
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61 | PIN3_AUDIO_ENABLED); |
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62 | } |
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63 | |||
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
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65 | } |
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66 | |||
6104 | serge | 67 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
68 | const struct radeon_hdmi_acr *acr) |
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2997 | Serge | 69 | { |
70 | struct drm_device *dev = encoder->dev; |
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71 | struct radeon_device *rdev = dev->dev_private; |
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6104 | serge | 72 | int bpc = 8; |
2997 | Serge | 73 | |
6104 | serge | 74 | if (encoder->crtc) { |
75 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
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76 | bpc = radeon_crtc->bpc; |
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77 | } |
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2997 | Serge | 78 | |
6104 | serge | 79 | if (bpc > 8) |
80 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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81 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
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82 | else |
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83 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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84 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
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85 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
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2997 | Serge | 86 | |
6104 | serge | 87 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); |
88 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); |
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89 | |||
90 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
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91 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); |
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92 | |||
93 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
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94 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); |
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2997 | Serge | 95 | } |
96 | |||
6104 | serge | 97 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
98 | struct drm_connector *connector, struct drm_display_mode *mode) |
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5078 | serge | 99 | { |
100 | struct radeon_device *rdev = encoder->dev->dev_private; |
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101 | u32 tmp = 0; |
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102 | |||
103 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
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104 | if (connector->latency_present[1]) |
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105 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
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106 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
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107 | else |
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108 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
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109 | } else { |
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110 | if (connector->latency_present[0]) |
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111 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
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112 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
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113 | else |
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114 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
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115 | } |
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6104 | serge | 116 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
5078 | serge | 117 | } |
118 | |||
6104 | serge | 119 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
120 | u8 *sadb, int sad_count) |
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5078 | serge | 121 | { |
122 | struct radeon_device *rdev = encoder->dev->dev_private; |
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123 | u32 tmp; |
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124 | |||
125 | /* program the speaker allocation */ |
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6104 | serge | 126 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
5078 | serge | 127 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
128 | /* set HDMI mode */ |
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129 | tmp |= HDMI_CONNECTION; |
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130 | if (sad_count) |
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131 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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132 | else |
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133 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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6104 | serge | 134 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
135 | } |
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5078 | serge | 136 | |
6104 | serge | 137 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
138 | u8 *sadb, int sad_count) |
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139 | { |
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140 | struct radeon_device *rdev = encoder->dev->dev_private; |
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141 | u32 tmp; |
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142 | |||
143 | /* program the speaker allocation */ |
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144 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
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145 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
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146 | /* set DP mode */ |
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147 | tmp |= DP_CONNECTION; |
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148 | if (sad_count) |
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149 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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150 | else |
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151 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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152 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
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5078 | serge | 153 | } |
154 | |||
6104 | serge | 155 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
156 | struct cea_sad *sads, int sad_count) |
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2997 | Serge | 157 | { |
6104 | serge | 158 | int i; |
3764 | Serge | 159 | struct radeon_device *rdev = encoder->dev->dev_private; |
160 | static const u16 eld_reg_to_type[][2] = { |
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161 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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165 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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166 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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167 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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168 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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169 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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173 | }; |
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174 | |||
175 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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176 | u32 value = 0; |
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5078 | serge | 177 | u8 stereo_freqs = 0; |
178 | int max_channels = -1; |
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3764 | Serge | 179 | int j; |
180 | |||
181 | for (j = 0; j < sad_count; j++) { |
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182 | struct cea_sad *sad = &sads[j]; |
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183 | |||
184 | if (sad->format == eld_reg_to_type[i][1]) { |
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5078 | serge | 185 | if (sad->channels > max_channels) { |
6104 | serge | 186 | value = MAX_CHANNELS(sad->channels) | |
187 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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188 | SUPPORTED_FREQUENCIES(sad->freq); |
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5078 | serge | 189 | max_channels = sad->channels; |
190 | } |
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191 | |||
3764 | Serge | 192 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
5078 | serge | 193 | stereo_freqs |= sad->freq; |
194 | else |
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6104 | serge | 195 | break; |
3764 | Serge | 196 | } |
197 | } |
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5078 | serge | 198 | |
199 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
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200 | |||
6104 | serge | 201 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
3764 | Serge | 202 | } |
2997 | Serge | 203 | } |
204 | |||
205 | /* |
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6104 | serge | 206 | * build a AVI Info Frame |
2997 | Serge | 207 | */ |
6104 | serge | 208 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
209 | unsigned char *buffer, size_t size) |
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2997 | Serge | 210 | { |
3764 | Serge | 211 | uint8_t *frame = buffer + 3; |
2997 | Serge | 212 | |
213 | WREG32(AFMT_AVI_INFO0 + offset, |
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214 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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215 | WREG32(AFMT_AVI_INFO1 + offset, |
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216 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
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217 | WREG32(AFMT_AVI_INFO2 + offset, |
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218 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
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219 | WREG32(AFMT_AVI_INFO3 + offset, |
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6104 | serge | 220 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
221 | |||
222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
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223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
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224 | ~HDMI_AVI_INFO_LINE_MASK); |
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2997 | Serge | 225 | } |
226 | |||
6104 | serge | 227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
228 | struct radeon_crtc *crtc, unsigned int clock) |
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5078 | serge | 229 | { |
6104 | serge | 230 | unsigned int max_ratio = clock / 24000; |
5078 | serge | 231 | u32 dto_phase; |
232 | u32 wallclock_ratio; |
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6104 | serge | 233 | u32 value; |
5078 | serge | 234 | |
6104 | serge | 235 | if (max_ratio >= 8) { |
236 | dto_phase = 192 * 1000; |
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237 | wallclock_ratio = 3; |
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238 | } else if (max_ratio >= 4) { |
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239 | dto_phase = 96 * 1000; |
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240 | wallclock_ratio = 2; |
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241 | } else if (max_ratio >= 2) { |
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242 | dto_phase = 48 * 1000; |
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243 | wallclock_ratio = 1; |
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244 | } else { |
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5078 | serge | 245 | dto_phase = 24 * 1000; |
6104 | serge | 246 | wallclock_ratio = 0; |
5078 | serge | 247 | } |
248 | |||
6104 | serge | 249 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
250 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
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251 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
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252 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); |
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253 | |||
254 | /* Two dtos; generally use dto0 for HDMI */ |
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255 | value = 0; |
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256 | |||
257 | if (crtc) |
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258 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
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259 | |||
260 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
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261 | |||
5078 | serge | 262 | /* Express [24MHz / target pixel clock] as an exact rational |
263 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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264 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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265 | */ |
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266 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
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6104 | serge | 267 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
5078 | serge | 268 | } |
269 | |||
6104 | serge | 270 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
271 | struct radeon_crtc *crtc, unsigned int clock) |
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2997 | Serge | 272 | { |
6104 | serge | 273 | u32 value; |
2997 | Serge | 274 | |
6104 | serge | 275 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
276 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
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277 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); |
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5078 | serge | 278 | |
6104 | serge | 279 | /* Two dtos; generally use dto1 for DP */ |
280 | value = 0; |
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281 | value |= DCCG_AUDIO_DTO_SEL; |
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2997 | Serge | 282 | |
6104 | serge | 283 | if (crtc) |
284 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
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2997 | Serge | 285 | |
6104 | serge | 286 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
5078 | serge | 287 | |
6104 | serge | 288 | /* Express [24MHz / target pixel clock] as an exact rational |
289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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291 | */ |
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292 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
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293 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
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294 | } |
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5078 | serge | 295 | |
6104 | serge | 296 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
297 | { |
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298 | struct drm_device *dev = encoder->dev; |
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299 | struct radeon_device *rdev = dev->dev_private; |
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300 | |||
2997 | Serge | 301 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
6104 | serge | 302 | HDMI_NULL_SEND | /* send null packets when required */ |
303 | HDMI_GC_SEND | /* send general control packets */ |
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304 | HDMI_GC_CONT); /* send general control packets every frame */ |
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305 | } |
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2997 | Serge | 306 | |
6104 | serge | 307 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) |
308 | { |
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309 | struct drm_device *dev = encoder->dev; |
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310 | struct radeon_device *rdev = dev->dev_private; |
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311 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
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312 | uint32_t val; |
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2997 | Serge | 313 | |
5078 | serge | 314 | val = RREG32(HDMI_CONTROL + offset); |
315 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
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316 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
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2997 | Serge | 317 | |
5078 | serge | 318 | switch (bpc) { |
319 | case 0: |
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320 | case 6: |
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321 | case 8: |
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322 | case 16: |
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323 | default: |
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324 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
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325 | connector->name, bpc); |
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326 | break; |
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327 | case 10: |
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328 | val |= HDMI_DEEP_COLOR_ENABLE; |
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329 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
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330 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
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331 | connector->name); |
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332 | break; |
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333 | case 12: |
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334 | val |= HDMI_DEEP_COLOR_ENABLE; |
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335 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
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336 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
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337 | connector->name); |
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338 | break; |
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339 | } |
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2997 | Serge | 340 | |
5078 | serge | 341 | WREG32(HDMI_CONTROL + offset, val); |
6104 | serge | 342 | } |
2997 | Serge | 343 | |
6104 | serge | 344 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
345 | { |
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346 | struct drm_device *dev = encoder->dev; |
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347 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 348 | |
349 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
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6104 | serge | 350 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
2997 | Serge | 351 | |
5078 | serge | 352 | WREG32(AFMT_60958_0 + offset, |
6104 | serge | 353 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
5078 | serge | 354 | |
355 | WREG32(AFMT_60958_1 + offset, |
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6104 | serge | 356 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
5078 | serge | 357 | |
358 | WREG32(AFMT_60958_2 + offset, |
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6104 | serge | 359 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
360 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
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361 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
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362 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
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363 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
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364 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
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5078 | serge | 365 | |
366 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
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6104 | serge | 367 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
5078 | serge | 368 | |
6104 | serge | 369 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
370 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
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371 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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5078 | serge | 372 | |
6104 | serge | 373 | /* allow 60958 channel status and send audio packets fields to be updated */ |
374 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
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375 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
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376 | } |
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5078 | serge | 377 | |
2997 | Serge | 378 | |
6104 | serge | 379 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
380 | { |
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381 | struct drm_device *dev = encoder->dev; |
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382 | struct radeon_device *rdev = dev->dev_private; |
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3764 | Serge | 383 | |
6104 | serge | 384 | if (mute) |
385 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); |
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5078 | serge | 386 | else |
6104 | serge | 387 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); |
2997 | Serge | 388 | } |
5078 | serge | 389 | |
390 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
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391 | { |
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5271 | serge | 392 | struct drm_device *dev = encoder->dev; |
393 | struct radeon_device *rdev = dev->dev_private; |
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5078 | serge | 394 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
395 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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396 | |||
397 | if (!dig || !dig->afmt) |
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398 | return; |
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399 | |||
6104 | serge | 400 | if (enable) { |
401 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
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5078 | serge | 402 | |
6104 | serge | 403 | if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
404 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
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405 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
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406 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ |
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407 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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408 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
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409 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
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410 | AFMT_AUDIO_SAMPLE_SEND); |
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411 | } else { |
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412 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
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413 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
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414 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
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415 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
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416 | ~AFMT_AUDIO_SAMPLE_SEND); |
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417 | } |
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418 | } else { |
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419 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
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420 | ~AFMT_AUDIO_SAMPLE_SEND); |
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421 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
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5271 | serge | 422 | } |
423 | |||
5078 | serge | 424 | dig->afmt->enabled = enable; |
425 | |||
426 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
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427 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); |
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428 | } |
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6104 | serge | 429 | |
430 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
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431 | { |
||
432 | struct drm_device *dev = encoder->dev; |
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433 | struct radeon_device *rdev = dev->dev_private; |
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434 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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435 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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436 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
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437 | |||
438 | if (!dig || !dig->afmt) |
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439 | return; |
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440 | |||
441 | if (enable && connector && |
||
442 | drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
||
443 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
||
444 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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445 | struct radeon_connector_atom_dig *dig_connector; |
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446 | uint32_t val; |
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447 | |||
448 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
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449 | AFMT_AUDIO_SAMPLE_SEND); |
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450 | |||
451 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
||
452 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
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453 | |||
454 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
||
455 | dig_connector = radeon_connector->con_priv; |
||
456 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
||
457 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
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458 | |||
459 | if (dig_connector->dp_clock == 162000) |
||
460 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); |
||
461 | else |
||
462 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
||
463 | |||
464 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
||
465 | } |
||
466 | |||
467 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
||
468 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
||
469 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
||
470 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
||
471 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
||
472 | } else { |
||
473 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
||
474 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
||
475 | ~AFMT_AUDIO_SAMPLE_SEND); |
||
476 | } |
||
477 | |||
478 | dig->afmt->enabled = enable; |
||
479 | }><>><>><>><>><>><>><>><>><>><>><>>> |