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2997 | Serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | * Rafał Miłecki |
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26 | */ |
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3764 | Serge | 27 | #include |
2997 | Serge | 28 | #include |
29 | #include |
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30 | #include "radeon.h" |
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31 | #include "radeon_asic.h" |
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32 | #include "evergreend.h" |
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33 | #include "atom.h" |
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34 | |||
35 | /* |
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36 | * update the N and CTS parameters for a given pixel clock rate |
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37 | */ |
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38 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
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39 | { |
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40 | struct drm_device *dev = encoder->dev; |
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41 | struct radeon_device *rdev = dev->dev_private; |
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42 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
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43 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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44 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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45 | uint32_t offset = dig->afmt->offset; |
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46 | |||
47 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); |
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48 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); |
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49 | |||
50 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); |
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51 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); |
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52 | |||
53 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); |
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54 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); |
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55 | } |
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56 | |||
3764 | Serge | 57 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
2997 | Serge | 58 | { |
3764 | Serge | 59 | struct radeon_device *rdev = encoder->dev->dev_private; |
60 | struct drm_connector *connector; |
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61 | struct radeon_connector *radeon_connector = NULL; |
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62 | struct cea_sad *sads; |
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63 | int i, sad_count; |
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64 | |||
65 | static const u16 eld_reg_to_type[][2] = { |
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66 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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67 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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68 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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69 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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70 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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71 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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72 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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73 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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74 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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75 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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76 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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77 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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78 | }; |
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79 | |||
80 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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81 | if (connector->encoder == encoder) |
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82 | radeon_connector = to_radeon_connector(connector); |
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83 | } |
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84 | |||
85 | if (!radeon_connector) { |
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86 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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87 | return; |
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88 | } |
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89 | |||
90 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); |
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91 | if (sad_count < 0) { |
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92 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
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93 | return; |
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94 | } |
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95 | BUG_ON(!sads); |
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96 | |||
97 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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98 | u32 value = 0; |
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99 | int j; |
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100 | |||
101 | for (j = 0; j < sad_count; j++) { |
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102 | struct cea_sad *sad = &sads[j]; |
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103 | |||
104 | if (sad->format == eld_reg_to_type[i][1]) { |
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105 | value = MAX_CHANNELS(sad->channels) | |
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106 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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107 | SUPPORTED_FREQUENCIES(sad->freq); |
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108 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
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109 | value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); |
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110 | break; |
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111 | } |
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112 | } |
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113 | WREG32(eld_reg_to_type[i][0], value); |
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114 | } |
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115 | |||
116 | kfree(sads); |
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2997 | Serge | 117 | } |
118 | |||
119 | /* |
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120 | * build a HDMI Video Info Frame |
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121 | */ |
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3764 | Serge | 122 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
123 | void *buffer, size_t size) |
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2997 | Serge | 124 | { |
125 | struct drm_device *dev = encoder->dev; |
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126 | struct radeon_device *rdev = dev->dev_private; |
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127 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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128 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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129 | uint32_t offset = dig->afmt->offset; |
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3764 | Serge | 130 | uint8_t *frame = buffer + 3; |
2997 | Serge | 131 | |
132 | /* Our header values (type, version, length) should be alright, Intel |
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133 | * is using the same. Checksum function also seems to be OK, it works |
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134 | * fine for audio infoframe. However calculated value is always lower |
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135 | * by 2 in comparison to fglrx. It breaks displaying anything in case |
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136 | * of TVs that strictly check the checksum. Hack it manually here to |
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137 | * workaround this issue. */ |
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138 | frame[0x0] += 2; |
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139 | |||
140 | WREG32(AFMT_AVI_INFO0 + offset, |
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141 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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142 | WREG32(AFMT_AVI_INFO1 + offset, |
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143 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
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144 | WREG32(AFMT_AVI_INFO2 + offset, |
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145 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
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146 | WREG32(AFMT_AVI_INFO3 + offset, |
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147 | frame[0xC] | (frame[0xD] << 8)); |
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148 | } |
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149 | |||
150 | /* |
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151 | * update the info frames with the data from the current display mode |
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152 | */ |
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153 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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154 | { |
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155 | struct drm_device *dev = encoder->dev; |
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156 | struct radeon_device *rdev = dev->dev_private; |
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157 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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158 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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3764 | Serge | 159 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
160 | struct hdmi_avi_infoframe frame; |
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2997 | Serge | 161 | uint32_t offset; |
3764 | Serge | 162 | ssize_t err; |
2997 | Serge | 163 | |
164 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
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165 | if (!dig->afmt->enabled) |
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166 | return; |
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167 | offset = dig->afmt->offset; |
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168 | |||
169 | // r600_audio_set_clock(encoder, mode->clock); |
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170 | |||
171 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
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172 | HDMI_NULL_SEND); /* send null packets when required */ |
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173 | |||
174 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
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175 | |||
176 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
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177 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
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178 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
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179 | |||
180 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
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181 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ |
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182 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ |
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183 | |||
184 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
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185 | HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ |
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186 | HDMI_ACR_SOURCE); /* select SW CTS value */ |
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187 | |||
188 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
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189 | HDMI_NULL_SEND | /* send null packets when required */ |
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190 | HDMI_GC_SEND | /* send general control packets */ |
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191 | HDMI_GC_CONT); /* send general control packets every frame */ |
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192 | |||
193 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, |
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194 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
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195 | HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ |
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196 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
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197 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
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198 | |||
199 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
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200 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
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201 | |||
202 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
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203 | HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ |
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204 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
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205 | |||
206 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ |
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207 | |||
3764 | Serge | 208 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
209 | if (err < 0) { |
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210 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
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211 | return; |
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212 | } |
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2997 | Serge | 213 | |
3764 | Serge | 214 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
215 | if (err < 0) { |
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216 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
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217 | return; |
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218 | } |
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219 | |||
220 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
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2997 | Serge | 221 | evergreen_hdmi_update_ACR(encoder, mode->clock); |
222 | |||
223 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
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224 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
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225 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
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226 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
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227 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
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228 | }>>><>><>><>><>><>><>><>><>><>><>>>> |