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1986 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Alex Deucher |
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25 | */ |
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26 | |||
2997 | Serge | 27 | #include |
1986 | serge | 28 | #include |
29 | #include |
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30 | |||
31 | /* |
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32 | * evergreen cards need to use the 3D engine to blit data which requires |
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33 | * quite a bit of hw state setup. Rather than pull the whole 3D driver |
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34 | * (which normally generates the 3D state) into the DRM, we opt to use |
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35 | * statically generated state tables. The regsiter state and shaders |
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36 | * were hand generated to support blitting functionality. See the 3D |
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37 | * driver or documentation for descriptions of the registers and |
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38 | * shader instructions. |
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39 | */ |
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40 | |||
41 | const u32 evergreen_default_state[] = |
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42 | { |
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43 | 0xc0016900, |
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44 | 0x0000023b, |
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45 | 0x00000000, /* SQ_LDS_ALLOC_PS */ |
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46 | |||
47 | 0xc0066900, |
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48 | 0x00000240, |
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49 | 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ |
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50 | 0x00000000, |
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51 | 0x00000000, |
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52 | 0x00000000, |
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53 | 0x00000000, |
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54 | 0x00000000, |
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55 | |||
56 | 0xc0046900, |
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57 | 0x00000247, |
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58 | 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ |
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59 | 0x00000000, |
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60 | 0x00000000, |
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61 | 0x00000000, |
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62 | |||
63 | 0xc0026900, |
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64 | 0x00000010, |
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65 | 0x00000000, /* DB_Z_INFO */ |
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66 | 0x00000000, /* DB_STENCIL_INFO */ |
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67 | |||
68 | 0xc0016900, |
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69 | 0x00000200, |
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70 | 0x00000000, /* DB_DEPTH_CONTROL */ |
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71 | |||
72 | 0xc0066900, |
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73 | 0x00000000, |
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74 | 0x00000060, /* DB_RENDER_CONTROL */ |
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75 | 0x00000000, /* DB_COUNT_CONTROL */ |
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76 | 0x00000000, /* DB_DEPTH_VIEW */ |
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77 | 0x0000002a, /* DB_RENDER_OVERRIDE */ |
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78 | 0x00000000, /* DB_RENDER_OVERRIDE2 */ |
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79 | 0x00000000, /* DB_HTILE_DATA_BASE */ |
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80 | |||
81 | 0xc0026900, |
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82 | 0x0000000a, |
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83 | 0x00000000, /* DB_STENCIL_CLEAR */ |
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84 | 0x00000000, /* DB_DEPTH_CLEAR */ |
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85 | |||
86 | 0xc0016900, |
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87 | 0x000002dc, |
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88 | 0x0000aa00, /* DB_ALPHA_TO_MASK */ |
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89 | |||
90 | 0xc0016900, |
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91 | 0x00000080, |
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92 | 0x00000000, /* PA_SC_WINDOW_OFFSET */ |
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93 | |||
94 | 0xc00d6900, |
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95 | 0x00000083, |
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96 | 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ |
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97 | 0x00000000, /* PA_SC_CLIPRECT_0_TL */ |
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98 | 0x20002000, /* PA_SC_CLIPRECT_0_BR */ |
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99 | 0x00000000, |
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100 | 0x20002000, |
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101 | 0x00000000, |
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102 | 0x20002000, |
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103 | 0x00000000, |
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104 | 0x20002000, |
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105 | 0xaaaaaaaa, /* PA_SC_EDGERULE */ |
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106 | 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ |
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107 | 0x0000000f, /* CB_TARGET_MASK */ |
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108 | 0x0000000f, /* CB_SHADER_MASK */ |
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109 | |||
110 | 0xc0226900, |
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111 | 0x00000094, |
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112 | 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ |
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113 | 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ |
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114 | 0x80000000, |
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115 | 0x20002000, |
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116 | 0x80000000, |
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117 | 0x20002000, |
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118 | 0x80000000, |
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119 | 0x20002000, |
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120 | 0x80000000, |
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121 | 0x20002000, |
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122 | 0x80000000, |
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123 | 0x20002000, |
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124 | 0x80000000, |
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125 | 0x20002000, |
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126 | 0x80000000, |
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127 | 0x20002000, |
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128 | 0x80000000, |
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129 | 0x20002000, |
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130 | 0x80000000, |
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131 | 0x20002000, |
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132 | 0x80000000, |
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133 | 0x20002000, |
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134 | 0x80000000, |
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135 | 0x20002000, |
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136 | 0x80000000, |
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137 | 0x20002000, |
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138 | 0x80000000, |
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139 | 0x20002000, |
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140 | 0x80000000, |
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141 | 0x20002000, |
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142 | 0x80000000, |
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143 | 0x20002000, |
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144 | 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ |
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145 | 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ |
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146 | |||
147 | 0xc0016900, |
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148 | 0x000000d4, |
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149 | 0x00000000, /* SX_MISC */ |
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150 | |||
151 | 0xc0026900, |
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152 | 0x00000292, |
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153 | 0x00000000, /* PA_SC_MODE_CNTL_0 */ |
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154 | 0x00000000, /* PA_SC_MODE_CNTL_1 */ |
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155 | |||
156 | 0xc0106900, |
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157 | 0x00000300, |
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158 | 0x00000000, /* PA_SC_LINE_CNTL */ |
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159 | 0x00000000, /* PA_SC_AA_CONFIG */ |
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160 | 0x00000005, /* PA_SU_VTX_CNTL */ |
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161 | 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ |
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162 | 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ |
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163 | 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ |
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164 | 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ |
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165 | 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */ |
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166 | 0x00000000, /* */ |
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167 | 0x00000000, /* */ |
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168 | 0x00000000, /* */ |
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169 | 0x00000000, /* */ |
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170 | 0x00000000, /* */ |
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171 | 0x00000000, /* */ |
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172 | 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */ |
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173 | 0xffffffff, /* PA_SC_AA_MASK */ |
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174 | |||
175 | 0xc00d6900, |
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176 | 0x00000202, |
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177 | 0x00cc0010, /* CB_COLOR_CONTROL */ |
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178 | 0x00000210, /* DB_SHADER_CONTROL */ |
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179 | 0x00010000, /* PA_CL_CLIP_CNTL */ |
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180 | 0x00000004, /* PA_SU_SC_MODE_CNTL */ |
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181 | 0x00000100, /* PA_CL_VTE_CNTL */ |
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182 | 0x00000000, /* PA_CL_VS_OUT_CNTL */ |
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183 | 0x00000000, /* PA_CL_NANINF_CNTL */ |
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184 | 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ |
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185 | 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ |
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186 | 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ |
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187 | 0x00000000, /* */ |
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188 | 0x00000000, /* */ |
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189 | 0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */ |
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190 | |||
191 | 0xc0066900, |
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192 | 0x000002de, |
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193 | 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ |
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194 | 0x00000000, /* */ |
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195 | 0x00000000, /* */ |
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196 | 0x00000000, /* */ |
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197 | 0x00000000, /* */ |
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198 | 0x00000000, /* */ |
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199 | |||
200 | 0xc0016900, |
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201 | 0x00000229, |
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202 | 0x00000000, /* SQ_PGM_START_FS */ |
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203 | |||
204 | 0xc0016900, |
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205 | 0x0000022a, |
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206 | 0x00000000, /* SQ_PGM_RESOURCES_FS */ |
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207 | |||
208 | 0xc0096900, |
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209 | 0x00000100, |
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210 | 0x00ffffff, /* VGT_MAX_VTX_INDX */ |
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211 | 0x00000000, /* */ |
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212 | 0x00000000, /* */ |
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213 | 0x00000000, /* */ |
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214 | 0x00000000, /* SX_ALPHA_TEST_CONTROL */ |
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215 | 0x00000000, /* CB_BLEND_RED */ |
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216 | 0x00000000, /* CB_BLEND_GREEN */ |
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217 | 0x00000000, /* CB_BLEND_BLUE */ |
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218 | 0x00000000, /* CB_BLEND_ALPHA */ |
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219 | |||
220 | 0xc0026900, |
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221 | 0x000002a8, |
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222 | 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ |
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223 | 0x00000000, /* */ |
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224 | |||
225 | 0xc0026900, |
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226 | 0x000002ad, |
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227 | 0x00000000, /* VGT_REUSE_OFF */ |
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228 | 0x00000000, /* */ |
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229 | |||
230 | 0xc0116900, |
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231 | 0x00000280, |
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232 | 0x00000000, /* PA_SU_POINT_SIZE */ |
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233 | 0x00000000, /* PA_SU_POINT_MINMAX */ |
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234 | 0x00000008, /* PA_SU_LINE_CNTL */ |
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235 | 0x00000000, /* PA_SC_LINE_STIPPLE */ |
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236 | 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ |
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237 | 0x00000000, /* VGT_HOS_CNTL */ |
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238 | 0x00000000, /* */ |
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239 | 0x00000000, /* */ |
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240 | 0x00000000, /* */ |
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241 | 0x00000000, /* */ |
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242 | 0x00000000, /* */ |
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243 | 0x00000000, /* */ |
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244 | 0x00000000, /* */ |
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245 | 0x00000000, /* */ |
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246 | 0x00000000, /* */ |
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247 | 0x00000000, /* */ |
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248 | 0x00000000, /* VGT_GS_MODE */ |
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249 | |||
250 | 0xc0016900, |
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251 | 0x000002a1, |
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252 | 0x00000000, /* VGT_PRIMITIVEID_EN */ |
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253 | |||
254 | 0xc0016900, |
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255 | 0x000002a5, |
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256 | 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ |
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257 | |||
258 | 0xc0016900, |
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259 | 0x000002d5, |
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260 | 0x00000000, /* VGT_SHADER_STAGES_EN */ |
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261 | |||
262 | 0xc0026900, |
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263 | 0x000002e5, |
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264 | 0x00000000, /* VGT_STRMOUT_CONFIG */ |
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265 | 0x00000000, /* */ |
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266 | |||
267 | 0xc0016900, |
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268 | 0x000001e0, |
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269 | 0x00000000, /* CB_BLEND0_CONTROL */ |
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270 | |||
271 | 0xc0016900, |
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272 | 0x000001b1, |
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273 | 0x00000000, /* SPI_VS_OUT_CONFIG */ |
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274 | |||
275 | 0xc0016900, |
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276 | 0x00000187, |
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277 | 0x00000000, /* SPI_VS_OUT_ID_0 */ |
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278 | |||
279 | 0xc0016900, |
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280 | 0x00000191, |
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281 | 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ |
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282 | |||
283 | 0xc00b6900, |
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284 | 0x000001b3, |
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285 | 0x20000001, /* SPI_PS_IN_CONTROL_0 */ |
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286 | 0x00000000, /* SPI_PS_IN_CONTROL_1 */ |
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287 | 0x00000000, /* SPI_INTERP_CONTROL_0 */ |
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288 | 0x00000000, /* SPI_INPUT_Z */ |
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289 | 0x00000000, /* SPI_FOG_CNTL */ |
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290 | 0x00100000, /* SPI_BARYC_CNTL */ |
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291 | 0x00000000, /* SPI_PS_IN_CONTROL_2 */ |
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292 | 0x00000000, /* */ |
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293 | 0x00000000, /* */ |
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294 | 0x00000000, /* */ |
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295 | 0x00000000, /* */ |
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296 | |||
297 | 0xc0026900, |
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298 | 0x00000316, |
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299 | 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
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300 | 0x00000010, /* */ |
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301 | }; |
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302 | |||
303 | const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state); |