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1430 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | //#include |
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1963 | serge | 26 | #include |
1430 | serge | 27 | #include "drmP.h" |
28 | #include "radeon.h" |
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1963 | serge | 29 | #include "radeon_asic.h" |
1430 | serge | 30 | #include "radeon_drm.h" |
1963 | serge | 31 | #include "evergreend.h" |
1430 | serge | 32 | #include "atom.h" |
33 | #include "avivod.h" |
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34 | #include "evergreen_reg.h" |
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35 | |||
1963 | serge | 36 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
37 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
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38 | |||
1430 | serge | 39 | static void evergreen_gpu_init(struct radeon_device *rdev); |
40 | void evergreen_fini(struct radeon_device *rdev); |
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41 | |||
42 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
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43 | { |
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44 | bool connected = false; |
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1963 | serge | 45 | |
46 | switch (hpd) { |
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47 | case RADEON_HPD_1: |
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48 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) |
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49 | connected = true; |
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50 | break; |
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51 | case RADEON_HPD_2: |
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52 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) |
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53 | connected = true; |
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54 | break; |
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55 | case RADEON_HPD_3: |
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56 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) |
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57 | connected = true; |
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58 | break; |
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59 | case RADEON_HPD_4: |
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60 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) |
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61 | connected = true; |
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62 | break; |
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63 | case RADEON_HPD_5: |
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64 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) |
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65 | connected = true; |
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66 | break; |
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67 | case RADEON_HPD_6: |
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68 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) |
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69 | connected = true; |
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70 | break; |
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71 | default: |
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72 | break; |
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73 | } |
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74 | |||
1430 | serge | 75 | return connected; |
76 | } |
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77 | |||
78 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, |
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79 | enum radeon_hpd_id hpd) |
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80 | { |
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1963 | serge | 81 | u32 tmp; |
82 | bool connected = evergreen_hpd_sense(rdev, hpd); |
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83 | |||
84 | switch (hpd) { |
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85 | case RADEON_HPD_1: |
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86 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
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87 | if (connected) |
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88 | tmp &= ~DC_HPDx_INT_POLARITY; |
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89 | else |
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90 | tmp |= DC_HPDx_INT_POLARITY; |
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91 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
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92 | break; |
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93 | case RADEON_HPD_2: |
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94 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
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95 | if (connected) |
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96 | tmp &= ~DC_HPDx_INT_POLARITY; |
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97 | else |
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98 | tmp |= DC_HPDx_INT_POLARITY; |
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99 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
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100 | break; |
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101 | case RADEON_HPD_3: |
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102 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
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103 | if (connected) |
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104 | tmp &= ~DC_HPDx_INT_POLARITY; |
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105 | else |
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106 | tmp |= DC_HPDx_INT_POLARITY; |
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107 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
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108 | break; |
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109 | case RADEON_HPD_4: |
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110 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
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111 | if (connected) |
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112 | tmp &= ~DC_HPDx_INT_POLARITY; |
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113 | else |
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114 | tmp |= DC_HPDx_INT_POLARITY; |
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115 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
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116 | break; |
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117 | case RADEON_HPD_5: |
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118 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
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119 | if (connected) |
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120 | tmp &= ~DC_HPDx_INT_POLARITY; |
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121 | else |
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122 | tmp |= DC_HPDx_INT_POLARITY; |
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123 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
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124 | break; |
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125 | case RADEON_HPD_6: |
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126 | tmp = RREG32(DC_HPD6_INT_CONTROL); |
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127 | if (connected) |
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128 | tmp &= ~DC_HPDx_INT_POLARITY; |
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129 | else |
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130 | tmp |= DC_HPDx_INT_POLARITY; |
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131 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
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132 | break; |
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133 | default: |
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134 | break; |
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135 | } |
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1430 | serge | 136 | } |
137 | |||
1963 | serge | 138 | #if 0 |
1430 | serge | 139 | void evergreen_hpd_init(struct radeon_device *rdev) |
140 | { |
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1963 | serge | 141 | struct drm_device *dev = rdev->ddev; |
142 | struct drm_connector *connector; |
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143 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | |
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144 | DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; |
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145 | |||
146 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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147 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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148 | switch (radeon_connector->hpd.hpd) { |
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149 | case RADEON_HPD_1: |
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150 | WREG32(DC_HPD1_CONTROL, tmp); |
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151 | rdev->irq.hpd[0] = true; |
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152 | break; |
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153 | case RADEON_HPD_2: |
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154 | WREG32(DC_HPD2_CONTROL, tmp); |
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155 | rdev->irq.hpd[1] = true; |
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156 | break; |
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157 | case RADEON_HPD_3: |
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158 | WREG32(DC_HPD3_CONTROL, tmp); |
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159 | rdev->irq.hpd[2] = true; |
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160 | break; |
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161 | case RADEON_HPD_4: |
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162 | WREG32(DC_HPD4_CONTROL, tmp); |
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163 | rdev->irq.hpd[3] = true; |
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164 | break; |
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165 | case RADEON_HPD_5: |
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166 | WREG32(DC_HPD5_CONTROL, tmp); |
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167 | rdev->irq.hpd[4] = true; |
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168 | break; |
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169 | case RADEON_HPD_6: |
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170 | WREG32(DC_HPD6_CONTROL, tmp); |
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171 | rdev->irq.hpd[5] = true; |
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172 | break; |
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173 | default: |
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174 | break; |
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175 | } |
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176 | } |
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177 | if (rdev->irq.installed) |
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178 | evergreen_irq_set(rdev); |
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1430 | serge | 179 | } |
180 | |||
1963 | serge | 181 | void evergreen_hpd_fini(struct radeon_device *rdev) |
182 | { |
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183 | struct drm_device *dev = rdev->ddev; |
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184 | struct drm_connector *connector; |
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1430 | serge | 185 | |
1963 | serge | 186 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
187 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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188 | switch (radeon_connector->hpd.hpd) { |
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189 | case RADEON_HPD_1: |
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190 | WREG32(DC_HPD1_CONTROL, 0); |
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191 | rdev->irq.hpd[0] = false; |
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192 | break; |
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193 | case RADEON_HPD_2: |
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194 | WREG32(DC_HPD2_CONTROL, 0); |
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195 | rdev->irq.hpd[1] = false; |
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196 | break; |
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197 | case RADEON_HPD_3: |
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198 | WREG32(DC_HPD3_CONTROL, 0); |
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199 | rdev->irq.hpd[2] = false; |
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200 | break; |
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201 | case RADEON_HPD_4: |
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202 | WREG32(DC_HPD4_CONTROL, 0); |
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203 | rdev->irq.hpd[3] = false; |
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204 | break; |
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205 | case RADEON_HPD_5: |
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206 | WREG32(DC_HPD5_CONTROL, 0); |
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207 | rdev->irq.hpd[4] = false; |
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208 | break; |
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209 | case RADEON_HPD_6: |
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210 | WREG32(DC_HPD6_CONTROL, 0); |
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211 | rdev->irq.hpd[5] = false; |
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212 | break; |
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213 | default: |
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214 | break; |
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215 | } |
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216 | } |
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1430 | serge | 217 | } |
218 | |||
1963 | serge | 219 | #endif |
220 | |||
221 | |||
222 | void evergreen_bandwidth_update(struct radeon_device *rdev) |
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1430 | serge | 223 | { |
224 | /* XXX */ |
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225 | } |
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226 | |||
1963 | serge | 227 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev) |
1430 | serge | 228 | { |
229 | unsigned i; |
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230 | u32 tmp; |
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231 | |||
232 | for (i = 0; i < rdev->usec_timeout; i++) { |
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233 | /* read MC_STATUS */ |
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234 | tmp = RREG32(SRBM_STATUS) & 0x1F00; |
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235 | if (!tmp) |
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236 | return 0; |
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237 | udelay(1); |
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238 | } |
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239 | return -1; |
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240 | } |
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241 | |||
242 | /* |
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243 | * GART |
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244 | */ |
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1963 | serge | 245 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) |
246 | { |
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247 | unsigned i; |
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248 | u32 tmp; |
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249 | |||
250 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
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251 | |||
252 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
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253 | for (i = 0; i < rdev->usec_timeout; i++) { |
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254 | /* read MC_STATUS */ |
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255 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); |
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256 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; |
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257 | if (tmp == 2) { |
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258 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); |
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259 | return; |
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260 | } |
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261 | if (tmp) { |
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262 | return; |
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263 | } |
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264 | udelay(1); |
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265 | } |
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266 | } |
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267 | |||
1430 | serge | 268 | int evergreen_pcie_gart_enable(struct radeon_device *rdev) |
269 | { |
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270 | u32 tmp; |
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1963 | serge | 271 | int r; |
1430 | serge | 272 | |
273 | if (rdev->gart.table.vram.robj == NULL) { |
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274 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
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275 | return -EINVAL; |
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276 | } |
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277 | r = radeon_gart_table_vram_pin(rdev); |
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278 | if (r) |
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279 | return r; |
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280 | radeon_gart_restore(rdev); |
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281 | /* Setup L2 cache */ |
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282 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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283 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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284 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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285 | WREG32(VM_L2_CNTL2, 0); |
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286 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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287 | /* Setup TLB control */ |
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288 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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289 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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290 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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291 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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1963 | serge | 292 | if (rdev->flags & RADEON_IS_IGP) { |
293 | WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); |
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294 | WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); |
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295 | WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); |
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296 | } else { |
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1430 | serge | 297 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
298 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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299 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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1963 | serge | 300 | } |
1430 | serge | 301 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
302 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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303 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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304 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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305 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
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306 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
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307 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
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308 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
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309 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
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310 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
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311 | (u32)(rdev->dummy_page.addr >> 12)); |
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1963 | serge | 312 | WREG32(VM_CONTEXT1_CNTL, 0); |
1430 | serge | 313 | |
1963 | serge | 314 | evergreen_pcie_gart_tlb_flush(rdev); |
1430 | serge | 315 | rdev->gart.ready = true; |
316 | return 0; |
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317 | } |
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318 | |||
319 | void evergreen_pcie_gart_disable(struct radeon_device *rdev) |
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320 | { |
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321 | u32 tmp; |
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1963 | serge | 322 | int r; |
1430 | serge | 323 | |
324 | /* Disable all tables */ |
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1963 | serge | 325 | WREG32(VM_CONTEXT0_CNTL, 0); |
326 | WREG32(VM_CONTEXT1_CNTL, 0); |
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1430 | serge | 327 | |
328 | /* Setup L2 cache */ |
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329 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
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330 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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331 | WREG32(VM_L2_CNTL2, 0); |
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332 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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333 | /* Setup TLB control */ |
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334 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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335 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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336 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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337 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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338 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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339 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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340 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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341 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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342 | if (rdev->gart.table.vram.robj) { |
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343 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
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344 | if (likely(r == 0)) { |
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345 | radeon_bo_kunmap(rdev->gart.table.vram.robj); |
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346 | radeon_bo_unpin(rdev->gart.table.vram.robj); |
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347 | radeon_bo_unreserve(rdev->gart.table.vram.robj); |
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348 | } |
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349 | } |
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350 | } |
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351 | |||
352 | void evergreen_pcie_gart_fini(struct radeon_device *rdev) |
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353 | { |
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354 | evergreen_pcie_gart_disable(rdev); |
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355 | radeon_gart_table_vram_free(rdev); |
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356 | radeon_gart_fini(rdev); |
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357 | } |
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358 | |||
359 | |||
360 | void evergreen_agp_enable(struct radeon_device *rdev) |
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361 | { |
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362 | u32 tmp; |
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363 | |||
364 | /* Setup L2 cache */ |
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365 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
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366 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
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367 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
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368 | WREG32(VM_L2_CNTL2, 0); |
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369 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
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370 | /* Setup TLB control */ |
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371 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
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372 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
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373 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
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374 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
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375 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
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376 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
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377 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
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378 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
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379 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
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380 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
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381 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
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1963 | serge | 382 | WREG32(VM_CONTEXT0_CNTL, 0); |
383 | WREG32(VM_CONTEXT1_CNTL, 0); |
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1430 | serge | 384 | } |
385 | |||
1963 | serge | 386 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
1430 | serge | 387 | { |
388 | save->vga_control[0] = RREG32(D1VGA_CONTROL); |
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389 | save->vga_control[1] = RREG32(D2VGA_CONTROL); |
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390 | save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); |
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391 | save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); |
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392 | save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); |
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393 | save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); |
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394 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
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395 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); |
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396 | save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); |
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397 | save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
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1963 | serge | 398 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 399 | save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); |
400 | save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
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401 | save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); |
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402 | save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
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1963 | serge | 403 | } |
1430 | serge | 404 | |
405 | /* Stop all video */ |
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406 | WREG32(VGA_RENDER_CONTROL, 0); |
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407 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); |
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408 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); |
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1963 | serge | 409 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 410 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
411 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); |
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412 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
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413 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); |
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1963 | serge | 414 | } |
1430 | serge | 415 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
416 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
||
1963 | serge | 417 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 418 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
419 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
||
420 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
||
421 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
||
1963 | serge | 422 | } |
1430 | serge | 423 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
424 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
||
1963 | serge | 425 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 426 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
427 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
||
428 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
||
429 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
||
1963 | serge | 430 | } |
1430 | serge | 431 | |
432 | WREG32(D1VGA_CONTROL, 0); |
||
433 | WREG32(D2VGA_CONTROL, 0); |
||
434 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
||
435 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
||
436 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
||
437 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
||
438 | } |
||
439 | |||
1963 | serge | 440 | void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) |
1430 | serge | 441 | { |
442 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, |
||
443 | upper_32_bits(rdev->mc.vram_start)); |
||
444 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, |
||
445 | upper_32_bits(rdev->mc.vram_start)); |
||
446 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, |
||
447 | (u32)rdev->mc.vram_start); |
||
448 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, |
||
449 | (u32)rdev->mc.vram_start); |
||
450 | |||
451 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, |
||
452 | upper_32_bits(rdev->mc.vram_start)); |
||
453 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, |
||
454 | upper_32_bits(rdev->mc.vram_start)); |
||
455 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, |
||
456 | (u32)rdev->mc.vram_start); |
||
457 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, |
||
458 | (u32)rdev->mc.vram_start); |
||
459 | |||
1963 | serge | 460 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 461 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, |
462 | upper_32_bits(rdev->mc.vram_start)); |
||
463 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, |
||
464 | upper_32_bits(rdev->mc.vram_start)); |
||
465 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, |
||
466 | (u32)rdev->mc.vram_start); |
||
467 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, |
||
468 | (u32)rdev->mc.vram_start); |
||
469 | |||
470 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, |
||
471 | upper_32_bits(rdev->mc.vram_start)); |
||
472 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, |
||
473 | upper_32_bits(rdev->mc.vram_start)); |
||
474 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, |
||
475 | (u32)rdev->mc.vram_start); |
||
476 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, |
||
477 | (u32)rdev->mc.vram_start); |
||
478 | |||
479 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, |
||
480 | upper_32_bits(rdev->mc.vram_start)); |
||
481 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, |
||
482 | upper_32_bits(rdev->mc.vram_start)); |
||
483 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, |
||
484 | (u32)rdev->mc.vram_start); |
||
485 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, |
||
486 | (u32)rdev->mc.vram_start); |
||
487 | |||
488 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, |
||
489 | upper_32_bits(rdev->mc.vram_start)); |
||
490 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, |
||
491 | upper_32_bits(rdev->mc.vram_start)); |
||
492 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, |
||
493 | (u32)rdev->mc.vram_start); |
||
494 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, |
||
495 | (u32)rdev->mc.vram_start); |
||
1963 | serge | 496 | } |
1430 | serge | 497 | |
498 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); |
||
499 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
||
500 | /* Unlock host access */ |
||
501 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); |
||
502 | mdelay(1); |
||
503 | /* Restore video state */ |
||
504 | WREG32(D1VGA_CONTROL, save->vga_control[0]); |
||
505 | WREG32(D2VGA_CONTROL, save->vga_control[1]); |
||
506 | WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); |
||
507 | WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); |
||
508 | WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); |
||
509 | WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); |
||
510 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); |
||
511 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); |
||
1963 | serge | 512 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 513 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
514 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); |
||
515 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
||
516 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); |
||
1963 | serge | 517 | } |
1430 | serge | 518 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); |
519 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); |
||
1963 | serge | 520 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 521 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); |
522 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); |
||
523 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); |
||
524 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); |
||
1963 | serge | 525 | } |
1430 | serge | 526 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
527 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
||
1963 | serge | 528 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1430 | serge | 529 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
530 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
||
531 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
||
532 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
||
1963 | serge | 533 | } |
1430 | serge | 534 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); |
535 | } |
||
536 | |||
1963 | serge | 537 | void evergreen_mc_program(struct radeon_device *rdev) |
1430 | serge | 538 | { |
539 | struct evergreen_mc_save save; |
||
540 | u32 tmp; |
||
541 | int i, j; |
||
542 | |||
543 | /* Initialize HDP */ |
||
544 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
||
545 | WREG32((0x2c14 + j), 0x00000000); |
||
546 | WREG32((0x2c18 + j), 0x00000000); |
||
547 | WREG32((0x2c1c + j), 0x00000000); |
||
548 | WREG32((0x2c20 + j), 0x00000000); |
||
549 | WREG32((0x2c24 + j), 0x00000000); |
||
550 | } |
||
551 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
||
552 | |||
553 | evergreen_mc_stop(rdev, &save); |
||
554 | if (evergreen_mc_wait_for_idle(rdev)) { |
||
555 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
556 | } |
||
557 | /* Lockout access through VGA aperture*/ |
||
558 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
||
559 | /* Update configuration */ |
||
560 | if (rdev->flags & RADEON_IS_AGP) { |
||
561 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
||
562 | /* VRAM before AGP */ |
||
563 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
564 | rdev->mc.vram_start >> 12); |
||
565 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
566 | rdev->mc.gtt_end >> 12); |
||
567 | } else { |
||
568 | /* VRAM after AGP */ |
||
569 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
570 | rdev->mc.gtt_start >> 12); |
||
571 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
572 | rdev->mc.vram_end >> 12); |
||
573 | } |
||
574 | } else { |
||
575 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
576 | rdev->mc.vram_start >> 12); |
||
577 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
578 | rdev->mc.vram_end >> 12); |
||
579 | } |
||
580 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
||
1963 | serge | 581 | if (rdev->flags & RADEON_IS_IGP) { |
582 | tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; |
||
583 | tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; |
||
584 | tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; |
||
585 | WREG32(MC_FUS_VM_FB_OFFSET, tmp); |
||
586 | } |
||
1430 | serge | 587 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
588 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
||
589 | WREG32(MC_VM_FB_LOCATION, tmp); |
||
590 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
||
1963 | serge | 591 | WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); |
592 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
||
1430 | serge | 593 | if (rdev->flags & RADEON_IS_AGP) { |
594 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
||
595 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
||
596 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
||
597 | } else { |
||
598 | WREG32(MC_VM_AGP_BASE, 0); |
||
599 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
||
600 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
||
601 | } |
||
602 | if (evergreen_mc_wait_for_idle(rdev)) { |
||
603 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
604 | } |
||
605 | evergreen_mc_resume(rdev, &save); |
||
606 | /* we need to own VRAM, so turn off the VGA renderer here |
||
607 | * to stop it overwriting our objects */ |
||
608 | rv515_vga_render_disable(rdev); |
||
609 | } |
||
610 | |||
611 | #if 0 |
||
612 | /* |
||
613 | * CP. |
||
614 | */ |
||
1963 | serge | 615 | |
616 | static int evergreen_cp_load_microcode(struct radeon_device *rdev) |
||
1430 | serge | 617 | { |
1963 | serge | 618 | const __be32 *fw_data; |
619 | int i; |
||
620 | |||
621 | if (!rdev->me_fw || !rdev->pfp_fw) |
||
622 | return -EINVAL; |
||
623 | |||
624 | r700_cp_stop(rdev); |
||
625 | WREG32(CP_RB_CNTL, |
||
626 | #ifdef __BIG_ENDIAN |
||
627 | BUF_SWAP_32BIT | |
||
628 | #endif |
||
629 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
||
630 | |||
631 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
||
632 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
633 | for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) |
||
634 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
||
635 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
636 | |||
637 | fw_data = (const __be32 *)rdev->me_fw->data; |
||
638 | WREG32(CP_ME_RAM_WADDR, 0); |
||
639 | for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) |
||
640 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
||
641 | |||
642 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
643 | WREG32(CP_ME_RAM_WADDR, 0); |
||
644 | WREG32(CP_ME_RAM_RADDR, 0); |
||
645 | return 0; |
||
1430 | serge | 646 | } |
647 | |||
1963 | serge | 648 | static int evergreen_cp_start(struct radeon_device *rdev) |
649 | { |
||
650 | int r, i; |
||
651 | uint32_t cp_me; |
||
1430 | serge | 652 | |
1963 | serge | 653 | r = radeon_ring_lock(rdev, 7); |
654 | if (r) { |
||
655 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
656 | return r; |
||
657 | } |
||
658 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
||
659 | radeon_ring_write(rdev, 0x1); |
||
660 | radeon_ring_write(rdev, 0x0); |
||
661 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); |
||
662 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
||
663 | radeon_ring_write(rdev, 0); |
||
664 | radeon_ring_write(rdev, 0); |
||
665 | radeon_ring_unlock_commit(rdev); |
||
666 | |||
667 | cp_me = 0xff; |
||
668 | WREG32(CP_ME_CNTL, cp_me); |
||
669 | |||
670 | r = radeon_ring_lock(rdev, evergreen_default_size + 19); |
||
671 | if (r) { |
||
672 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
||
673 | return r; |
||
674 | } |
||
675 | |||
676 | /* setup clear context state */ |
||
677 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
||
678 | radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
||
679 | |||
680 | for (i = 0; i < evergreen_default_size; i++) |
||
681 | radeon_ring_write(rdev, evergreen_default_state[i]); |
||
682 | |||
683 | radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
||
684 | radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); |
||
685 | |||
686 | /* set clear context state */ |
||
687 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
||
688 | radeon_ring_write(rdev, 0); |
||
689 | |||
690 | /* SQ_VTX_BASE_VTX_LOC */ |
||
691 | radeon_ring_write(rdev, 0xc0026f00); |
||
692 | radeon_ring_write(rdev, 0x00000000); |
||
693 | radeon_ring_write(rdev, 0x00000000); |
||
694 | radeon_ring_write(rdev, 0x00000000); |
||
695 | |||
696 | /* Clear consts */ |
||
697 | radeon_ring_write(rdev, 0xc0036f00); |
||
698 | radeon_ring_write(rdev, 0x00000bc4); |
||
699 | radeon_ring_write(rdev, 0xffffffff); |
||
700 | radeon_ring_write(rdev, 0xffffffff); |
||
701 | radeon_ring_write(rdev, 0xffffffff); |
||
702 | |||
703 | radeon_ring_write(rdev, 0xc0026900); |
||
704 | radeon_ring_write(rdev, 0x00000316); |
||
705 | radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
||
706 | radeon_ring_write(rdev, 0x00000010); /* */ |
||
707 | |||
708 | radeon_ring_unlock_commit(rdev); |
||
709 | |||
710 | return 0; |
||
711 | } |
||
712 | |||
713 | int evergreen_cp_resume(struct radeon_device *rdev) |
||
1430 | serge | 714 | { |
1963 | serge | 715 | u32 tmp; |
716 | u32 rb_bufsz; |
||
717 | int r; |
||
1430 | serge | 718 | |
1963 | serge | 719 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ |
720 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | |
||
721 | SOFT_RESET_PA | |
||
722 | SOFT_RESET_SH | |
||
723 | SOFT_RESET_VGT | |
||
724 | SOFT_RESET_SX)); |
||
725 | RREG32(GRBM_SOFT_RESET); |
||
726 | mdelay(15); |
||
727 | WREG32(GRBM_SOFT_RESET, 0); |
||
728 | RREG32(GRBM_SOFT_RESET); |
||
729 | |||
730 | /* Set ring buffer size */ |
||
731 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); |
||
732 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
||
733 | #ifdef __BIG_ENDIAN |
||
734 | tmp |= BUF_SWAP_32BIT; |
||
735 | #endif |
||
736 | WREG32(CP_RB_CNTL, tmp); |
||
737 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
||
738 | |||
739 | /* Set the write pointer delay */ |
||
740 | WREG32(CP_RB_WPTR_DELAY, 0); |
||
741 | |||
742 | /* Initialize the ring buffer's read and write pointers */ |
||
743 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
||
744 | WREG32(CP_RB_RPTR_WR, 0); |
||
745 | WREG32(CP_RB_WPTR, 0); |
||
746 | |||
747 | /* set the wb address wether it's enabled or not */ |
||
748 | WREG32(CP_RB_RPTR_ADDR, |
||
749 | #ifdef __BIG_ENDIAN |
||
750 | RB_RPTR_SWAP(2) | |
||
751 | #endif |
||
752 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
||
753 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
||
754 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
||
755 | |||
756 | if (rdev->wb.enabled) |
||
757 | WREG32(SCRATCH_UMSK, 0xff); |
||
758 | else { |
||
759 | tmp |= RB_NO_UPDATE; |
||
760 | WREG32(SCRATCH_UMSK, 0); |
||
761 | } |
||
762 | |||
763 | mdelay(1); |
||
764 | WREG32(CP_RB_CNTL, tmp); |
||
765 | |||
766 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); |
||
767 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
||
768 | |||
769 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
||
770 | rdev->cp.wptr = RREG32(CP_RB_WPTR); |
||
771 | |||
772 | evergreen_cp_start(rdev); |
||
773 | rdev->cp.ready = true; |
||
774 | r = radeon_ring_test(rdev); |
||
775 | if (r) { |
||
776 | rdev->cp.ready = false; |
||
777 | return r; |
||
778 | } |
||
1430 | serge | 779 | return 0; |
780 | } |
||
781 | |||
782 | /* |
||
783 | * Core functions |
||
784 | */ |
||
1963 | serge | 785 | static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, |
786 | u32 num_tile_pipes, |
||
1430 | serge | 787 | u32 num_backends, |
788 | u32 backend_disable_mask) |
||
789 | { |
||
790 | u32 backend_map = 0; |
||
1963 | serge | 791 | u32 enabled_backends_mask = 0; |
792 | u32 enabled_backends_count = 0; |
||
793 | u32 cur_pipe; |
||
794 | u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; |
||
795 | u32 cur_backend = 0; |
||
796 | u32 i; |
||
797 | bool force_no_swizzle; |
||
1430 | serge | 798 | |
1963 | serge | 799 | if (num_tile_pipes > EVERGREEN_MAX_PIPES) |
800 | num_tile_pipes = EVERGREEN_MAX_PIPES; |
||
801 | if (num_tile_pipes < 1) |
||
802 | num_tile_pipes = 1; |
||
803 | if (num_backends > EVERGREEN_MAX_BACKENDS) |
||
804 | num_backends = EVERGREEN_MAX_BACKENDS; |
||
805 | if (num_backends < 1) |
||
806 | num_backends = 1; |
||
807 | |||
808 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { |
||
809 | if (((backend_disable_mask >> i) & 1) == 0) { |
||
810 | enabled_backends_mask |= (1 << i); |
||
811 | ++enabled_backends_count; |
||
812 | } |
||
813 | if (enabled_backends_count == num_backends) |
||
814 | break; |
||
815 | } |
||
816 | |||
817 | if (enabled_backends_count == 0) { |
||
818 | enabled_backends_mask = 1; |
||
819 | enabled_backends_count = 1; |
||
820 | } |
||
821 | |||
822 | if (enabled_backends_count != num_backends) |
||
823 | num_backends = enabled_backends_count; |
||
824 | |||
825 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); |
||
826 | switch (rdev->family) { |
||
827 | case CHIP_CEDAR: |
||
828 | case CHIP_REDWOOD: |
||
829 | case CHIP_PALM: |
||
830 | case CHIP_SUMO: |
||
831 | case CHIP_SUMO2: |
||
832 | case CHIP_TURKS: |
||
833 | case CHIP_CAICOS: |
||
834 | force_no_swizzle = false; |
||
835 | break; |
||
836 | case CHIP_CYPRESS: |
||
837 | case CHIP_HEMLOCK: |
||
838 | case CHIP_JUNIPER: |
||
839 | case CHIP_BARTS: |
||
840 | default: |
||
841 | force_no_swizzle = true; |
||
842 | break; |
||
843 | } |
||
844 | if (force_no_swizzle) { |
||
845 | bool last_backend_enabled = false; |
||
846 | |||
847 | force_no_swizzle = false; |
||
848 | for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { |
||
849 | if (((enabled_backends_mask >> i) & 1) == 1) { |
||
850 | if (last_backend_enabled) |
||
851 | force_no_swizzle = true; |
||
852 | last_backend_enabled = true; |
||
853 | } else |
||
854 | last_backend_enabled = false; |
||
855 | } |
||
856 | } |
||
857 | |||
858 | switch (num_tile_pipes) { |
||
859 | case 1: |
||
860 | case 3: |
||
861 | case 5: |
||
862 | case 7: |
||
863 | DRM_ERROR("odd number of pipes!\n"); |
||
864 | break; |
||
865 | case 2: |
||
866 | swizzle_pipe[0] = 0; |
||
867 | swizzle_pipe[1] = 1; |
||
868 | break; |
||
869 | case 4: |
||
870 | if (force_no_swizzle) { |
||
871 | swizzle_pipe[0] = 0; |
||
872 | swizzle_pipe[1] = 1; |
||
873 | swizzle_pipe[2] = 2; |
||
874 | swizzle_pipe[3] = 3; |
||
875 | } else { |
||
876 | swizzle_pipe[0] = 0; |
||
877 | swizzle_pipe[1] = 2; |
||
878 | swizzle_pipe[2] = 1; |
||
879 | swizzle_pipe[3] = 3; |
||
880 | } |
||
881 | break; |
||
882 | case 6: |
||
883 | if (force_no_swizzle) { |
||
884 | swizzle_pipe[0] = 0; |
||
885 | swizzle_pipe[1] = 1; |
||
886 | swizzle_pipe[2] = 2; |
||
887 | swizzle_pipe[3] = 3; |
||
888 | swizzle_pipe[4] = 4; |
||
889 | swizzle_pipe[5] = 5; |
||
890 | } else { |
||
891 | swizzle_pipe[0] = 0; |
||
892 | swizzle_pipe[1] = 2; |
||
893 | swizzle_pipe[2] = 4; |
||
894 | swizzle_pipe[3] = 1; |
||
895 | swizzle_pipe[4] = 3; |
||
896 | swizzle_pipe[5] = 5; |
||
897 | } |
||
898 | break; |
||
899 | case 8: |
||
900 | if (force_no_swizzle) { |
||
901 | swizzle_pipe[0] = 0; |
||
902 | swizzle_pipe[1] = 1; |
||
903 | swizzle_pipe[2] = 2; |
||
904 | swizzle_pipe[3] = 3; |
||
905 | swizzle_pipe[4] = 4; |
||
906 | swizzle_pipe[5] = 5; |
||
907 | swizzle_pipe[6] = 6; |
||
908 | swizzle_pipe[7] = 7; |
||
909 | } else { |
||
910 | swizzle_pipe[0] = 0; |
||
911 | swizzle_pipe[1] = 2; |
||
912 | swizzle_pipe[2] = 4; |
||
913 | swizzle_pipe[3] = 6; |
||
914 | swizzle_pipe[4] = 1; |
||
915 | swizzle_pipe[5] = 3; |
||
916 | swizzle_pipe[6] = 5; |
||
917 | swizzle_pipe[7] = 7; |
||
918 | } |
||
919 | break; |
||
920 | } |
||
921 | |||
922 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
||
923 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
||
924 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; |
||
925 | |||
926 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); |
||
927 | |||
928 | cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; |
||
929 | } |
||
930 | |||
1430 | serge | 931 | return backend_map; |
932 | } |
||
933 | #endif |
||
934 | |||
935 | static void evergreen_gpu_init(struct radeon_device *rdev) |
||
936 | { |
||
1963 | serge | 937 | u32 cc_rb_backend_disable = 0; |
938 | u32 cc_gc_shader_pipe_config; |
||
939 | u32 gb_addr_config = 0; |
||
940 | u32 mc_shared_chmap, mc_arb_ramcfg; |
||
941 | u32 gb_backend_map; |
||
942 | u32 grbm_gfx_index; |
||
943 | u32 sx_debug_1; |
||
944 | u32 smx_dc_ctl0; |
||
945 | u32 sq_config; |
||
946 | u32 sq_lds_resource_mgmt; |
||
947 | u32 sq_gpr_resource_mgmt_1; |
||
948 | u32 sq_gpr_resource_mgmt_2; |
||
949 | u32 sq_gpr_resource_mgmt_3; |
||
950 | u32 sq_thread_resource_mgmt; |
||
951 | u32 sq_thread_resource_mgmt_2; |
||
952 | u32 sq_stack_resource_mgmt_1; |
||
953 | u32 sq_stack_resource_mgmt_2; |
||
954 | u32 sq_stack_resource_mgmt_3; |
||
955 | u32 vgt_cache_invalidation; |
||
956 | u32 hdp_host_path_cntl, tmp; |
||
957 | int i, j, num_shader_engines, ps_thread_count; |
||
958 | |||
959 | switch (rdev->family) { |
||
960 | case CHIP_CYPRESS: |
||
961 | case CHIP_HEMLOCK: |
||
962 | rdev->config.evergreen.num_ses = 2; |
||
963 | rdev->config.evergreen.max_pipes = 4; |
||
964 | rdev->config.evergreen.max_tile_pipes = 8; |
||
965 | rdev->config.evergreen.max_simds = 10; |
||
966 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; |
||
967 | rdev->config.evergreen.max_gprs = 256; |
||
968 | rdev->config.evergreen.max_threads = 248; |
||
969 | rdev->config.evergreen.max_gs_threads = 32; |
||
970 | rdev->config.evergreen.max_stack_entries = 512; |
||
971 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
972 | rdev->config.evergreen.sx_max_export_size = 256; |
||
973 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
974 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
975 | rdev->config.evergreen.max_hw_contexts = 8; |
||
976 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
977 | |||
978 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; |
||
979 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
980 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
981 | break; |
||
982 | case CHIP_JUNIPER: |
||
983 | rdev->config.evergreen.num_ses = 1; |
||
984 | rdev->config.evergreen.max_pipes = 4; |
||
985 | rdev->config.evergreen.max_tile_pipes = 4; |
||
986 | rdev->config.evergreen.max_simds = 10; |
||
987 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; |
||
988 | rdev->config.evergreen.max_gprs = 256; |
||
989 | rdev->config.evergreen.max_threads = 248; |
||
990 | rdev->config.evergreen.max_gs_threads = 32; |
||
991 | rdev->config.evergreen.max_stack_entries = 512; |
||
992 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
993 | rdev->config.evergreen.sx_max_export_size = 256; |
||
994 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
995 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
996 | rdev->config.evergreen.max_hw_contexts = 8; |
||
997 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
998 | |||
999 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; |
||
1000 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1001 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1002 | break; |
||
1003 | case CHIP_REDWOOD: |
||
1004 | rdev->config.evergreen.num_ses = 1; |
||
1005 | rdev->config.evergreen.max_pipes = 4; |
||
1006 | rdev->config.evergreen.max_tile_pipes = 4; |
||
1007 | rdev->config.evergreen.max_simds = 5; |
||
1008 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; |
||
1009 | rdev->config.evergreen.max_gprs = 256; |
||
1010 | rdev->config.evergreen.max_threads = 248; |
||
1011 | rdev->config.evergreen.max_gs_threads = 32; |
||
1012 | rdev->config.evergreen.max_stack_entries = 256; |
||
1013 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1014 | rdev->config.evergreen.sx_max_export_size = 256; |
||
1015 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
1016 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
1017 | rdev->config.evergreen.max_hw_contexts = 8; |
||
1018 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
1019 | |||
1020 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; |
||
1021 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1022 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1023 | break; |
||
1024 | case CHIP_CEDAR: |
||
1025 | default: |
||
1026 | rdev->config.evergreen.num_ses = 1; |
||
1027 | rdev->config.evergreen.max_pipes = 2; |
||
1028 | rdev->config.evergreen.max_tile_pipes = 2; |
||
1029 | rdev->config.evergreen.max_simds = 2; |
||
1030 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
||
1031 | rdev->config.evergreen.max_gprs = 256; |
||
1032 | rdev->config.evergreen.max_threads = 192; |
||
1033 | rdev->config.evergreen.max_gs_threads = 16; |
||
1034 | rdev->config.evergreen.max_stack_entries = 256; |
||
1035 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1036 | rdev->config.evergreen.sx_max_export_size = 128; |
||
1037 | rdev->config.evergreen.sx_max_export_pos_size = 32; |
||
1038 | rdev->config.evergreen.sx_max_export_smx_size = 96; |
||
1039 | rdev->config.evergreen.max_hw_contexts = 4; |
||
1040 | rdev->config.evergreen.sq_num_cf_insts = 1; |
||
1041 | |||
1042 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
||
1043 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1044 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1045 | break; |
||
1046 | case CHIP_PALM: |
||
1047 | rdev->config.evergreen.num_ses = 1; |
||
1048 | rdev->config.evergreen.max_pipes = 2; |
||
1049 | rdev->config.evergreen.max_tile_pipes = 2; |
||
1050 | rdev->config.evergreen.max_simds = 2; |
||
1051 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
||
1052 | rdev->config.evergreen.max_gprs = 256; |
||
1053 | rdev->config.evergreen.max_threads = 192; |
||
1054 | rdev->config.evergreen.max_gs_threads = 16; |
||
1055 | rdev->config.evergreen.max_stack_entries = 256; |
||
1056 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1057 | rdev->config.evergreen.sx_max_export_size = 128; |
||
1058 | rdev->config.evergreen.sx_max_export_pos_size = 32; |
||
1059 | rdev->config.evergreen.sx_max_export_smx_size = 96; |
||
1060 | rdev->config.evergreen.max_hw_contexts = 4; |
||
1061 | rdev->config.evergreen.sq_num_cf_insts = 1; |
||
1062 | |||
1063 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
||
1064 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1065 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1066 | break; |
||
1067 | case CHIP_SUMO: |
||
1068 | rdev->config.evergreen.num_ses = 1; |
||
1069 | rdev->config.evergreen.max_pipes = 4; |
||
1070 | rdev->config.evergreen.max_tile_pipes = 2; |
||
1071 | if (rdev->pdev->device == 0x9648) |
||
1072 | rdev->config.evergreen.max_simds = 3; |
||
1073 | else if ((rdev->pdev->device == 0x9647) || |
||
1074 | (rdev->pdev->device == 0x964a)) |
||
1075 | rdev->config.evergreen.max_simds = 4; |
||
1076 | else |
||
1077 | rdev->config.evergreen.max_simds = 5; |
||
1078 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; |
||
1079 | rdev->config.evergreen.max_gprs = 256; |
||
1080 | rdev->config.evergreen.max_threads = 248; |
||
1081 | rdev->config.evergreen.max_gs_threads = 32; |
||
1082 | rdev->config.evergreen.max_stack_entries = 256; |
||
1083 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1084 | rdev->config.evergreen.sx_max_export_size = 256; |
||
1085 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
1086 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
1087 | rdev->config.evergreen.max_hw_contexts = 8; |
||
1088 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
1089 | |||
1090 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
||
1091 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1092 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1093 | break; |
||
1094 | case CHIP_SUMO2: |
||
1095 | rdev->config.evergreen.num_ses = 1; |
||
1096 | rdev->config.evergreen.max_pipes = 4; |
||
1097 | rdev->config.evergreen.max_tile_pipes = 4; |
||
1098 | rdev->config.evergreen.max_simds = 2; |
||
1099 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
||
1100 | rdev->config.evergreen.max_gprs = 256; |
||
1101 | rdev->config.evergreen.max_threads = 248; |
||
1102 | rdev->config.evergreen.max_gs_threads = 32; |
||
1103 | rdev->config.evergreen.max_stack_entries = 512; |
||
1104 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1105 | rdev->config.evergreen.sx_max_export_size = 256; |
||
1106 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
1107 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
1108 | rdev->config.evergreen.max_hw_contexts = 8; |
||
1109 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
1110 | |||
1111 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
||
1112 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1113 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1114 | break; |
||
1115 | case CHIP_BARTS: |
||
1116 | rdev->config.evergreen.num_ses = 2; |
||
1117 | rdev->config.evergreen.max_pipes = 4; |
||
1118 | rdev->config.evergreen.max_tile_pipes = 8; |
||
1119 | rdev->config.evergreen.max_simds = 7; |
||
1120 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; |
||
1121 | rdev->config.evergreen.max_gprs = 256; |
||
1122 | rdev->config.evergreen.max_threads = 248; |
||
1123 | rdev->config.evergreen.max_gs_threads = 32; |
||
1124 | rdev->config.evergreen.max_stack_entries = 512; |
||
1125 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1126 | rdev->config.evergreen.sx_max_export_size = 256; |
||
1127 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
1128 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
1129 | rdev->config.evergreen.max_hw_contexts = 8; |
||
1130 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
1131 | |||
1132 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; |
||
1133 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1134 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1135 | break; |
||
1136 | case CHIP_TURKS: |
||
1137 | rdev->config.evergreen.num_ses = 1; |
||
1138 | rdev->config.evergreen.max_pipes = 4; |
||
1139 | rdev->config.evergreen.max_tile_pipes = 4; |
||
1140 | rdev->config.evergreen.max_simds = 6; |
||
1141 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; |
||
1142 | rdev->config.evergreen.max_gprs = 256; |
||
1143 | rdev->config.evergreen.max_threads = 248; |
||
1144 | rdev->config.evergreen.max_gs_threads = 32; |
||
1145 | rdev->config.evergreen.max_stack_entries = 256; |
||
1146 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1147 | rdev->config.evergreen.sx_max_export_size = 256; |
||
1148 | rdev->config.evergreen.sx_max_export_pos_size = 64; |
||
1149 | rdev->config.evergreen.sx_max_export_smx_size = 192; |
||
1150 | rdev->config.evergreen.max_hw_contexts = 8; |
||
1151 | rdev->config.evergreen.sq_num_cf_insts = 2; |
||
1152 | |||
1153 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; |
||
1154 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1155 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1156 | break; |
||
1157 | case CHIP_CAICOS: |
||
1158 | rdev->config.evergreen.num_ses = 1; |
||
1159 | rdev->config.evergreen.max_pipes = 4; |
||
1160 | rdev->config.evergreen.max_tile_pipes = 2; |
||
1161 | rdev->config.evergreen.max_simds = 2; |
||
1162 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; |
||
1163 | rdev->config.evergreen.max_gprs = 256; |
||
1164 | rdev->config.evergreen.max_threads = 192; |
||
1165 | rdev->config.evergreen.max_gs_threads = 16; |
||
1166 | rdev->config.evergreen.max_stack_entries = 256; |
||
1167 | rdev->config.evergreen.sx_num_of_sets = 4; |
||
1168 | rdev->config.evergreen.sx_max_export_size = 128; |
||
1169 | rdev->config.evergreen.sx_max_export_pos_size = 32; |
||
1170 | rdev->config.evergreen.sx_max_export_smx_size = 96; |
||
1171 | rdev->config.evergreen.max_hw_contexts = 4; |
||
1172 | rdev->config.evergreen.sq_num_cf_insts = 1; |
||
1173 | |||
1174 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
||
1175 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; |
||
1176 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; |
||
1177 | break; |
||
1178 | } |
||
1179 | |||
1180 | /* Initialize HDP */ |
||
1181 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
||
1182 | WREG32((0x2c14 + j), 0x00000000); |
||
1183 | WREG32((0x2c18 + j), 0x00000000); |
||
1184 | WREG32((0x2c1c + j), 0x00000000); |
||
1185 | WREG32((0x2c20 + j), 0x00000000); |
||
1186 | WREG32((0x2c24 + j), 0x00000000); |
||
1187 | } |
||
1188 | |||
1189 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
||
1190 | |||
1191 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; |
||
1192 | |||
1193 | cc_gc_shader_pipe_config |= |
||
1194 | INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) |
||
1195 | & EVERGREEN_MAX_PIPES_MASK); |
||
1196 | cc_gc_shader_pipe_config |= |
||
1197 | INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) |
||
1198 | & EVERGREEN_MAX_SIMDS_MASK); |
||
1199 | |||
1200 | cc_rb_backend_disable = |
||
1201 | BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) |
||
1202 | & EVERGREEN_MAX_BACKENDS_MASK); |
||
1203 | |||
1204 | |||
1205 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
||
1206 | if (rdev->flags & RADEON_IS_IGP) |
||
1207 | mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); |
||
1208 | else |
||
1209 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
||
1210 | |||
1211 | switch (rdev->config.evergreen.max_tile_pipes) { |
||
1212 | case 1: |
||
1213 | default: |
||
1214 | gb_addr_config |= NUM_PIPES(0); |
||
1215 | break; |
||
1216 | case 2: |
||
1217 | gb_addr_config |= NUM_PIPES(1); |
||
1218 | break; |
||
1219 | case 4: |
||
1220 | gb_addr_config |= NUM_PIPES(2); |
||
1221 | break; |
||
1222 | case 8: |
||
1223 | gb_addr_config |= NUM_PIPES(3); |
||
1224 | break; |
||
1225 | } |
||
1226 | |||
1227 | gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
||
1228 | gb_addr_config |= BANK_INTERLEAVE_SIZE(0); |
||
1229 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); |
||
1230 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); |
||
1231 | gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ |
||
1232 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); |
||
1233 | |||
1234 | if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) |
||
1235 | gb_addr_config |= ROW_SIZE(2); |
||
1236 | else |
||
1237 | gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); |
||
1238 | |||
1239 | if (rdev->ddev->pdev->device == 0x689e) { |
||
1240 | u32 efuse_straps_4; |
||
1241 | u32 efuse_straps_3; |
||
1242 | u8 efuse_box_bit_131_124; |
||
1243 | |||
1244 | WREG32(RCU_IND_INDEX, 0x204); |
||
1245 | efuse_straps_4 = RREG32(RCU_IND_DATA); |
||
1246 | WREG32(RCU_IND_INDEX, 0x203); |
||
1247 | efuse_straps_3 = RREG32(RCU_IND_DATA); |
||
1248 | efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); |
||
1249 | |||
1250 | switch(efuse_box_bit_131_124) { |
||
1251 | case 0x00: |
||
1252 | gb_backend_map = 0x76543210; |
||
1253 | break; |
||
1254 | case 0x55: |
||
1255 | gb_backend_map = 0x77553311; |
||
1256 | break; |
||
1257 | case 0x56: |
||
1258 | gb_backend_map = 0x77553300; |
||
1259 | break; |
||
1260 | case 0x59: |
||
1261 | gb_backend_map = 0x77552211; |
||
1262 | break; |
||
1263 | case 0x66: |
||
1264 | gb_backend_map = 0x77443300; |
||
1265 | break; |
||
1266 | case 0x99: |
||
1267 | gb_backend_map = 0x66552211; |
||
1268 | break; |
||
1269 | case 0x5a: |
||
1270 | gb_backend_map = 0x77552200; |
||
1271 | break; |
||
1272 | case 0xaa: |
||
1273 | gb_backend_map = 0x66442200; |
||
1274 | break; |
||
1275 | case 0x95: |
||
1276 | gb_backend_map = 0x66553311; |
||
1277 | break; |
||
1278 | default: |
||
1279 | DRM_ERROR("bad backend map, using default\n"); |
||
1280 | gb_backend_map = |
||
1281 | evergreen_get_tile_pipe_to_backend_map(rdev, |
||
1282 | rdev->config.evergreen.max_tile_pipes, |
||
1283 | rdev->config.evergreen.max_backends, |
||
1284 | ((EVERGREEN_MAX_BACKENDS_MASK << |
||
1285 | rdev->config.evergreen.max_backends) & |
||
1286 | EVERGREEN_MAX_BACKENDS_MASK)); |
||
1287 | break; |
||
1288 | } |
||
1289 | } else if (rdev->ddev->pdev->device == 0x68b9) { |
||
1290 | u32 efuse_straps_3; |
||
1291 | u8 efuse_box_bit_127_124; |
||
1292 | |||
1293 | WREG32(RCU_IND_INDEX, 0x203); |
||
1294 | efuse_straps_3 = RREG32(RCU_IND_DATA); |
||
1295 | efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); |
||
1296 | |||
1297 | switch(efuse_box_bit_127_124) { |
||
1298 | case 0x0: |
||
1299 | gb_backend_map = 0x00003210; |
||
1300 | break; |
||
1301 | case 0x5: |
||
1302 | case 0x6: |
||
1303 | case 0x9: |
||
1304 | case 0xa: |
||
1305 | gb_backend_map = 0x00003311; |
||
1306 | break; |
||
1307 | default: |
||
1308 | DRM_ERROR("bad backend map, using default\n"); |
||
1309 | gb_backend_map = |
||
1310 | evergreen_get_tile_pipe_to_backend_map(rdev, |
||
1311 | rdev->config.evergreen.max_tile_pipes, |
||
1312 | rdev->config.evergreen.max_backends, |
||
1313 | ((EVERGREEN_MAX_BACKENDS_MASK << |
||
1314 | rdev->config.evergreen.max_backends) & |
||
1315 | EVERGREEN_MAX_BACKENDS_MASK)); |
||
1316 | break; |
||
1317 | } |
||
1318 | } else { |
||
1319 | switch (rdev->family) { |
||
1320 | case CHIP_CYPRESS: |
||
1321 | case CHIP_HEMLOCK: |
||
1322 | case CHIP_BARTS: |
||
1323 | gb_backend_map = 0x66442200; |
||
1324 | break; |
||
1325 | case CHIP_JUNIPER: |
||
1326 | gb_backend_map = 0x00006420; |
||
1327 | break; |
||
1328 | default: |
||
1329 | gb_backend_map = |
||
1330 | evergreen_get_tile_pipe_to_backend_map(rdev, |
||
1331 | rdev->config.evergreen.max_tile_pipes, |
||
1332 | rdev->config.evergreen.max_backends, |
||
1333 | ((EVERGREEN_MAX_BACKENDS_MASK << |
||
1334 | rdev->config.evergreen.max_backends) & |
||
1335 | EVERGREEN_MAX_BACKENDS_MASK)); |
||
1336 | } |
||
1337 | } |
||
1338 | |||
1339 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
||
1340 | * not have bank info, so create a custom tiling dword. |
||
1341 | * bits 3:0 num_pipes |
||
1342 | * bits 7:4 num_banks |
||
1343 | * bits 11:8 group_size |
||
1344 | * bits 15:12 row_size |
||
1345 | */ |
||
1346 | rdev->config.evergreen.tile_config = 0; |
||
1347 | switch (rdev->config.evergreen.max_tile_pipes) { |
||
1348 | case 1: |
||
1349 | default: |
||
1350 | rdev->config.evergreen.tile_config |= (0 << 0); |
||
1351 | break; |
||
1352 | case 2: |
||
1353 | rdev->config.evergreen.tile_config |= (1 << 0); |
||
1354 | break; |
||
1355 | case 4: |
||
1356 | rdev->config.evergreen.tile_config |= (2 << 0); |
||
1357 | break; |
||
1358 | case 8: |
||
1359 | rdev->config.evergreen.tile_config |= (3 << 0); |
||
1360 | break; |
||
1361 | } |
||
1362 | /* num banks is 8 on all fusion asics */ |
||
1363 | if (rdev->flags & RADEON_IS_IGP) |
||
1364 | rdev->config.evergreen.tile_config |= 8 << 4; |
||
1365 | else |
||
1366 | rdev->config.evergreen.tile_config |= |
||
1367 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; |
||
1368 | rdev->config.evergreen.tile_config |= |
||
1369 | ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; |
||
1370 | rdev->config.evergreen.tile_config |= |
||
1371 | ((gb_addr_config & 0x30000000) >> 28) << 12; |
||
1372 | |||
1373 | WREG32(GB_BACKEND_MAP, gb_backend_map); |
||
1374 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
||
1375 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
||
1376 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
||
1377 | |||
1378 | evergreen_program_channel_remap(rdev); |
||
1379 | |||
1380 | num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; |
||
1381 | grbm_gfx_index = INSTANCE_BROADCAST_WRITES; |
||
1382 | |||
1383 | for (i = 0; i < rdev->config.evergreen.num_ses; i++) { |
||
1384 | u32 rb = cc_rb_backend_disable | (0xf0 << 16); |
||
1385 | u32 sp = cc_gc_shader_pipe_config; |
||
1386 | u32 gfx = grbm_gfx_index | SE_INDEX(i); |
||
1387 | |||
1388 | if (i == num_shader_engines) { |
||
1389 | rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); |
||
1390 | sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); |
||
1391 | } |
||
1392 | |||
1393 | WREG32(GRBM_GFX_INDEX, gfx); |
||
1394 | WREG32(RLC_GFX_INDEX, gfx); |
||
1395 | |||
1396 | WREG32(CC_RB_BACKEND_DISABLE, rb); |
||
1397 | WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); |
||
1398 | WREG32(GC_USER_RB_BACKEND_DISABLE, rb); |
||
1399 | WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); |
||
1400 | } |
||
1401 | |||
1402 | grbm_gfx_index |= SE_BROADCAST_WRITES; |
||
1403 | WREG32(GRBM_GFX_INDEX, grbm_gfx_index); |
||
1404 | WREG32(RLC_GFX_INDEX, grbm_gfx_index); |
||
1405 | |||
1406 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
||
1407 | WREG32(CGTS_TCC_DISABLE, 0); |
||
1408 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
||
1409 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
||
1410 | |||
1411 | /* set HW defaults for 3D engine */ |
||
1412 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
||
1413 | ROQ_IB2_START(0x2b))); |
||
1414 | |||
1415 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
||
1416 | |||
1417 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | |
||
1418 | SYNC_GRADIENT | |
||
1419 | SYNC_WALKER | |
||
1420 | SYNC_ALIGNER)); |
||
1421 | |||
1422 | sx_debug_1 = RREG32(SX_DEBUG_1); |
||
1423 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
||
1424 | WREG32(SX_DEBUG_1, sx_debug_1); |
||
1425 | |||
1426 | |||
1427 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
||
1428 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); |
||
1429 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); |
||
1430 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
||
1431 | |||
1432 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | |
||
1433 | POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | |
||
1434 | SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); |
||
1435 | |||
1436 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | |
||
1437 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | |
||
1438 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); |
||
1439 | |||
1440 | WREG32(VGT_NUM_INSTANCES, 1); |
||
1441 | WREG32(SPI_CONFIG_CNTL, 0); |
||
1442 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
||
1443 | WREG32(CP_PERFMON_CNTL, 0); |
||
1444 | |||
1445 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | |
||
1446 | FETCH_FIFO_HIWATER(0x4) | |
||
1447 | DONE_FIFO_HIWATER(0xe0) | |
||
1448 | ALU_UPDATE_FIFO_HIWATER(0x8))); |
||
1449 | |||
1450 | sq_config = RREG32(SQ_CONFIG); |
||
1451 | sq_config &= ~(PS_PRIO(3) | |
||
1452 | VS_PRIO(3) | |
||
1453 | GS_PRIO(3) | |
||
1454 | ES_PRIO(3)); |
||
1455 | sq_config |= (VC_ENABLE | |
||
1456 | EXPORT_SRC_C | |
||
1457 | PS_PRIO(0) | |
||
1458 | VS_PRIO(1) | |
||
1459 | GS_PRIO(2) | |
||
1460 | ES_PRIO(3)); |
||
1461 | |||
1462 | switch (rdev->family) { |
||
1463 | case CHIP_CEDAR: |
||
1464 | case CHIP_PALM: |
||
1465 | case CHIP_SUMO: |
||
1466 | case CHIP_SUMO2: |
||
1467 | case CHIP_CAICOS: |
||
1468 | /* no vertex cache */ |
||
1469 | sq_config &= ~VC_ENABLE; |
||
1470 | break; |
||
1471 | default: |
||
1472 | break; |
||
1473 | } |
||
1474 | |||
1475 | sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); |
||
1476 | |||
1477 | sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); |
||
1478 | sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); |
||
1479 | sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); |
||
1480 | sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); |
||
1481 | sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); |
||
1482 | sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); |
||
1483 | sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); |
||
1484 | |||
1485 | switch (rdev->family) { |
||
1486 | case CHIP_CEDAR: |
||
1487 | case CHIP_PALM: |
||
1488 | case CHIP_SUMO: |
||
1489 | case CHIP_SUMO2: |
||
1490 | ps_thread_count = 96; |
||
1491 | break; |
||
1492 | default: |
||
1493 | ps_thread_count = 128; |
||
1494 | break; |
||
1495 | } |
||
1496 | |||
1497 | sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); |
||
1498 | sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
||
1499 | sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
||
1500 | sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
||
1501 | sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
||
1502 | sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
||
1503 | |||
1504 | sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1505 | sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1506 | sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1507 | sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1508 | sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1509 | sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); |
||
1510 | |||
1511 | WREG32(SQ_CONFIG, sq_config); |
||
1512 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); |
||
1513 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); |
||
1514 | WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); |
||
1515 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
||
1516 | WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); |
||
1517 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); |
||
1518 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); |
||
1519 | WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); |
||
1520 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); |
||
1521 | WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); |
||
1522 | |||
1523 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
||
1524 | FORCE_EOV_MAX_REZ_CNT(255))); |
||
1525 | |||
1526 | switch (rdev->family) { |
||
1527 | case CHIP_CEDAR: |
||
1528 | case CHIP_PALM: |
||
1529 | case CHIP_SUMO: |
||
1530 | case CHIP_SUMO2: |
||
1531 | case CHIP_CAICOS: |
||
1532 | vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); |
||
1533 | break; |
||
1534 | default: |
||
1535 | vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); |
||
1536 | break; |
||
1537 | } |
||
1538 | vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); |
||
1539 | WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); |
||
1540 | |||
1541 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
||
1542 | WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); |
||
1543 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
||
1544 | |||
1545 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); |
||
1546 | WREG32(VGT_OUT_DEALLOC_CNTL, 16); |
||
1547 | |||
1548 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
||
1549 | WREG32(CB_PERF_CTR0_SEL_1, 0); |
||
1550 | WREG32(CB_PERF_CTR1_SEL_0, 0); |
||
1551 | WREG32(CB_PERF_CTR1_SEL_1, 0); |
||
1552 | WREG32(CB_PERF_CTR2_SEL_0, 0); |
||
1553 | WREG32(CB_PERF_CTR2_SEL_1, 0); |
||
1554 | WREG32(CB_PERF_CTR3_SEL_0, 0); |
||
1555 | WREG32(CB_PERF_CTR3_SEL_1, 0); |
||
1556 | |||
1557 | /* clear render buffer base addresses */ |
||
1558 | WREG32(CB_COLOR0_BASE, 0); |
||
1559 | WREG32(CB_COLOR1_BASE, 0); |
||
1560 | WREG32(CB_COLOR2_BASE, 0); |
||
1561 | WREG32(CB_COLOR3_BASE, 0); |
||
1562 | WREG32(CB_COLOR4_BASE, 0); |
||
1563 | WREG32(CB_COLOR5_BASE, 0); |
||
1564 | WREG32(CB_COLOR6_BASE, 0); |
||
1565 | WREG32(CB_COLOR7_BASE, 0); |
||
1566 | WREG32(CB_COLOR8_BASE, 0); |
||
1567 | WREG32(CB_COLOR9_BASE, 0); |
||
1568 | WREG32(CB_COLOR10_BASE, 0); |
||
1569 | WREG32(CB_COLOR11_BASE, 0); |
||
1570 | |||
1571 | /* set the shader const cache sizes to 0 */ |
||
1572 | for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) |
||
1573 | WREG32(i, 0); |
||
1574 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) |
||
1575 | WREG32(i, 0); |
||
1576 | |||
1577 | tmp = RREG32(HDP_MISC_CNTL); |
||
1578 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; |
||
1579 | WREG32(HDP_MISC_CNTL, tmp); |
||
1580 | |||
1581 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
||
1582 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
||
1583 | |||
1584 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); |
||
1585 | |||
1586 | udelay(50); |
||
1587 | |||
1430 | serge | 1588 | } |
1589 | |||
1590 | int evergreen_mc_init(struct radeon_device *rdev) |
||
1591 | { |
||
1592 | u32 tmp; |
||
1593 | int chansize, numchan; |
||
1594 | |||
1595 | /* Get VRAM informations */ |
||
1596 | rdev->mc.vram_is_ddr = true; |
||
1597 | tmp = RREG32(MC_ARB_RAMCFG); |
||
1598 | if (tmp & CHANSIZE_OVERRIDE) { |
||
1599 | chansize = 16; |
||
1600 | } else if (tmp & CHANSIZE_MASK) { |
||
1601 | chansize = 64; |
||
1602 | } else { |
||
1603 | chansize = 32; |
||
1604 | } |
||
1605 | tmp = RREG32(MC_SHARED_CHMAP); |
||
1606 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
1607 | case 0: |
||
1608 | default: |
||
1609 | numchan = 1; |
||
1610 | break; |
||
1611 | case 1: |
||
1612 | numchan = 2; |
||
1613 | break; |
||
1614 | case 2: |
||
1615 | numchan = 4; |
||
1616 | break; |
||
1617 | case 3: |
||
1618 | numchan = 8; |
||
1619 | break; |
||
1620 | } |
||
1621 | rdev->mc.vram_width = numchan * chansize; |
||
1622 | /* Could aper size report 0 ? */ |
||
1963 | serge | 1623 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1624 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
||
1430 | serge | 1625 | /* Setup GPU memory space */ |
1963 | serge | 1626 | if (rdev->flags & RADEON_IS_IGP) { |
1627 | /* size in bytes on fusion */ |
||
1628 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
||
1629 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
||
1630 | } else { |
||
1430 | serge | 1631 | /* size in MB on evergreen */ |
1632 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
||
1633 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
||
1963 | serge | 1634 | } |
1430 | serge | 1635 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
1963 | serge | 1636 | r700_vram_gtt_location(rdev, &rdev->mc); |
1637 | radeon_update_bandwidth_info(rdev); |
||
1638 | |||
1430 | serge | 1639 | return 0; |
1640 | } |
||
1641 | |||
1963 | serge | 1642 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev) |
1430 | serge | 1643 | { |
1644 | /* FIXME: implement for evergreen */ |
||
1963 | serge | 1645 | return false; |
1646 | } |
||
1647 | |||
1648 | static int evergreen_gpu_soft_reset(struct radeon_device *rdev) |
||
1649 | { |
||
1650 | struct evergreen_mc_save save; |
||
1651 | u32 grbm_reset = 0; |
||
1652 | |||
1653 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
||
1654 | return 0; |
||
1655 | |||
1656 | dev_info(rdev->dev, "GPU softreset \n"); |
||
1657 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
||
1658 | RREG32(GRBM_STATUS)); |
||
1659 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
||
1660 | RREG32(GRBM_STATUS_SE0)); |
||
1661 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
||
1662 | RREG32(GRBM_STATUS_SE1)); |
||
1663 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
||
1664 | RREG32(SRBM_STATUS)); |
||
1665 | evergreen_mc_stop(rdev, &save); |
||
1666 | if (evergreen_mc_wait_for_idle(rdev)) { |
||
1667 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
1668 | } |
||
1669 | /* Disable CP parsing/prefetching */ |
||
1670 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); |
||
1671 | |||
1672 | /* reset all the gfx blocks */ |
||
1673 | grbm_reset = (SOFT_RESET_CP | |
||
1674 | SOFT_RESET_CB | |
||
1675 | SOFT_RESET_DB | |
||
1676 | SOFT_RESET_PA | |
||
1677 | SOFT_RESET_SC | |
||
1678 | SOFT_RESET_SPI | |
||
1679 | SOFT_RESET_SH | |
||
1680 | SOFT_RESET_SX | |
||
1681 | SOFT_RESET_TC | |
||
1682 | SOFT_RESET_TA | |
||
1683 | SOFT_RESET_VC | |
||
1684 | SOFT_RESET_VGT); |
||
1685 | |||
1686 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); |
||
1687 | WREG32(GRBM_SOFT_RESET, grbm_reset); |
||
1688 | (void)RREG32(GRBM_SOFT_RESET); |
||
1689 | udelay(50); |
||
1690 | WREG32(GRBM_SOFT_RESET, 0); |
||
1691 | (void)RREG32(GRBM_SOFT_RESET); |
||
1692 | /* Wait a little for things to settle down */ |
||
1693 | udelay(50); |
||
1694 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", |
||
1695 | RREG32(GRBM_STATUS)); |
||
1696 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
||
1697 | RREG32(GRBM_STATUS_SE0)); |
||
1698 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
||
1699 | RREG32(GRBM_STATUS_SE1)); |
||
1700 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", |
||
1701 | RREG32(SRBM_STATUS)); |
||
1702 | evergreen_mc_resume(rdev, &save); |
||
1430 | serge | 1703 | return 0; |
1704 | } |
||
1705 | |||
1963 | serge | 1706 | int evergreen_asic_reset(struct radeon_device *rdev) |
1707 | { |
||
1708 | return evergreen_gpu_soft_reset(rdev); |
||
1709 | } |
||
1710 | |||
1711 | /* Interrupts */ |
||
1712 | |||
1713 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) |
||
1714 | { |
||
1715 | switch (crtc) { |
||
1716 | case 0: |
||
1717 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); |
||
1718 | case 1: |
||
1719 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); |
||
1720 | case 2: |
||
1721 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); |
||
1722 | case 3: |
||
1723 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
1724 | case 4: |
||
1725 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); |
||
1726 | case 5: |
||
1727 | return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1728 | default: |
||
1729 | return 0; |
||
1730 | } |
||
1731 | } |
||
1732 | |||
1733 | void evergreen_disable_interrupt_state(struct radeon_device *rdev) |
||
1734 | { |
||
1735 | u32 tmp; |
||
1736 | |||
1737 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
||
1738 | WREG32(GRBM_INT_CNTL, 0); |
||
1739 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
||
1740 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
||
1741 | if (!(rdev->flags & RADEON_IS_IGP)) { |
||
1742 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
||
1743 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
||
1744 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
||
1745 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
||
1746 | } |
||
1747 | |||
1748 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
||
1749 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
||
1750 | if (!(rdev->flags & RADEON_IS_IGP)) { |
||
1751 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
||
1752 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
||
1753 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
||
1754 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
||
1755 | } |
||
1756 | |||
1757 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
||
1758 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
||
1759 | |||
1760 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1761 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
||
1762 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1763 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
||
1764 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1765 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
||
1766 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1767 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
||
1768 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1769 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
||
1770 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
||
1771 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
||
1772 | |||
1773 | } |
||
1430 | serge | 1774 | static int evergreen_startup(struct radeon_device *rdev) |
1775 | { |
||
1776 | int r; |
||
1777 | |||
1778 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
||
1779 | r = r600_init_microcode(rdev); |
||
1780 | if (r) { |
||
1781 | DRM_ERROR("Failed to load firmware!\n"); |
||
1782 | return r; |
||
1783 | } |
||
1784 | } |
||
1963 | serge | 1785 | |
1430 | serge | 1786 | evergreen_mc_program(rdev); |
1787 | if (rdev->flags & RADEON_IS_AGP) { |
||
1963 | serge | 1788 | evergreen_agp_enable(rdev); |
1430 | serge | 1789 | } else { |
1790 | r = evergreen_pcie_gart_enable(rdev); |
||
1791 | if (r) |
||
1792 | return r; |
||
1793 | } |
||
1794 | evergreen_gpu_init(rdev); |
||
1795 | #if 0 |
||
1963 | serge | 1796 | r = evergreen_blit_init(rdev); |
1797 | if (r) { |
||
1798 | evergreen_blit_fini(rdev); |
||
1799 | rdev->asic->copy = NULL; |
||
1800 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
||
1801 | } |
||
1430 | serge | 1802 | |
1963 | serge | 1803 | /* allocate wb buffer */ |
1804 | r = radeon_wb_init(rdev); |
||
1805 | if (r) |
||
1806 | return r; |
||
1807 | #endif |
||
1808 | |||
1809 | /* Enable IRQ */ |
||
1810 | r = r600_irq_init(rdev); |
||
1811 | if (r) { |
||
1812 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
||
1813 | radeon_irq_kms_fini(rdev); |
||
1814 | return r; |
||
1815 | } |
||
1816 | // evergreen_irq_set(rdev); |
||
1817 | |||
1430 | serge | 1818 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1819 | if (r) |
||
1820 | return r; |
||
1821 | r = evergreen_cp_load_microcode(rdev); |
||
1822 | if (r) |
||
1823 | return r; |
||
1963 | serge | 1824 | r = evergreen_cp_resume(rdev); |
1430 | serge | 1825 | if (r) |
1826 | return r; |
||
1827 | /* write back buffer are not vital so don't worry about failure */ |
||
1828 | r600_wb_enable(rdev); |
||
1963 | serge | 1829 | |
1430 | serge | 1830 | return 0; |
1831 | } |
||
1832 | |||
1833 | int evergreen_resume(struct radeon_device *rdev) |
||
1834 | { |
||
1835 | int r; |
||
1836 | |||
1837 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
||
1838 | * posting will perform necessary task to bring back GPU into good |
||
1839 | * shape. |
||
1840 | */ |
||
1841 | /* post card */ |
||
1842 | atom_asic_init(rdev->mode_info.atom_context); |
||
1843 | |||
1844 | r = evergreen_startup(rdev); |
||
1845 | if (r) { |
||
1846 | DRM_ERROR("r600 startup failed on resume\n"); |
||
1847 | return r; |
||
1848 | } |
||
1849 | #if 0 |
||
1850 | r = r600_ib_test(rdev); |
||
1851 | if (r) { |
||
1852 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
||
1853 | return r; |
||
1854 | } |
||
1855 | #endif |
||
1856 | return r; |
||
1857 | |||
1858 | } |
||
1859 | |||
1860 | int evergreen_suspend(struct radeon_device *rdev) |
||
1861 | { |
||
1862 | int r; |
||
1863 | |||
1864 | /* FIXME: we should wait for ring to be empty */ |
||
1865 | r700_cp_stop(rdev); |
||
1866 | rdev->cp.ready = false; |
||
1867 | r600_wb_disable(rdev); |
||
1868 | evergreen_pcie_gart_disable(rdev); |
||
1963 | serge | 1869 | #if 0 |
1430 | serge | 1870 | /* unpin shaders bo */ |
1871 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
1872 | if (likely(r == 0)) { |
||
1873 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
||
1874 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
1875 | } |
||
1876 | #endif |
||
1877 | return 0; |
||
1878 | } |
||
1879 | |||
1880 | static bool evergreen_card_posted(struct radeon_device *rdev) |
||
1881 | { |
||
1882 | u32 reg; |
||
1883 | |||
1884 | /* first check CRTCs */ |
||
1885 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
||
1886 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
||
1887 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
||
1888 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
||
1889 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
||
1890 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1891 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
||
1892 | return true; |
||
1893 | |||
1894 | /* then check MEM_SIZE, in case the crtcs are off */ |
||
1895 | if (RREG32(CONFIG_MEMSIZE)) |
||
1896 | return true; |
||
1897 | |||
1898 | return false; |
||
1899 | } |
||
1900 | |||
1901 | /* Plan is to move initialization in that function and use |
||
1902 | * helper function so that radeon_device_init pretty much |
||
1903 | * do nothing more than calling asic specific function. This |
||
1904 | * should also allow to remove a bunch of callback function |
||
1905 | * like vram_info. |
||
1906 | */ |
||
1907 | int evergreen_init(struct radeon_device *rdev) |
||
1908 | { |
||
1909 | int r; |
||
1910 | |||
1911 | r = radeon_dummy_page_init(rdev); |
||
1912 | if (r) |
||
1913 | return r; |
||
1914 | /* This don't do much */ |
||
1915 | r = radeon_gem_init(rdev); |
||
1916 | if (r) |
||
1917 | return r; |
||
1918 | /* Read BIOS */ |
||
1919 | if (!radeon_get_bios(rdev)) { |
||
1920 | if (ASIC_IS_AVIVO(rdev)) |
||
1921 | return -EINVAL; |
||
1922 | } |
||
1923 | /* Must be an ATOMBIOS */ |
||
1924 | if (!rdev->is_atom_bios) { |
||
1925 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
||
1926 | return -EINVAL; |
||
1927 | } |
||
1928 | r = radeon_atombios_init(rdev); |
||
1929 | if (r) |
||
1930 | return r; |
||
1931 | /* Post card if necessary */ |
||
1932 | if (!evergreen_card_posted(rdev)) { |
||
1933 | if (!rdev->bios) { |
||
1934 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
1935 | return -EINVAL; |
||
1936 | } |
||
1937 | DRM_INFO("GPU not posted. posting now...\n"); |
||
1938 | atom_asic_init(rdev->mode_info.atom_context); |
||
1939 | } |
||
1940 | /* Initialize scratch registers */ |
||
1941 | r600_scratch_init(rdev); |
||
1942 | /* Initialize surface registers */ |
||
1943 | radeon_surface_init(rdev); |
||
1944 | /* Initialize clocks */ |
||
1945 | radeon_get_clock_info(rdev->ddev); |
||
1946 | /* Fence driver */ |
||
1963 | serge | 1947 | // r = radeon_fence_driver_init(rdev); |
1948 | // if (r) |
||
1949 | // return r; |
||
1430 | serge | 1950 | /* initialize AGP */ |
1951 | if (rdev->flags & RADEON_IS_AGP) { |
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1952 | r = radeon_agp_init(rdev); |
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1953 | if (r) |
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1954 | radeon_agp_disable(rdev); |
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1955 | } |
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1956 | /* initialize memory controller */ |
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1957 | r = evergreen_mc_init(rdev); |
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1958 | if (r) |
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1959 | return r; |
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1960 | /* Memory manager */ |
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1961 | r = radeon_bo_init(rdev); |
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1962 | if (r) |
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1963 | return r; |
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1963 | serge | 1964 | |
1430 | serge | 1965 | r = radeon_irq_kms_init(rdev); |
1966 | if (r) |
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1967 | return r; |
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1968 | |||
1969 | rdev->cp.ring_obj = NULL; |
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1970 | r600_ring_init(rdev, 1024 * 1024); |
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1971 | |||
1963 | serge | 1972 | // rdev->ih.ring_obj = NULL; |
1973 | // r600_ih_ring_init(rdev, 64 * 1024); |
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1430 | serge | 1974 | |
1975 | r = r600_pcie_gart_init(rdev); |
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1976 | if (r) |
||
1977 | return r; |
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1963 | serge | 1978 | |
1979 | rdev->accel_working = true; |
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1430 | serge | 1980 | r = evergreen_startup(rdev); |
1981 | if (r) { |
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1963 | serge | 1982 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1983 | r700_cp_fini(rdev); |
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1984 | r600_irq_fini(rdev); |
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1985 | radeon_irq_kms_fini(rdev); |
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1986 | evergreen_pcie_gart_fini(rdev); |
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1430 | serge | 1987 | rdev->accel_working = false; |
1988 | } |
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1989 | if (rdev->accel_working) { |
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1963 | serge | 1990 | r = radeon_ib_pool_init(rdev); |
1991 | if (r) { |
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1992 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
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1993 | rdev->accel_working = false; |
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1994 | } |
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1995 | r = r600_ib_test(rdev); |
||
1996 | if (r) { |
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1997 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
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1998 | rdev->accel_working = false; |
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1999 | } |
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1430 | serge | 2000 | } |
2001 | return 0; |
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2002 | } |
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2003 | |||
2004 | void evergreen_fini(struct radeon_device *rdev) |
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2005 | { |
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1963 | serge | 2006 | /*r600_blit_fini(rdev);*/ |
2007 | r700_cp_fini(rdev); |
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1430 | serge | 2008 | r600_irq_fini(rdev); |
1963 | serge | 2009 | radeon_wb_fini(rdev); |
1430 | serge | 2010 | radeon_irq_kms_fini(rdev); |
2011 | evergreen_pcie_gart_fini(rdev); |
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1963 | serge | 2012 | radeon_gem_fini(rdev); |
2013 | radeon_fence_driver_fini(rdev); |
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2014 | radeon_agp_fini(rdev); |
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2015 | radeon_bo_fini(rdev); |
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2016 | radeon_atombios_fini(rdev); |
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1430 | serge | 2017 | kfree(rdev->bios); |
2018 | rdev->bios = NULL; |
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1963 | serge | 2019 | radeon_dummy_page_fini(rdev); |
1430 | serge | 2020 | }>>><>>><>><>><>><>><>><>><>><> |