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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #include |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "sid.h" |
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27 | |||
28 | static u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
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29 | u32 block_offset, u32 reg) |
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30 | { |
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31 | unsigned long flags; |
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32 | u32 r; |
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33 | |||
34 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
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35 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
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36 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); |
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37 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
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38 | |||
39 | return r; |
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40 | } |
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41 | |||
42 | static void dce6_endpoint_wreg(struct radeon_device *rdev, |
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43 | u32 block_offset, u32 reg, u32 v) |
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44 | { |
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45 | unsigned long flags; |
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46 | |||
47 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
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48 | if (ASIC_IS_DCE8(rdev)) |
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49 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
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50 | else |
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51 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, |
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52 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); |
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53 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); |
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54 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
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55 | } |
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56 | |||
57 | #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) |
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58 | #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) |
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59 | |||
60 | |||
61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) |
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62 | { |
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63 | int i; |
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64 | u32 offset, tmp; |
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65 | |||
66 | for (i = 0; i < rdev->audio.num_pins; i++) { |
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67 | offset = rdev->audio.pin[i].offset; |
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68 | tmp = RREG32_ENDPOINT(offset, |
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69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
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70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) |
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71 | rdev->audio.pin[i].connected = false; |
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72 | else |
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73 | rdev->audio.pin[i].connected = true; |
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74 | } |
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75 | } |
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76 | |||
77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) |
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78 | { |
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79 | int i; |
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80 | |||
81 | dce6_afmt_get_connected_pins(rdev); |
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82 | |||
83 | for (i = 0; i < rdev->audio.num_pins; i++) { |
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84 | if (rdev->audio.pin[i].connected) |
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85 | return &rdev->audio.pin[i]; |
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86 | } |
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87 | DRM_ERROR("No connected audio pins found!\n"); |
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88 | return NULL; |
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89 | } |
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90 | |||
91 | void dce6_afmt_select_pin(struct drm_encoder *encoder) |
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92 | { |
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93 | struct radeon_device *rdev = encoder->dev->dev_private; |
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94 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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95 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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96 | u32 offset; |
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97 | |||
98 | if (!dig || !dig->afmt || !dig->afmt->pin) |
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99 | return; |
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100 | |||
101 | offset = dig->afmt->offset; |
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102 | |||
103 | WREG32(AFMT_AUDIO_SRC_CONTROL + offset, |
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104 | AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); |
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105 | } |
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106 | |||
107 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
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108 | struct drm_display_mode *mode) |
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109 | { |
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110 | struct radeon_device *rdev = encoder->dev->dev_private; |
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111 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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112 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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113 | struct drm_connector *connector; |
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114 | struct radeon_connector *radeon_connector = NULL; |
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115 | u32 tmp = 0, offset; |
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116 | |||
117 | if (!dig || !dig->afmt || !dig->afmt->pin) |
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118 | return; |
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119 | |||
120 | offset = dig->afmt->pin->offset; |
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121 | |||
122 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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123 | if (connector->encoder == encoder) { |
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124 | radeon_connector = to_radeon_connector(connector); |
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125 | break; |
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126 | } |
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127 | } |
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128 | |||
129 | if (!radeon_connector) { |
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130 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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131 | return; |
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132 | } |
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133 | |||
134 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
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135 | if (connector->latency_present[1]) |
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136 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
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137 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
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138 | else |
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139 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
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140 | } else { |
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141 | if (connector->latency_present[0]) |
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142 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
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143 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
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144 | else |
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145 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
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146 | } |
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147 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
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148 | } |
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149 | |||
150 | void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
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151 | { |
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152 | struct radeon_device *rdev = encoder->dev->dev_private; |
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153 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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154 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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155 | struct drm_connector *connector; |
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156 | struct radeon_connector *radeon_connector = NULL; |
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157 | u32 offset, tmp; |
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5271 | serge | 158 | u8 *sadb = NULL; |
5078 | serge | 159 | int sad_count; |
160 | |||
161 | if (!dig || !dig->afmt || !dig->afmt->pin) |
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162 | return; |
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163 | |||
164 | offset = dig->afmt->pin->offset; |
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165 | |||
166 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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167 | if (connector->encoder == encoder) { |
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168 | radeon_connector = to_radeon_connector(connector); |
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169 | break; |
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170 | } |
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171 | } |
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172 | |||
173 | if (!radeon_connector) { |
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174 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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175 | return; |
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176 | } |
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177 | |||
178 | sad_count = drm_edid_to_speaker_allocation(radeon_connector_edid(connector), &sadb); |
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5179 | serge | 179 | if (sad_count < 0) { |
180 | DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
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181 | sad_count = 0; |
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5078 | serge | 182 | } |
183 | |||
184 | /* program the speaker allocation */ |
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185 | tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
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186 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
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187 | /* set HDMI mode */ |
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188 | tmp |= HDMI_CONNECTION; |
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189 | if (sad_count) |
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190 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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191 | else |
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192 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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193 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
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194 | |||
195 | kfree(sadb); |
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196 | } |
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197 | |||
198 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) |
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199 | { |
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200 | struct radeon_device *rdev = encoder->dev->dev_private; |
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201 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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202 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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203 | u32 offset; |
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204 | struct drm_connector *connector; |
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205 | struct radeon_connector *radeon_connector = NULL; |
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206 | struct cea_sad *sads; |
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207 | int i, sad_count; |
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208 | |||
209 | static const u16 eld_reg_to_type[][2] = { |
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210 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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211 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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212 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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213 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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214 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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215 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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216 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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217 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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218 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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219 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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220 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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221 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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222 | }; |
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223 | |||
224 | if (!dig || !dig->afmt || !dig->afmt->pin) |
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225 | return; |
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226 | |||
227 | offset = dig->afmt->pin->offset; |
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228 | |||
229 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
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230 | if (connector->encoder == encoder) { |
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231 | radeon_connector = to_radeon_connector(connector); |
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232 | break; |
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233 | } |
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234 | } |
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235 | |||
236 | if (!radeon_connector) { |
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237 | DRM_ERROR("Couldn't find encoder's connector\n"); |
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238 | return; |
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239 | } |
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240 | |||
241 | sad_count = drm_edid_to_sad(radeon_connector_edid(connector), &sads); |
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242 | if (sad_count <= 0) { |
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243 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
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244 | return; |
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245 | } |
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246 | BUG_ON(!sads); |
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247 | |||
248 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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249 | u32 value = 0; |
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250 | u8 stereo_freqs = 0; |
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251 | int max_channels = -1; |
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252 | int j; |
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253 | |||
254 | for (j = 0; j < sad_count; j++) { |
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255 | struct cea_sad *sad = &sads[j]; |
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256 | |||
257 | if (sad->format == eld_reg_to_type[i][1]) { |
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258 | if (sad->channels > max_channels) { |
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259 | value = MAX_CHANNELS(sad->channels) | |
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260 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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261 | SUPPORTED_FREQUENCIES(sad->freq); |
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262 | max_channels = sad->channels; |
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263 | } |
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264 | |||
265 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
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266 | stereo_freqs |= sad->freq; |
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267 | else |
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268 | break; |
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269 | } |
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270 | } |
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271 | |||
272 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
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273 | |||
274 | WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); |
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275 | } |
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276 | |||
277 | kfree(sads); |
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278 | } |
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279 | |||
280 | static int dce6_audio_chipset_supported(struct radeon_device *rdev) |
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281 | { |
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282 | return !ASIC_IS_NODCE(rdev); |
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283 | } |
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284 | |||
285 | void dce6_audio_enable(struct radeon_device *rdev, |
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286 | struct r600_audio_pin *pin, |
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5271 | serge | 287 | u8 enable_mask) |
5078 | serge | 288 | { |
289 | if (!pin) |
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290 | return; |
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291 | |||
5271 | serge | 292 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
293 | enable_mask ? AUDIO_ENABLED : 0); |
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5078 | serge | 294 | } |
295 | |||
296 | static const u32 pin_offsets[7] = |
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297 | { |
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298 | (0x5e00 - 0x5e00), |
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299 | (0x5e18 - 0x5e00), |
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300 | (0x5e30 - 0x5e00), |
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301 | (0x5e48 - 0x5e00), |
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302 | (0x5e60 - 0x5e00), |
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303 | (0x5e78 - 0x5e00), |
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304 | (0x5e90 - 0x5e00), |
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305 | }; |
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306 | |||
307 | int dce6_audio_init(struct radeon_device *rdev) |
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308 | { |
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309 | int i; |
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310 | |||
311 | if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) |
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312 | return 0; |
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313 | |||
314 | rdev->audio.enabled = true; |
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315 | |||
316 | if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */ |
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317 | rdev->audio.num_pins = 7; |
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318 | else if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */ |
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319 | rdev->audio.num_pins = 3; |
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320 | else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */ |
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321 | rdev->audio.num_pins = 7; |
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322 | else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */ |
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323 | rdev->audio.num_pins = 6; |
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324 | else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */ |
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325 | rdev->audio.num_pins = 2; |
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326 | else /* SI: 6 streams, 6 endpoints */ |
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327 | rdev->audio.num_pins = 6; |
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328 | |||
329 | for (i = 0; i < rdev->audio.num_pins; i++) { |
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330 | rdev->audio.pin[i].channels = -1; |
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331 | rdev->audio.pin[i].rate = -1; |
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332 | rdev->audio.pin[i].bits_per_sample = -1; |
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333 | rdev->audio.pin[i].status_bits = 0; |
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334 | rdev->audio.pin[i].category_code = 0; |
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335 | rdev->audio.pin[i].connected = false; |
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336 | rdev->audio.pin[i].offset = pin_offsets[i]; |
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337 | rdev->audio.pin[i].id = i; |
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338 | /* disable audio. it will be set up later */ |
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339 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); |
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340 | } |
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341 | |||
342 | return 0; |
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343 | } |
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344 | |||
345 | void dce6_audio_fini(struct radeon_device *rdev) |
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346 | { |
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347 | int i; |
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348 | |||
349 | if (!rdev->audio.enabled) |
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350 | return; |
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351 | |||
352 | for (i = 0; i < rdev->audio.num_pins; i++) |
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353 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); |
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354 | |||
355 | rdev->audio.enabled = false; |
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356 | }>>>>=>>>> |