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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #ifndef __CYPRESS_DPM_H__ |
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24 | #define __CYPRESS_DPM_H__ |
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25 | |||
26 | #include "rv770_dpm.h" |
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27 | #include "evergreen_smc.h" |
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28 | |||
29 | struct evergreen_mc_reg_entry { |
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30 | u32 mclk_max; |
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31 | u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; |
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32 | }; |
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33 | |||
34 | struct evergreen_mc_reg_table { |
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35 | u8 last; |
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36 | u8 num_entries; |
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37 | u16 valid_flag; |
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38 | struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; |
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39 | SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; |
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40 | }; |
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41 | |||
42 | struct evergreen_ulv_param { |
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43 | bool supported; |
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44 | struct rv7xx_pl *pl; |
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45 | }; |
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46 | |||
47 | struct evergreen_arb_registers { |
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48 | u32 mc_arb_dram_timing; |
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49 | u32 mc_arb_dram_timing2; |
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50 | u32 mc_arb_rfsh_rate; |
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51 | u32 mc_arb_burst_time; |
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52 | }; |
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53 | |||
54 | struct at { |
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55 | u32 rlp; |
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56 | u32 rmp; |
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57 | u32 lhp; |
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58 | u32 lmp; |
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59 | }; |
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60 | |||
61 | struct evergreen_power_info { |
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62 | /* must be first! */ |
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63 | struct rv7xx_power_info rv7xx; |
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64 | /* flags */ |
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65 | bool vddci_control; |
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66 | bool dynamic_ac_timing; |
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67 | bool abm; |
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68 | bool mcls; |
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69 | bool light_sleep; |
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70 | bool memory_transition; |
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71 | bool pcie_performance_request; |
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72 | bool pcie_performance_request_registered; |
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73 | bool sclk_deep_sleep; |
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74 | bool dll_default_on; |
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75 | bool ls_clock_gating; |
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76 | bool smu_uvd_hs; |
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77 | bool uvd_enabled; |
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78 | /* stored values */ |
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79 | u16 acpi_vddci; |
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80 | u8 mvdd_high_index; |
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81 | u8 mvdd_low_index; |
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82 | u32 mclk_edc_wr_enable_threshold; |
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83 | struct evergreen_mc_reg_table mc_reg_table; |
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84 | struct atom_voltage_table vddc_voltage_table; |
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85 | struct atom_voltage_table vddci_voltage_table; |
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86 | struct evergreen_arb_registers bootup_arb_registers; |
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87 | struct evergreen_ulv_param ulv; |
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88 | struct at ats[2]; |
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89 | /* smc offsets */ |
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90 | u16 mc_reg_table_start; |
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91 | struct radeon_ps current_rps; |
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92 | struct rv7xx_ps current_ps; |
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93 | struct radeon_ps requested_rps; |
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94 | struct rv7xx_ps requested_ps; |
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95 | }; |
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96 | |||
97 | #define CYPRESS_HASI_DFLT 400000 |
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98 | #define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 |
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99 | #define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 |
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100 | #define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 |
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101 | #define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 |
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102 | #define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 |
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103 | #define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 |
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104 | #define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 |
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105 | #define CYPRESS_VRC_DFLT 0xC00033 |
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106 | |||
107 | #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 |
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108 | #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 |
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109 | #define PCIE_PERF_REQ_PECI_GEN1 2 |
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110 | #define PCIE_PERF_REQ_PECI_GEN2 3 |
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111 | #define PCIE_PERF_REQ_PECI_GEN3 4 |
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112 | |||
113 | int cypress_convert_power_level_to_smc(struct radeon_device *rdev, |
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114 | struct rv7xx_pl *pl, |
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115 | RV770_SMC_HW_PERFORMANCE_LEVEL *level, |
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116 | u8 watermark_level); |
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117 | int cypress_populate_smc_acpi_state(struct radeon_device *rdev, |
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118 | RV770_SMC_STATETABLE *table); |
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119 | int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, |
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120 | RV770_SMC_STATETABLE *table); |
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121 | int cypress_populate_smc_initial_state(struct radeon_device *rdev, |
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122 | struct radeon_ps *radeon_initial_state, |
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123 | RV770_SMC_STATETABLE *table); |
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124 | u32 cypress_calculate_burst_time(struct radeon_device *rdev, |
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125 | u32 engine_clock, u32 memory_clock); |
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126 | void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, |
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127 | struct radeon_ps *radeon_new_state, |
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128 | struct radeon_ps *radeon_current_state); |
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129 | int cypress_upload_sw_state(struct radeon_device *rdev, |
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130 | struct radeon_ps *radeon_new_state); |
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131 | int cypress_upload_mc_reg_table(struct radeon_device *rdev, |
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132 | struct radeon_ps *radeon_new_state); |
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133 | void cypress_program_memory_timing_parameters(struct radeon_device *rdev, |
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134 | struct radeon_ps *radeon_new_state); |
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135 | void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, |
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136 | struct radeon_ps *radeon_new_state, |
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137 | struct radeon_ps *radeon_current_state); |
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138 | int cypress_construct_voltage_tables(struct radeon_device *rdev); |
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139 | int cypress_get_mvdd_configuration(struct radeon_device *rdev); |
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140 | void cypress_enable_spread_spectrum(struct radeon_device *rdev, |
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141 | bool enable); |
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142 | void cypress_enable_display_gap(struct radeon_device *rdev); |
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143 | int cypress_get_table_locations(struct radeon_device *rdev); |
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144 | int cypress_populate_mc_reg_table(struct radeon_device *rdev, |
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145 | struct radeon_ps *radeon_boot_state); |
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146 | void cypress_program_response_times(struct radeon_device *rdev); |
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147 | int cypress_notify_smc_display_change(struct radeon_device *rdev, |
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148 | bool has_display); |
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149 | void cypress_enable_sclk_control(struct radeon_device *rdev, |
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150 | bool enable); |
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151 | void cypress_enable_mclk_control(struct radeon_device *rdev, |
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152 | bool enable); |
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153 | void cypress_start_dpm(struct radeon_device *rdev); |
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154 | void cypress_advertise_gen2_capability(struct radeon_device *rdev); |
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155 | u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); |
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156 | u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, |
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157 | u32 memory_clock, bool strobe_mode); |
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158 | u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk); |
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159 | |||
160 | #endif |