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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5078 | serge | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |||
| 24 | static const u32 SECT_CONTEXT_def_1[] = |
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| 25 | { |
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| 26 | 0x00000000, // DB_RENDER_CONTROL |
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| 27 | 0x00000000, // DB_COUNT_CONTROL |
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| 28 | 0x00000000, // DB_DEPTH_VIEW |
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| 29 | 0x00000000, // DB_RENDER_OVERRIDE |
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| 30 | 0x00000000, // DB_RENDER_OVERRIDE2 |
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| 31 | 0x00000000, // DB_HTILE_DATA_BASE |
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| 32 | 0, // HOLE |
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| 33 | 0, // HOLE |
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| 34 | 0, // HOLE |
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| 35 | 0, // HOLE |
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| 36 | 0x00000000, // DB_STENCIL_CLEAR |
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| 37 | 0x00000000, // DB_DEPTH_CLEAR |
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| 38 | 0x00000000, // PA_SC_SCREEN_SCISSOR_TL |
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| 39 | 0x40004000, // PA_SC_SCREEN_SCISSOR_BR |
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| 40 | 0, // HOLE |
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| 41 | 0, // HOLE |
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| 42 | 0x00000000, // DB_Z_INFO |
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| 43 | 0x00000000, // DB_STENCIL_INFO |
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| 44 | 0x00000000, // DB_Z_READ_BASE |
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| 45 | 0x00000000, // DB_STENCIL_READ_BASE |
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| 46 | 0x00000000, // DB_Z_WRITE_BASE |
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| 47 | 0x00000000, // DB_STENCIL_WRITE_BASE |
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| 48 | 0x00000000, // DB_DEPTH_SIZE |
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| 49 | 0x00000000, // DB_DEPTH_SLICE |
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| 50 | 0, // HOLE |
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| 51 | 0, // HOLE |
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| 52 | 0, // HOLE |
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| 53 | 0, // HOLE |
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| 54 | 0, // HOLE |
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| 55 | 0, // HOLE |
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| 56 | 0, // HOLE |
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| 57 | 0, // HOLE |
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| 58 | 0, // HOLE |
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| 59 | 0, // HOLE |
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| 60 | 0, // HOLE |
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| 61 | 0, // HOLE |
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| 62 | 0, // HOLE |
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| 63 | 0, // HOLE |
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| 64 | 0, // HOLE |
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| 65 | 0, // HOLE |
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| 66 | 0, // HOLE |
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| 67 | 0, // HOLE |
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| 68 | 0, // HOLE |
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| 69 | 0, // HOLE |
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| 70 | 0, // HOLE |
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| 71 | 0, // HOLE |
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| 72 | 0, // HOLE |
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| 73 | 0, // HOLE |
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| 74 | 0, // HOLE |
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| 75 | 0, // HOLE |
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| 76 | 0, // HOLE |
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| 77 | 0, // HOLE |
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| 78 | 0, // HOLE |
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| 79 | 0, // HOLE |
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| 80 | 0, // HOLE |
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| 81 | 0, // HOLE |
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| 82 | 0, // HOLE |
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| 83 | 0, // HOLE |
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| 84 | 0, // HOLE |
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| 85 | 0, // HOLE |
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| 86 | 0, // HOLE |
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| 87 | 0, // HOLE |
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| 88 | 0, // HOLE |
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| 89 | 0, // HOLE |
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| 90 | 0, // HOLE |
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| 91 | 0, // HOLE |
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| 92 | 0, // HOLE |
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| 93 | 0, // HOLE |
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| 94 | 0, // HOLE |
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| 95 | 0, // HOLE |
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| 96 | 0, // HOLE |
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| 97 | 0, // HOLE |
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| 98 | 0, // HOLE |
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| 99 | 0, // HOLE |
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| 100 | 0, // HOLE |
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| 101 | 0, // HOLE |
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| 102 | 0, // HOLE |
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| 103 | 0, // HOLE |
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| 104 | 0, // HOLE |
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| 105 | 0, // HOLE |
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| 106 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_0 |
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| 107 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_1 |
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| 108 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_2 |
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| 109 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_3 |
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| 110 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_4 |
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| 111 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_5 |
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| 112 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_6 |
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| 113 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_7 |
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| 114 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_8 |
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| 115 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_9 |
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| 116 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_10 |
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| 117 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_11 |
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| 118 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_12 |
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| 119 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_13 |
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| 120 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_14 |
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| 121 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_PS_15 |
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| 122 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_0 |
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| 123 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_1 |
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| 124 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_2 |
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| 125 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_3 |
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| 126 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_4 |
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| 127 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_5 |
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| 128 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_6 |
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| 129 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_7 |
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| 130 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_8 |
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| 131 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_9 |
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| 132 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_10 |
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| 133 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_11 |
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| 134 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_12 |
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| 135 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_13 |
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| 136 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_14 |
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| 137 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_VS_15 |
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| 138 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_0 |
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| 139 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_1 |
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| 140 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_2 |
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| 141 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_3 |
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| 142 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_4 |
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| 143 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_5 |
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| 144 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_6 |
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| 145 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_7 |
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| 146 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_8 |
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| 147 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_9 |
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| 148 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_10 |
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| 149 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_11 |
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| 150 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_12 |
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| 151 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_13 |
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| 152 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_14 |
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| 153 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_GS_15 |
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| 154 | 0x00000000, // PA_SC_WINDOW_OFFSET |
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| 155 | 0x80000000, // PA_SC_WINDOW_SCISSOR_TL |
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| 156 | 0x40004000, // PA_SC_WINDOW_SCISSOR_BR |
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| 157 | 0x0000ffff, // PA_SC_CLIPRECT_RULE |
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| 158 | 0x00000000, // PA_SC_CLIPRECT_0_TL |
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| 159 | 0x40004000, // PA_SC_CLIPRECT_0_BR |
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| 160 | 0x00000000, // PA_SC_CLIPRECT_1_TL |
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| 161 | 0x40004000, // PA_SC_CLIPRECT_1_BR |
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| 162 | 0x00000000, // PA_SC_CLIPRECT_2_TL |
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| 163 | 0x40004000, // PA_SC_CLIPRECT_2_BR |
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| 164 | 0x00000000, // PA_SC_CLIPRECT_3_TL |
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| 165 | 0x40004000, // PA_SC_CLIPRECT_3_BR |
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| 166 | 0xaa99aaaa, // PA_SC_EDGERULE |
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| 167 | 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET |
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| 168 | 0xffffffff, // CB_TARGET_MASK |
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| 169 | 0xffffffff, // CB_SHADER_MASK |
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| 170 | 0x80000000, // PA_SC_GENERIC_SCISSOR_TL |
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| 171 | 0x40004000, // PA_SC_GENERIC_SCISSOR_BR |
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| 172 | 0x00000000, // COHER_DEST_BASE_0 |
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| 173 | 0x00000000, // COHER_DEST_BASE_1 |
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| 174 | 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL |
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| 175 | 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR |
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| 176 | 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL |
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| 177 | 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR |
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| 178 | 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL |
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| 179 | 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR |
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| 180 | 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL |
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| 181 | 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR |
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| 182 | 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL |
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| 183 | 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR |
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| 184 | 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL |
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| 185 | 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR |
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| 186 | 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL |
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| 187 | 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR |
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| 188 | 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL |
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| 189 | 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR |
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| 190 | 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL |
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| 191 | 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR |
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| 192 | 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL |
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| 193 | 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR |
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| 194 | 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL |
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| 195 | 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR |
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| 196 | 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL |
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| 197 | 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR |
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| 198 | 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL |
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| 199 | 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR |
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| 200 | 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL |
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| 201 | 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR |
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| 202 | 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL |
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| 203 | 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR |
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| 204 | 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL |
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| 205 | 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR |
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| 206 | 0x00000000, // PA_SC_VPORT_ZMIN_0 |
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| 207 | 0x3f800000, // PA_SC_VPORT_ZMAX_0 |
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| 208 | 0x00000000, // PA_SC_VPORT_ZMIN_1 |
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| 209 | 0x3f800000, // PA_SC_VPORT_ZMAX_1 |
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| 210 | 0x00000000, // PA_SC_VPORT_ZMIN_2 |
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| 211 | 0x3f800000, // PA_SC_VPORT_ZMAX_2 |
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| 212 | 0x00000000, // PA_SC_VPORT_ZMIN_3 |
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| 213 | 0x3f800000, // PA_SC_VPORT_ZMAX_3 |
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| 214 | 0x00000000, // PA_SC_VPORT_ZMIN_4 |
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| 215 | 0x3f800000, // PA_SC_VPORT_ZMAX_4 |
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| 216 | 0x00000000, // PA_SC_VPORT_ZMIN_5 |
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| 217 | 0x3f800000, // PA_SC_VPORT_ZMAX_5 |
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| 218 | 0x00000000, // PA_SC_VPORT_ZMIN_6 |
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| 219 | 0x3f800000, // PA_SC_VPORT_ZMAX_6 |
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| 220 | 0x00000000, // PA_SC_VPORT_ZMIN_7 |
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| 221 | 0x3f800000, // PA_SC_VPORT_ZMAX_7 |
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| 222 | 0x00000000, // PA_SC_VPORT_ZMIN_8 |
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| 223 | 0x3f800000, // PA_SC_VPORT_ZMAX_8 |
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| 224 | 0x00000000, // PA_SC_VPORT_ZMIN_9 |
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| 225 | 0x3f800000, // PA_SC_VPORT_ZMAX_9 |
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| 226 | 0x00000000, // PA_SC_VPORT_ZMIN_10 |
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| 227 | 0x3f800000, // PA_SC_VPORT_ZMAX_10 |
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| 228 | 0x00000000, // PA_SC_VPORT_ZMIN_11 |
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| 229 | 0x3f800000, // PA_SC_VPORT_ZMAX_11 |
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| 230 | 0x00000000, // PA_SC_VPORT_ZMIN_12 |
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| 231 | 0x3f800000, // PA_SC_VPORT_ZMAX_12 |
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| 232 | 0x00000000, // PA_SC_VPORT_ZMIN_13 |
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| 233 | 0x3f800000, // PA_SC_VPORT_ZMAX_13 |
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| 234 | 0x00000000, // PA_SC_VPORT_ZMIN_14 |
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| 235 | 0x3f800000, // PA_SC_VPORT_ZMAX_14 |
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| 236 | 0x00000000, // PA_SC_VPORT_ZMIN_15 |
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| 237 | 0x3f800000, // PA_SC_VPORT_ZMAX_15 |
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| 238 | 0x00000000, // SX_MISC |
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| 239 | 0x00000000, // SX_SURFACE_SYNC |
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| 240 | 0x00000000, // CP_PERFMON_CNTX_CNTL |
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| 241 | 0, // HOLE |
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| 242 | 0, // HOLE |
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| 243 | 0, // HOLE |
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| 244 | 0, // HOLE |
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| 245 | 0, // HOLE |
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| 246 | 0, // HOLE |
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| 247 | 0, // HOLE |
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| 248 | 0, // HOLE |
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| 249 | 0, // HOLE |
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| 250 | 0x00000000, // SQ_VTX_SEMANTIC_0 |
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| 251 | 0x00000000, // SQ_VTX_SEMANTIC_1 |
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| 252 | 0x00000000, // SQ_VTX_SEMANTIC_2 |
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| 253 | 0x00000000, // SQ_VTX_SEMANTIC_3 |
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| 254 | 0x00000000, // SQ_VTX_SEMANTIC_4 |
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| 255 | 0x00000000, // SQ_VTX_SEMANTIC_5 |
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| 256 | 0x00000000, // SQ_VTX_SEMANTIC_6 |
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| 257 | 0x00000000, // SQ_VTX_SEMANTIC_7 |
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| 258 | 0x00000000, // SQ_VTX_SEMANTIC_8 |
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| 259 | 0x00000000, // SQ_VTX_SEMANTIC_9 |
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| 260 | 0x00000000, // SQ_VTX_SEMANTIC_10 |
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| 261 | 0x00000000, // SQ_VTX_SEMANTIC_11 |
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| 262 | 0x00000000, // SQ_VTX_SEMANTIC_12 |
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| 263 | 0x00000000, // SQ_VTX_SEMANTIC_13 |
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| 264 | 0x00000000, // SQ_VTX_SEMANTIC_14 |
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| 265 | 0x00000000, // SQ_VTX_SEMANTIC_15 |
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| 266 | 0x00000000, // SQ_VTX_SEMANTIC_16 |
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| 267 | 0x00000000, // SQ_VTX_SEMANTIC_17 |
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| 268 | 0x00000000, // SQ_VTX_SEMANTIC_18 |
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| 269 | 0x00000000, // SQ_VTX_SEMANTIC_19 |
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| 270 | 0x00000000, // SQ_VTX_SEMANTIC_20 |
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| 271 | 0x00000000, // SQ_VTX_SEMANTIC_21 |
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| 272 | 0x00000000, // SQ_VTX_SEMANTIC_22 |
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| 273 | 0x00000000, // SQ_VTX_SEMANTIC_23 |
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| 274 | 0x00000000, // SQ_VTX_SEMANTIC_24 |
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| 275 | 0x00000000, // SQ_VTX_SEMANTIC_25 |
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| 276 | 0x00000000, // SQ_VTX_SEMANTIC_26 |
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| 277 | 0x00000000, // SQ_VTX_SEMANTIC_27 |
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| 278 | 0x00000000, // SQ_VTX_SEMANTIC_28 |
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| 279 | 0x00000000, // SQ_VTX_SEMANTIC_29 |
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| 280 | 0x00000000, // SQ_VTX_SEMANTIC_30 |
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| 281 | 0x00000000, // SQ_VTX_SEMANTIC_31 |
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| 282 | 0xffffffff, // VGT_MAX_VTX_INDX |
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| 283 | 0x00000000, // VGT_MIN_VTX_INDX |
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| 284 | 0x00000000, // VGT_INDX_OFFSET |
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| 285 | 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX |
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| 286 | 0x00000000, // SX_ALPHA_TEST_CONTROL |
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| 287 | 0x00000000, // CB_BLEND_RED |
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| 288 | 0x00000000, // CB_BLEND_GREEN |
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| 289 | 0x00000000, // CB_BLEND_BLUE |
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| 290 | 0x00000000, // CB_BLEND_ALPHA |
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| 291 | 0, // HOLE |
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| 292 | 0, // HOLE |
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| 293 | 0, // HOLE |
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| 294 | 0x00000000, // DB_STENCILREFMASK |
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| 295 | 0x00000000, // DB_STENCILREFMASK_BF |
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| 296 | 0x00000000, // SX_ALPHA_REF |
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| 297 | 0x00000000, // PA_CL_VPORT_XSCALE |
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| 298 | 0x00000000, // PA_CL_VPORT_XOFFSET |
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| 299 | 0x00000000, // PA_CL_VPORT_YSCALE |
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| 300 | 0x00000000, // PA_CL_VPORT_YOFFSET |
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| 301 | 0x00000000, // PA_CL_VPORT_ZSCALE |
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| 302 | 0x00000000, // PA_CL_VPORT_ZOFFSET |
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| 303 | 0x00000000, // PA_CL_VPORT_XSCALE_1 |
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| 304 | 0x00000000, // PA_CL_VPORT_XOFFSET_1 |
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| 305 | 0x00000000, // PA_CL_VPORT_YSCALE_1 |
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| 306 | 0x00000000, // PA_CL_VPORT_YOFFSET_1 |
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| 307 | 0x00000000, // PA_CL_VPORT_ZSCALE_1 |
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| 308 | 0x00000000, // PA_CL_VPORT_ZOFFSET_1 |
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| 309 | 0x00000000, // PA_CL_VPORT_XSCALE_2 |
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| 310 | 0x00000000, // PA_CL_VPORT_XOFFSET_2 |
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| 311 | 0x00000000, // PA_CL_VPORT_YSCALE_2 |
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| 312 | 0x00000000, // PA_CL_VPORT_YOFFSET_2 |
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| 313 | 0x00000000, // PA_CL_VPORT_ZSCALE_2 |
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| 314 | 0x00000000, // PA_CL_VPORT_ZOFFSET_2 |
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| 315 | 0x00000000, // PA_CL_VPORT_XSCALE_3 |
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| 316 | 0x00000000, // PA_CL_VPORT_XOFFSET_3 |
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| 317 | 0x00000000, // PA_CL_VPORT_YSCALE_3 |
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| 318 | 0x00000000, // PA_CL_VPORT_YOFFSET_3 |
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| 319 | 0x00000000, // PA_CL_VPORT_ZSCALE_3 |
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| 320 | 0x00000000, // PA_CL_VPORT_ZOFFSET_3 |
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| 321 | 0x00000000, // PA_CL_VPORT_XSCALE_4 |
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| 322 | 0x00000000, // PA_CL_VPORT_XOFFSET_4 |
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| 323 | 0x00000000, // PA_CL_VPORT_YSCALE_4 |
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| 324 | 0x00000000, // PA_CL_VPORT_YOFFSET_4 |
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| 325 | 0x00000000, // PA_CL_VPORT_ZSCALE_4 |
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| 326 | 0x00000000, // PA_CL_VPORT_ZOFFSET_4 |
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| 327 | 0x00000000, // PA_CL_VPORT_XSCALE_5 |
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| 328 | 0x00000000, // PA_CL_VPORT_XOFFSET_5 |
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| 329 | 0x00000000, // PA_CL_VPORT_YSCALE_5 |
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| 330 | 0x00000000, // PA_CL_VPORT_YOFFSET_5 |
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| 331 | 0x00000000, // PA_CL_VPORT_ZSCALE_5 |
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| 332 | 0x00000000, // PA_CL_VPORT_ZOFFSET_5 |
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| 333 | 0x00000000, // PA_CL_VPORT_XSCALE_6 |
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| 334 | 0x00000000, // PA_CL_VPORT_XOFFSET_6 |
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| 335 | 0x00000000, // PA_CL_VPORT_YSCALE_6 |
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| 336 | 0x00000000, // PA_CL_VPORT_YOFFSET_6 |
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| 337 | 0x00000000, // PA_CL_VPORT_ZSCALE_6 |
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| 338 | 0x00000000, // PA_CL_VPORT_ZOFFSET_6 |
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| 339 | 0x00000000, // PA_CL_VPORT_XSCALE_7 |
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| 340 | 0x00000000, // PA_CL_VPORT_XOFFSET_7 |
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| 341 | 0x00000000, // PA_CL_VPORT_YSCALE_7 |
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| 342 | 0x00000000, // PA_CL_VPORT_YOFFSET_7 |
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| 343 | 0x00000000, // PA_CL_VPORT_ZSCALE_7 |
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| 344 | 0x00000000, // PA_CL_VPORT_ZOFFSET_7 |
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| 345 | 0x00000000, // PA_CL_VPORT_XSCALE_8 |
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| 346 | 0x00000000, // PA_CL_VPORT_XOFFSET_8 |
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| 347 | 0x00000000, // PA_CL_VPORT_YSCALE_8 |
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| 348 | 0x00000000, // PA_CL_VPORT_YOFFSET_8 |
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| 349 | 0x00000000, // PA_CL_VPORT_ZSCALE_8 |
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| 350 | 0x00000000, // PA_CL_VPORT_ZOFFSET_8 |
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| 351 | 0x00000000, // PA_CL_VPORT_XSCALE_9 |
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| 352 | 0x00000000, // PA_CL_VPORT_XOFFSET_9 |
||
| 353 | 0x00000000, // PA_CL_VPORT_YSCALE_9 |
||
| 354 | 0x00000000, // PA_CL_VPORT_YOFFSET_9 |
||
| 355 | 0x00000000, // PA_CL_VPORT_ZSCALE_9 |
||
| 356 | 0x00000000, // PA_CL_VPORT_ZOFFSET_9 |
||
| 357 | 0x00000000, // PA_CL_VPORT_XSCALE_10 |
||
| 358 | 0x00000000, // PA_CL_VPORT_XOFFSET_10 |
||
| 359 | 0x00000000, // PA_CL_VPORT_YSCALE_10 |
||
| 360 | 0x00000000, // PA_CL_VPORT_YOFFSET_10 |
||
| 361 | 0x00000000, // PA_CL_VPORT_ZSCALE_10 |
||
| 362 | 0x00000000, // PA_CL_VPORT_ZOFFSET_10 |
||
| 363 | 0x00000000, // PA_CL_VPORT_XSCALE_11 |
||
| 364 | 0x00000000, // PA_CL_VPORT_XOFFSET_11 |
||
| 365 | 0x00000000, // PA_CL_VPORT_YSCALE_11 |
||
| 366 | 0x00000000, // PA_CL_VPORT_YOFFSET_11 |
||
| 367 | 0x00000000, // PA_CL_VPORT_ZSCALE_11 |
||
| 368 | 0x00000000, // PA_CL_VPORT_ZOFFSET_11 |
||
| 369 | 0x00000000, // PA_CL_VPORT_XSCALE_12 |
||
| 370 | 0x00000000, // PA_CL_VPORT_XOFFSET_12 |
||
| 371 | 0x00000000, // PA_CL_VPORT_YSCALE_12 |
||
| 372 | 0x00000000, // PA_CL_VPORT_YOFFSET_12 |
||
| 373 | 0x00000000, // PA_CL_VPORT_ZSCALE_12 |
||
| 374 | 0x00000000, // PA_CL_VPORT_ZOFFSET_12 |
||
| 375 | 0x00000000, // PA_CL_VPORT_XSCALE_13 |
||
| 376 | 0x00000000, // PA_CL_VPORT_XOFFSET_13 |
||
| 377 | 0x00000000, // PA_CL_VPORT_YSCALE_13 |
||
| 378 | 0x00000000, // PA_CL_VPORT_YOFFSET_13 |
||
| 379 | 0x00000000, // PA_CL_VPORT_ZSCALE_13 |
||
| 380 | 0x00000000, // PA_CL_VPORT_ZOFFSET_13 |
||
| 381 | 0x00000000, // PA_CL_VPORT_XSCALE_14 |
||
| 382 | 0x00000000, // PA_CL_VPORT_XOFFSET_14 |
||
| 383 | 0x00000000, // PA_CL_VPORT_YSCALE_14 |
||
| 384 | 0x00000000, // PA_CL_VPORT_YOFFSET_14 |
||
| 385 | 0x00000000, // PA_CL_VPORT_ZSCALE_14 |
||
| 386 | 0x00000000, // PA_CL_VPORT_ZOFFSET_14 |
||
| 387 | 0x00000000, // PA_CL_VPORT_XSCALE_15 |
||
| 388 | 0x00000000, // PA_CL_VPORT_XOFFSET_15 |
||
| 389 | 0x00000000, // PA_CL_VPORT_YSCALE_15 |
||
| 390 | 0x00000000, // PA_CL_VPORT_YOFFSET_15 |
||
| 391 | 0x00000000, // PA_CL_VPORT_ZSCALE_15 |
||
| 392 | 0x00000000, // PA_CL_VPORT_ZOFFSET_15 |
||
| 393 | 0x00000000, // PA_CL_UCP_0_X |
||
| 394 | 0x00000000, // PA_CL_UCP_0_Y |
||
| 395 | 0x00000000, // PA_CL_UCP_0_Z |
||
| 396 | 0x00000000, // PA_CL_UCP_0_W |
||
| 397 | 0x00000000, // PA_CL_UCP_1_X |
||
| 398 | 0x00000000, // PA_CL_UCP_1_Y |
||
| 399 | 0x00000000, // PA_CL_UCP_1_Z |
||
| 400 | 0x00000000, // PA_CL_UCP_1_W |
||
| 401 | 0x00000000, // PA_CL_UCP_2_X |
||
| 402 | 0x00000000, // PA_CL_UCP_2_Y |
||
| 403 | 0x00000000, // PA_CL_UCP_2_Z |
||
| 404 | 0x00000000, // PA_CL_UCP_2_W |
||
| 405 | 0x00000000, // PA_CL_UCP_3_X |
||
| 406 | 0x00000000, // PA_CL_UCP_3_Y |
||
| 407 | 0x00000000, // PA_CL_UCP_3_Z |
||
| 408 | 0x00000000, // PA_CL_UCP_3_W |
||
| 409 | 0x00000000, // PA_CL_UCP_4_X |
||
| 410 | 0x00000000, // PA_CL_UCP_4_Y |
||
| 411 | 0x00000000, // PA_CL_UCP_4_Z |
||
| 412 | 0x00000000, // PA_CL_UCP_4_W |
||
| 413 | 0x00000000, // PA_CL_UCP_5_X |
||
| 414 | 0x00000000, // PA_CL_UCP_5_Y |
||
| 415 | 0x00000000, // PA_CL_UCP_5_Z |
||
| 416 | 0x00000000, // PA_CL_UCP_5_W |
||
| 417 | 0x00000000, // SPI_VS_OUT_ID_0 |
||
| 418 | 0x00000000, // SPI_VS_OUT_ID_1 |
||
| 419 | 0x00000000, // SPI_VS_OUT_ID_2 |
||
| 420 | 0x00000000, // SPI_VS_OUT_ID_3 |
||
| 421 | 0x00000000, // SPI_VS_OUT_ID_4 |
||
| 422 | 0x00000000, // SPI_VS_OUT_ID_5 |
||
| 423 | 0x00000000, // SPI_VS_OUT_ID_6 |
||
| 424 | 0x00000000, // SPI_VS_OUT_ID_7 |
||
| 425 | 0x00000000, // SPI_VS_OUT_ID_8 |
||
| 426 | 0x00000000, // SPI_VS_OUT_ID_9 |
||
| 427 | 0x00000000, // SPI_PS_INPUT_CNTL_0 |
||
| 428 | 0x00000000, // SPI_PS_INPUT_CNTL_1 |
||
| 429 | 0x00000000, // SPI_PS_INPUT_CNTL_2 |
||
| 430 | 0x00000000, // SPI_PS_INPUT_CNTL_3 |
||
| 431 | 0x00000000, // SPI_PS_INPUT_CNTL_4 |
||
| 432 | 0x00000000, // SPI_PS_INPUT_CNTL_5 |
||
| 433 | 0x00000000, // SPI_PS_INPUT_CNTL_6 |
||
| 434 | 0x00000000, // SPI_PS_INPUT_CNTL_7 |
||
| 435 | 0x00000000, // SPI_PS_INPUT_CNTL_8 |
||
| 436 | 0x00000000, // SPI_PS_INPUT_CNTL_9 |
||
| 437 | 0x00000000, // SPI_PS_INPUT_CNTL_10 |
||
| 438 | 0x00000000, // SPI_PS_INPUT_CNTL_11 |
||
| 439 | 0x00000000, // SPI_PS_INPUT_CNTL_12 |
||
| 440 | 0x00000000, // SPI_PS_INPUT_CNTL_13 |
||
| 441 | 0x00000000, // SPI_PS_INPUT_CNTL_14 |
||
| 442 | 0x00000000, // SPI_PS_INPUT_CNTL_15 |
||
| 443 | 0x00000000, // SPI_PS_INPUT_CNTL_16 |
||
| 444 | 0x00000000, // SPI_PS_INPUT_CNTL_17 |
||
| 445 | 0x00000000, // SPI_PS_INPUT_CNTL_18 |
||
| 446 | 0x00000000, // SPI_PS_INPUT_CNTL_19 |
||
| 447 | 0x00000000, // SPI_PS_INPUT_CNTL_20 |
||
| 448 | 0x00000000, // SPI_PS_INPUT_CNTL_21 |
||
| 449 | 0x00000000, // SPI_PS_INPUT_CNTL_22 |
||
| 450 | 0x00000000, // SPI_PS_INPUT_CNTL_23 |
||
| 451 | 0x00000000, // SPI_PS_INPUT_CNTL_24 |
||
| 452 | 0x00000000, // SPI_PS_INPUT_CNTL_25 |
||
| 453 | 0x00000000, // SPI_PS_INPUT_CNTL_26 |
||
| 454 | 0x00000000, // SPI_PS_INPUT_CNTL_27 |
||
| 455 | 0x00000000, // SPI_PS_INPUT_CNTL_28 |
||
| 456 | 0x00000000, // SPI_PS_INPUT_CNTL_29 |
||
| 457 | 0x00000000, // SPI_PS_INPUT_CNTL_30 |
||
| 458 | 0x00000000, // SPI_PS_INPUT_CNTL_31 |
||
| 459 | 0x00000000, // SPI_VS_OUT_CONFIG |
||
| 460 | 0x00000001, // SPI_THREAD_GROUPING |
||
| 461 | 0x00000000, // SPI_PS_IN_CONTROL_0 |
||
| 462 | 0x00000000, // SPI_PS_IN_CONTROL_1 |
||
| 463 | 0x00000000, // SPI_INTERP_CONTROL_0 |
||
| 464 | 0x00000000, // SPI_INPUT_Z |
||
| 465 | 0x00000000, // SPI_FOG_CNTL |
||
| 466 | 0x00000000, // SPI_BARYC_CNTL |
||
| 467 | 0x00000000, // SPI_PS_IN_CONTROL_2 |
||
| 468 | 0x00000000, // SPI_COMPUTE_INPUT_CNTL |
||
| 469 | 0x00000000, // SPI_COMPUTE_NUM_THREAD_X |
||
| 470 | 0x00000000, // SPI_COMPUTE_NUM_THREAD_Y |
||
| 471 | 0x00000000, // SPI_COMPUTE_NUM_THREAD_Z |
||
| 472 | 0, // HOLE |
||
| 473 | 0, // HOLE |
||
| 474 | 0, // HOLE |
||
| 475 | 0, // HOLE |
||
| 476 | 0, // HOLE |
||
| 477 | 0, // HOLE |
||
| 478 | 0, // HOLE |
||
| 479 | 0, // HOLE |
||
| 480 | 0, // HOLE |
||
| 481 | 0, // HOLE |
||
| 482 | 0x00000000, // GDS_ADDR_BASE |
||
| 483 | 0x00003fff, // GDS_ADDR_SIZE |
||
| 484 | 0x00000001, // GDS_ORDERED_WAVE_PER_SE |
||
| 485 | 0x00000000, // GDS_APPEND_CONSUME_UAV0 |
||
| 486 | 0x00000000, // GDS_APPEND_CONSUME_UAV1 |
||
| 487 | 0x00000000, // GDS_APPEND_CONSUME_UAV2 |
||
| 488 | 0x00000000, // GDS_APPEND_CONSUME_UAV3 |
||
| 489 | 0x00000000, // GDS_APPEND_CONSUME_UAV4 |
||
| 490 | 0x00000000, // GDS_APPEND_CONSUME_UAV5 |
||
| 491 | 0x00000000, // GDS_APPEND_CONSUME_UAV6 |
||
| 492 | 0x00000000, // GDS_APPEND_CONSUME_UAV7 |
||
| 493 | 0x00000000, // GDS_APPEND_CONSUME_UAV8 |
||
| 494 | 0x00000000, // GDS_APPEND_CONSUME_UAV9 |
||
| 495 | 0x00000000, // GDS_APPEND_CONSUME_UAV10 |
||
| 496 | 0x00000000, // GDS_APPEND_CONSUME_UAV11 |
||
| 497 | 0, // HOLE |
||
| 498 | 0, // HOLE |
||
| 499 | 0, // HOLE |
||
| 500 | 0, // HOLE |
||
| 501 | 0, // HOLE |
||
| 502 | 0, // HOLE |
||
| 503 | 0, // HOLE |
||
| 504 | 0, // HOLE |
||
| 505 | 0, // HOLE |
||
| 506 | 0x00000000, // CB_BLEND0_CONTROL |
||
| 507 | 0x00000000, // CB_BLEND1_CONTROL |
||
| 508 | 0x00000000, // CB_BLEND2_CONTROL |
||
| 509 | 0x00000000, // CB_BLEND3_CONTROL |
||
| 510 | 0x00000000, // CB_BLEND4_CONTROL |
||
| 511 | 0x00000000, // CB_BLEND5_CONTROL |
||
| 512 | 0x00000000, // CB_BLEND6_CONTROL |
||
| 513 | 0x00000000, // CB_BLEND7_CONTROL |
||
| 514 | }; |
||
| 515 | static const u32 SECT_CONTEXT_def_2[] = |
||
| 516 | { |
||
| 517 | 0x00000000, // PA_CL_POINT_X_RAD |
||
| 518 | 0x00000000, // PA_CL_POINT_Y_RAD |
||
| 519 | 0x00000000, // PA_CL_POINT_SIZE |
||
| 520 | 0x00000000, // PA_CL_POINT_CULL_RAD |
||
| 521 | 0x00000000, // VGT_DMA_BASE_HI |
||
| 522 | 0x00000000, // VGT_DMA_BASE |
||
| 523 | }; |
||
| 524 | static const u32 SECT_CONTEXT_def_3[] = |
||
| 525 | { |
||
| 526 | 0x00000000, // DB_DEPTH_CONTROL |
||
| 527 | 0, // HOLE |
||
| 528 | 0x00000000, // CB_COLOR_CONTROL |
||
| 529 | 0x00000200, // DB_SHADER_CONTROL |
||
| 530 | 0x00000000, // PA_CL_CLIP_CNTL |
||
| 531 | 0x00000000, // PA_SU_SC_MODE_CNTL |
||
| 532 | 0x00000000, // PA_CL_VTE_CNTL |
||
| 533 | 0x00000000, // PA_CL_VS_OUT_CNTL |
||
| 534 | 0x00000000, // PA_CL_NANINF_CNTL |
||
| 535 | 0x00000000, // PA_SU_LINE_STIPPLE_CNTL |
||
| 536 | 0x00000000, // PA_SU_LINE_STIPPLE_SCALE |
||
| 537 | 0x00000000, // PA_SU_PRIM_FILTER_CNTL |
||
| 538 | 0x00000000, // SQ_LSTMP_RING_ITEMSIZE |
||
| 539 | 0x00000000, // SQ_HSTMP_RING_ITEMSIZE |
||
| 540 | 0x00000000, // SQ_DYN_GPR_RESOURCE_LIMIT_1 |
||
| 541 | 0, // HOLE |
||
| 542 | 0x00000000, // SQ_PGM_START_PS |
||
| 543 | 0x00000000, // SQ_PGM_RESOURCES_PS |
||
| 544 | 0x00000000, // SQ_PGM_RESOURCES_2_PS |
||
| 545 | 0x00000000, // SQ_PGM_EXPORTS_PS |
||
| 546 | 0, // HOLE |
||
| 547 | 0, // HOLE |
||
| 548 | 0, // HOLE |
||
| 549 | 0x00000000, // SQ_PGM_START_VS |
||
| 550 | 0x00000000, // SQ_PGM_RESOURCES_VS |
||
| 551 | 0x00000000, // SQ_PGM_RESOURCES_2_VS |
||
| 552 | 0, // HOLE |
||
| 553 | 0, // HOLE |
||
| 554 | 0, // HOLE |
||
| 555 | 0x00000000, // SQ_PGM_START_GS |
||
| 556 | 0x00000000, // SQ_PGM_RESOURCES_GS |
||
| 557 | 0x00000000, // SQ_PGM_RESOURCES_2_GS |
||
| 558 | 0, // HOLE |
||
| 559 | 0, // HOLE |
||
| 560 | 0, // HOLE |
||
| 561 | 0x00000000, // SQ_PGM_START_ES |
||
| 562 | 0x00000000, // SQ_PGM_RESOURCES_ES |
||
| 563 | 0x00000000, // SQ_PGM_RESOURCES_2_ES |
||
| 564 | 0, // HOLE |
||
| 565 | 0, // HOLE |
||
| 566 | 0, // HOLE |
||
| 567 | 0x00000000, // SQ_PGM_START_FS |
||
| 568 | 0x00000000, // SQ_PGM_RESOURCES_FS |
||
| 569 | 0, // HOLE |
||
| 570 | 0, // HOLE |
||
| 571 | 0, // HOLE |
||
| 572 | 0x00000000, // SQ_PGM_START_HS |
||
| 573 | 0x00000000, // SQ_PGM_RESOURCES_HS |
||
| 574 | 0x00000000, // SQ_PGM_RESOURCES_2_HS |
||
| 575 | 0, // HOLE |
||
| 576 | 0, // HOLE |
||
| 577 | 0, // HOLE |
||
| 578 | 0x00000000, // SQ_PGM_START_LS |
||
| 579 | 0x00000000, // SQ_PGM_RESOURCES_LS |
||
| 580 | 0x00000000, // SQ_PGM_RESOURCES_2_LS |
||
| 581 | }; |
||
| 582 | static const u32 SECT_CONTEXT_def_4[] = |
||
| 583 | { |
||
| 584 | 0x00000000, // SQ_LDS_ALLOC |
||
| 585 | 0x00000000, // SQ_LDS_ALLOC_PS |
||
| 586 | 0x00000000, // SQ_VTX_SEMANTIC_CLEAR |
||
| 587 | 0, // HOLE |
||
| 588 | 0x00000000, // SQ_THREAD_TRACE_CTRL |
||
| 589 | 0, // HOLE |
||
| 590 | 0x00000000, // SQ_ESGS_RING_ITEMSIZE |
||
| 591 | 0x00000000, // SQ_GSVS_RING_ITEMSIZE |
||
| 592 | 0x00000000, // SQ_ESTMP_RING_ITEMSIZE |
||
| 593 | 0x00000000, // SQ_GSTMP_RING_ITEMSIZE |
||
| 594 | 0x00000000, // SQ_VSTMP_RING_ITEMSIZE |
||
| 595 | 0x00000000, // SQ_PSTMP_RING_ITEMSIZE |
||
| 596 | 0, // HOLE |
||
| 597 | 0x00000000, // SQ_GS_VERT_ITEMSIZE |
||
| 598 | 0x00000000, // SQ_GS_VERT_ITEMSIZE_1 |
||
| 599 | 0x00000000, // SQ_GS_VERT_ITEMSIZE_2 |
||
| 600 | 0x00000000, // SQ_GS_VERT_ITEMSIZE_3 |
||
| 601 | 0x00000000, // SQ_GSVS_RING_OFFSET_1 |
||
| 602 | 0x00000000, // SQ_GSVS_RING_OFFSET_2 |
||
| 603 | 0x00000000, // SQ_GSVS_RING_OFFSET_3 |
||
| 604 | 0, // HOLE |
||
| 605 | 0, // HOLE |
||
| 606 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_0 |
||
| 607 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_1 |
||
| 608 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_2 |
||
| 609 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_3 |
||
| 610 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_4 |
||
| 611 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_5 |
||
| 612 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_6 |
||
| 613 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_7 |
||
| 614 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_8 |
||
| 615 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_9 |
||
| 616 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_10 |
||
| 617 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_11 |
||
| 618 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_12 |
||
| 619 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_13 |
||
| 620 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_14 |
||
| 621 | 0x00000000, // SQ_ALU_CONST_CACHE_PS_15 |
||
| 622 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_0 |
||
| 623 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_1 |
||
| 624 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_2 |
||
| 625 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_3 |
||
| 626 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_4 |
||
| 627 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_5 |
||
| 628 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_6 |
||
| 629 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_7 |
||
| 630 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_8 |
||
| 631 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_9 |
||
| 632 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_10 |
||
| 633 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_11 |
||
| 634 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_12 |
||
| 635 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_13 |
||
| 636 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_14 |
||
| 637 | 0x00000000, // SQ_ALU_CONST_CACHE_VS_15 |
||
| 638 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_0 |
||
| 639 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_1 |
||
| 640 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_2 |
||
| 641 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_3 |
||
| 642 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_4 |
||
| 643 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_5 |
||
| 644 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_6 |
||
| 645 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_7 |
||
| 646 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_8 |
||
| 647 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_9 |
||
| 648 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_10 |
||
| 649 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_11 |
||
| 650 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_12 |
||
| 651 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_13 |
||
| 652 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_14 |
||
| 653 | 0x00000000, // SQ_ALU_CONST_CACHE_GS_15 |
||
| 654 | 0x00000000, // PA_SU_POINT_SIZE |
||
| 655 | 0x00000000, // PA_SU_POINT_MINMAX |
||
| 656 | 0x00000000, // PA_SU_LINE_CNTL |
||
| 657 | 0x00000000, // PA_SC_LINE_STIPPLE |
||
| 658 | 0x00000000, // VGT_OUTPUT_PATH_CNTL |
||
| 659 | 0x00000000, // VGT_HOS_CNTL |
||
| 660 | 0x00000000, // VGT_HOS_MAX_TESS_LEVEL |
||
| 661 | 0x00000000, // VGT_HOS_MIN_TESS_LEVEL |
||
| 662 | 0x00000000, // VGT_HOS_REUSE_DEPTH |
||
| 663 | 0x00000000, // VGT_GROUP_PRIM_TYPE |
||
| 664 | 0x00000000, // VGT_GROUP_FIRST_DECR |
||
| 665 | 0x00000000, // VGT_GROUP_DECR |
||
| 666 | 0x00000000, // VGT_GROUP_VECT_0_CNTL |
||
| 667 | 0x00000000, // VGT_GROUP_VECT_1_CNTL |
||
| 668 | 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL |
||
| 669 | 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL |
||
| 670 | 0x00000000, // VGT_GS_MODE |
||
| 671 | 0, // HOLE |
||
| 672 | 0x00000000, // PA_SC_MODE_CNTL_0 |
||
| 673 | 0x00000000, // PA_SC_MODE_CNTL_1 |
||
| 674 | 0x00000000, // VGT_ENHANCE |
||
| 675 | 0x00000000, // VGT_GS_PER_ES |
||
| 676 | 0x00000000, // VGT_ES_PER_GS |
||
| 677 | 0x00000000, // VGT_GS_PER_VS |
||
| 678 | 0, // HOLE |
||
| 679 | 0, // HOLE |
||
| 680 | 0, // HOLE |
||
| 681 | 0x00000000, // VGT_GS_OUT_PRIM_TYPE |
||
| 682 | }; |
||
| 683 | static const u32 SECT_CONTEXT_def_5[] = |
||
| 684 | { |
||
| 685 | 0x00000000, // VGT_DMA_MAX_SIZE |
||
| 686 | 0x00000000, // VGT_DMA_INDEX_TYPE |
||
| 687 | 0, // HOLE |
||
| 688 | 0x00000000, // VGT_PRIMITIVEID_EN |
||
| 689 | 0x00000000, // VGT_DMA_NUM_INSTANCES |
||
| 690 | }; |
||
| 691 | static const u32 SECT_CONTEXT_def_6[] = |
||
| 692 | { |
||
| 693 | 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN |
||
| 694 | 0, // HOLE |
||
| 695 | 0, // HOLE |
||
| 696 | 0x00000000, // VGT_INSTANCE_STEP_RATE_0 |
||
| 697 | 0x00000000, // VGT_INSTANCE_STEP_RATE_1 |
||
| 698 | 0, // HOLE |
||
| 699 | 0, // HOLE |
||
| 700 | 0, // HOLE |
||
| 701 | 0x00000000, // VGT_REUSE_OFF |
||
| 702 | 0x00000000, // VGT_VTX_CNT_EN |
||
| 703 | 0x00000000, // DB_HTILE_SURFACE |
||
| 704 | 0x00000000, // DB_SRESULTS_COMPARE_STATE0 |
||
| 705 | 0x00000000, // DB_SRESULTS_COMPARE_STATE1 |
||
| 706 | 0x00000000, // DB_PRELOAD_CONTROL |
||
| 707 | 0, // HOLE |
||
| 708 | 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0 |
||
| 709 | 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0 |
||
| 710 | 0x00000000, // VGT_STRMOUT_BUFFER_BASE_0 |
||
| 711 | 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0 |
||
| 712 | 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1 |
||
| 713 | 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1 |
||
| 714 | 0x00000000, // VGT_STRMOUT_BUFFER_BASE_1 |
||
| 715 | 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1 |
||
| 716 | 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2 |
||
| 717 | 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2 |
||
| 718 | 0x00000000, // VGT_STRMOUT_BUFFER_BASE_2 |
||
| 719 | 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2 |
||
| 720 | 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3 |
||
| 721 | 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3 |
||
| 722 | 0x00000000, // VGT_STRMOUT_BUFFER_BASE_3 |
||
| 723 | 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3 |
||
| 724 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_0 |
||
| 725 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_1 |
||
| 726 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_2 |
||
| 727 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_3 |
||
| 728 | 0, // HOLE |
||
| 729 | 0, // HOLE |
||
| 730 | 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET |
||
| 731 | 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE |
||
| 732 | 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE |
||
| 733 | 0, // HOLE |
||
| 734 | 0x00000000, // VGT_GS_MAX_VERT_OUT |
||
| 735 | 0, // HOLE |
||
| 736 | 0, // HOLE |
||
| 737 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_0 |
||
| 738 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_1 |
||
| 739 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_2 |
||
| 740 | 0x00000000, // VGT_STRMOUT_BASE_OFFSET_HI_3 |
||
| 741 | 0x00000000, // VGT_SHADER_STAGES_EN |
||
| 742 | 0x00000000, // VGT_LS_HS_CONFIG |
||
| 743 | 0x00000000, // VGT_LS_SIZE |
||
| 744 | 0x00000000, // VGT_HS_SIZE |
||
| 745 | 0x00000000, // VGT_LS_HS_ALLOC |
||
| 746 | 0x00000000, // VGT_HS_PATCH_CONST |
||
| 747 | 0x00000000, // VGT_TF_PARAM |
||
| 748 | 0x00000000, // DB_ALPHA_TO_MASK |
||
| 749 | }; |
||
| 750 | static const u32 SECT_CONTEXT_def_7[] = |
||
| 751 | { |
||
| 752 | 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL |
||
| 753 | 0x00000000, // PA_SU_POLY_OFFSET_CLAMP |
||
| 754 | 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE |
||
| 755 | 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET |
||
| 756 | 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE |
||
| 757 | 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET |
||
| 758 | 0x00000000, // VGT_GS_INSTANCE_CNT |
||
| 759 | 0x00000000, // VGT_STRMOUT_CONFIG |
||
| 760 | 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG |
||
| 761 | 0x00000000, // CB_IMMED0_BASE |
||
| 762 | 0x00000000, // CB_IMMED1_BASE |
||
| 763 | 0x00000000, // CB_IMMED2_BASE |
||
| 764 | 0x00000000, // CB_IMMED3_BASE |
||
| 765 | 0x00000000, // CB_IMMED4_BASE |
||
| 766 | 0x00000000, // CB_IMMED5_BASE |
||
| 767 | 0x00000000, // CB_IMMED6_BASE |
||
| 768 | 0x00000000, // CB_IMMED7_BASE |
||
| 769 | 0x00000000, // CB_IMMED8_BASE |
||
| 770 | 0x00000000, // CB_IMMED9_BASE |
||
| 771 | 0x00000000, // CB_IMMED10_BASE |
||
| 772 | 0x00000000, // CB_IMMED11_BASE |
||
| 773 | 0, // HOLE |
||
| 774 | 0, // HOLE |
||
| 775 | 0, // HOLE |
||
| 776 | 0, // HOLE |
||
| 777 | 0, // HOLE |
||
| 778 | 0, // HOLE |
||
| 779 | 0, // HOLE |
||
| 780 | 0, // HOLE |
||
| 781 | 0, // HOLE |
||
| 782 | 0, // HOLE |
||
| 783 | 0, // HOLE |
||
| 784 | 0, // HOLE |
||
| 785 | 0, // HOLE |
||
| 786 | 0x00001000, // PA_SC_LINE_CNTL |
||
| 787 | 0x00000000, // PA_SC_AA_CONFIG |
||
| 788 | 0x00000005, // PA_SU_VTX_CNTL |
||
| 789 | 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ |
||
| 790 | 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ |
||
| 791 | 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ |
||
| 792 | 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ |
||
| 793 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_0 |
||
| 794 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_1 |
||
| 795 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_2 |
||
| 796 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_3 |
||
| 797 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_4 |
||
| 798 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_5 |
||
| 799 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_6 |
||
| 800 | 0x00000000, // PA_SC_AA_SAMPLE_LOCS_7 |
||
| 801 | 0xffffffff, // PA_SC_AA_MASK |
||
| 802 | 0x00000000, // CB_CLRCMP_CONTROL |
||
| 803 | 0x00000000, // CB_CLRCMP_SRC |
||
| 804 | 0x00000000, // CB_CLRCMP_DST |
||
| 805 | 0x00000000, // CB_CLRCMP_MSK |
||
| 806 | 0, // HOLE |
||
| 807 | 0, // HOLE |
||
| 808 | 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL |
||
| 809 | 0x00000010, // VGT_OUT_DEALLOC_CNTL |
||
| 810 | 0x00000000, // CB_COLOR0_BASE |
||
| 811 | 0x00000000, // CB_COLOR0_PITCH |
||
| 812 | 0x00000000, // CB_COLOR0_SLICE |
||
| 813 | 0x00000000, // CB_COLOR0_VIEW |
||
| 814 | 0x00000000, // CB_COLOR0_INFO |
||
| 815 | 0x00000000, // CB_COLOR0_ATTRIB |
||
| 816 | 0x00000000, // CB_COLOR0_DIM |
||
| 817 | 0x00000000, // CB_COLOR0_CMASK |
||
| 818 | 0x00000000, // CB_COLOR0_CMASK_SLICE |
||
| 819 | 0x00000000, // CB_COLOR0_FMASK |
||
| 820 | 0x00000000, // CB_COLOR0_FMASK_SLICE |
||
| 821 | 0x00000000, // CB_COLOR0_CLEAR_WORD0 |
||
| 822 | 0x00000000, // CB_COLOR0_CLEAR_WORD1 |
||
| 823 | 0x00000000, // CB_COLOR0_CLEAR_WORD2 |
||
| 824 | 0x00000000, // CB_COLOR0_CLEAR_WORD3 |
||
| 825 | 0x00000000, // CB_COLOR1_BASE |
||
| 826 | 0x00000000, // CB_COLOR1_PITCH |
||
| 827 | 0x00000000, // CB_COLOR1_SLICE |
||
| 828 | 0x00000000, // CB_COLOR1_VIEW |
||
| 829 | 0x00000000, // CB_COLOR1_INFO |
||
| 830 | 0x00000000, // CB_COLOR1_ATTRIB |
||
| 831 | 0x00000000, // CB_COLOR1_DIM |
||
| 832 | 0x00000000, // CB_COLOR1_CMASK |
||
| 833 | 0x00000000, // CB_COLOR1_CMASK_SLICE |
||
| 834 | 0x00000000, // CB_COLOR1_FMASK |
||
| 835 | 0x00000000, // CB_COLOR1_FMASK_SLICE |
||
| 836 | 0x00000000, // CB_COLOR1_CLEAR_WORD0 |
||
| 837 | 0x00000000, // CB_COLOR1_CLEAR_WORD1 |
||
| 838 | 0x00000000, // CB_COLOR1_CLEAR_WORD2 |
||
| 839 | 0x00000000, // CB_COLOR1_CLEAR_WORD3 |
||
| 840 | 0x00000000, // CB_COLOR2_BASE |
||
| 841 | 0x00000000, // CB_COLOR2_PITCH |
||
| 842 | 0x00000000, // CB_COLOR2_SLICE |
||
| 843 | 0x00000000, // CB_COLOR2_VIEW |
||
| 844 | 0x00000000, // CB_COLOR2_INFO |
||
| 845 | 0x00000000, // CB_COLOR2_ATTRIB |
||
| 846 | 0x00000000, // CB_COLOR2_DIM |
||
| 847 | 0x00000000, // CB_COLOR2_CMASK |
||
| 848 | 0x00000000, // CB_COLOR2_CMASK_SLICE |
||
| 849 | 0x00000000, // CB_COLOR2_FMASK |
||
| 850 | 0x00000000, // CB_COLOR2_FMASK_SLICE |
||
| 851 | 0x00000000, // CB_COLOR2_CLEAR_WORD0 |
||
| 852 | 0x00000000, // CB_COLOR2_CLEAR_WORD1 |
||
| 853 | 0x00000000, // CB_COLOR2_CLEAR_WORD2 |
||
| 854 | 0x00000000, // CB_COLOR2_CLEAR_WORD3 |
||
| 855 | 0x00000000, // CB_COLOR3_BASE |
||
| 856 | 0x00000000, // CB_COLOR3_PITCH |
||
| 857 | 0x00000000, // CB_COLOR3_SLICE |
||
| 858 | 0x00000000, // CB_COLOR3_VIEW |
||
| 859 | 0x00000000, // CB_COLOR3_INFO |
||
| 860 | 0x00000000, // CB_COLOR3_ATTRIB |
||
| 861 | 0x00000000, // CB_COLOR3_DIM |
||
| 862 | 0x00000000, // CB_COLOR3_CMASK |
||
| 863 | 0x00000000, // CB_COLOR3_CMASK_SLICE |
||
| 864 | 0x00000000, // CB_COLOR3_FMASK |
||
| 865 | 0x00000000, // CB_COLOR3_FMASK_SLICE |
||
| 866 | 0x00000000, // CB_COLOR3_CLEAR_WORD0 |
||
| 867 | 0x00000000, // CB_COLOR3_CLEAR_WORD1 |
||
| 868 | 0x00000000, // CB_COLOR3_CLEAR_WORD2 |
||
| 869 | 0x00000000, // CB_COLOR3_CLEAR_WORD3 |
||
| 870 | 0x00000000, // CB_COLOR4_BASE |
||
| 871 | 0x00000000, // CB_COLOR4_PITCH |
||
| 872 | 0x00000000, // CB_COLOR4_SLICE |
||
| 873 | 0x00000000, // CB_COLOR4_VIEW |
||
| 874 | 0x00000000, // CB_COLOR4_INFO |
||
| 875 | 0x00000000, // CB_COLOR4_ATTRIB |
||
| 876 | 0x00000000, // CB_COLOR4_DIM |
||
| 877 | 0x00000000, // CB_COLOR4_CMASK |
||
| 878 | 0x00000000, // CB_COLOR4_CMASK_SLICE |
||
| 879 | 0x00000000, // CB_COLOR4_FMASK |
||
| 880 | 0x00000000, // CB_COLOR4_FMASK_SLICE |
||
| 881 | 0x00000000, // CB_COLOR4_CLEAR_WORD0 |
||
| 882 | 0x00000000, // CB_COLOR4_CLEAR_WORD1 |
||
| 883 | 0x00000000, // CB_COLOR4_CLEAR_WORD2 |
||
| 884 | 0x00000000, // CB_COLOR4_CLEAR_WORD3 |
||
| 885 | 0x00000000, // CB_COLOR5_BASE |
||
| 886 | 0x00000000, // CB_COLOR5_PITCH |
||
| 887 | 0x00000000, // CB_COLOR5_SLICE |
||
| 888 | 0x00000000, // CB_COLOR5_VIEW |
||
| 889 | 0x00000000, // CB_COLOR5_INFO |
||
| 890 | 0x00000000, // CB_COLOR5_ATTRIB |
||
| 891 | 0x00000000, // CB_COLOR5_DIM |
||
| 892 | 0x00000000, // CB_COLOR5_CMASK |
||
| 893 | 0x00000000, // CB_COLOR5_CMASK_SLICE |
||
| 894 | 0x00000000, // CB_COLOR5_FMASK |
||
| 895 | 0x00000000, // CB_COLOR5_FMASK_SLICE |
||
| 896 | 0x00000000, // CB_COLOR5_CLEAR_WORD0 |
||
| 897 | 0x00000000, // CB_COLOR5_CLEAR_WORD1 |
||
| 898 | 0x00000000, // CB_COLOR5_CLEAR_WORD2 |
||
| 899 | 0x00000000, // CB_COLOR5_CLEAR_WORD3 |
||
| 900 | 0x00000000, // CB_COLOR6_BASE |
||
| 901 | 0x00000000, // CB_COLOR6_PITCH |
||
| 902 | 0x00000000, // CB_COLOR6_SLICE |
||
| 903 | 0x00000000, // CB_COLOR6_VIEW |
||
| 904 | 0x00000000, // CB_COLOR6_INFO |
||
| 905 | 0x00000000, // CB_COLOR6_ATTRIB |
||
| 906 | 0x00000000, // CB_COLOR6_DIM |
||
| 907 | 0x00000000, // CB_COLOR6_CMASK |
||
| 908 | 0x00000000, // CB_COLOR6_CMASK_SLICE |
||
| 909 | 0x00000000, // CB_COLOR6_FMASK |
||
| 910 | 0x00000000, // CB_COLOR6_FMASK_SLICE |
||
| 911 | 0x00000000, // CB_COLOR6_CLEAR_WORD0 |
||
| 912 | 0x00000000, // CB_COLOR6_CLEAR_WORD1 |
||
| 913 | 0x00000000, // CB_COLOR6_CLEAR_WORD2 |
||
| 914 | 0x00000000, // CB_COLOR6_CLEAR_WORD3 |
||
| 915 | 0x00000000, // CB_COLOR7_BASE |
||
| 916 | 0x00000000, // CB_COLOR7_PITCH |
||
| 917 | 0x00000000, // CB_COLOR7_SLICE |
||
| 918 | 0x00000000, // CB_COLOR7_VIEW |
||
| 919 | 0x00000000, // CB_COLOR7_INFO |
||
| 920 | 0x00000000, // CB_COLOR7_ATTRIB |
||
| 921 | 0x00000000, // CB_COLOR7_DIM |
||
| 922 | 0x00000000, // CB_COLOR7_CMASK |
||
| 923 | 0x00000000, // CB_COLOR7_CMASK_SLICE |
||
| 924 | 0x00000000, // CB_COLOR7_FMASK |
||
| 925 | 0x00000000, // CB_COLOR7_FMASK_SLICE |
||
| 926 | 0x00000000, // CB_COLOR7_CLEAR_WORD0 |
||
| 927 | 0x00000000, // CB_COLOR7_CLEAR_WORD1 |
||
| 928 | 0x00000000, // CB_COLOR7_CLEAR_WORD2 |
||
| 929 | 0x00000000, // CB_COLOR7_CLEAR_WORD3 |
||
| 930 | 0x00000000, // CB_COLOR8_BASE |
||
| 931 | 0x00000000, // CB_COLOR8_PITCH |
||
| 932 | 0x00000000, // CB_COLOR8_SLICE |
||
| 933 | 0x00000000, // CB_COLOR8_VIEW |
||
| 934 | 0x00000000, // CB_COLOR8_INFO |
||
| 935 | 0x00000000, // CB_COLOR8_ATTRIB |
||
| 936 | 0x00000000, // CB_COLOR8_DIM |
||
| 937 | 0x00000000, // CB_COLOR9_BASE |
||
| 938 | 0x00000000, // CB_COLOR9_PITCH |
||
| 939 | 0x00000000, // CB_COLOR9_SLICE |
||
| 940 | 0x00000000, // CB_COLOR9_VIEW |
||
| 941 | 0x00000000, // CB_COLOR9_INFO |
||
| 942 | 0x00000000, // CB_COLOR9_ATTRIB |
||
| 943 | 0x00000000, // CB_COLOR9_DIM |
||
| 944 | 0x00000000, // CB_COLOR10_BASE |
||
| 945 | 0x00000000, // CB_COLOR10_PITCH |
||
| 946 | 0x00000000, // CB_COLOR10_SLICE |
||
| 947 | 0x00000000, // CB_COLOR10_VIEW |
||
| 948 | 0x00000000, // CB_COLOR10_INFO |
||
| 949 | 0x00000000, // CB_COLOR10_ATTRIB |
||
| 950 | 0x00000000, // CB_COLOR10_DIM |
||
| 951 | 0x00000000, // CB_COLOR11_BASE |
||
| 952 | 0x00000000, // CB_COLOR11_PITCH |
||
| 953 | 0x00000000, // CB_COLOR11_SLICE |
||
| 954 | 0x00000000, // CB_COLOR11_VIEW |
||
| 955 | 0x00000000, // CB_COLOR11_INFO |
||
| 956 | 0x00000000, // CB_COLOR11_ATTRIB |
||
| 957 | 0x00000000, // CB_COLOR11_DIM |
||
| 958 | 0, // HOLE |
||
| 959 | 0, // HOLE |
||
| 960 | 0, // HOLE |
||
| 961 | 0, // HOLE |
||
| 962 | 0, // HOLE |
||
| 963 | 0, // HOLE |
||
| 964 | 0, // HOLE |
||
| 965 | 0, // HOLE |
||
| 966 | 0, // HOLE |
||
| 967 | 0, // HOLE |
||
| 968 | 0, // HOLE |
||
| 969 | 0, // HOLE |
||
| 970 | 0, // HOLE |
||
| 971 | 0, // HOLE |
||
| 972 | 0, // HOLE |
||
| 973 | 0, // HOLE |
||
| 974 | 0, // HOLE |
||
| 975 | 0, // HOLE |
||
| 976 | 0, // HOLE |
||
| 977 | 0, // HOLE |
||
| 978 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_0 |
||
| 979 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_1 |
||
| 980 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_2 |
||
| 981 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_3 |
||
| 982 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_4 |
||
| 983 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_5 |
||
| 984 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_6 |
||
| 985 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_7 |
||
| 986 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_8 |
||
| 987 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_9 |
||
| 988 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_10 |
||
| 989 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_11 |
||
| 990 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_12 |
||
| 991 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_13 |
||
| 992 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_14 |
||
| 993 | 0x00000000, // SQ_ALU_CONST_CACHE_HS_15 |
||
| 994 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_0 |
||
| 995 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_1 |
||
| 996 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_2 |
||
| 997 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_3 |
||
| 998 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_4 |
||
| 999 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_5 |
||
| 1000 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_6 |
||
| 1001 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_7 |
||
| 1002 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_8 |
||
| 1003 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_9 |
||
| 1004 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_10 |
||
| 1005 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_11 |
||
| 1006 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_12 |
||
| 1007 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_13 |
||
| 1008 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_14 |
||
| 1009 | 0x00000000, // SQ_ALU_CONST_CACHE_LS_15 |
||
| 1010 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_0 |
||
| 1011 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_1 |
||
| 1012 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_2 |
||
| 1013 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_3 |
||
| 1014 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_4 |
||
| 1015 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_5 |
||
| 1016 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_6 |
||
| 1017 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_7 |
||
| 1018 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_8 |
||
| 1019 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_9 |
||
| 1020 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_10 |
||
| 1021 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_11 |
||
| 1022 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_12 |
||
| 1023 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_13 |
||
| 1024 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_14 |
||
| 1025 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_HS_15 |
||
| 1026 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_0 |
||
| 1027 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_1 |
||
| 1028 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_2 |
||
| 1029 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_3 |
||
| 1030 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_4 |
||
| 1031 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_5 |
||
| 1032 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_6 |
||
| 1033 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_7 |
||
| 1034 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_8 |
||
| 1035 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_9 |
||
| 1036 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_10 |
||
| 1037 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_11 |
||
| 1038 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_12 |
||
| 1039 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_13 |
||
| 1040 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_14 |
||
| 1041 | 0x00000000, // SQ_ALU_CONST_BUFFER_SIZE_LS_15 |
||
| 1042 | }; |
||
| 1043 | static const struct cs_extent_def SECT_CONTEXT_defs[] = |
||
| 1044 | { |
||
| 1045 | {SECT_CONTEXT_def_1, 0x0000a000, 488 }, |
||
| 1046 | {SECT_CONTEXT_def_2, 0x0000a1f5, 6 }, |
||
| 1047 | {SECT_CONTEXT_def_3, 0x0000a200, 55 }, |
||
| 1048 | {SECT_CONTEXT_def_4, 0x0000a23a, 98 }, |
||
| 1049 | {SECT_CONTEXT_def_5, 0x0000a29e, 5 }, |
||
| 1050 | {SECT_CONTEXT_def_6, 0x0000a2a5, 56 }, |
||
| 1051 | {SECT_CONTEXT_def_7, 0x0000a2de, 290 }, |
||
| 1052 | { 0, 0, 0 } |
||
| 1053 | }; |
||
| 1054 | static const u32 SECT_CLEAR_def_1[] = |
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| 1055 | { |
||
| 1056 | 0xffffffff, // SQ_TEX_SAMPLER_CLEAR |
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| 1057 | 0xffffffff, // SQ_TEX_RESOURCE_CLEAR |
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| 1058 | 0xffffffff, // SQ_LOOP_BOOL_CLEAR |
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| 1059 | }; |
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| 1060 | static const struct cs_extent_def SECT_CLEAR_defs[] = |
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| 1061 | { |
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| 1062 | {SECT_CLEAR_def_1, 0x0000ffc0, 3 }, |
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| 1063 | { 0, 0, 0 } |
||
| 1064 | }; |
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| 1065 | static const u32 SECT_CTRLCONST_def_1[] = |
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| 1066 | { |
||
| 1067 | 0x00000000, // SQ_VTX_BASE_VTX_LOC |
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| 1068 | 0x00000000, // SQ_VTX_START_INST_LOC |
||
| 1069 | }; |
||
| 1070 | static const struct cs_extent_def SECT_CTRLCONST_defs[] = |
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| 1071 | { |
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| 1072 | {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 }, |
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| 1073 | { 0, 0, 0 } |
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| 1074 | }; |
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| 1075 | static const struct cs_section_def evergreen_cs_data[] = { |
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| 1076 | { SECT_CONTEXT_defs, SECT_CONTEXT }, |
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| 1077 | { SECT_CLEAR_defs, SECT_CLEAR }, |
||
| 1078 | { SECT_CTRLCONST_defs, SECT_CTRLCONST }, |
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| 1079 | { 0, SECT_NONE } |
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| 1080 | }; |