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1403 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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2997 | Serge | 25 | * Jerome Glisse |
1403 | serge | 26 | */ |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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2997 | Serge | 33 | #include |
1403 | serge | 34 | |
35 | /* move these to drm_dp_helper.c/h */ |
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36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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3192 | Serge | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
1403 | serge | 38 | |
39 | static char *voltage_names[] = { |
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40 | "0.4V", "0.6V", "0.8V", "1.2V" |
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41 | }; |
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42 | static char *pre_emph_names[] = { |
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43 | "0dB", "3.5dB", "6dB", "9.5dB" |
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44 | }; |
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45 | |||
1963 | serge | 46 | /***** radeon AUX functions *****/ |
5078 | serge | 47 | |
48 | /* Atom needs data in little endian format |
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49 | * so swap as appropriate when copying data to |
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50 | * or from atom. Note that atom operates on |
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51 | * dw units. |
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52 | */ |
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53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
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54 | { |
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55 | #ifdef __BIG_ENDIAN |
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56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ |
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57 | u32 *dst32, *src32; |
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58 | int i; |
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59 | |||
60 | memcpy(src_tmp, src, num_bytes); |
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61 | src32 = (u32 *)src_tmp; |
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62 | dst32 = (u32 *)dst_tmp; |
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63 | if (to_le) { |
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64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
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65 | dst32[i] = cpu_to_le32(src32[i]); |
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66 | memcpy(dst, dst_tmp, num_bytes); |
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67 | } else { |
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68 | u8 dws = num_bytes & ~3; |
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69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
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70 | dst32[i] = le32_to_cpu(src32[i]); |
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71 | memcpy(dst, dst_tmp, dws); |
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72 | if (num_bytes % 4) { |
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73 | for (i = 0; i < (num_bytes % 4); i++) |
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74 | dst[dws+i] = dst_tmp[dws+i]; |
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75 | } |
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76 | } |
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77 | #else |
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78 | memcpy(dst, src, num_bytes); |
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79 | #endif |
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80 | } |
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81 | |||
1963 | serge | 82 | union aux_channel_transaction { |
83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
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84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
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1403 | serge | 85 | }; |
86 | |||
1963 | serge | 87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
88 | u8 *send, int send_bytes, |
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89 | u8 *recv, int recv_size, |
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90 | u8 delay, u8 *ack) |
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1403 | serge | 91 | { |
1963 | serge | 92 | struct drm_device *dev = chan->dev; |
93 | struct radeon_device *rdev = dev->dev_private; |
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94 | union aux_channel_transaction args; |
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95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
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96 | unsigned char *base; |
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97 | int recv_bytes; |
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5078 | serge | 98 | int r = 0; |
1403 | serge | 99 | |
1963 | serge | 100 | memset(&args, 0, sizeof(args)); |
1403 | serge | 101 | |
5078 | serge | 102 | mutex_lock(&chan->mutex); |
5271 | serge | 103 | mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); |
5078 | serge | 104 | |
2997 | Serge | 105 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
1403 | serge | 106 | |
5078 | serge | 107 | radeon_atom_copy_swap(base, send, send_bytes, true); |
1963 | serge | 108 | |
5078 | serge | 109 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
110 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); |
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1963 | serge | 111 | args.v1.ucDataOutLen = 0; |
112 | args.v1.ucChannelID = chan->rec.i2c_id; |
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113 | args.v1.ucDelay = delay / 10; |
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114 | if (ASIC_IS_DCE4(rdev)) |
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115 | args.v2.ucHPD_ID = chan->rec.hpd; |
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116 | |||
5271 | serge | 117 | atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1963 | serge | 118 | |
119 | *ack = args.v1.ucReplyStatus; |
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120 | |||
121 | /* timeout */ |
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122 | if (args.v1.ucReplyStatus == 1) { |
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123 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
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5078 | serge | 124 | r = -ETIMEDOUT; |
125 | goto done; |
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6104 | serge | 126 | } |
1963 | serge | 127 | |
128 | /* flags not zero */ |
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129 | if (args.v1.ucReplyStatus == 2) { |
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130 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
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5078 | serge | 131 | r = -EIO; |
132 | goto done; |
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6104 | serge | 133 | } |
1963 | serge | 134 | |
135 | /* error */ |
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136 | if (args.v1.ucReplyStatus == 3) { |
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137 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
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5078 | serge | 138 | r = -EIO; |
139 | goto done; |
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6104 | serge | 140 | } |
1963 | serge | 141 | |
142 | recv_bytes = args.v1.ucDataOutLen; |
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143 | if (recv_bytes > recv_size) |
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144 | recv_bytes = recv_size; |
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145 | |||
146 | if (recv && recv_size) |
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5078 | serge | 147 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
1963 | serge | 148 | |
5078 | serge | 149 | r = recv_bytes; |
150 | done: |
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5271 | serge | 151 | mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); |
5078 | serge | 152 | mutex_unlock(&chan->mutex); |
153 | |||
154 | return r; |
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1963 | serge | 155 | } |
156 | |||
5078 | serge | 157 | #define BARE_ADDRESS_SIZE 3 |
158 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
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159 | |||
160 | static ssize_t |
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6104 | serge | 161 | radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
1963 | serge | 162 | { |
5078 | serge | 163 | struct radeon_i2c_chan *chan = |
164 | container_of(aux, struct radeon_i2c_chan, aux); |
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1963 | serge | 165 | int ret; |
5078 | serge | 166 | u8 tx_buf[20]; |
167 | size_t tx_size; |
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168 | u8 ack, delay = 0; |
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1963 | serge | 169 | |
5078 | serge | 170 | if (WARN_ON(msg->size > 16)) |
171 | return -E2BIG; |
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1963 | serge | 172 | |
5078 | serge | 173 | tx_buf[0] = msg->address & 0xff; |
6104 | serge | 174 | tx_buf[1] = (msg->address >> 8) & 0xff; |
175 | tx_buf[2] = (msg->request << 4) | |
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176 | ((msg->address >> 16) & 0xf); |
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5078 | serge | 177 | tx_buf[3] = msg->size ? (msg->size - 1) : 0; |
1963 | serge | 178 | |
5078 | serge | 179 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
180 | case DP_AUX_NATIVE_WRITE: |
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181 | case DP_AUX_I2C_WRITE: |
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6104 | serge | 182 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
183 | /* The atom implementation only supports writes with a max payload of |
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184 | * 12 bytes since it uses 4 bits for the total count (header + payload) |
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185 | * in the parameter space. The atom interface supports 16 byte |
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186 | * payloads for reads. The hw itself supports up to 16 bytes of payload. |
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187 | */ |
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188 | if (WARN_ON_ONCE(msg->size > 12)) |
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189 | return -E2BIG; |
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5078 | serge | 190 | /* tx_size needs to be 4 even for bare address packets since the atom |
191 | * table needs the info in tx_buf[3]. |
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192 | */ |
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193 | tx_size = HEADER_SIZE + msg->size; |
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194 | if (msg->size == 0) |
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195 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
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1963 | serge | 196 | else |
5078 | serge | 197 | tx_buf[3] |= tx_size << 4; |
198 | memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); |
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199 | ret = radeon_process_aux_ch(chan, |
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200 | tx_buf, tx_size, NULL, 0, delay, &ack); |
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201 | if (ret >= 0) |
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202 | /* Return payload size. */ |
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203 | ret = msg->size; |
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204 | break; |
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205 | case DP_AUX_NATIVE_READ: |
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206 | case DP_AUX_I2C_READ: |
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207 | /* tx_size needs to be 4 even for bare address packets since the atom |
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208 | * table needs the info in tx_buf[3]. |
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209 | */ |
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210 | tx_size = HEADER_SIZE; |
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211 | if (msg->size == 0) |
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212 | tx_buf[3] |= BARE_ADDRESS_SIZE << 4; |
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213 | else |
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214 | tx_buf[3] |= tx_size << 4; |
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215 | ret = radeon_process_aux_ch(chan, |
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216 | tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); |
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217 | break; |
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218 | default: |
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219 | ret = -EINVAL; |
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220 | break; |
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6104 | serge | 221 | } |
1963 | serge | 222 | |
5078 | serge | 223 | if (ret >= 0) |
224 | msg->reply = ack >> 4; |
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1963 | serge | 225 | |
6104 | serge | 226 | return ret; |
1963 | serge | 227 | } |
1403 | serge | 228 | |
5078 | serge | 229 | void radeon_dp_aux_init(struct radeon_connector *radeon_connector) |
1963 | serge | 230 | { |
6104 | serge | 231 | struct drm_device *dev = radeon_connector->base.dev; |
232 | struct radeon_device *rdev = dev->dev_private; |
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1963 | serge | 233 | int ret; |
234 | |||
5078 | serge | 235 | radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; |
236 | radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; |
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6104 | serge | 237 | if (ASIC_IS_DCE5(rdev)) { |
238 | if (radeon_auxch) |
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239 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; |
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240 | else |
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241 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
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242 | } else { |
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243 | radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; |
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244 | } |
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1963 | serge | 245 | |
5078 | serge | 246 | ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); |
247 | if (!ret) |
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248 | radeon_connector->ddc_bus->has_aux = true; |
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1963 | serge | 249 | |
5078 | serge | 250 | WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); |
1403 | serge | 251 | } |
252 | |||
1963 | serge | 253 | /***** general DP utility functions *****/ |
1403 | serge | 254 | |
5271 | serge | 255 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 |
256 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 |
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1403 | serge | 257 | |
6104 | serge | 258 | static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], |
1403 | serge | 259 | int lane_count, |
260 | u8 train_set[4]) |
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261 | { |
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262 | u8 v = 0; |
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263 | u8 p = 0; |
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264 | int lane; |
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265 | |||
266 | for (lane = 0; lane < lane_count; lane++) { |
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3192 | Serge | 267 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
268 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
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1403 | serge | 269 | |
1963 | serge | 270 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
1403 | serge | 271 | lane, |
272 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
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273 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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274 | |||
275 | if (this_v > v) |
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276 | v = this_v; |
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277 | if (this_p > p) |
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278 | p = this_p; |
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279 | } |
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280 | |||
281 | if (v >= DP_VOLTAGE_MAX) |
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1963 | serge | 282 | v |= DP_TRAIN_MAX_SWING_REACHED; |
1403 | serge | 283 | |
1963 | serge | 284 | if (p >= DP_PRE_EMPHASIS_MAX) |
285 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
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1403 | serge | 286 | |
1963 | serge | 287 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
1403 | serge | 288 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
289 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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290 | |||
291 | for (lane = 0; lane < 4; lane++) |
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292 | train_set[lane] = v | p; |
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293 | } |
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294 | |||
1963 | serge | 295 | /* convert bits per color to bits per pixel */ |
296 | /* get bpc from the EDID */ |
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297 | static int convert_bpc_to_bpp(int bpc) |
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298 | { |
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299 | if (bpc == 0) |
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300 | return 24; |
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301 | else |
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302 | return bpc * 3; |
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303 | } |
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1403 | serge | 304 | |
1963 | serge | 305 | /***** radeon specific DP functions *****/ |
1403 | serge | 306 | |
6661 | serge | 307 | int radeon_dp_get_dp_link_config(struct drm_connector *connector, |
6104 | serge | 308 | const u8 dpcd[DP_DPCD_SIZE], |
6661 | serge | 309 | unsigned pix_clock, |
310 | unsigned *dp_lanes, unsigned *dp_rate) |
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1963 | serge | 311 | { |
2997 | Serge | 312 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
6661 | serge | 313 | static const unsigned link_rates[3] = { 162000, 270000, 540000 }; |
314 | unsigned max_link_rate = drm_dp_max_link_rate(dpcd); |
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315 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); |
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316 | unsigned lane_num, i, max_pix_clock; |
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1403 | serge | 317 | |
6661 | serge | 318 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
319 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { |
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320 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; |
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321 | if (max_pix_clock >= pix_clock) { |
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322 | *dp_lanes = lane_num; |
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323 | *dp_rate = link_rates[i]; |
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324 | return 0; |
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1403 | serge | 325 | } |
326 | } |
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1963 | serge | 327 | } |
1403 | serge | 328 | |
6661 | serge | 329 | return -EINVAL; |
1403 | serge | 330 | } |
331 | |||
1963 | serge | 332 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
333 | int action, int dp_clock, |
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334 | u8 ucconfig, u8 lane_num) |
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1403 | serge | 335 | { |
336 | DP_ENCODER_SERVICE_PARAMETERS args; |
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337 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
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338 | |||
339 | memset(&args, 0, sizeof(args)); |
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340 | args.ucLinkClock = dp_clock / 10; |
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341 | args.ucConfig = ucconfig; |
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342 | args.ucAction = action; |
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343 | args.ucLaneNum = lane_num; |
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344 | args.ucStatus = 0; |
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345 | |||
346 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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347 | return args.ucStatus; |
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348 | } |
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349 | |||
350 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
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351 | { |
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352 | struct drm_device *dev = radeon_connector->base.dev; |
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353 | struct radeon_device *rdev = dev->dev_private; |
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354 | |||
355 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
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5078 | serge | 356 | radeon_connector->ddc_bus->rec.i2c_id, 0); |
1403 | serge | 357 | } |
358 | |||
2997 | Serge | 359 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
360 | { |
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361 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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362 | u8 buf[3]; |
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363 | |||
364 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
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365 | return; |
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366 | |||
5078 | serge | 367 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) |
2997 | Serge | 368 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
369 | buf[0], buf[1], buf[2]); |
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370 | |||
5078 | serge | 371 | if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) |
2997 | Serge | 372 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
373 | buf[0], buf[1], buf[2]); |
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374 | } |
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375 | |||
1403 | serge | 376 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
377 | { |
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378 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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3192 | Serge | 379 | u8 msg[DP_DPCD_SIZE]; |
6104 | serge | 380 | int ret, i; |
1403 | serge | 381 | |
6104 | serge | 382 | for (i = 0; i < 7; i++) { |
383 | ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, |
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384 | DP_DPCD_SIZE); |
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385 | if (ret == DP_DPCD_SIZE) { |
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386 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
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2997 | Serge | 387 | |
6104 | serge | 388 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), |
389 | dig_connector->dpcd); |
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5078 | serge | 390 | |
6104 | serge | 391 | radeon_dp_probe_oui(radeon_connector); |
3764 | Serge | 392 | |
6104 | serge | 393 | return true; |
394 | } |
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1403 | serge | 395 | } |
396 | dig_connector->dpcd[0] = 0; |
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397 | return false; |
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398 | } |
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399 | |||
2997 | Serge | 400 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
6104 | serge | 401 | struct drm_connector *connector) |
1963 | serge | 402 | { |
403 | struct drm_device *dev = encoder->dev; |
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404 | struct radeon_device *rdev = dev->dev_private; |
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2997 | Serge | 405 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5078 | serge | 406 | struct radeon_connector_atom_dig *dig_connector; |
1963 | serge | 407 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
2997 | Serge | 408 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
409 | u8 tmp; |
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1963 | serge | 410 | |
411 | if (!ASIC_IS_DCE4(rdev)) |
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2997 | Serge | 412 | return panel_mode; |
1963 | serge | 413 | |
5078 | serge | 414 | if (!radeon_connector->con_priv) |
415 | return panel_mode; |
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416 | |||
417 | dig_connector = radeon_connector->con_priv; |
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418 | |||
2997 | Serge | 419 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
420 | /* DP bridge chips */ |
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5078 | serge | 421 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
422 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
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6104 | serge | 423 | if (tmp & 1) |
424 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
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425 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
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426 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
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427 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
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428 | else |
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429 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
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5078 | serge | 430 | } |
2997 | Serge | 431 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
432 | /* eDP */ |
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5078 | serge | 433 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, |
434 | DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { |
||
6104 | serge | 435 | if (tmp & 1) |
436 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
437 | } |
||
2997 | Serge | 438 | } |
1963 | serge | 439 | |
2997 | Serge | 440 | return panel_mode; |
1963 | serge | 441 | } |
442 | |||
1403 | serge | 443 | void radeon_dp_set_link_config(struct drm_connector *connector, |
2997 | Serge | 444 | const struct drm_display_mode *mode) |
1403 | serge | 445 | { |
1963 | serge | 446 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1403 | serge | 447 | struct radeon_connector_atom_dig *dig_connector; |
6661 | serge | 448 | int ret; |
1403 | serge | 449 | |
450 | if (!radeon_connector->con_priv) |
||
451 | return; |
||
452 | dig_connector = radeon_connector->con_priv; |
||
453 | |||
1963 | serge | 454 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
455 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
||
6661 | serge | 456 | ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, |
457 | mode->clock, |
||
458 | &dig_connector->dp_lane_count, |
||
459 | &dig_connector->dp_clock); |
||
460 | if (ret) { |
||
461 | dig_connector->dp_clock = 0; |
||
462 | dig_connector->dp_lane_count = 0; |
||
463 | } |
||
1963 | serge | 464 | } |
1403 | serge | 465 | } |
466 | |||
1963 | serge | 467 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1403 | serge | 468 | struct drm_display_mode *mode) |
469 | { |
||
1963 | serge | 470 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
471 | struct radeon_connector_atom_dig *dig_connector; |
||
6661 | serge | 472 | unsigned dp_clock, dp_lanes; |
473 | int ret; |
||
1403 | serge | 474 | |
6104 | serge | 475 | if ((mode->clock > 340000) && |
476 | (!radeon_connector_is_dp12_capable(connector))) |
||
477 | return MODE_CLOCK_HIGH; |
||
478 | |||
1963 | serge | 479 | if (!radeon_connector->con_priv) |
480 | return MODE_CLOCK_HIGH; |
||
481 | dig_connector = radeon_connector->con_priv; |
||
482 | |||
6661 | serge | 483 | ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, |
484 | mode->clock, |
||
485 | &dp_lanes, |
||
486 | &dp_clock); |
||
487 | if (ret) |
||
488 | return MODE_CLOCK_HIGH; |
||
1963 | serge | 489 | |
490 | if ((dp_clock == 540000) && |
||
491 | (!radeon_connector_is_dp12_capable(connector))) |
||
492 | return MODE_CLOCK_HIGH; |
||
493 | |||
494 | return MODE_OK; |
||
1403 | serge | 495 | } |
496 | |||
2997 | Serge | 497 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
498 | { |
||
499 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
500 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
501 | |||
5078 | serge | 502 | if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) |
503 | <= 0) |
||
2997 | Serge | 504 | return false; |
3192 | Serge | 505 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
2997 | Serge | 506 | return false; |
507 | return true; |
||
508 | } |
||
509 | |||
5078 | serge | 510 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
511 | u8 power_state) |
||
512 | { |
||
513 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
514 | struct radeon_connector_atom_dig *dig_connector; |
||
515 | |||
516 | if (!radeon_connector->con_priv) |
||
517 | return; |
||
518 | |||
519 | dig_connector = radeon_connector->con_priv; |
||
520 | |||
521 | /* power up/down the sink */ |
||
522 | if (dig_connector->dpcd[0] >= 0x11) { |
||
523 | drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, |
||
524 | DP_SET_POWER, power_state); |
||
525 | usleep_range(1000, 2000); |
||
526 | } |
||
527 | } |
||
528 | |||
529 | |||
1963 | serge | 530 | struct radeon_dp_link_train_info { |
531 | struct radeon_device *rdev; |
||
532 | struct drm_encoder *encoder; |
||
533 | struct drm_connector *connector; |
||
534 | int enc_id; |
||
535 | int dp_clock; |
||
536 | int dp_lane_count; |
||
537 | bool tp3_supported; |
||
3192 | Serge | 538 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1963 | serge | 539 | u8 train_set[4]; |
1403 | serge | 540 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1963 | serge | 541 | u8 tries; |
2160 | serge | 542 | bool use_dpencoder; |
5078 | serge | 543 | struct drm_dp_aux *aux; |
1963 | serge | 544 | }; |
1403 | serge | 545 | |
1963 | serge | 546 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
547 | { |
||
548 | /* set the initial vs/emph on the source */ |
||
549 | atombios_dig_transmitter_setup(dp_info->encoder, |
||
550 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
||
551 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
||
552 | |||
553 | /* set the vs/emph on the sink */ |
||
5078 | serge | 554 | drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, |
555 | dp_info->train_set, dp_info->dp_lane_count); |
||
1403 | serge | 556 | } |
557 | |||
1963 | serge | 558 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
1403 | serge | 559 | { |
1963 | serge | 560 | int rtp = 0; |
1403 | serge | 561 | |
1963 | serge | 562 | /* set training pattern on the source */ |
2160 | serge | 563 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
1963 | serge | 564 | switch (tp) { |
565 | case DP_TRAINING_PATTERN_1: |
||
566 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
||
567 | break; |
||
568 | case DP_TRAINING_PATTERN_2: |
||
569 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
||
570 | break; |
||
571 | case DP_TRAINING_PATTERN_3: |
||
572 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
||
573 | break; |
||
574 | } |
||
575 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
||
576 | } else { |
||
577 | switch (tp) { |
||
578 | case DP_TRAINING_PATTERN_1: |
||
579 | rtp = 0; |
||
580 | break; |
||
581 | case DP_TRAINING_PATTERN_2: |
||
582 | rtp = 1; |
||
583 | break; |
||
584 | } |
||
585 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
||
586 | dp_info->dp_clock, dp_info->enc_id, rtp); |
||
1403 | serge | 587 | } |
588 | |||
1963 | serge | 589 | /* enable training pattern on the sink */ |
5078 | serge | 590 | drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); |
1403 | serge | 591 | } |
592 | |||
1963 | serge | 593 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 594 | { |
2997 | Serge | 595 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
596 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
1963 | serge | 597 | u8 tmp; |
1403 | serge | 598 | |
1963 | serge | 599 | /* power up the sink */ |
5078 | serge | 600 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
1403 | serge | 601 | |
1963 | serge | 602 | /* possibly enable downspread on the sink */ |
603 | if (dp_info->dpcd[3] & 0x1) |
||
5078 | serge | 604 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 605 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
1963 | serge | 606 | else |
5078 | serge | 607 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 608 | DP_DOWNSPREAD_CTRL, 0); |
1403 | serge | 609 | |
6104 | serge | 610 | if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) |
5078 | serge | 611 | drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); |
1403 | serge | 612 | |
1963 | serge | 613 | /* set the lane count on the sink */ |
614 | tmp = dp_info->dp_lane_count; |
||
5078 | serge | 615 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
1963 | serge | 616 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
5078 | serge | 617 | drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); |
1963 | serge | 618 | |
619 | /* set the link rate on the sink */ |
||
3192 | Serge | 620 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
5078 | serge | 621 | drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); |
1963 | serge | 622 | |
623 | /* start training on the source */ |
||
2160 | serge | 624 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 625 | atombios_dig_encoder_setup(dp_info->encoder, |
626 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
||
627 | else |
||
628 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
||
629 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
630 | |||
631 | /* disable the training pattern on the sink */ |
||
5078 | serge | 632 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 633 | DP_TRAINING_PATTERN_SET, |
634 | DP_TRAINING_PATTERN_DISABLE); |
||
1963 | serge | 635 | |
636 | return 0; |
||
1403 | serge | 637 | } |
638 | |||
1963 | serge | 639 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 640 | { |
1963 | serge | 641 | udelay(400); |
1403 | serge | 642 | |
1963 | serge | 643 | /* disable the training pattern on the sink */ |
5078 | serge | 644 | drm_dp_dpcd_writeb(dp_info->aux, |
6104 | serge | 645 | DP_TRAINING_PATTERN_SET, |
646 | DP_TRAINING_PATTERN_DISABLE); |
||
1403 | serge | 647 | |
1963 | serge | 648 | /* disable the training pattern on the source */ |
2160 | serge | 649 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 650 | atombios_dig_encoder_setup(dp_info->encoder, |
651 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
||
652 | else |
||
653 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
||
654 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
1403 | serge | 655 | |
1963 | serge | 656 | return 0; |
657 | } |
||
1403 | serge | 658 | |
1963 | serge | 659 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
660 | { |
||
661 | bool clock_recovery; |
||
662 | u8 voltage; |
||
663 | int i; |
||
1403 | serge | 664 | |
1963 | serge | 665 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
666 | memset(dp_info->train_set, 0, 4); |
||
667 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 668 | |
669 | udelay(400); |
||
670 | |||
671 | /* clock recovery loop */ |
||
672 | clock_recovery = false; |
||
1963 | serge | 673 | dp_info->tries = 0; |
1403 | serge | 674 | voltage = 0xff; |
1963 | serge | 675 | while (1) { |
3192 | Serge | 676 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
1963 | serge | 677 | |
5078 | serge | 678 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
679 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 680 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 681 | break; |
2997 | Serge | 682 | } |
1403 | serge | 683 | |
3192 | Serge | 684 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 685 | clock_recovery = true; |
686 | break; |
||
687 | } |
||
688 | |||
1963 | serge | 689 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
690 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1403 | serge | 691 | break; |
692 | } |
||
1963 | serge | 693 | if (i == dp_info->dp_lane_count) { |
1403 | serge | 694 | DRM_ERROR("clock recovery reached max voltage\n"); |
695 | break; |
||
696 | } |
||
697 | |||
1963 | serge | 698 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
699 | ++dp_info->tries; |
||
700 | if (dp_info->tries == 5) { |
||
1403 | serge | 701 | DRM_ERROR("clock recovery tried 5 times\n"); |
702 | break; |
||
703 | } |
||
704 | } else |
||
1963 | serge | 705 | dp_info->tries = 0; |
1403 | serge | 706 | |
1963 | serge | 707 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1403 | serge | 708 | |
709 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 710 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
711 | |||
712 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 713 | } |
1963 | serge | 714 | if (!clock_recovery) { |
1403 | serge | 715 | DRM_ERROR("clock recovery failed\n"); |
1963 | serge | 716 | return -1; |
717 | } else { |
||
718 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
||
719 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
720 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
||
1403 | serge | 721 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 722 | return 0; |
723 | } |
||
724 | } |
||
1403 | serge | 725 | |
1963 | serge | 726 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
727 | { |
||
728 | bool channel_eq; |
||
1403 | serge | 729 | |
1963 | serge | 730 | if (dp_info->tp3_supported) |
731 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
||
1430 | serge | 732 | else |
1963 | serge | 733 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
1403 | serge | 734 | |
735 | /* channel equalization loop */ |
||
1963 | serge | 736 | dp_info->tries = 0; |
1403 | serge | 737 | channel_eq = false; |
1963 | serge | 738 | while (1) { |
3192 | Serge | 739 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
1963 | serge | 740 | |
5078 | serge | 741 | if (drm_dp_dpcd_read_link_status(dp_info->aux, |
742 | dp_info->link_status) <= 0) { |
||
2997 | Serge | 743 | DRM_ERROR("displayport link status failed\n"); |
1403 | serge | 744 | break; |
2997 | Serge | 745 | } |
1403 | serge | 746 | |
3192 | Serge | 747 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 748 | channel_eq = true; |
749 | break; |
||
750 | } |
||
751 | |||
752 | /* Try 5 times */ |
||
1963 | serge | 753 | if (dp_info->tries > 5) { |
1403 | serge | 754 | DRM_ERROR("channel eq failed: 5 tries\n"); |
755 | break; |
||
756 | } |
||
757 | |||
758 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 759 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
1403 | serge | 760 | |
1963 | serge | 761 | radeon_dp_update_vs_emph(dp_info); |
762 | dp_info->tries++; |
||
1403 | serge | 763 | } |
764 | |||
1963 | serge | 765 | if (!channel_eq) { |
1403 | serge | 766 | DRM_ERROR("channel eq failed\n"); |
1963 | serge | 767 | return -1; |
768 | } else { |
||
769 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
||
770 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
771 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
1403 | serge | 772 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 773 | return 0; |
774 | } |
||
1403 | serge | 775 | } |
776 | |||
1963 | serge | 777 | void radeon_dp_link_train(struct drm_encoder *encoder, |
778 | struct drm_connector *connector) |
||
1403 | serge | 779 | { |
1963 | serge | 780 | struct drm_device *dev = encoder->dev; |
781 | struct radeon_device *rdev = dev->dev_private; |
||
782 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
783 | struct radeon_encoder_atom_dig *dig; |
||
784 | struct radeon_connector *radeon_connector; |
||
785 | struct radeon_connector_atom_dig *dig_connector; |
||
786 | struct radeon_dp_link_train_info dp_info; |
||
2160 | serge | 787 | int index; |
788 | u8 tmp, frev, crev; |
||
1403 | serge | 789 | |
1963 | serge | 790 | if (!radeon_encoder->enc_priv) |
791 | return; |
||
792 | dig = radeon_encoder->enc_priv; |
||
1403 | serge | 793 | |
1963 | serge | 794 | radeon_connector = to_radeon_connector(connector); |
795 | if (!radeon_connector->con_priv) |
||
796 | return; |
||
797 | dig_connector = radeon_connector->con_priv; |
||
1403 | serge | 798 | |
1963 | serge | 799 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
800 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
||
801 | return; |
||
1403 | serge | 802 | |
2160 | serge | 803 | /* DPEncoderService newer than 1.1 can't program properly the |
804 | * training pattern. When facing such version use the |
||
805 | * DIGXEncoderControl (X== 1 | 2) |
||
806 | */ |
||
807 | dp_info.use_dpencoder = true; |
||
808 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
809 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
||
810 | if (crev > 1) { |
||
811 | dp_info.use_dpencoder = false; |
||
812 | } |
||
813 | } |
||
814 | |||
1963 | serge | 815 | dp_info.enc_id = 0; |
816 | if (dig->dig_encoder) |
||
817 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
||
818 | else |
||
819 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
||
820 | if (dig->linkb) |
||
821 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
||
822 | else |
||
823 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
||
1403 | serge | 824 | |
5078 | serge | 825 | if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) |
826 | == 1) { |
||
6104 | serge | 827 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
828 | dp_info.tp3_supported = true; |
||
829 | else |
||
830 | dp_info.tp3_supported = false; |
||
5078 | serge | 831 | } else { |
832 | dp_info.tp3_supported = false; |
||
833 | } |
||
1403 | serge | 834 | |
3192 | Serge | 835 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
1963 | serge | 836 | dp_info.rdev = rdev; |
837 | dp_info.encoder = encoder; |
||
838 | dp_info.connector = connector; |
||
839 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
||
840 | dp_info.dp_clock = dig_connector->dp_clock; |
||
5078 | serge | 841 | dp_info.aux = &radeon_connector->ddc_bus->aux; |
1403 | serge | 842 | |
1963 | serge | 843 | if (radeon_dp_link_train_init(&dp_info)) |
844 | goto done; |
||
845 | if (radeon_dp_link_train_cr(&dp_info)) |
||
846 | goto done; |
||
847 | if (radeon_dp_link_train_ce(&dp_info)) |
||
848 | goto done; |
||
849 | done: |
||
850 | if (radeon_dp_link_train_finish(&dp_info)) |
||
851 | return; |
||
1403 | serge | 852 | }=>>=>=>>=>>=><=>=>>>><>><>><>><>><>>>> |