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1403 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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2997 | Serge | 25 | * Jerome Glisse |
1403 | serge | 26 | */ |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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2997 | Serge | 33 | #include |
1403 | serge | 34 | |
35 | /* move these to drm_dp_helper.c/h */ |
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36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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3192 | Serge | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
1403 | serge | 38 | |
39 | static char *voltage_names[] = { |
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40 | "0.4V", "0.6V", "0.8V", "1.2V" |
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41 | }; |
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42 | static char *pre_emph_names[] = { |
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43 | "0dB", "3.5dB", "6dB", "9.5dB" |
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44 | }; |
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45 | |||
1963 | serge | 46 | /***** radeon AUX functions *****/ |
47 | union aux_channel_transaction { |
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48 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
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49 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
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1403 | serge | 50 | }; |
51 | |||
1963 | serge | 52 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
53 | u8 *send, int send_bytes, |
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54 | u8 *recv, int recv_size, |
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55 | u8 delay, u8 *ack) |
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1403 | serge | 56 | { |
1963 | serge | 57 | struct drm_device *dev = chan->dev; |
58 | struct radeon_device *rdev = dev->dev_private; |
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59 | union aux_channel_transaction args; |
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60 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
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61 | unsigned char *base; |
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62 | int recv_bytes; |
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1403 | serge | 63 | |
1963 | serge | 64 | memset(&args, 0, sizeof(args)); |
1403 | serge | 65 | |
2997 | Serge | 66 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
1403 | serge | 67 | |
1963 | serge | 68 | memcpy(base, send, send_bytes); |
69 | |||
2997 | Serge | 70 | args.v1.lpAuxRequest = 0 + 4; |
71 | args.v1.lpDataOut = 16 + 4; |
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1963 | serge | 72 | args.v1.ucDataOutLen = 0; |
73 | args.v1.ucChannelID = chan->rec.i2c_id; |
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74 | args.v1.ucDelay = delay / 10; |
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75 | if (ASIC_IS_DCE4(rdev)) |
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76 | args.v2.ucHPD_ID = chan->rec.hpd; |
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77 | |||
78 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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79 | |||
80 | *ack = args.v1.ucReplyStatus; |
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81 | |||
82 | /* timeout */ |
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83 | if (args.v1.ucReplyStatus == 1) { |
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84 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
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85 | return -ETIMEDOUT; |
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1403 | serge | 86 | } |
1963 | serge | 87 | |
88 | /* flags not zero */ |
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89 | if (args.v1.ucReplyStatus == 2) { |
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90 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
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91 | return -EBUSY; |
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1403 | serge | 92 | } |
1963 | serge | 93 | |
94 | /* error */ |
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95 | if (args.v1.ucReplyStatus == 3) { |
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96 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
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97 | return -EIO; |
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1403 | serge | 98 | } |
1963 | serge | 99 | |
100 | recv_bytes = args.v1.ucDataOutLen; |
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101 | if (recv_bytes > recv_size) |
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102 | recv_bytes = recv_size; |
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103 | |||
104 | if (recv && recv_size) |
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105 | memcpy(recv, base + 16, recv_bytes); |
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106 | |||
107 | return recv_bytes; |
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108 | } |
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109 | |||
110 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, |
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111 | u16 address, u8 *send, u8 send_bytes, u8 delay) |
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112 | { |
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113 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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114 | int ret; |
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115 | u8 msg[20]; |
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116 | int msg_bytes = send_bytes + 4; |
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117 | u8 ack; |
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2997 | Serge | 118 | unsigned retry; |
1963 | serge | 119 | |
120 | if (send_bytes > 16) |
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121 | return -1; |
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122 | |||
123 | msg[0] = address; |
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124 | msg[1] = address >> 8; |
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125 | msg[2] = AUX_NATIVE_WRITE << 4; |
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126 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
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127 | memcpy(&msg[4], send, send_bytes); |
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128 | |||
2997 | Serge | 129 | for (retry = 0; retry < 4; retry++) { |
1963 | serge | 130 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
131 | msg, msg_bytes, NULL, 0, delay, &ack); |
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2997 | Serge | 132 | if (ret == -EBUSY) |
133 | continue; |
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134 | else if (ret < 0) |
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1963 | serge | 135 | return ret; |
136 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
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2997 | Serge | 137 | return send_bytes; |
1963 | serge | 138 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
139 | udelay(400); |
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140 | else |
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141 | return -EIO; |
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1403 | serge | 142 | } |
1963 | serge | 143 | |
2997 | Serge | 144 | return -EIO; |
1963 | serge | 145 | } |
146 | |||
147 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
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148 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
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149 | { |
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150 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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151 | u8 msg[4]; |
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152 | int msg_bytes = 4; |
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153 | u8 ack; |
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154 | int ret; |
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2997 | Serge | 155 | unsigned retry; |
1963 | serge | 156 | |
157 | msg[0] = address; |
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158 | msg[1] = address >> 8; |
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159 | msg[2] = AUX_NATIVE_READ << 4; |
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160 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
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161 | |||
2997 | Serge | 162 | for (retry = 0; retry < 4; retry++) { |
1963 | serge | 163 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
164 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
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2997 | Serge | 165 | if (ret == -EBUSY) |
166 | continue; |
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167 | else if (ret < 0) |
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1963 | serge | 168 | return ret; |
169 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
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170 | return ret; |
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171 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
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172 | udelay(400); |
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2997 | Serge | 173 | else if (ret == 0) |
174 | return -EPROTO; |
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1403 | serge | 175 | else |
1963 | serge | 176 | return -EIO; |
1403 | serge | 177 | } |
2997 | Serge | 178 | |
179 | return -EIO; |
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1963 | serge | 180 | } |
1403 | serge | 181 | |
1963 | serge | 182 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
183 | u16 reg, u8 val) |
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184 | { |
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185 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); |
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1403 | serge | 186 | } |
187 | |||
1963 | serge | 188 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, |
189 | u16 reg) |
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1403 | serge | 190 | { |
1963 | serge | 191 | u8 val = 0; |
1403 | serge | 192 | |
1963 | serge | 193 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); |
1403 | serge | 194 | |
1963 | serge | 195 | return val; |
196 | } |
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1403 | serge | 197 | |
1963 | serge | 198 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
199 | u8 write_byte, u8 *read_byte) |
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200 | { |
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201 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
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202 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; |
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203 | u16 address = algo_data->address; |
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204 | u8 msg[5]; |
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205 | u8 reply[2]; |
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206 | unsigned retry; |
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207 | int msg_bytes; |
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208 | int reply_bytes = 1; |
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209 | int ret; |
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210 | u8 ack; |
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211 | |||
212 | /* Set up the command byte */ |
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213 | if (mode & MODE_I2C_READ) |
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214 | msg[2] = AUX_I2C_READ << 4; |
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215 | else |
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216 | msg[2] = AUX_I2C_WRITE << 4; |
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217 | |||
218 | if (!(mode & MODE_I2C_STOP)) |
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219 | msg[2] |= AUX_I2C_MOT << 4; |
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220 | |||
221 | msg[0] = address; |
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222 | msg[1] = address >> 8; |
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223 | |||
224 | switch (mode) { |
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225 | case MODE_I2C_WRITE: |
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226 | msg_bytes = 5; |
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227 | msg[3] = msg_bytes << 4; |
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228 | msg[4] = write_byte; |
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1403 | serge | 229 | break; |
1963 | serge | 230 | case MODE_I2C_READ: |
231 | msg_bytes = 4; |
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232 | msg[3] = msg_bytes << 4; |
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1403 | serge | 233 | break; |
234 | default: |
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1963 | serge | 235 | msg_bytes = 4; |
236 | msg[3] = 3 << 4; |
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1403 | serge | 237 | break; |
238 | } |
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1963 | serge | 239 | |
240 | for (retry = 0; retry < 4; retry++) { |
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241 | ret = radeon_process_aux_ch(auxch, |
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242 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
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2997 | Serge | 243 | if (ret == -EBUSY) |
244 | continue; |
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245 | else if (ret < 0) { |
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1963 | serge | 246 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
247 | return ret; |
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1403 | serge | 248 | } |
1963 | serge | 249 | |
250 | switch (ack & AUX_NATIVE_REPLY_MASK) { |
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251 | case AUX_NATIVE_REPLY_ACK: |
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252 | /* I2C-over-AUX Reply field is only valid |
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253 | * when paired with AUX ACK. |
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254 | */ |
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1403 | serge | 255 | break; |
1963 | serge | 256 | case AUX_NATIVE_REPLY_NACK: |
257 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
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258 | return -EREMOTEIO; |
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259 | case AUX_NATIVE_REPLY_DEFER: |
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260 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
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261 | udelay(400); |
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262 | continue; |
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263 | default: |
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264 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); |
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265 | return -EREMOTEIO; |
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266 | } |
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267 | |||
268 | switch (ack & AUX_I2C_REPLY_MASK) { |
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269 | case AUX_I2C_REPLY_ACK: |
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270 | if (mode == MODE_I2C_READ) |
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271 | *read_byte = reply[0]; |
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272 | return ret; |
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273 | case AUX_I2C_REPLY_NACK: |
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274 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
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275 | return -EREMOTEIO; |
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276 | case AUX_I2C_REPLY_DEFER: |
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277 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
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278 | udelay(400); |
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1403 | serge | 279 | break; |
280 | default: |
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1963 | serge | 281 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
282 | return -EREMOTEIO; |
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1403 | serge | 283 | } |
284 | } |
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285 | |||
2997 | Serge | 286 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
1963 | serge | 287 | return -EREMOTEIO; |
1403 | serge | 288 | } |
289 | |||
1963 | serge | 290 | /***** general DP utility functions *****/ |
1403 | serge | 291 | |
292 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
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1963 | serge | 293 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
1403 | serge | 294 | |
295 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
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296 | int lane_count, |
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297 | u8 train_set[4]) |
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298 | { |
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299 | u8 v = 0; |
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300 | u8 p = 0; |
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301 | int lane; |
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302 | |||
303 | for (lane = 0; lane < lane_count; lane++) { |
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3192 | Serge | 304 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
305 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
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1403 | serge | 306 | |
1963 | serge | 307 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
1403 | serge | 308 | lane, |
309 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
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310 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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311 | |||
312 | if (this_v > v) |
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313 | v = this_v; |
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314 | if (this_p > p) |
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315 | p = this_p; |
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316 | } |
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317 | |||
318 | if (v >= DP_VOLTAGE_MAX) |
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1963 | serge | 319 | v |= DP_TRAIN_MAX_SWING_REACHED; |
1403 | serge | 320 | |
1963 | serge | 321 | if (p >= DP_PRE_EMPHASIS_MAX) |
322 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
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1403 | serge | 323 | |
1963 | serge | 324 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
1403 | serge | 325 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
326 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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327 | |||
328 | for (lane = 0; lane < 4; lane++) |
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329 | train_set[lane] = v | p; |
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330 | } |
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331 | |||
1963 | serge | 332 | /* convert bits per color to bits per pixel */ |
333 | /* get bpc from the EDID */ |
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334 | static int convert_bpc_to_bpp(int bpc) |
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335 | { |
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336 | if (bpc == 0) |
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337 | return 24; |
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338 | else |
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339 | return bpc * 3; |
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340 | } |
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1403 | serge | 341 | |
1963 | serge | 342 | /* get the max pix clock supported by the link rate and lane num */ |
343 | static int dp_get_max_dp_pix_clock(int link_rate, |
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344 | int lane_num, |
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345 | int bpp) |
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1403 | serge | 346 | { |
1963 | serge | 347 | return (link_rate * lane_num * 8) / bpp; |
348 | } |
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1403 | serge | 349 | |
1963 | serge | 350 | /***** radeon specific DP functions *****/ |
1403 | serge | 351 | |
1963 | serge | 352 | /* First get the min lane# when low rate is used according to pixel clock |
353 | * (prefer low rate), second check max lane# supported by DP panel, |
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354 | * if the max lane# < low rate lane# then use max lane# instead. |
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355 | */ |
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356 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
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357 | u8 dpcd[DP_DPCD_SIZE], |
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358 | int pix_clock) |
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359 | { |
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2997 | Serge | 360 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
3192 | Serge | 361 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
362 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
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1963 | serge | 363 | int lane_num; |
364 | int max_dp_pix_clock; |
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1403 | serge | 365 | |
1963 | serge | 366 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { |
367 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); |
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368 | if (pix_clock <= max_dp_pix_clock) |
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369 | break; |
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1403 | serge | 370 | } |
371 | |||
1963 | serge | 372 | return lane_num; |
1403 | serge | 373 | } |
374 | |||
1963 | serge | 375 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
376 | u8 dpcd[DP_DPCD_SIZE], |
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377 | int pix_clock) |
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1403 | serge | 378 | { |
2997 | Serge | 379 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
1963 | serge | 380 | int lane_num, max_pix_clock; |
1403 | serge | 381 | |
2997 | Serge | 382 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
383 | ENCODER_OBJECT_ID_NUTMEG) |
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1963 | serge | 384 | return 270000; |
1403 | serge | 385 | |
1963 | serge | 386 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); |
387 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); |
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388 | if (pix_clock <= max_pix_clock) |
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389 | return 162000; |
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390 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); |
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391 | if (pix_clock <= max_pix_clock) |
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392 | return 270000; |
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393 | if (radeon_connector_is_dp12_capable(connector)) { |
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394 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); |
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395 | if (pix_clock <= max_pix_clock) |
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396 | return 540000; |
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397 | } |
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1403 | serge | 398 | |
3192 | Serge | 399 | return drm_dp_max_link_rate(dpcd); |
1403 | serge | 400 | } |
401 | |||
1963 | serge | 402 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
403 | int action, int dp_clock, |
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404 | u8 ucconfig, u8 lane_num) |
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1403 | serge | 405 | { |
406 | DP_ENCODER_SERVICE_PARAMETERS args; |
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407 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
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408 | |||
409 | memset(&args, 0, sizeof(args)); |
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410 | args.ucLinkClock = dp_clock / 10; |
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411 | args.ucConfig = ucconfig; |
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412 | args.ucAction = action; |
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413 | args.ucLaneNum = lane_num; |
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414 | args.ucStatus = 0; |
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415 | |||
416 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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417 | return args.ucStatus; |
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418 | } |
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419 | |||
420 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
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421 | { |
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422 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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423 | struct drm_device *dev = radeon_connector->base.dev; |
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424 | struct radeon_device *rdev = dev->dev_private; |
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425 | |||
426 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
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427 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
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428 | } |
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429 | |||
2997 | Serge | 430 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
431 | { |
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432 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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433 | u8 buf[3]; |
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434 | |||
435 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
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436 | return; |
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437 | |||
438 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) |
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439 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
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440 | buf[0], buf[1], buf[2]); |
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441 | |||
442 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) |
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443 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
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444 | buf[0], buf[1], buf[2]); |
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445 | } |
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446 | |||
1403 | serge | 447 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
448 | { |
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449 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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3192 | Serge | 450 | u8 msg[DP_DPCD_SIZE]; |
1963 | serge | 451 | int ret, i; |
1403 | serge | 452 | |
3192 | Serge | 453 | ENTER(); |
454 | |||
455 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, |
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456 | DP_DPCD_SIZE, 0); |
||
1963 | serge | 457 | if (ret > 0) { |
3192 | Serge | 458 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
1963 | serge | 459 | DRM_DEBUG_KMS("DPCD: "); |
3192 | Serge | 460 | for (i = 0; i < DP_DPCD_SIZE; i++) |
1963 | serge | 461 | DRM_DEBUG_KMS("%02x ", msg[i]); |
462 | DRM_DEBUG_KMS("\n"); |
||
2997 | Serge | 463 | |
464 | radeon_dp_probe_oui(radeon_connector); |
||
3192 | Serge | 465 | LEAVE(); |
1403 | serge | 466 | return true; |
467 | } |
||
3192 | Serge | 468 | FAIL(); |
1403 | serge | 469 | dig_connector->dpcd[0] = 0; |
470 | return false; |
||
471 | } |
||
472 | |||
2997 | Serge | 473 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
1963 | serge | 474 | struct drm_connector *connector) |
475 | { |
||
476 | struct drm_device *dev = encoder->dev; |
||
477 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 478 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1963 | serge | 479 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
2997 | Serge | 480 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
481 | u8 tmp; |
||
1963 | serge | 482 | |
483 | if (!ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 484 | return panel_mode; |
1963 | serge | 485 | |
2997 | Serge | 486 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
487 | /* DP bridge chips */ |
||
488 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
||
489 | if (tmp & 1) |
||
490 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
491 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
||
492 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
||
1963 | serge | 493 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
2997 | Serge | 494 | else |
495 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
||
496 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
||
497 | /* eDP */ |
||
498 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
||
499 | if (tmp & 1) |
||
500 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
501 | } |
||
1963 | serge | 502 | |
2997 | Serge | 503 | return panel_mode; |
1963 | serge | 504 | } |
505 | |||
1403 | serge | 506 | void radeon_dp_set_link_config(struct drm_connector *connector, |
2997 | Serge | 507 | const struct drm_display_mode *mode) |
1403 | serge | 508 | { |
1963 | serge | 509 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1403 | serge | 510 | struct radeon_connector_atom_dig *dig_connector; |
511 | |||
512 | if (!radeon_connector->con_priv) |
||
513 | return; |
||
514 | dig_connector = radeon_connector->con_priv; |
||
515 | |||
1963 | serge | 516 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
517 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
||
1403 | serge | 518 | dig_connector->dp_clock = |
1963 | serge | 519 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
1403 | serge | 520 | dig_connector->dp_lane_count = |
1963 | serge | 521 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); |
522 | } |
||
1403 | serge | 523 | } |
524 | |||
1963 | serge | 525 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1403 | serge | 526 | struct drm_display_mode *mode) |
527 | { |
||
1963 | serge | 528 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
529 | struct radeon_connector_atom_dig *dig_connector; |
||
530 | int dp_clock; |
||
1403 | serge | 531 | |
1963 | serge | 532 | if (!radeon_connector->con_priv) |
533 | return MODE_CLOCK_HIGH; |
||
534 | dig_connector = radeon_connector->con_priv; |
||
535 | |||
536 | dp_clock = |
||
537 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
||
538 | |||
539 | if ((dp_clock == 540000) && |
||
540 | (!radeon_connector_is_dp12_capable(connector))) |
||
541 | return MODE_CLOCK_HIGH; |
||
542 | |||
543 | return MODE_OK; |
||
1403 | serge | 544 | } |
545 | |||
1963 | serge | 546 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
1403 | serge | 547 | u8 link_status[DP_LINK_STATUS_SIZE]) |
548 | { |
||
549 | int ret; |
||
1963 | serge | 550 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
551 | link_status, DP_LINK_STATUS_SIZE, 100); |
||
552 | if (ret <= 0) { |
||
1403 | serge | 553 | return false; |
554 | } |
||
555 | |||
2997 | Serge | 556 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
1403 | serge | 557 | return true; |
558 | } |
||
559 | |||
2997 | Serge | 560 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
561 | { |
||
562 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
563 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
564 | |||
565 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) |
||
566 | return false; |
||
3192 | Serge | 567 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
2997 | Serge | 568 | return false; |
569 | return true; |
||
570 | } |
||
571 | |||
1963 | serge | 572 | struct radeon_dp_link_train_info { |
573 | struct radeon_device *rdev; |
||
574 | struct drm_encoder *encoder; |
||
575 | struct drm_connector *connector; |
||
576 | struct radeon_connector *radeon_connector; |
||
577 | int enc_id; |
||
578 | int dp_clock; |
||
579 | int dp_lane_count; |
||
580 | bool tp3_supported; |
||
3192 | Serge | 581 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1963 | serge | 582 | u8 train_set[4]; |
1403 | serge | 583 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1963 | serge | 584 | u8 tries; |
2160 | serge | 585 | bool use_dpencoder; |
1963 | serge | 586 | }; |
1403 | serge | 587 | |
1963 | serge | 588 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
589 | { |
||
590 | /* set the initial vs/emph on the source */ |
||
591 | atombios_dig_transmitter_setup(dp_info->encoder, |
||
592 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
||
593 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
||
594 | |||
595 | /* set the vs/emph on the sink */ |
||
596 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, |
||
597 | dp_info->train_set, dp_info->dp_lane_count, 0); |
||
1403 | serge | 598 | } |
599 | |||
1963 | serge | 600 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
1403 | serge | 601 | { |
1963 | serge | 602 | int rtp = 0; |
1403 | serge | 603 | |
1963 | serge | 604 | /* set training pattern on the source */ |
2160 | serge | 605 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
1963 | serge | 606 | switch (tp) { |
607 | case DP_TRAINING_PATTERN_1: |
||
608 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
||
609 | break; |
||
610 | case DP_TRAINING_PATTERN_2: |
||
611 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
||
612 | break; |
||
613 | case DP_TRAINING_PATTERN_3: |
||
614 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
||
615 | break; |
||
616 | } |
||
617 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
||
618 | } else { |
||
619 | switch (tp) { |
||
620 | case DP_TRAINING_PATTERN_1: |
||
621 | rtp = 0; |
||
622 | break; |
||
623 | case DP_TRAINING_PATTERN_2: |
||
624 | rtp = 1; |
||
625 | break; |
||
626 | } |
||
627 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
||
628 | dp_info->dp_clock, dp_info->enc_id, rtp); |
||
1403 | serge | 629 | } |
630 | |||
1963 | serge | 631 | /* enable training pattern on the sink */ |
632 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
||
1403 | serge | 633 | } |
634 | |||
1963 | serge | 635 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 636 | { |
2997 | Serge | 637 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
638 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
1963 | serge | 639 | u8 tmp; |
1403 | serge | 640 | |
1963 | serge | 641 | /* power up the sink */ |
642 | if (dp_info->dpcd[0] >= 0x11) |
||
643 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
644 | DP_SET_POWER, DP_SET_POWER_D0); |
||
1403 | serge | 645 | |
1963 | serge | 646 | /* possibly enable downspread on the sink */ |
647 | if (dp_info->dpcd[3] & 0x1) |
||
648 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
649 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
||
650 | else |
||
651 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
652 | DP_DOWNSPREAD_CTRL, 0); |
||
1403 | serge | 653 | |
2997 | Serge | 654 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
655 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
||
656 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); |
||
657 | } |
||
1403 | serge | 658 | |
1963 | serge | 659 | /* set the lane count on the sink */ |
660 | tmp = dp_info->dp_lane_count; |
||
2997 | Serge | 661 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
662 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) |
||
1963 | serge | 663 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
664 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
||
665 | |||
666 | /* set the link rate on the sink */ |
||
3192 | Serge | 667 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
1963 | serge | 668 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
669 | |||
670 | /* start training on the source */ |
||
2160 | serge | 671 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 672 | atombios_dig_encoder_setup(dp_info->encoder, |
673 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
||
674 | else |
||
675 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
||
676 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
677 | |||
678 | /* disable the training pattern on the sink */ |
||
679 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
680 | DP_TRAINING_PATTERN_SET, |
||
681 | DP_TRAINING_PATTERN_DISABLE); |
||
682 | |||
683 | return 0; |
||
1403 | serge | 684 | } |
685 | |||
1963 | serge | 686 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 687 | { |
1963 | serge | 688 | udelay(400); |
1403 | serge | 689 | |
1963 | serge | 690 | /* disable the training pattern on the sink */ |
691 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
692 | DP_TRAINING_PATTERN_SET, |
||
693 | DP_TRAINING_PATTERN_DISABLE); |
||
1403 | serge | 694 | |
1963 | serge | 695 | /* disable the training pattern on the source */ |
2160 | serge | 696 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 697 | atombios_dig_encoder_setup(dp_info->encoder, |
698 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
||
699 | else |
||
700 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
||
701 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
1403 | serge | 702 | |
1963 | serge | 703 | return 0; |
704 | } |
||
1403 | serge | 705 | |
1963 | serge | 706 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
707 | { |
||
708 | bool clock_recovery; |
||
709 | u8 voltage; |
||
710 | int i; |
||
1403 | serge | 711 | |
1963 | serge | 712 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
713 | memset(dp_info->train_set, 0, 4); |
||
714 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 715 | |
716 | udelay(400); |
||
717 | |||
718 | /* clock recovery loop */ |
||
719 | clock_recovery = false; |
||
1963 | serge | 720 | dp_info->tries = 0; |
1403 | serge | 721 | voltage = 0xff; |
1963 | serge | 722 | while (1) { |
3192 | Serge | 723 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
1963 | serge | 724 | |
2997 | Serge | 725 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
726 | DRM_ERROR("displayport link status failed\n"); |
||
1403 | serge | 727 | break; |
2997 | Serge | 728 | } |
1403 | serge | 729 | |
3192 | Serge | 730 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 731 | clock_recovery = true; |
732 | break; |
||
733 | } |
||
734 | |||
1963 | serge | 735 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
736 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1403 | serge | 737 | break; |
738 | } |
||
1963 | serge | 739 | if (i == dp_info->dp_lane_count) { |
1403 | serge | 740 | DRM_ERROR("clock recovery reached max voltage\n"); |
741 | break; |
||
742 | } |
||
743 | |||
1963 | serge | 744 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
745 | ++dp_info->tries; |
||
746 | if (dp_info->tries == 5) { |
||
1403 | serge | 747 | DRM_ERROR("clock recovery tried 5 times\n"); |
748 | break; |
||
749 | } |
||
750 | } else |
||
1963 | serge | 751 | dp_info->tries = 0; |
1403 | serge | 752 | |
1963 | serge | 753 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1403 | serge | 754 | |
755 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 756 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
757 | |||
758 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 759 | } |
1963 | serge | 760 | if (!clock_recovery) { |
1403 | serge | 761 | DRM_ERROR("clock recovery failed\n"); |
1963 | serge | 762 | return -1; |
763 | } else { |
||
764 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
||
765 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
766 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
||
1403 | serge | 767 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 768 | return 0; |
769 | } |
||
770 | } |
||
1403 | serge | 771 | |
1963 | serge | 772 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
773 | { |
||
774 | bool channel_eq; |
||
1403 | serge | 775 | |
1963 | serge | 776 | if (dp_info->tp3_supported) |
777 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
||
1430 | serge | 778 | else |
1963 | serge | 779 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
1403 | serge | 780 | |
781 | /* channel equalization loop */ |
||
1963 | serge | 782 | dp_info->tries = 0; |
1403 | serge | 783 | channel_eq = false; |
1963 | serge | 784 | while (1) { |
3192 | Serge | 785 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
1963 | serge | 786 | |
2997 | Serge | 787 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
788 | DRM_ERROR("displayport link status failed\n"); |
||
1403 | serge | 789 | break; |
2997 | Serge | 790 | } |
1403 | serge | 791 | |
3192 | Serge | 792 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 793 | channel_eq = true; |
794 | break; |
||
795 | } |
||
796 | |||
797 | /* Try 5 times */ |
||
1963 | serge | 798 | if (dp_info->tries > 5) { |
1403 | serge | 799 | DRM_ERROR("channel eq failed: 5 tries\n"); |
800 | break; |
||
801 | } |
||
802 | |||
803 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 804 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
1403 | serge | 805 | |
1963 | serge | 806 | radeon_dp_update_vs_emph(dp_info); |
807 | dp_info->tries++; |
||
1403 | serge | 808 | } |
809 | |||
1963 | serge | 810 | if (!channel_eq) { |
1403 | serge | 811 | DRM_ERROR("channel eq failed\n"); |
1963 | serge | 812 | return -1; |
813 | } else { |
||
814 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
||
815 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
816 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
1403 | serge | 817 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 818 | return 0; |
819 | } |
||
1403 | serge | 820 | } |
821 | |||
1963 | serge | 822 | void radeon_dp_link_train(struct drm_encoder *encoder, |
823 | struct drm_connector *connector) |
||
1403 | serge | 824 | { |
1963 | serge | 825 | struct drm_device *dev = encoder->dev; |
826 | struct radeon_device *rdev = dev->dev_private; |
||
827 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
828 | struct radeon_encoder_atom_dig *dig; |
||
829 | struct radeon_connector *radeon_connector; |
||
830 | struct radeon_connector_atom_dig *dig_connector; |
||
831 | struct radeon_dp_link_train_info dp_info; |
||
2160 | serge | 832 | int index; |
833 | u8 tmp, frev, crev; |
||
1403 | serge | 834 | |
1963 | serge | 835 | if (!radeon_encoder->enc_priv) |
836 | return; |
||
837 | dig = radeon_encoder->enc_priv; |
||
1403 | serge | 838 | |
1963 | serge | 839 | radeon_connector = to_radeon_connector(connector); |
840 | if (!radeon_connector->con_priv) |
||
841 | return; |
||
842 | dig_connector = radeon_connector->con_priv; |
||
1403 | serge | 843 | |
1963 | serge | 844 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
845 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
||
846 | return; |
||
1403 | serge | 847 | |
2160 | serge | 848 | /* DPEncoderService newer than 1.1 can't program properly the |
849 | * training pattern. When facing such version use the |
||
850 | * DIGXEncoderControl (X== 1 | 2) |
||
851 | */ |
||
852 | dp_info.use_dpencoder = true; |
||
853 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
854 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
||
855 | if (crev > 1) { |
||
856 | dp_info.use_dpencoder = false; |
||
857 | } |
||
858 | } |
||
859 | |||
1963 | serge | 860 | dp_info.enc_id = 0; |
861 | if (dig->dig_encoder) |
||
862 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
||
863 | else |
||
864 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
||
865 | if (dig->linkb) |
||
866 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
||
867 | else |
||
868 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
||
1403 | serge | 869 | |
1963 | serge | 870 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
871 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
||
872 | dp_info.tp3_supported = true; |
||
873 | else |
||
874 | dp_info.tp3_supported = false; |
||
1403 | serge | 875 | |
3192 | Serge | 876 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
1963 | serge | 877 | dp_info.rdev = rdev; |
878 | dp_info.encoder = encoder; |
||
879 | dp_info.connector = connector; |
||
880 | dp_info.radeon_connector = radeon_connector; |
||
881 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
||
882 | dp_info.dp_clock = dig_connector->dp_clock; |
||
1403 | serge | 883 | |
1963 | serge | 884 | if (radeon_dp_link_train_init(&dp_info)) |
885 | goto done; |
||
886 | if (radeon_dp_link_train_cr(&dp_info)) |
||
887 | goto done; |
||
888 | if (radeon_dp_link_train_ce(&dp_info)) |
||
889 | goto done; |
||
890 | done: |
||
891 | if (radeon_dp_link_train_finish(&dp_info)) |
||
892 | return; |
||
1403 | serge | 893 | }>=>>=>=>=>=>=><=>>>>>>>><>><>><>><>><>><>>>><>><>>>><>><> |