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1403 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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2997 | Serge | 25 | * Jerome Glisse |
1403 | serge | 26 | */ |
2997 | Serge | 27 | #include |
28 | #include |
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1403 | serge | 29 | #include "radeon.h" |
30 | |||
31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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2997 | Serge | 33 | #include |
1403 | serge | 34 | |
35 | /* move these to drm_dp_helper.c/h */ |
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36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
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37 | #define DP_LINK_STATUS_SIZE 6 |
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38 | #define DP_DPCD_SIZE 8 |
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39 | |||
40 | static char *voltage_names[] = { |
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41 | "0.4V", "0.6V", "0.8V", "1.2V" |
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42 | }; |
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43 | static char *pre_emph_names[] = { |
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44 | "0dB", "3.5dB", "6dB", "9.5dB" |
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45 | }; |
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46 | |||
1963 | serge | 47 | /***** radeon AUX functions *****/ |
48 | union aux_channel_transaction { |
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49 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
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50 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
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1403 | serge | 51 | }; |
52 | |||
1963 | serge | 53 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
54 | u8 *send, int send_bytes, |
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55 | u8 *recv, int recv_size, |
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56 | u8 delay, u8 *ack) |
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1403 | serge | 57 | { |
1963 | serge | 58 | struct drm_device *dev = chan->dev; |
59 | struct radeon_device *rdev = dev->dev_private; |
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60 | union aux_channel_transaction args; |
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61 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
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62 | unsigned char *base; |
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63 | int recv_bytes; |
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1403 | serge | 64 | |
1963 | serge | 65 | memset(&args, 0, sizeof(args)); |
1403 | serge | 66 | |
2997 | Serge | 67 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
1403 | serge | 68 | |
1963 | serge | 69 | memcpy(base, send, send_bytes); |
70 | |||
2997 | Serge | 71 | args.v1.lpAuxRequest = 0 + 4; |
72 | args.v1.lpDataOut = 16 + 4; |
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1963 | serge | 73 | args.v1.ucDataOutLen = 0; |
74 | args.v1.ucChannelID = chan->rec.i2c_id; |
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75 | args.v1.ucDelay = delay / 10; |
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76 | if (ASIC_IS_DCE4(rdev)) |
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77 | args.v2.ucHPD_ID = chan->rec.hpd; |
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78 | |||
79 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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80 | |||
81 | *ack = args.v1.ucReplyStatus; |
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82 | |||
83 | /* timeout */ |
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84 | if (args.v1.ucReplyStatus == 1) { |
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85 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
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86 | return -ETIMEDOUT; |
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1403 | serge | 87 | } |
1963 | serge | 88 | |
89 | /* flags not zero */ |
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90 | if (args.v1.ucReplyStatus == 2) { |
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91 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
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92 | return -EBUSY; |
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1403 | serge | 93 | } |
1963 | serge | 94 | |
95 | /* error */ |
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96 | if (args.v1.ucReplyStatus == 3) { |
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97 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
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98 | return -EIO; |
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1403 | serge | 99 | } |
1963 | serge | 100 | |
101 | recv_bytes = args.v1.ucDataOutLen; |
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102 | if (recv_bytes > recv_size) |
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103 | recv_bytes = recv_size; |
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104 | |||
105 | if (recv && recv_size) |
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106 | memcpy(recv, base + 16, recv_bytes); |
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107 | |||
108 | return recv_bytes; |
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109 | } |
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110 | |||
111 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, |
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112 | u16 address, u8 *send, u8 send_bytes, u8 delay) |
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113 | { |
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114 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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115 | int ret; |
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116 | u8 msg[20]; |
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117 | int msg_bytes = send_bytes + 4; |
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118 | u8 ack; |
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2997 | Serge | 119 | unsigned retry; |
1963 | serge | 120 | |
121 | if (send_bytes > 16) |
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122 | return -1; |
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123 | |||
124 | msg[0] = address; |
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125 | msg[1] = address >> 8; |
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126 | msg[2] = AUX_NATIVE_WRITE << 4; |
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127 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
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128 | memcpy(&msg[4], send, send_bytes); |
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129 | |||
2997 | Serge | 130 | for (retry = 0; retry < 4; retry++) { |
1963 | serge | 131 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
132 | msg, msg_bytes, NULL, 0, delay, &ack); |
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2997 | Serge | 133 | if (ret == -EBUSY) |
134 | continue; |
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135 | else if (ret < 0) |
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1963 | serge | 136 | return ret; |
137 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
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2997 | Serge | 138 | return send_bytes; |
1963 | serge | 139 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
140 | udelay(400); |
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141 | else |
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142 | return -EIO; |
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1403 | serge | 143 | } |
1963 | serge | 144 | |
2997 | Serge | 145 | return -EIO; |
1963 | serge | 146 | } |
147 | |||
148 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
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149 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
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150 | { |
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151 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
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152 | u8 msg[4]; |
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153 | int msg_bytes = 4; |
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154 | u8 ack; |
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155 | int ret; |
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2997 | Serge | 156 | unsigned retry; |
1963 | serge | 157 | |
158 | msg[0] = address; |
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159 | msg[1] = address >> 8; |
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160 | msg[2] = AUX_NATIVE_READ << 4; |
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161 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
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162 | |||
2997 | Serge | 163 | for (retry = 0; retry < 4; retry++) { |
1963 | serge | 164 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
165 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
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2997 | Serge | 166 | if (ret == -EBUSY) |
167 | continue; |
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168 | else if (ret < 0) |
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1963 | serge | 169 | return ret; |
170 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
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171 | return ret; |
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172 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
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173 | udelay(400); |
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2997 | Serge | 174 | else if (ret == 0) |
175 | return -EPROTO; |
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1403 | serge | 176 | else |
1963 | serge | 177 | return -EIO; |
1403 | serge | 178 | } |
2997 | Serge | 179 | |
180 | return -EIO; |
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1963 | serge | 181 | } |
1403 | serge | 182 | |
1963 | serge | 183 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
184 | u16 reg, u8 val) |
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185 | { |
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186 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); |
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1403 | serge | 187 | } |
188 | |||
1963 | serge | 189 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, |
190 | u16 reg) |
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1403 | serge | 191 | { |
1963 | serge | 192 | u8 val = 0; |
1403 | serge | 193 | |
1963 | serge | 194 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); |
1403 | serge | 195 | |
1963 | serge | 196 | return val; |
197 | } |
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1403 | serge | 198 | |
1963 | serge | 199 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
200 | u8 write_byte, u8 *read_byte) |
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201 | { |
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202 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
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203 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; |
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204 | u16 address = algo_data->address; |
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205 | u8 msg[5]; |
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206 | u8 reply[2]; |
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207 | unsigned retry; |
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208 | int msg_bytes; |
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209 | int reply_bytes = 1; |
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210 | int ret; |
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211 | u8 ack; |
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212 | |||
213 | /* Set up the command byte */ |
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214 | if (mode & MODE_I2C_READ) |
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215 | msg[2] = AUX_I2C_READ << 4; |
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216 | else |
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217 | msg[2] = AUX_I2C_WRITE << 4; |
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218 | |||
219 | if (!(mode & MODE_I2C_STOP)) |
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220 | msg[2] |= AUX_I2C_MOT << 4; |
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221 | |||
222 | msg[0] = address; |
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223 | msg[1] = address >> 8; |
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224 | |||
225 | switch (mode) { |
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226 | case MODE_I2C_WRITE: |
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227 | msg_bytes = 5; |
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228 | msg[3] = msg_bytes << 4; |
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229 | msg[4] = write_byte; |
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1403 | serge | 230 | break; |
1963 | serge | 231 | case MODE_I2C_READ: |
232 | msg_bytes = 4; |
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233 | msg[3] = msg_bytes << 4; |
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1403 | serge | 234 | break; |
235 | default: |
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1963 | serge | 236 | msg_bytes = 4; |
237 | msg[3] = 3 << 4; |
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1403 | serge | 238 | break; |
239 | } |
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1963 | serge | 240 | |
241 | for (retry = 0; retry < 4; retry++) { |
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242 | ret = radeon_process_aux_ch(auxch, |
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243 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
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2997 | Serge | 244 | if (ret == -EBUSY) |
245 | continue; |
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246 | else if (ret < 0) { |
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1963 | serge | 247 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
248 | return ret; |
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1403 | serge | 249 | } |
1963 | serge | 250 | |
251 | switch (ack & AUX_NATIVE_REPLY_MASK) { |
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252 | case AUX_NATIVE_REPLY_ACK: |
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253 | /* I2C-over-AUX Reply field is only valid |
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254 | * when paired with AUX ACK. |
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255 | */ |
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1403 | serge | 256 | break; |
1963 | serge | 257 | case AUX_NATIVE_REPLY_NACK: |
258 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
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259 | return -EREMOTEIO; |
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260 | case AUX_NATIVE_REPLY_DEFER: |
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261 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
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262 | udelay(400); |
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263 | continue; |
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264 | default: |
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265 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); |
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266 | return -EREMOTEIO; |
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267 | } |
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268 | |||
269 | switch (ack & AUX_I2C_REPLY_MASK) { |
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270 | case AUX_I2C_REPLY_ACK: |
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271 | if (mode == MODE_I2C_READ) |
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272 | *read_byte = reply[0]; |
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273 | return ret; |
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274 | case AUX_I2C_REPLY_NACK: |
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275 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
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276 | return -EREMOTEIO; |
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277 | case AUX_I2C_REPLY_DEFER: |
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278 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
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279 | udelay(400); |
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1403 | serge | 280 | break; |
281 | default: |
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1963 | serge | 282 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
283 | return -EREMOTEIO; |
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1403 | serge | 284 | } |
285 | } |
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286 | |||
2997 | Serge | 287 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
1963 | serge | 288 | return -EREMOTEIO; |
1403 | serge | 289 | } |
290 | |||
1963 | serge | 291 | /***** general DP utility functions *****/ |
1403 | serge | 292 | |
293 | static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) |
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294 | { |
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295 | return link_status[r - DP_LANE0_1_STATUS]; |
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296 | } |
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297 | |||
298 | static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], |
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299 | int lane) |
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300 | { |
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301 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
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302 | int s = (lane & 1) * 4; |
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303 | u8 l = dp_link_status(link_status, i); |
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304 | return (l >> s) & 0xf; |
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305 | } |
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306 | |||
307 | static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
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308 | int lane_count) |
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309 | { |
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310 | int lane; |
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311 | u8 lane_status; |
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312 | |||
313 | for (lane = 0; lane < lane_count; lane++) { |
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314 | lane_status = dp_get_lane_status(link_status, lane); |
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315 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
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316 | return false; |
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317 | } |
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318 | return true; |
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319 | } |
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320 | |||
321 | static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
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322 | int lane_count) |
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323 | { |
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324 | u8 lane_align; |
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325 | u8 lane_status; |
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326 | int lane; |
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327 | |||
328 | lane_align = dp_link_status(link_status, |
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329 | DP_LANE_ALIGN_STATUS_UPDATED); |
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330 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
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331 | return false; |
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332 | for (lane = 0; lane < lane_count; lane++) { |
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333 | lane_status = dp_get_lane_status(link_status, lane); |
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334 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) |
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335 | return false; |
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336 | } |
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337 | return true; |
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338 | } |
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339 | |||
1963 | serge | 340 | static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
1403 | serge | 341 | int lane) |
342 | |||
343 | { |
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344 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
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345 | int s = ((lane & 1) ? |
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346 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
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347 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
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348 | u8 l = dp_link_status(link_status, i); |
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349 | |||
350 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
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351 | } |
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352 | |||
1963 | serge | 353 | static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
1403 | serge | 354 | int lane) |
355 | { |
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356 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
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357 | int s = ((lane & 1) ? |
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358 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
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359 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
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360 | u8 l = dp_link_status(link_status, i); |
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361 | |||
362 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
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363 | } |
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364 | |||
365 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
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1963 | serge | 366 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
1403 | serge | 367 | |
368 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
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369 | int lane_count, |
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370 | u8 train_set[4]) |
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371 | { |
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372 | u8 v = 0; |
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373 | u8 p = 0; |
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374 | int lane; |
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375 | |||
376 | for (lane = 0; lane < lane_count; lane++) { |
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377 | u8 this_v = dp_get_adjust_request_voltage(link_status, lane); |
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378 | u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); |
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379 | |||
1963 | serge | 380 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
1403 | serge | 381 | lane, |
382 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
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383 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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384 | |||
385 | if (this_v > v) |
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386 | v = this_v; |
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387 | if (this_p > p) |
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388 | p = this_p; |
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389 | } |
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390 | |||
391 | if (v >= DP_VOLTAGE_MAX) |
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1963 | serge | 392 | v |= DP_TRAIN_MAX_SWING_REACHED; |
1403 | serge | 393 | |
1963 | serge | 394 | if (p >= DP_PRE_EMPHASIS_MAX) |
395 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
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1403 | serge | 396 | |
1963 | serge | 397 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
1403 | serge | 398 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
399 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
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400 | |||
401 | for (lane = 0; lane < 4; lane++) |
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402 | train_set[lane] = v | p; |
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403 | } |
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404 | |||
1963 | serge | 405 | /* convert bits per color to bits per pixel */ |
406 | /* get bpc from the EDID */ |
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407 | static int convert_bpc_to_bpp(int bpc) |
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408 | { |
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409 | if (bpc == 0) |
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410 | return 24; |
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411 | else |
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412 | return bpc * 3; |
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413 | } |
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1403 | serge | 414 | |
1963 | serge | 415 | /* get the max pix clock supported by the link rate and lane num */ |
416 | static int dp_get_max_dp_pix_clock(int link_rate, |
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417 | int lane_num, |
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418 | int bpp) |
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1403 | serge | 419 | { |
1963 | serge | 420 | return (link_rate * lane_num * 8) / bpp; |
421 | } |
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1403 | serge | 422 | |
1963 | serge | 423 | static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE]) |
424 | { |
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425 | switch (dpcd[DP_MAX_LINK_RATE]) { |
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426 | case DP_LINK_BW_1_62: |
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427 | default: |
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428 | return 162000; |
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429 | case DP_LINK_BW_2_7: |
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430 | return 270000; |
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431 | case DP_LINK_BW_5_4: |
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432 | return 540000; |
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433 | } |
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434 | } |
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1403 | serge | 435 | |
1963 | serge | 436 | static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) |
437 | { |
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438 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
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439 | } |
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1403 | serge | 440 | |
1963 | serge | 441 | static u8 dp_get_dp_link_rate_coded(int link_rate) |
442 | { |
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443 | switch (link_rate) { |
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444 | case 162000: |
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445 | default: |
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446 | return DP_LINK_BW_1_62; |
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447 | case 270000: |
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448 | return DP_LINK_BW_2_7; |
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449 | case 540000: |
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450 | return DP_LINK_BW_5_4; |
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451 | } |
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452 | } |
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1403 | serge | 453 | |
1963 | serge | 454 | /***** radeon specific DP functions *****/ |
1403 | serge | 455 | |
1963 | serge | 456 | /* First get the min lane# when low rate is used according to pixel clock |
457 | * (prefer low rate), second check max lane# supported by DP panel, |
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458 | * if the max lane# < low rate lane# then use max lane# instead. |
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459 | */ |
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460 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
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461 | u8 dpcd[DP_DPCD_SIZE], |
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462 | int pix_clock) |
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463 | { |
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2997 | Serge | 464 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
1963 | serge | 465 | int max_link_rate = dp_get_max_link_rate(dpcd); |
466 | int max_lane_num = dp_get_max_lane_number(dpcd); |
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467 | int lane_num; |
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468 | int max_dp_pix_clock; |
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1403 | serge | 469 | |
1963 | serge | 470 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { |
471 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); |
||
472 | if (pix_clock <= max_dp_pix_clock) |
||
473 | break; |
||
1403 | serge | 474 | } |
475 | |||
1963 | serge | 476 | return lane_num; |
1403 | serge | 477 | } |
478 | |||
1963 | serge | 479 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
480 | u8 dpcd[DP_DPCD_SIZE], |
||
481 | int pix_clock) |
||
1403 | serge | 482 | { |
2997 | Serge | 483 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
1963 | serge | 484 | int lane_num, max_pix_clock; |
1403 | serge | 485 | |
2997 | Serge | 486 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
487 | ENCODER_OBJECT_ID_NUTMEG) |
||
1963 | serge | 488 | return 270000; |
1403 | serge | 489 | |
1963 | serge | 490 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); |
491 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); |
||
492 | if (pix_clock <= max_pix_clock) |
||
493 | return 162000; |
||
494 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); |
||
495 | if (pix_clock <= max_pix_clock) |
||
496 | return 270000; |
||
497 | if (radeon_connector_is_dp12_capable(connector)) { |
||
498 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); |
||
499 | if (pix_clock <= max_pix_clock) |
||
500 | return 540000; |
||
501 | } |
||
1403 | serge | 502 | |
1963 | serge | 503 | return dp_get_max_link_rate(dpcd); |
1403 | serge | 504 | } |
505 | |||
1963 | serge | 506 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
507 | int action, int dp_clock, |
||
508 | u8 ucconfig, u8 lane_num) |
||
1403 | serge | 509 | { |
510 | DP_ENCODER_SERVICE_PARAMETERS args; |
||
511 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
512 | |||
513 | memset(&args, 0, sizeof(args)); |
||
514 | args.ucLinkClock = dp_clock / 10; |
||
515 | args.ucConfig = ucconfig; |
||
516 | args.ucAction = action; |
||
517 | args.ucLaneNum = lane_num; |
||
518 | args.ucStatus = 0; |
||
519 | |||
520 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
521 | return args.ucStatus; |
||
522 | } |
||
523 | |||
524 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
||
525 | { |
||
526 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
527 | struct drm_device *dev = radeon_connector->base.dev; |
||
528 | struct radeon_device *rdev = dev->dev_private; |
||
529 | |||
530 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
||
531 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
||
532 | } |
||
533 | |||
2997 | Serge | 534 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
535 | { |
||
536 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
537 | u8 buf[3]; |
||
538 | |||
539 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
||
540 | return; |
||
541 | |||
542 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) |
||
543 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
||
544 | buf[0], buf[1], buf[2]); |
||
545 | |||
546 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) |
||
547 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
||
548 | buf[0], buf[1], buf[2]); |
||
549 | } |
||
550 | |||
1403 | serge | 551 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
552 | { |
||
553 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
554 | u8 msg[25]; |
||
1963 | serge | 555 | int ret, i; |
1403 | serge | 556 | |
1963 | serge | 557 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0); |
558 | if (ret > 0) { |
||
1403 | serge | 559 | memcpy(dig_connector->dpcd, msg, 8); |
1963 | serge | 560 | DRM_DEBUG_KMS("DPCD: "); |
1403 | serge | 561 | for (i = 0; i < 8; i++) |
1963 | serge | 562 | DRM_DEBUG_KMS("%02x ", msg[i]); |
563 | DRM_DEBUG_KMS("\n"); |
||
2997 | Serge | 564 | |
565 | radeon_dp_probe_oui(radeon_connector); |
||
566 | |||
1403 | serge | 567 | return true; |
568 | } |
||
569 | dig_connector->dpcd[0] = 0; |
||
570 | return false; |
||
571 | } |
||
572 | |||
2997 | Serge | 573 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
1963 | serge | 574 | struct drm_connector *connector) |
575 | { |
||
576 | struct drm_device *dev = encoder->dev; |
||
577 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 578 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1963 | serge | 579 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
2997 | Serge | 580 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
581 | u8 tmp; |
||
1963 | serge | 582 | |
583 | if (!ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 584 | return panel_mode; |
1963 | serge | 585 | |
2997 | Serge | 586 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
587 | /* DP bridge chips */ |
||
588 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
||
589 | if (tmp & 1) |
||
590 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
591 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
||
592 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
||
1963 | serge | 593 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
2997 | Serge | 594 | else |
595 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
||
596 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
||
597 | /* eDP */ |
||
598 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
||
599 | if (tmp & 1) |
||
600 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
||
601 | } |
||
1963 | serge | 602 | |
2997 | Serge | 603 | return panel_mode; |
1963 | serge | 604 | } |
605 | |||
1403 | serge | 606 | void radeon_dp_set_link_config(struct drm_connector *connector, |
2997 | Serge | 607 | const struct drm_display_mode *mode) |
1403 | serge | 608 | { |
1963 | serge | 609 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1403 | serge | 610 | struct radeon_connector_atom_dig *dig_connector; |
611 | |||
612 | if (!radeon_connector->con_priv) |
||
613 | return; |
||
614 | dig_connector = radeon_connector->con_priv; |
||
615 | |||
1963 | serge | 616 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
617 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
||
1403 | serge | 618 | dig_connector->dp_clock = |
1963 | serge | 619 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
1403 | serge | 620 | dig_connector->dp_lane_count = |
1963 | serge | 621 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); |
622 | } |
||
1403 | serge | 623 | } |
624 | |||
1963 | serge | 625 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
1403 | serge | 626 | struct drm_display_mode *mode) |
627 | { |
||
1963 | serge | 628 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
629 | struct radeon_connector_atom_dig *dig_connector; |
||
630 | int dp_clock; |
||
1403 | serge | 631 | |
1963 | serge | 632 | if (!radeon_connector->con_priv) |
633 | return MODE_CLOCK_HIGH; |
||
634 | dig_connector = radeon_connector->con_priv; |
||
635 | |||
636 | dp_clock = |
||
637 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
||
638 | |||
639 | if ((dp_clock == 540000) && |
||
640 | (!radeon_connector_is_dp12_capable(connector))) |
||
641 | return MODE_CLOCK_HIGH; |
||
642 | |||
643 | return MODE_OK; |
||
1403 | serge | 644 | } |
645 | |||
1963 | serge | 646 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
1403 | serge | 647 | u8 link_status[DP_LINK_STATUS_SIZE]) |
648 | { |
||
649 | int ret; |
||
1963 | serge | 650 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
651 | link_status, DP_LINK_STATUS_SIZE, 100); |
||
652 | if (ret <= 0) { |
||
1403 | serge | 653 | return false; |
654 | } |
||
655 | |||
2997 | Serge | 656 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
1403 | serge | 657 | return true; |
658 | } |
||
659 | |||
2997 | Serge | 660 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
661 | { |
||
662 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
663 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
||
664 | |||
665 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) |
||
666 | return false; |
||
667 | if (dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
||
668 | return false; |
||
669 | return true; |
||
670 | } |
||
671 | |||
1963 | serge | 672 | struct radeon_dp_link_train_info { |
673 | struct radeon_device *rdev; |
||
674 | struct drm_encoder *encoder; |
||
675 | struct drm_connector *connector; |
||
676 | struct radeon_connector *radeon_connector; |
||
677 | int enc_id; |
||
678 | int dp_clock; |
||
679 | int dp_lane_count; |
||
680 | int rd_interval; |
||
681 | bool tp3_supported; |
||
682 | u8 dpcd[8]; |
||
683 | u8 train_set[4]; |
||
1403 | serge | 684 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1963 | serge | 685 | u8 tries; |
2160 | serge | 686 | bool use_dpencoder; |
1963 | serge | 687 | }; |
1403 | serge | 688 | |
1963 | serge | 689 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
690 | { |
||
691 | /* set the initial vs/emph on the source */ |
||
692 | atombios_dig_transmitter_setup(dp_info->encoder, |
||
693 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
||
694 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
||
695 | |||
696 | /* set the vs/emph on the sink */ |
||
697 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, |
||
698 | dp_info->train_set, dp_info->dp_lane_count, 0); |
||
1403 | serge | 699 | } |
700 | |||
1963 | serge | 701 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
1403 | serge | 702 | { |
1963 | serge | 703 | int rtp = 0; |
1403 | serge | 704 | |
1963 | serge | 705 | /* set training pattern on the source */ |
2160 | serge | 706 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
1963 | serge | 707 | switch (tp) { |
708 | case DP_TRAINING_PATTERN_1: |
||
709 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
||
710 | break; |
||
711 | case DP_TRAINING_PATTERN_2: |
||
712 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
||
713 | break; |
||
714 | case DP_TRAINING_PATTERN_3: |
||
715 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
||
716 | break; |
||
717 | } |
||
718 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
||
719 | } else { |
||
720 | switch (tp) { |
||
721 | case DP_TRAINING_PATTERN_1: |
||
722 | rtp = 0; |
||
723 | break; |
||
724 | case DP_TRAINING_PATTERN_2: |
||
725 | rtp = 1; |
||
726 | break; |
||
727 | } |
||
728 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
||
729 | dp_info->dp_clock, dp_info->enc_id, rtp); |
||
1403 | serge | 730 | } |
731 | |||
1963 | serge | 732 | /* enable training pattern on the sink */ |
733 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
||
1403 | serge | 734 | } |
735 | |||
1963 | serge | 736 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 737 | { |
2997 | Serge | 738 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
739 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
1963 | serge | 740 | u8 tmp; |
1403 | serge | 741 | |
1963 | serge | 742 | /* power up the sink */ |
743 | if (dp_info->dpcd[0] >= 0x11) |
||
744 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
745 | DP_SET_POWER, DP_SET_POWER_D0); |
||
1403 | serge | 746 | |
1963 | serge | 747 | /* possibly enable downspread on the sink */ |
748 | if (dp_info->dpcd[3] & 0x1) |
||
749 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
750 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
||
751 | else |
||
752 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
753 | DP_DOWNSPREAD_CTRL, 0); |
||
1403 | serge | 754 | |
2997 | Serge | 755 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
756 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
||
757 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); |
||
758 | } |
||
1403 | serge | 759 | |
1963 | serge | 760 | /* set the lane count on the sink */ |
761 | tmp = dp_info->dp_lane_count; |
||
2997 | Serge | 762 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
763 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) |
||
1963 | serge | 764 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
765 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
||
766 | |||
767 | /* set the link rate on the sink */ |
||
768 | tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); |
||
769 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
||
770 | |||
771 | /* start training on the source */ |
||
2160 | serge | 772 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 773 | atombios_dig_encoder_setup(dp_info->encoder, |
774 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
||
775 | else |
||
776 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
||
777 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
778 | |||
779 | /* disable the training pattern on the sink */ |
||
780 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
781 | DP_TRAINING_PATTERN_SET, |
||
782 | DP_TRAINING_PATTERN_DISABLE); |
||
783 | |||
784 | return 0; |
||
1403 | serge | 785 | } |
786 | |||
1963 | serge | 787 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
1403 | serge | 788 | { |
1963 | serge | 789 | udelay(400); |
1403 | serge | 790 | |
1963 | serge | 791 | /* disable the training pattern on the sink */ |
792 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
||
793 | DP_TRAINING_PATTERN_SET, |
||
794 | DP_TRAINING_PATTERN_DISABLE); |
||
1403 | serge | 795 | |
1963 | serge | 796 | /* disable the training pattern on the source */ |
2160 | serge | 797 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
1963 | serge | 798 | atombios_dig_encoder_setup(dp_info->encoder, |
799 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
||
800 | else |
||
801 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
||
802 | dp_info->dp_clock, dp_info->enc_id, 0); |
||
1403 | serge | 803 | |
1963 | serge | 804 | return 0; |
805 | } |
||
1403 | serge | 806 | |
1963 | serge | 807 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
808 | { |
||
809 | bool clock_recovery; |
||
810 | u8 voltage; |
||
811 | int i; |
||
1403 | serge | 812 | |
1963 | serge | 813 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
814 | memset(dp_info->train_set, 0, 4); |
||
815 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 816 | |
817 | udelay(400); |
||
818 | |||
819 | /* clock recovery loop */ |
||
820 | clock_recovery = false; |
||
1963 | serge | 821 | dp_info->tries = 0; |
1403 | serge | 822 | voltage = 0xff; |
1963 | serge | 823 | while (1) { |
824 | if (dp_info->rd_interval == 0) |
||
1403 | serge | 825 | udelay(100); |
1963 | serge | 826 | else |
827 | mdelay(dp_info->rd_interval * 4); |
||
828 | |||
2997 | Serge | 829 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
830 | DRM_ERROR("displayport link status failed\n"); |
||
1403 | serge | 831 | break; |
2997 | Serge | 832 | } |
1403 | serge | 833 | |
1963 | serge | 834 | if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 835 | clock_recovery = true; |
836 | break; |
||
837 | } |
||
838 | |||
1963 | serge | 839 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
840 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1403 | serge | 841 | break; |
842 | } |
||
1963 | serge | 843 | if (i == dp_info->dp_lane_count) { |
1403 | serge | 844 | DRM_ERROR("clock recovery reached max voltage\n"); |
845 | break; |
||
846 | } |
||
847 | |||
1963 | serge | 848 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
849 | ++dp_info->tries; |
||
850 | if (dp_info->tries == 5) { |
||
1403 | serge | 851 | DRM_ERROR("clock recovery tried 5 times\n"); |
852 | break; |
||
853 | } |
||
854 | } else |
||
1963 | serge | 855 | dp_info->tries = 0; |
1403 | serge | 856 | |
1963 | serge | 857 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1403 | serge | 858 | |
859 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 860 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
861 | |||
862 | radeon_dp_update_vs_emph(dp_info); |
||
1403 | serge | 863 | } |
1963 | serge | 864 | if (!clock_recovery) { |
1403 | serge | 865 | DRM_ERROR("clock recovery failed\n"); |
1963 | serge | 866 | return -1; |
867 | } else { |
||
868 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
||
869 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
870 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
||
1403 | serge | 871 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 872 | return 0; |
873 | } |
||
874 | } |
||
1403 | serge | 875 | |
1963 | serge | 876 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
877 | { |
||
878 | bool channel_eq; |
||
1403 | serge | 879 | |
1963 | serge | 880 | if (dp_info->tp3_supported) |
881 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
||
1430 | serge | 882 | else |
1963 | serge | 883 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
1403 | serge | 884 | |
885 | /* channel equalization loop */ |
||
1963 | serge | 886 | dp_info->tries = 0; |
1403 | serge | 887 | channel_eq = false; |
1963 | serge | 888 | while (1) { |
889 | if (dp_info->rd_interval == 0) |
||
1403 | serge | 890 | udelay(400); |
1963 | serge | 891 | else |
892 | mdelay(dp_info->rd_interval * 4); |
||
893 | |||
2997 | Serge | 894 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
895 | DRM_ERROR("displayport link status failed\n"); |
||
1403 | serge | 896 | break; |
2997 | Serge | 897 | } |
1403 | serge | 898 | |
1963 | serge | 899 | if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
1403 | serge | 900 | channel_eq = true; |
901 | break; |
||
902 | } |
||
903 | |||
904 | /* Try 5 times */ |
||
1963 | serge | 905 | if (dp_info->tries > 5) { |
1403 | serge | 906 | DRM_ERROR("channel eq failed: 5 tries\n"); |
907 | break; |
||
908 | } |
||
909 | |||
910 | /* Compute new train_set as requested by sink */ |
||
1963 | serge | 911 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
1403 | serge | 912 | |
1963 | serge | 913 | radeon_dp_update_vs_emph(dp_info); |
914 | dp_info->tries++; |
||
1403 | serge | 915 | } |
916 | |||
1963 | serge | 917 | if (!channel_eq) { |
1403 | serge | 918 | DRM_ERROR("channel eq failed\n"); |
1963 | serge | 919 | return -1; |
920 | } else { |
||
921 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
||
922 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
||
923 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
||
1403 | serge | 924 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
1963 | serge | 925 | return 0; |
926 | } |
||
1403 | serge | 927 | } |
928 | |||
1963 | serge | 929 | void radeon_dp_link_train(struct drm_encoder *encoder, |
930 | struct drm_connector *connector) |
||
1403 | serge | 931 | { |
1963 | serge | 932 | struct drm_device *dev = encoder->dev; |
933 | struct radeon_device *rdev = dev->dev_private; |
||
934 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
935 | struct radeon_encoder_atom_dig *dig; |
||
936 | struct radeon_connector *radeon_connector; |
||
937 | struct radeon_connector_atom_dig *dig_connector; |
||
938 | struct radeon_dp_link_train_info dp_info; |
||
2160 | serge | 939 | int index; |
940 | u8 tmp, frev, crev; |
||
1403 | serge | 941 | |
1963 | serge | 942 | if (!radeon_encoder->enc_priv) |
943 | return; |
||
944 | dig = radeon_encoder->enc_priv; |
||
1403 | serge | 945 | |
1963 | serge | 946 | radeon_connector = to_radeon_connector(connector); |
947 | if (!radeon_connector->con_priv) |
||
948 | return; |
||
949 | dig_connector = radeon_connector->con_priv; |
||
1403 | serge | 950 | |
1963 | serge | 951 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
952 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
||
953 | return; |
||
1403 | serge | 954 | |
2160 | serge | 955 | /* DPEncoderService newer than 1.1 can't program properly the |
956 | * training pattern. When facing such version use the |
||
957 | * DIGXEncoderControl (X== 1 | 2) |
||
958 | */ |
||
959 | dp_info.use_dpencoder = true; |
||
960 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
||
961 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
||
962 | if (crev > 1) { |
||
963 | dp_info.use_dpencoder = false; |
||
964 | } |
||
965 | } |
||
966 | |||
1963 | serge | 967 | dp_info.enc_id = 0; |
968 | if (dig->dig_encoder) |
||
969 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
||
970 | else |
||
971 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
||
972 | if (dig->linkb) |
||
973 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
||
974 | else |
||
975 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
||
1403 | serge | 976 | |
1963 | serge | 977 | dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL); |
978 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
||
979 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
||
980 | dp_info.tp3_supported = true; |
||
981 | else |
||
982 | dp_info.tp3_supported = false; |
||
1403 | serge | 983 | |
1963 | serge | 984 | memcpy(dp_info.dpcd, dig_connector->dpcd, 8); |
985 | dp_info.rdev = rdev; |
||
986 | dp_info.encoder = encoder; |
||
987 | dp_info.connector = connector; |
||
988 | dp_info.radeon_connector = radeon_connector; |
||
989 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
||
990 | dp_info.dp_clock = dig_connector->dp_clock; |
||
1403 | serge | 991 | |
1963 | serge | 992 | if (radeon_dp_link_train_init(&dp_info)) |
993 | goto done; |
||
994 | if (radeon_dp_link_train_cr(&dp_info)) |
||
995 | goto done; |
||
996 | if (radeon_dp_link_train_ce(&dp_info)) |
||
997 | goto done; |
||
998 | done: |
||
999 | if (radeon_dp_link_train_finish(&dp_info)) |
||
1000 | return; |
||
1403 | serge | 1001 | }>=>>=>=>=>=>=><=>>>>>><>><>>>>>><>><>><>><>><>><>>>><>><>>>><>><> |