WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/atombios_crtc.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1179	serge	26	#include
		27	#include
		28	#include
1963	serge	29	#include
1123	serge	30	#include "radeon.h"
		31	#include "atom.h"
		32	#include "atom-bits.h"
		33
1179	serge	34	static void atombios_overscan_setup(struct drm_crtc *crtc,
		35	struct drm_display_mode *mode,
		36	struct drm_display_mode *adjusted_mode)
		37	{
		38	struct drm_device *dev = crtc->dev;
		39	struct radeon_device *rdev = dev->dev_private;
		40	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		41	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
		42	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
		43	int a1, a2;
		44
		45	memset(&args, 0, sizeof(args));
		46
		47	args.ucCRTC = radeon_crtc->crtc_id;
		48
		49	switch (radeon_crtc->rmx_type) {
		50	case RMX_CENTER:
1963	serge	51	args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		52	args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		53	args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
		54	args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
1179	serge	55	break;
		56	case RMX_ASPECT:
		57	a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
		58	a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
		59
		60	if (a1 > a2) {
1963	serge	61	args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
		62	args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
1179	serge	63	} else if (a2 > a1) {
1963	serge	64	args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
		65	args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
1179	serge	66	}
		67	break;
		68	case RMX_FULL:
		69	default:
1963	serge	70	args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
		71	args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
		72	args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
		73	args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
1179	serge	74	break;
		75	}
1963	serge	76	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1179	serge	77	}
		78
		79	static void atombios_scaler_setup(struct drm_crtc *crtc)
		80	{
		81	struct drm_device *dev = crtc->dev;
		82	struct radeon_device *rdev = dev->dev_private;
		83	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		84	ENABLE_SCALER_PS_ALLOCATION args;
		85	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
2997	Serge	86	struct radeon_encoder *radeon_encoder =
		87	to_radeon_encoder(radeon_crtc->encoder);
1179	serge	88	/* fixme - fill in enc_priv for atom dac */
		89	enum radeon_tv_std tv_std = TV_STD_NTSC;
		90	bool is_tv = false, is_cv = false;
		91
		92	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
		93	return;
		94
3031	serge	95	if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
		96	struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
		97	tv_std = tv_dac->tv_std;
		98	is_tv = true;
		99	}
1179	serge	100
		101	memset(&args, 0, sizeof(args));
		102
		103	args.ucScaler = radeon_crtc->crtc_id;
		104
		105	if (is_tv) {
		106	switch (tv_std) {
		107	case TV_STD_NTSC:
		108	default:
		109	args.ucTVStandard = ATOM_TV_NTSC;
		110	break;
		111	case TV_STD_PAL:
		112	args.ucTVStandard = ATOM_TV_PAL;
		113	break;
		114	case TV_STD_PAL_M:
		115	args.ucTVStandard = ATOM_TV_PALM;
		116	break;
		117	case TV_STD_PAL_60:
		118	args.ucTVStandard = ATOM_TV_PAL60;
		119	break;
		120	case TV_STD_NTSC_J:
		121	args.ucTVStandard = ATOM_TV_NTSCJ;
		122	break;
		123	case TV_STD_SCART_PAL:
		124	args.ucTVStandard = ATOM_TV_PAL; /* ??? */
		125	break;
		126	case TV_STD_SECAM:
		127	args.ucTVStandard = ATOM_TV_SECAM;
		128	break;
		129	case TV_STD_PAL_CN:
		130	args.ucTVStandard = ATOM_TV_PALCN;
		131	break;
		132	}
		133	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		134	} else if (is_cv) {
		135	args.ucTVStandard = ATOM_TV_CV;
		136	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		137	} else {
		138	switch (radeon_crtc->rmx_type) {
		139	case RMX_FULL:
		140	args.ucEnable = ATOM_SCALER_EXPANSION;
		141	break;
		142	case RMX_CENTER:
		143	args.ucEnable = ATOM_SCALER_CENTER;
		144	break;
		145	case RMX_ASPECT:
		146	args.ucEnable = ATOM_SCALER_EXPANSION;
		147	break;
		148	default:
		149	if (ASIC_IS_AVIVO(rdev))
		150	args.ucEnable = ATOM_SCALER_DISABLE;
		151	else
		152	args.ucEnable = ATOM_SCALER_CENTER;
		153	break;
		154	}
		155	}
		156	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		157	if ((is_tv \|\| is_cv)
		158	&& rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
		159	atom_rv515_force_tv_scaler(rdev, radeon_crtc);
		160	}
		161	}
		162
1123	serge	163	static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
		164	{
		165	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		166	struct drm_device *dev = crtc->dev;
		167	struct radeon_device *rdev = dev->dev_private;
		168	int index =
		169	GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
		170	ENABLE_CRTC_PS_ALLOCATION args;
		171
		172	memset(&args, 0, sizeof(args));
		173
		174	args.ucCRTC = radeon_crtc->crtc_id;
		175	args.ucEnable = lock;
		176
		177	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		178	}
		179
		180	static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
		181	{
		182	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		183	struct drm_device *dev = crtc->dev;
		184	struct radeon_device *rdev = dev->dev_private;
		185	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
		186	ENABLE_CRTC_PS_ALLOCATION args;
		187
		188	memset(&args, 0, sizeof(args));
		189
		190	args.ucCRTC = radeon_crtc->crtc_id;
		191	args.ucEnable = state;
		192
		193	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		194	}
		195
		196	static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
		197	{
		198	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		199	struct drm_device *dev = crtc->dev;
		200	struct radeon_device *rdev = dev->dev_private;
		201	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
		202	ENABLE_CRTC_PS_ALLOCATION args;
		203
		204	memset(&args, 0, sizeof(args));
		205
		206	args.ucCRTC = radeon_crtc->crtc_id;
		207	args.ucEnable = state;
		208
		209	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		210	}
		211
5078	serge	212	static const u32 vga_control_regs[6] =
		213	{
		214	AVIVO_D1VGA_CONTROL,
		215	AVIVO_D2VGA_CONTROL,
		216	EVERGREEN_D3VGA_CONTROL,
		217	EVERGREEN_D4VGA_CONTROL,
		218	EVERGREEN_D5VGA_CONTROL,
		219	EVERGREEN_D6VGA_CONTROL,
		220	};
		221
1123	serge	222	static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
		223	{
		224	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		225	struct drm_device *dev = crtc->dev;
		226	struct radeon_device *rdev = dev->dev_private;
		227	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
		228	BLANK_CRTC_PS_ALLOCATION args;
5078	serge	229	u32 vga_control = 0;
1123	serge	230
		231	memset(&args, 0, sizeof(args));
		232
5078	serge	233	if (ASIC_IS_DCE8(rdev)) {
		234	vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
		235	WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control \| 1);
		236	}
		237
1123	serge	238	args.ucCRTC = radeon_crtc->crtc_id;
		239	args.ucBlanking = state;
		240
		241	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
5078	serge	242
		243	if (ASIC_IS_DCE8(rdev)) {
		244	WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
		245	}
1123	serge	246	}
		247
2997	Serge	248	static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
		249	{
		250	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		251	struct drm_device *dev = crtc->dev;
		252	struct radeon_device *rdev = dev->dev_private;
		253	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
		254	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
		255
		256	memset(&args, 0, sizeof(args));
		257
		258	args.ucDispPipeId = radeon_crtc->crtc_id;
		259	args.ucEnable = state;
		260
		261	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		262	}
		263
1123	serge	264	void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
		265	{
		266	struct drm_device *dev = crtc->dev;
		267	struct radeon_device *rdev = dev->dev_private;
1321	serge	268	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	269
		270	switch (mode) {
		271	case DRM_MODE_DPMS_ON:
1963	serge	272	radeon_crtc->enabled = true;
1430	serge	273	atombios_enable_crtc(crtc, ATOM_ENABLE);
2997	Serge	274	if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
1430	serge	275	atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
		276	atombios_blank_crtc(crtc, ATOM_DISABLE);
3031	serge	277	drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
1321	serge	278	radeon_crtc_load_lut(crtc);
1123	serge	279	break;
		280	case DRM_MODE_DPMS_STANDBY:
		281	case DRM_MODE_DPMS_SUSPEND:
		282	case DRM_MODE_DPMS_OFF:
3031	serge	283	drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
1963	serge	284	if (radeon_crtc->enabled)
3031	serge	285	atombios_blank_crtc(crtc, ATOM_ENABLE);
2997	Serge	286	if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
1430	serge	287	atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
		288	atombios_enable_crtc(crtc, ATOM_DISABLE);
1963	serge	289	radeon_crtc->enabled = false;
1123	serge	290	break;
		291	}
5078	serge	292	/* adjust pm to dpms */
		293	radeon_pm_compute_clocks(rdev);
1123	serge	294	}
		295
		296	static void
		297	atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
1268	serge	298	struct drm_display_mode *mode)
1123	serge	299	{
1268	serge	300	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	301	struct drm_device *dev = crtc->dev;
		302	struct radeon_device *rdev = dev->dev_private;
1268	serge	303	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
1123	serge	304	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
1268	serge	305	u16 misc = 0;
1123	serge	306
1268	serge	307	memset(&args, 0, sizeof(args));
1963	serge	308	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
1268	serge	309	args.usH_Blanking_Time =
1963	serge	310	cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
		311	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
1268	serge	312	args.usV_Blanking_Time =
1963	serge	313	cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
1268	serge	314	args.usH_SyncOffset =
1963	serge	315	cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
1268	serge	316	args.usH_SyncWidth =
		317	cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
		318	args.usV_SyncOffset =
1963	serge	319	cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
1268	serge	320	args.usV_SyncWidth =
		321	cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
1963	serge	322	args.ucH_Border = radeon_crtc->h_border;
		323	args.ucV_Border = radeon_crtc->v_border;
1123	serge	324
1268	serge	325	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		326	misc \|= ATOM_VSYNC_POLARITY;
		327	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		328	misc \|= ATOM_HSYNC_POLARITY;
		329	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		330	misc \|= ATOM_COMPOSITESYNC;
		331	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		332	misc \|= ATOM_INTERLACE;
6104	serge	333	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		334	misc \|= ATOM_DOUBLE_CLOCK_MODE;
1268	serge	335	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
6104	serge	336	misc \|= ATOM_H_REPLICATIONBY2 \| ATOM_V_REPLICATIONBY2;
1268	serge	337
		338	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
		339	args.ucCRTC = radeon_crtc->crtc_id;
		340
		341	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1123	serge	342	}
		343
1268	serge	344	static void atombios_crtc_set_timing(struct drm_crtc *crtc,
		345	struct drm_display_mode *mode)
1123	serge	346	{
1268	serge	347	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	348	struct drm_device *dev = crtc->dev;
		349	struct radeon_device *rdev = dev->dev_private;
1268	serge	350	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
1123	serge	351	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
1268	serge	352	u16 misc = 0;
1123	serge	353
1268	serge	354	memset(&args, 0, sizeof(args));
		355	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
		356	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
		357	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
		358	args.usH_SyncWidth =
		359	cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
		360	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
		361	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
		362	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
		363	args.usV_SyncWidth =
		364	cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
1123	serge	365
1963	serge	366	args.ucOverscanRight = radeon_crtc->h_border;
		367	args.ucOverscanLeft = radeon_crtc->h_border;
		368	args.ucOverscanBottom = radeon_crtc->v_border;
		369	args.ucOverscanTop = radeon_crtc->v_border;
		370
1268	serge	371	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		372	misc \|= ATOM_VSYNC_POLARITY;
		373	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		374	misc \|= ATOM_HSYNC_POLARITY;
		375	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		376	misc \|= ATOM_COMPOSITESYNC;
		377	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		378	misc \|= ATOM_INTERLACE;
6104	serge	379	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		380	misc \|= ATOM_DOUBLE_CLOCK_MODE;
1268	serge	381	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
6104	serge	382	misc \|= ATOM_H_REPLICATIONBY2 \| ATOM_V_REPLICATIONBY2;
1268	serge	383
		384	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
		385	args.ucCRTC = radeon_crtc->crtc_id;
		386
		387	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1123	serge	388	}
		389
2997	Serge	390	static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
1963	serge	391	{
		392	u32 ss_cntl;
		393
		394	if (ASIC_IS_DCE4(rdev)) {
2997	Serge	395	switch (pll_id) {
1963	serge	396	case ATOM_PPLL1:
		397	ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
		398	ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
		399	WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
		400	break;
		401	case ATOM_PPLL2:
		402	ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
		403	ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
		404	WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
		405	break;
		406	case ATOM_DCPLL:
		407	case ATOM_PPLL_INVALID:
		408	return;
		409	}
		410	} else if (ASIC_IS_AVIVO(rdev)) {
2997	Serge	411	switch (pll_id) {
1963	serge	412	case ATOM_PPLL1:
		413	ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
		414	ss_cntl &= ~1;
		415	WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
		416	break;
		417	case ATOM_PPLL2:
		418	ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
		419	ss_cntl &= ~1;
		420	WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
		421	break;
		422	case ATOM_DCPLL:
		423	case ATOM_PPLL_INVALID:
		424	return;
		425	}
		426	}
		427	}
		428
		429
1430	serge	430	union atom_enable_ss {
1963	serge	431	ENABLE_LVDS_SS_PARAMETERS lvds_ss;
		432	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
1430	serge	433	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
1963	serge	434	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
		435	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
1430	serge	436	};
		437
2997	Serge	438	static void atombios_crtc_program_ss(struct radeon_device *rdev,
1963	serge	439	int enable,
		440	int pll_id,
2997	Serge	441	int crtc_id,
1963	serge	442	struct radeon_atom_ss *ss)
1268	serge	443	{
2997	Serge	444	unsigned i;
1268	serge	445	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
1430	serge	446	union atom_enable_ss args;
1268	serge	447
5078	serge	448	if (enable) {
		449	/* Don't mess with SS if percentage is 0 or external ss.
		450	* SS is already disabled previously, and disabling it
		451	* again can cause display problems if the pll is already
		452	* programmed.
		453	*/
		454	if (ss->percentage == 0)
		455	return;
		456	if (ss->type & ATOM_EXTERNAL_SS_MASK)
		457	return;
		458	} else {
2997	Serge	459	for (i = 0; i < rdev->num_crtc; i++) {
		460	if (rdev->mode_info.crtcs[i] &&
		461	rdev->mode_info.crtcs[i]->enabled &&
		462	i != crtc_id &&
		463	pll_id == rdev->mode_info.crtcs[i]->pll_id) {
		464	/* one other crtc is using this pll don't turn
		465	* off spread spectrum as it might turn off
		466	* display on active crtc
		467	*/
		468	return;
		469	}
		470	}
		471	}
		472
1963	serge	473	memset(&args, 0, sizeof(args));
1430	serge	474
1963	serge	475	if (ASIC_IS_DCE5(rdev)) {
		476	args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
		477	args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		478	switch (pll_id) {
		479	case ATOM_PPLL1:
		480	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P1PLL;
		481	break;
		482	case ATOM_PPLL2:
		483	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P2PLL;
		484	break;
		485	case ATOM_DCPLL:
		486	args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_DCPLL;
		487	break;
		488	case ATOM_PPLL_INVALID:
		489	return;
		490	}
2997	Serge	491	args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		492	args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
1963	serge	493	args.v3.ucEnable = enable;
		494	} else if (ASIC_IS_DCE4(rdev)) {
		495	args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		496	args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		497	switch (pll_id) {
		498	case ATOM_PPLL1:
		499	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P1PLL;
		500	break;
		501	case ATOM_PPLL2:
		502	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P2PLL;
		503	break;
		504	case ATOM_DCPLL:
		505	args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_DCPLL;
		506	break;
		507	case ATOM_PPLL_INVALID:
3031	serge	508	return;
1963	serge	509	}
2997	Serge	510	args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		511	args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
1963	serge	512	args.v2.ucEnable = enable;
		513	} else if (ASIC_IS_DCE3(rdev)) {
		514	args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		515	args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		516	args.v1.ucSpreadSpectrumStep = ss->step;
		517	args.v1.ucSpreadSpectrumDelay = ss->delay;
		518	args.v1.ucSpreadSpectrumRange = ss->range;
		519	args.v1.ucPpll = pll_id;
		520	args.v1.ucEnable = enable;
		521	} else if (ASIC_IS_AVIVO(rdev)) {
		522	if ((enable == ATOM_DISABLE) \|\| (ss->percentage == 0) \|\|
		523	(ss->type & ATOM_EXTERNAL_SS_MASK)) {
2997	Serge	524	atombios_disable_ss(rdev, pll_id);
3031	serge	525	return;
1268	serge	526	}
1963	serge	527	args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		528	args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		529	args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
		530	args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
		531	args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
		532	args.lvds_ss_2.ucEnable = enable;
1268	serge	533	} else {
5078	serge	534	if (enable == ATOM_DISABLE) {
2997	Serge	535	atombios_disable_ss(rdev, pll_id);
1963	serge	536	return;
3031	serge	537	}
1963	serge	538	args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
		539	args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
		540	args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
		541	args.lvds_ss.ucSpreadSpectrumStepSize_Delay \|= (ss->delay & 7) << 4;
		542	args.lvds_ss.ucEnable = enable;
		543	}
1430	serge	544	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1268	serge	545	}
		546
1404	serge	547	union adjust_pixel_clock {
		548	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
1430	serge	549	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
1404	serge	550	};
		551
		552	static u32 atombios_adjust_pll(struct drm_crtc *crtc,
2997	Serge	553	struct drm_display_mode *mode)
1123	serge	554	{
2997	Serge	555	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1123	serge	556	struct drm_device *dev = crtc->dev;
		557	struct radeon_device *rdev = dev->dev_private;
2997	Serge	558	struct drm_encoder *encoder = radeon_crtc->encoder;
		559	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		560	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1404	serge	561	u32 adjusted_clock = mode->clock;
2997	Serge	562	int encoder_mode = atombios_get_encoder_mode(encoder);
1963	serge	563	u32 dp_clock = mode->clock;
5078	serge	564	u32 clock = mode->clock;
		565	int bpc = radeon_crtc->bpc;
2997	Serge	566	bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
1123	serge	567
1404	serge	568	/* reset the pll flags */
2997	Serge	569	radeon_crtc->pll_flags = 0;
1123	serge	570
		571	if (ASIC_IS_AVIVO(rdev)) {
1179	serge	572	if ((rdev->family == CHIP_RS600) \|\|
		573	(rdev->family == CHIP_RS690) \|\|
		574	(rdev->family == CHIP_RS740))
2997	Serge	575	radeon_crtc->pll_flags \|= (/RADEON_PLL_USE_FRAC_FB_DIV \|/
3031	serge	576	RADEON_PLL_PREFER_CLOSEST_LOWER);
1179	serge	577
1123	serge	578	if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
2997	Serge	579	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_HIGH_FB_DIV;
1123	serge	580	else
2997	Serge	581	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_LOW_REF_DIV;
1963	serge	582
		583	if (rdev->family < CHIP_RV770)
2997	Serge	584	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_MINM_OVER_MAXP;
		585	/* use frac fb div on APUs */
5078	serge	586	if (ASIC_IS_DCE41(rdev) \|\| ASIC_IS_DCE61(rdev) \|\| ASIC_IS_DCE8(rdev))
2997	Serge	587	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
3764	Serge	588	/* use frac fb div on RS780/RS880 */
		589	if ((rdev->family == CHIP_RS780) \|\| (rdev->family == CHIP_RS880))
		590	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
3192	Serge	591	if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
		592	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
1123	serge	593	} else {
2997	Serge	594	radeon_crtc->pll_flags \|= RADEON_PLL_LEGACY;
1123	serge	595
		596	if (mode->clock > 200000) /* range limits??? */
2997	Serge	597	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_HIGH_FB_DIV;
1123	serge	598	else
2997	Serge	599	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_LOW_REF_DIV;
1123	serge	600	}
		601
3031	serge	602	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT \| ATOM_DEVICE_DFP_SUPPORT)) \|\|
		603	(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
		604	if (connector) {
		605	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		606	struct radeon_connector_atom_dig *dig_connector =
		607	radeon_connector->con_priv;
1963	serge	608
3031	serge	609	dp_clock = dig_connector->dp_clock;
		610	}
		611	}
1963	serge	612
6104	serge	613	if (radeon_encoder->is_mst_encoder) {
		614	struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
		615	struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
		616
		617	dp_clock = dig_connector->dp_clock;
		618	}
		619
3031	serge	620	/* use recommended ref_div for ss */
		621	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2997	Serge	622	if (radeon_crtc->ss_enabled) {
		623	if (radeon_crtc->ss.refdiv) {
		624	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
		625	radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
3031	serge	626	if (ASIC_IS_AVIVO(rdev))
2997	Serge	627	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
1963	serge	628	}
3031	serge	629	}
		630	}
1963	serge	631
3031	serge	632	if (ASIC_IS_AVIVO(rdev)) {
		633	/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
		634	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
		635	adjusted_clock = mode->clock * 2;
		636	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
2997	Serge	637	radeon_crtc->pll_flags \|= RADEON_PLL_PREFER_CLOSEST_LOWER;
3031	serge	638	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2997	Serge	639	radeon_crtc->pll_flags \|= RADEON_PLL_IS_LCD;
3031	serge	640	} else {
		641	if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
2997	Serge	642	radeon_crtc->pll_flags \|= RADEON_PLL_NO_ODD_POST_DIV;
3031	serge	643	if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
2997	Serge	644	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
1123	serge	645	}
		646
5078	serge	647	/* adjust pll for deep color modes */
		648	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
		649	switch (bpc) {
		650	case 8:
		651	default:
		652	break;
		653	case 10:
		654	clock = (clock * 5) / 4;
		655	break;
		656	case 12:
		657	clock = (clock * 3) / 2;
		658	break;
		659	case 16:
		660	clock = clock * 2;
		661	break;
		662	}
		663	}
		664
1268	serge	665	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
		666	* accordingly based on the encoder/transmitter to work around
		667	* special hw requirements.
		668	*/
		669	if (ASIC_IS_DCE3(rdev)) {
1404	serge	670	union adjust_pixel_clock args;
		671	u8 frev, crev;
		672	int index;
1268	serge	673
1404	serge	674	index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
1963	serge	675	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		676	&crev))
		677	return adjusted_clock;
1268	serge	678
1404	serge	679	memset(&args, 0, sizeof(args));
		680
		681	switch (frev) {
		682	case 1:
		683	switch (crev) {
		684	case 1:
		685	case 2:
5078	serge	686	args.v1.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	687	args.v1.ucTransmitterID = radeon_encoder->encoder_id;
1430	serge	688	args.v1.ucEncodeMode = encoder_mode;
2997	Serge	689	if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
3031	serge	690	args.v1.ucConfig \|=
		691	ADJUST_DISPLAY_CONFIG_SS_ENABLE;
1404	serge	692
3031	serge	693	atom_execute_table(rdev->mode_info.atom_context,
1404	serge	694	index, (uint32_t *)&args);
		695	adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
		696	break;
1430	serge	697	case 3:
5078	serge	698	args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
1430	serge	699	args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
		700	args.v3.sInput.ucEncodeMode = encoder_mode;
		701	args.v3.sInput.ucDispPllConfig = 0;
2997	Serge	702	if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
1963	serge	703	args.v3.sInput.ucDispPllConfig \|=
		704	DISPPLL_CONFIG_SS_ENABLE;
2997	Serge	705	if (ENCODER_MODE_IS_DP(encoder_mode)) {
3031	serge	706	args.v3.sInput.ucDispPllConfig \|=
		707	DISPPLL_CONFIG_COHERENT_MODE;
		708	/* 16200 or 27000 */
		709	args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
2997	Serge	710	} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		711	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3031	serge	712	if (dig->coherent_mode)
		713	args.v3.sInput.ucDispPllConfig \|=
		714	DISPPLL_CONFIG_COHERENT_MODE;
2997	Serge	715	if (is_duallink)
3031	serge	716	args.v3.sInput.ucDispPllConfig \|=
		717	DISPPLL_CONFIG_DUAL_LINK;
		718	}
2997	Serge	719	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
		720	ENCODER_OBJECT_ID_NONE)
		721	args.v3.sInput.ucExtTransmitterID =
		722	radeon_encoder_get_dp_bridge_encoder_id(encoder);
		723	else
1986	serge	724	args.v3.sInput.ucExtTransmitterID = 0;
		725
1430	serge	726	atom_execute_table(rdev->mode_info.atom_context,
		727	index, (uint32_t *)&args);
		728	adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
		729	if (args.v3.sOutput.ucRefDiv) {
2997	Serge	730	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
		731	radeon_crtc->pll_flags \|= RADEON_PLL_USE_REF_DIV;
		732	radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
1430	serge	733	}
		734	if (args.v3.sOutput.ucPostDiv) {
2997	Serge	735	radeon_crtc->pll_flags \|= RADEON_PLL_USE_FRAC_FB_DIV;
		736	radeon_crtc->pll_flags \|= RADEON_PLL_USE_POST_DIV;
		737	radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
1430	serge	738	}
		739	break;
1404	serge	740	default:
		741	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		742	return adjusted_clock;
		743	}
		744	break;
		745	default:
		746	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		747	return adjusted_clock;
		748	}
1268	serge	749	}
1404	serge	750	return adjusted_clock;
		751	}
1268	serge	752
1404	serge	753	union set_pixel_clock {
		754	SET_PIXEL_CLOCK_PS_ALLOCATION base;
		755	PIXEL_CLOCK_PARAMETERS v1;
		756	PIXEL_CLOCK_PARAMETERS_V2 v2;
		757	PIXEL_CLOCK_PARAMETERS_V3 v3;
1430	serge	758	PIXEL_CLOCK_PARAMETERS_V5 v5;
1963	serge	759	PIXEL_CLOCK_PARAMETERS_V6 v6;
1404	serge	760	};
		761
1963	serge	762	/* on DCE5, make sure the voltage is high enough to support the
		763	* required disp clk.
		764	*/
2997	Serge	765	static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
1963	serge	766	u32 dispclk)
1404	serge	767	{
1430	serge	768	u8 frev, crev;
		769	int index;
		770	union set_pixel_clock args;
		771
		772	memset(&args, 0, sizeof(args));
		773
		774	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
1963	serge	775	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		776	&crev))
		777	return;
1430	serge	778
		779	switch (frev) {
		780	case 1:
		781	switch (crev) {
		782	case 5:
		783	/* if the default dcpll clock is specified,
		784	* SetPixelClock provides the dividers
		785	*/
		786	args.v5.ucCRTC = ATOM_CRTC_INVALID;
1963	serge	787	args.v5.usPixelClock = cpu_to_le16(dispclk);
1430	serge	788	args.v5.ucPpll = ATOM_DCPLL;
		789	break;
1963	serge	790	case 6:
		791	/* if the default dcpll clock is specified,
		792	* SetPixelClock provides the dividers
		793	*/
		794	args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
5078	serge	795	if (ASIC_IS_DCE61(rdev) \|\| ASIC_IS_DCE8(rdev))
2997	Serge	796	args.v6.ucPpll = ATOM_EXT_PLL1;
		797	else if (ASIC_IS_DCE6(rdev))
		798	args.v6.ucPpll = ATOM_PPLL0;
		799	else
3031	serge	800	args.v6.ucPpll = ATOM_DCPLL;
1963	serge	801	break;
1430	serge	802	default:
		803	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		804	return;
		805	}
		806	break;
		807	default:
		808	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		809	return;
		810	}
		811	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		812	}
		813
1963	serge	814	static void atombios_crtc_program_pll(struct drm_crtc *crtc,
2160	serge	815	u32 crtc_id,
1963	serge	816	int pll_id,
		817	u32 encoder_mode,
		818	u32 encoder_id,
		819	u32 clock,
		820	u32 ref_div,
		821	u32 fb_div,
		822	u32 frac_fb_div,
		823	u32 post_div,
		824	int bpc,
		825	bool ss_enabled,
		826	struct radeon_atom_ss *ss)
1430	serge	827	{
1404	serge	828	struct drm_device *dev = crtc->dev;
		829	struct radeon_device *rdev = dev->dev_private;
		830	u8 frev, crev;
1963	serge	831	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
1404	serge	832	union set_pixel_clock args;
		833
		834	memset(&args, 0, sizeof(args));
		835
1963	serge	836	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
		837	&crev))
1404	serge	838	return;
		839
1123	serge	840	switch (frev) {
		841	case 1:
		842	switch (crev) {
		843	case 1:
1963	serge	844	if (clock == ATOM_DISABLE)
		845	return;
		846	args.v1.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	847	args.v1.usRefDiv = cpu_to_le16(ref_div);
		848	args.v1.usFbDiv = cpu_to_le16(fb_div);
		849	args.v1.ucFracFbDiv = frac_fb_div;
		850	args.v1.ucPostDiv = post_div;
1963	serge	851	args.v1.ucPpll = pll_id;
		852	args.v1.ucCRTC = crtc_id;
1404	serge	853	args.v1.ucRefDivSrc = 1;
1123	serge	854	break;
		855	case 2:
1963	serge	856	args.v2.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	857	args.v2.usRefDiv = cpu_to_le16(ref_div);
		858	args.v2.usFbDiv = cpu_to_le16(fb_div);
		859	args.v2.ucFracFbDiv = frac_fb_div;
		860	args.v2.ucPostDiv = post_div;
1963	serge	861	args.v2.ucPpll = pll_id;
		862	args.v2.ucCRTC = crtc_id;
1404	serge	863	args.v2.ucRefDivSrc = 1;
1123	serge	864	break;
		865	case 3:
1963	serge	866	args.v3.usPixelClock = cpu_to_le16(clock / 10);
1404	serge	867	args.v3.usRefDiv = cpu_to_le16(ref_div);
		868	args.v3.usFbDiv = cpu_to_le16(fb_div);
		869	args.v3.ucFracFbDiv = frac_fb_div;
		870	args.v3.ucPostDiv = post_div;
1963	serge	871	args.v3.ucPpll = pll_id;
2997	Serge	872	if (crtc_id == ATOM_CRTC2)
		873	args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
		874	else
		875	args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
1963	serge	876	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		877	args.v3.ucMiscInfo \|= PIXEL_CLOCK_MISC_REF_DIV_SRC;
		878	args.v3.ucTransmitterId = encoder_id;
1430	serge	879	args.v3.ucEncoderMode = encoder_mode;
1123	serge	880	break;
1430	serge	881	case 5:
1963	serge	882	args.v5.ucCRTC = crtc_id;
		883	args.v5.usPixelClock = cpu_to_le16(clock / 10);
1430	serge	884	args.v5.ucRefDiv = ref_div;
		885	args.v5.usFbDiv = cpu_to_le16(fb_div);
		886	args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
		887	args.v5.ucPostDiv = post_div;
		888	args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
1963	serge	889	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		890	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
5078	serge	891	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
6104	serge	892	switch (bpc) {
		893	case 8:
		894	default:
		895	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
		896	break;
		897	case 10:
5078	serge	898	/* yes this is correct, the atom define is wrong */
		899	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
		900	break;
		901	case 12:
		902	/* yes this is correct, the atom define is wrong */
6104	serge	903	args.v5.ucMiscInfo \|= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
		904	break;
		905	}
1963	serge	906	}
		907	args.v5.ucTransmitterID = encoder_id;
1430	serge	908	args.v5.ucEncoderMode = encoder_mode;
1963	serge	909	args.v5.ucPpll = pll_id;
1430	serge	910	break;
1963	serge	911	case 6:
2160	serge	912	args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 \| clock / 10);
1963	serge	913	args.v6.ucRefDiv = ref_div;
		914	args.v6.usFbDiv = cpu_to_le16(fb_div);
		915	args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
		916	args.v6.ucPostDiv = post_div;
		917	args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
		918	if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
		919	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
5078	serge	920	if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
6104	serge	921	switch (bpc) {
		922	case 8:
		923	default:
		924	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
		925	break;
		926	case 10:
5078	serge	927	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
6104	serge	928	break;
		929	case 12:
5078	serge	930	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
6104	serge	931	break;
		932	case 16:
		933	args.v6.ucMiscInfo \|= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
		934	break;
		935	}
1963	serge	936	}
		937	args.v6.ucTransmitterID = encoder_id;
		938	args.v6.ucEncoderMode = encoder_mode;
		939	args.v6.ucPpll = pll_id;
		940	break;
1123	serge	941	default:
		942	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		943	return;
		944	}
		945	break;
		946	default:
		947	DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		948	return;
		949	}
		950
		951	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		952	}
		953
2997	Serge	954	static bool atombios_crtc_prepare_pll(struct drm_crtc crtc, struct drm_display_mode mode)
1430	serge	955	{
		956	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		957	struct drm_device *dev = crtc->dev;
		958	struct radeon_device *rdev = dev->dev_private;
2997	Serge	959	struct radeon_encoder *radeon_encoder =
		960	to_radeon_encoder(radeon_crtc->encoder);
		961	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1963	serge	962
2997	Serge	963	radeon_crtc->bpc = 8;
		964	radeon_crtc->ss_enabled = false;
1963	serge	965
6104	serge	966	if (radeon_encoder->is_mst_encoder) {
		967	radeon_dp_mst_prepare_pll(crtc, mode);
		968	} else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT \| ATOM_DEVICE_DFP_SUPPORT)) \|\|
2997	Serge	969	(radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
1963	serge	970	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		971	struct drm_connector *connector =
2997	Serge	972	radeon_get_connector_for_encoder(radeon_crtc->encoder);
1963	serge	973	struct radeon_connector *radeon_connector =
		974	to_radeon_connector(connector);
		975	struct radeon_connector_atom_dig *dig_connector =
		976	radeon_connector->con_priv;
		977	int dp_clock;
5078	serge	978
		979	/* Assign mode clock for hdmi deep color max clock limit check */
		980	radeon_connector->pixelclock_for_modeset = mode->clock;
2997	Serge	981	radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
1963	serge	982
		983	switch (encoder_mode) {
2997	Serge	984	case ATOM_ENCODER_MODE_DP_MST:
1963	serge	985	case ATOM_ENCODER_MODE_DP:
		986	/* DP/eDP */
		987	dp_clock = dig_connector->dp_clock / 10;
3031	serge	988	if (ASIC_IS_DCE4(rdev))
2997	Serge	989	radeon_crtc->ss_enabled =
		990	radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
3031	serge	991	ASIC_INTERNAL_SS_ON_DP,
		992	dp_clock);
		993	else {
		994	if (dp_clock == 16200) {
2997	Serge	995	radeon_crtc->ss_enabled =
		996	radeon_atombios_get_ppll_ss_info(rdev,
		997	&radeon_crtc->ss,
3031	serge	998	ATOM_DP_SS_ID2);
2997	Serge	999	if (!radeon_crtc->ss_enabled)
		1000	radeon_crtc->ss_enabled =
		1001	radeon_atombios_get_ppll_ss_info(rdev,
		1002	&radeon_crtc->ss,
3031	serge	1003	ATOM_DP_SS_ID1);
5078	serge	1004	} else {
2997	Serge	1005	radeon_crtc->ss_enabled =
		1006	radeon_atombios_get_ppll_ss_info(rdev,
		1007	&radeon_crtc->ss,
3031	serge	1008	ATOM_DP_SS_ID1);
6104	serge	1009	}
5078	serge	1010	/* disable spread spectrum on DCE3 DP */
		1011	radeon_crtc->ss_enabled = false;
		1012	}
1963	serge	1013	break;
		1014	case ATOM_ENCODER_MODE_LVDS:
		1015	if (ASIC_IS_DCE4(rdev))
2997	Serge	1016	radeon_crtc->ss_enabled =
		1017	radeon_atombios_get_asic_ss_info(rdev,
		1018	&radeon_crtc->ss,
3031	serge	1019	dig->lcd_ss_id,
		1020	mode->clock / 10);
1963	serge	1021	else
2997	Serge	1022	radeon_crtc->ss_enabled =
		1023	radeon_atombios_get_ppll_ss_info(rdev,
		1024	&radeon_crtc->ss,
3031	serge	1025	dig->lcd_ss_id);
1963	serge	1026	break;
		1027	case ATOM_ENCODER_MODE_DVI:
		1028	if (ASIC_IS_DCE4(rdev))
2997	Serge	1029	radeon_crtc->ss_enabled =
		1030	radeon_atombios_get_asic_ss_info(rdev,
		1031	&radeon_crtc->ss,
1963	serge	1032	ASIC_INTERNAL_SS_ON_TMDS,
		1033	mode->clock / 10);
		1034	break;
		1035	case ATOM_ENCODER_MODE_HDMI:
		1036	if (ASIC_IS_DCE4(rdev))
2997	Serge	1037	radeon_crtc->ss_enabled =
		1038	radeon_atombios_get_asic_ss_info(rdev,
		1039	&radeon_crtc->ss,
1963	serge	1040	ASIC_INTERNAL_SS_ON_HDMI,
		1041	mode->clock / 10);
		1042	break;
		1043	default:
		1044	break;
		1045	}
		1046	}
		1047
		1048	/* adjust pixel clock as needed */
2997	Serge	1049	radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1963	serge	1050
2997	Serge	1051	return true;
		1052	}
		1053
		1054	static void atombios_crtc_set_pll(struct drm_crtc crtc, struct drm_display_mode mode)
		1055	{
		1056	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1057	struct drm_device *dev = crtc->dev;
		1058	struct radeon_device *rdev = dev->dev_private;
		1059	struct radeon_encoder *radeon_encoder =
		1060	to_radeon_encoder(radeon_crtc->encoder);
		1061	u32 pll_clock = mode->clock;
5078	serge	1062	u32 clock = mode->clock;
2997	Serge	1063	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
		1064	struct radeon_pll *pll;
		1065	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
		1066
5078	serge	1067	/* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
		1068	if (ASIC_IS_DCE5(rdev) &&
		1069	(encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
		1070	(radeon_crtc->bpc > 8))
		1071	clock = radeon_crtc->adjusted_clock;
		1072
2997	Serge	1073	switch (radeon_crtc->pll_id) {
		1074	case ATOM_PPLL1:
		1075	pll = &rdev->clock.p1pll;
		1076	break;
		1077	case ATOM_PPLL2:
		1078	pll = &rdev->clock.p2pll;
		1079	break;
		1080	case ATOM_DCPLL:
		1081	case ATOM_PPLL_INVALID:
		1082	default:
		1083	pll = &rdev->clock.dcpll;
		1084	break;
		1085	}
		1086
		1087	/* update pll params */
		1088	pll->flags = radeon_crtc->pll_flags;
		1089	pll->reference_div = radeon_crtc->pll_reference_div;
		1090	pll->post_div = radeon_crtc->pll_post_div;
		1091
1963	serge	1092	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		1093	/* TV seems to prefer the legacy algo on some boards */
2997	Serge	1094	radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1095	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1096	else if (ASIC_IS_AVIVO(rdev))
2997	Serge	1097	radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1098	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1099	else
2997	Serge	1100	radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
		1101	&fb_div, &frac_fb_div, &ref_div, &post_div);
1963	serge	1102
2997	Serge	1103	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
		1104	radeon_crtc->crtc_id, &radeon_crtc->ss);
1963	serge	1105
		1106	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
5078	serge	1107	encoder_mode, radeon_encoder->encoder_id, clock,
2997	Serge	1108	ref_div, fb_div, frac_fb_div, post_div,
		1109	radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1963	serge	1110
2997	Serge	1111	if (radeon_crtc->ss_enabled) {
1963	serge	1112	/* calculate ss amount and step size */
		1113	if (ASIC_IS_DCE4(rdev)) {
		1114	u32 step_size;
5078	serge	1115	u32 amount = (((fb_div * 10) + frac_fb_div) *
		1116	(u32)radeon_crtc->ss.percentage) /
		1117	(100 * (u32)radeon_crtc->ss.percentage_divider);
2997	Serge	1118	radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
		1119	radeon_crtc->ss.amount \|= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1963	serge	1120	ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
2997	Serge	1121	if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
5078	serge	1122	step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1963	serge	1123	(125 * 25 * pll->reference_freq / 100);
		1124	else
5078	serge	1125	step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1963	serge	1126	(125 * 25 * pll->reference_freq / 100);
2997	Serge	1127	radeon_crtc->ss.step = step_size;
1963	serge	1128	}
		1129
6104	serge	1130	atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
		1131	radeon_crtc->crtc_id, &radeon_crtc->ss);
1963	serge	1132	}
		1133	}
		1134
		1135	static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
3031	serge	1136	struct drm_framebuffer *fb,
		1137	int x, int y, int atomic)
1963	serge	1138	{
		1139	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1140	struct drm_device *dev = crtc->dev;
		1141	struct radeon_device *rdev = dev->dev_private;
1430	serge	1142	struct radeon_framebuffer *radeon_fb;
1963	serge	1143	struct drm_framebuffer *target_fb;
1430	serge	1144	struct drm_gem_object *obj;
		1145	struct radeon_bo *rbo;
		1146	uint64_t fb_location;
		1147	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
2997	Serge	1148	unsigned bankw, bankh, mtaspect, tile_split;
1963	serge	1149	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
		1150	u32 tmp, viewport_w, viewport_h;
1430	serge	1151	int r;
5078	serge	1152	bool bypass_lut = false;
1430	serge	1153
		1154	/* no fb bound */
5078	serge	1155	if (!atomic && !crtc->primary->fb) {
1963	serge	1156	DRM_DEBUG_KMS("No FB bound\n");
1430	serge	1157	return 0;
		1158	}
		1159
1963	serge	1160	if (atomic) {
		1161	radeon_fb = to_radeon_framebuffer(fb);
		1162	target_fb = fb;
		1163	}
		1164	else {
5078	serge	1165	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		1166	target_fb = crtc->primary->fb;
1963	serge	1167	}
1430	serge	1168
1963	serge	1169	/* If atomic, assume fb object is pinned & idle & fenced and
		1170	* just update base pointers
		1171	*/
1430	serge	1172	obj = radeon_fb->obj;
1963	serge	1173	rbo = gem_to_radeon_bo(obj);
6104	serge	1174	r = radeon_bo_reserve(rbo, false);
		1175	if (unlikely(r != 0))
		1176	return r;
1963	serge	1177
		1178	if (atomic)
		1179	fb_location = radeon_bo_gpu_offset(rbo);
		1180	else {
3031	serge	1181	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		1182	if (unlikely(r != 0)) {
		1183	radeon_bo_unreserve(rbo);
		1184	return -EINVAL;
		1185	}
1430	serge	1186	}
1963	serge	1187
1430	serge	1188	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
6104	serge	1189	radeon_bo_unreserve(rbo);
1430	serge	1190
5078	serge	1191	switch (target_fb->pixel_format) {
		1192	case DRM_FORMAT_C8:
1430	serge	1193	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) \|
		1194	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
		1195	break;
5078	serge	1196	case DRM_FORMAT_XRGB4444:
		1197	case DRM_FORMAT_ARGB4444:
1430	serge	1198	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
5078	serge	1199	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
		1200	#ifdef __BIG_ENDIAN
		1201	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1202	#endif
		1203	break;
		1204	case DRM_FORMAT_XRGB1555:
		1205	case DRM_FORMAT_ARGB1555:
		1206	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
1430	serge	1207	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
5078	serge	1208	#ifdef __BIG_ENDIAN
		1209	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1210	#endif
1430	serge	1211	break;
5078	serge	1212	case DRM_FORMAT_BGRX5551:
		1213	case DRM_FORMAT_BGRA5551:
1430	serge	1214	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
5078	serge	1215	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
		1216	#ifdef __BIG_ENDIAN
		1217	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1218	#endif
		1219	break;
		1220	case DRM_FORMAT_RGB565:
		1221	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) \|
1430	serge	1222	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1963	serge	1223	#ifdef __BIG_ENDIAN
		1224	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
		1225	#endif
1430	serge	1226	break;
5078	serge	1227	case DRM_FORMAT_XRGB8888:
		1228	case DRM_FORMAT_ARGB8888:
1430	serge	1229	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1230	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1963	serge	1231	#ifdef __BIG_ENDIAN
		1232	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1233	#endif
1430	serge	1234	break;
5078	serge	1235	case DRM_FORMAT_XRGB2101010:
		1236	case DRM_FORMAT_ARGB2101010:
		1237	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1238	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
		1239	#ifdef __BIG_ENDIAN
		1240	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1241	#endif
		1242	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1243	bypass_lut = true;
		1244	break;
		1245	case DRM_FORMAT_BGRX1010102:
		1246	case DRM_FORMAT_BGRA1010102:
		1247	fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) \|
		1248	EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
		1249	#ifdef __BIG_ENDIAN
		1250	fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
		1251	#endif
		1252	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1253	bypass_lut = true;
		1254	break;
1430	serge	1255	default:
5078	serge	1256	DRM_ERROR("Unsupported screen format %s\n",
		1257	drm_get_format_name(target_fb->pixel_format));
1430	serge	1258	return -EINVAL;
		1259	}
		1260
2997	Serge	1261	if (tiling_flags & RADEON_TILING_MACRO) {
5078	serge	1262	evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
		1263
		1264	/* Set NUM_BANKS. */
		1265	if (rdev->family >= CHIP_TAHITI) {
		1266	unsigned index, num_banks;
		1267
6104	serge	1268	if (rdev->family >= CHIP_BONAIRE) {
5078	serge	1269	unsigned tileb, tile_split_bytes;
		1270
6104	serge	1271	/* Calculate the macrotile mode index. */
		1272	tile_split_bytes = 64 << tile_split;
		1273	tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
		1274	tileb = min(tile_split_bytes, tileb);
5078	serge	1275
		1276	for (index = 0; tileb > 64; index++)
6104	serge	1277	tileb >>= 1;
5078	serge	1278
6104	serge	1279	if (index >= 16) {
		1280	DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
		1281	target_fb->bits_per_pixel, tile_split);
		1282	return -EINVAL;
		1283	}
5078	serge	1284
6104	serge	1285	num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
5078	serge	1286	} else {
		1287	switch (target_fb->bits_per_pixel) {
		1288	case 8:
		1289	index = 10;
		1290	break;
		1291	case 16:
		1292	index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
		1293	break;
		1294	default:
		1295	case 32:
		1296	index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
		1297	break;
		1298	}
		1299
		1300	num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
		1301	}
		1302
		1303	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(num_banks);
		1304	} else {
		1305	/* NI and older. */
		1306	if (rdev->family >= CHIP_CAYMAN)
6104	serge	1307	tmp = rdev->config.cayman.tile_config;
		1308	else
		1309	tmp = rdev->config.evergreen.tile_config;
2997	Serge	1310
6104	serge	1311	switch ((tmp & 0xf0) >> 4) {
		1312	case 0: /* 4 banks */
		1313	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
		1314	break;
		1315	case 1: /* 8 banks */
		1316	default:
		1317	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
		1318	break;
		1319	case 2: /* 16 banks */
		1320	fb_format \|= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
		1321	break;
		1322	}
2997	Serge	1323	}
		1324
1963	serge	1325	fb_format \|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
2997	Serge	1326	fb_format \|= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
		1327	fb_format \|= EVERGREEN_GRPH_BANK_WIDTH(bankw);
		1328	fb_format \|= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
		1329	fb_format \|= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
5078	serge	1330	if (rdev->family >= CHIP_BONAIRE) {
		1331	/* XXX need to know more about the surface tiling mode */
		1332	fb_format \|= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
		1333	}
2997	Serge	1334	} else if (tiling_flags & RADEON_TILING_MICRO)
1963	serge	1335	fb_format \|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
		1336
5078	serge	1337	if (rdev->family >= CHIP_BONAIRE) {
		1338	/* Read the pipe config from the 2D TILED SCANOUT mode.
		1339	* It should be the same for the other modes too, but not all
		1340	* modes set the pipe config field. */
		1341	u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
		1342
		1343	fb_format \|= CIK_GRPH_PIPE_CONFIG(pipe_config);
		1344	} else if ((rdev->family == CHIP_TAHITI) \|\|
6104	serge	1345	(rdev->family == CHIP_PITCAIRN))
2997	Serge	1346	fb_format \|= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
5078	serge	1347	else if ((rdev->family == CHIP_VERDE) \|\|
		1348	(rdev->family == CHIP_OLAND) \|\|
		1349	(rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
2997	Serge	1350	fb_format \|= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
		1351
1430	serge	1352	switch (radeon_crtc->crtc_id) {
		1353	case 0:
		1354	WREG32(AVIVO_D1VGA_CONTROL, 0);
		1355	break;
		1356	case 1:
		1357	WREG32(AVIVO_D2VGA_CONTROL, 0);
		1358	break;
		1359	case 2:
		1360	WREG32(EVERGREEN_D3VGA_CONTROL, 0);
		1361	break;
		1362	case 3:
		1363	WREG32(EVERGREEN_D4VGA_CONTROL, 0);
		1364	break;
		1365	case 4:
		1366	WREG32(EVERGREEN_D5VGA_CONTROL, 0);
		1367	break;
		1368	case 5:
		1369	WREG32(EVERGREEN_D6VGA_CONTROL, 0);
		1370	break;
		1371	default:
		1372	break;
		1373	}
		1374
		1375	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
		1376	upper_32_bits(fb_location));
		1377	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
		1378	upper_32_bits(fb_location));
		1379	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1380	(u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
		1381	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1382	(u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
		1383	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1963	serge	1384	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1430	serge	1385
5078	serge	1386	/*
		1387	* The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
		1388	* for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
		1389	* retain the full precision throughout the pipeline.
		1390	*/
		1391	WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
		1392	(bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
		1393	~EVERGREEN_LUT_10BIT_BYPASS_EN);
		1394
		1395	if (bypass_lut)
		1396	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
		1397
1430	serge	1398	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
		1399	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
		1400	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
		1401	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1963	serge	1402	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
		1403	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1430	serge	1404
2997	Serge	1405	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1430	serge	1406	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
		1407	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
		1408
5078	serge	1409	if (rdev->family >= CHIP_BONAIRE)
		1410	WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		1411	target_fb->height);
		1412	else
6104	serge	1413	WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		1414	target_fb->height);
1430	serge	1415	x &= ~3;
		1416	y &= ~1;
		1417	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
		1418	(x << 16) \| y);
1963	serge	1419	viewport_w = crtc->mode.hdisplay;
		1420	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
6104	serge	1421	if ((rdev->family >= CHIP_BONAIRE) &&
		1422	(crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
		1423	viewport_h *= 2;
1430	serge	1424	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1963	serge	1425	(viewport_w << 16) \| viewport_h);
1430	serge	1426
1963	serge	1427	/* pageflip setup */
		1428	/* make sure flip is at vb rather than hb */
		1429	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
		1430	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
		1431	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1430	serge	1432
5078	serge	1433	/* set pageflip to happen only at start of vblank interval (front porch) */
		1434	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1963	serge	1435
5078	serge	1436	if (!atomic && fb && fb != crtc->primary->fb) {
1963	serge	1437	radeon_fb = to_radeon_framebuffer(fb);
		1438	rbo = gem_to_radeon_bo(radeon_fb->obj);
1430	serge	1439	r = radeon_bo_reserve(rbo, false);
		1440	if (unlikely(r != 0))
		1441	return r;
		1442	radeon_bo_unpin(rbo);
		1443	radeon_bo_unreserve(rbo);
		1444	}
		1445
		1446	/* Bytes per pixel may have changed */
		1447	radeon_bandwidth_update(rdev);
		1448
		1449	return 0;
		1450	}
		1451
1963	serge	1452	static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
		1453	struct drm_framebuffer *fb,
		1454	int x, int y, int atomic)
1123	serge	1455	{
		1456	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1457	struct drm_device *dev = crtc->dev;
		1458	struct radeon_device *rdev = dev->dev_private;
		1459	struct radeon_framebuffer *radeon_fb;
		1460	struct drm_gem_object *obj;
1321	serge	1461	struct radeon_bo *rbo;
1963	serge	1462	struct drm_framebuffer *target_fb;
1123	serge	1463	uint64_t fb_location;
1179	serge	1464	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1963	serge	1465	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
		1466	u32 tmp, viewport_w, viewport_h;
1321	serge	1467	int r;
5078	serge	1468	bool bypass_lut = false;
1123	serge	1469
1321	serge	1470	/* no fb bound */
5078	serge	1471	if (!atomic && !crtc->primary->fb) {
1963	serge	1472	DRM_DEBUG_KMS("No FB bound\n");
1321	serge	1473	return 0;
		1474	}
1123	serge	1475
1963	serge	1476	if (atomic) {
		1477	radeon_fb = to_radeon_framebuffer(fb);
		1478	target_fb = fb;
		1479	}
		1480	else {
5078	serge	1481	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		1482	target_fb = crtc->primary->fb;
1963	serge	1483	}
1123	serge	1484
		1485	obj = radeon_fb->obj;
1963	serge	1486	rbo = gem_to_radeon_bo(obj);
1404	serge	1487	r = radeon_bo_reserve(rbo, false);
		1488	if (unlikely(r != 0))
		1489	return r;
1963	serge	1490
		1491	/* If atomic, assume fb object is pinned & idle & fenced and
		1492	* just update base pointers
		1493	*/
		1494	if (atomic)
		1495	fb_location = radeon_bo_gpu_offset(rbo);
		1496	else {
3031	serge	1497	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		1498	if (unlikely(r != 0)) {
		1499	radeon_bo_unreserve(rbo);
		1500	return -EINVAL;
		1501	}
1404	serge	1502	}
		1503	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
		1504	radeon_bo_unreserve(rbo);
1123	serge	1505
5078	serge	1506	switch (target_fb->pixel_format) {
		1507	case DRM_FORMAT_C8:
1179	serge	1508	fb_format =
		1509	AVIVO_D1GRPH_CONTROL_DEPTH_8BPP \|
		1510	AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
		1511	break;
5078	serge	1512	case DRM_FORMAT_XRGB4444:
		1513	case DRM_FORMAT_ARGB4444:
1123	serge	1514	fb_format =
		1515	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
5078	serge	1516	AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
		1517	#ifdef __BIG_ENDIAN
		1518	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1519	#endif
		1520	break;
		1521	case DRM_FORMAT_XRGB1555:
		1522	fb_format =
		1523	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
1123	serge	1524	AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
5078	serge	1525	#ifdef __BIG_ENDIAN
		1526	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1527	#endif
1123	serge	1528	break;
5078	serge	1529	case DRM_FORMAT_RGB565:
1123	serge	1530	fb_format =
		1531	AVIVO_D1GRPH_CONTROL_DEPTH_16BPP \|
		1532	AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1963	serge	1533	#ifdef __BIG_ENDIAN
		1534	fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
		1535	#endif
1123	serge	1536	break;
5078	serge	1537	case DRM_FORMAT_XRGB8888:
		1538	case DRM_FORMAT_ARGB8888:
1123	serge	1539	fb_format =
		1540	AVIVO_D1GRPH_CONTROL_DEPTH_32BPP \|
		1541	AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1963	serge	1542	#ifdef __BIG_ENDIAN
		1543	fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
		1544	#endif
1123	serge	1545	break;
5078	serge	1546	case DRM_FORMAT_XRGB2101010:
		1547	case DRM_FORMAT_ARGB2101010:
		1548	fb_format =
		1549	AVIVO_D1GRPH_CONTROL_DEPTH_32BPP \|
		1550	AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
		1551	#ifdef __BIG_ENDIAN
		1552	fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
		1553	#endif
		1554	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
		1555	bypass_lut = true;
		1556	break;
1123	serge	1557	default:
5078	serge	1558	DRM_ERROR("Unsupported screen format %s\n",
		1559	drm_get_format_name(target_fb->pixel_format));
1123	serge	1560	return -EINVAL;
		1561	}
		1562
1963	serge	1563	if (rdev->family >= CHIP_R600) {
		1564	if (tiling_flags & RADEON_TILING_MACRO)
		1565	fb_format \|= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
		1566	else if (tiling_flags & RADEON_TILING_MICRO)
		1567	fb_format \|= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
		1568	} else {
3031	serge	1569	if (tiling_flags & RADEON_TILING_MACRO)
		1570	fb_format \|= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1179	serge	1571
3031	serge	1572	if (tiling_flags & RADEON_TILING_MICRO)
		1573	fb_format \|= AVIVO_D1GRPH_TILED;
1963	serge	1574	}
1179	serge	1575
1123	serge	1576	if (radeon_crtc->crtc_id == 0)
		1577	WREG32(AVIVO_D1VGA_CONTROL, 0);
		1578	else
		1579	WREG32(AVIVO_D2VGA_CONTROL, 0);
1268	serge	1580
		1581	if (rdev->family >= CHIP_RV770) {
		1582	if (radeon_crtc->crtc_id) {
1963	serge	1583	WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
		1584	WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1268	serge	1585	} else {
1963	serge	1586	WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
		1587	WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1268	serge	1588	}
		1589	}
1123	serge	1590	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
		1591	(u32) fb_location);
		1592	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
		1593	radeon_crtc->crtc_offset, (u32) fb_location);
		1594	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1963	serge	1595	if (rdev->family >= CHIP_R600)
		1596	WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1123	serge	1597
5078	serge	1598	/* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
		1599	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
		1600	(bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
		1601
		1602	if (bypass_lut)
		1603	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
		1604
1123	serge	1605	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
		1606	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
		1607	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
		1608	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1963	serge	1609	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
		1610	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1123	serge	1611
2997	Serge	1612	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1123	serge	1613	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
		1614	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
		1615
		1616	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
2997	Serge	1617	target_fb->height);
1123	serge	1618	x &= ~3;
		1619	y &= ~1;
		1620	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
		1621	(x << 16) \| y);
1963	serge	1622	viewport_w = crtc->mode.hdisplay;
		1623	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1123	serge	1624	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1963	serge	1625	(viewport_w << 16) \| viewport_h);
1123	serge	1626
1963	serge	1627	/* pageflip setup */
		1628	/* make sure flip is at vb rather than hb */
		1629	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
		1630	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
		1631	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1123	serge	1632
5078	serge	1633	/* set pageflip to happen only at start of vblank interval (front porch) */
		1634	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1963	serge	1635
5078	serge	1636	if (!atomic && fb && fb != crtc->primary->fb) {
1963	serge	1637	radeon_fb = to_radeon_framebuffer(fb);
		1638	rbo = gem_to_radeon_bo(radeon_fb->obj);
1404	serge	1639	r = radeon_bo_reserve(rbo, false);
		1640	if (unlikely(r != 0))
		1641	return r;
		1642	radeon_bo_unpin(rbo);
		1643	radeon_bo_unreserve(rbo);
		1644	}
1246	serge	1645
1268	serge	1646	/* Bytes per pixel may have changed */
		1647	radeon_bandwidth_update(rdev);
		1648
1123	serge	1649	return 0;
		1650	}
		1651
1404	serge	1652	int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
		1653	struct drm_framebuffer *old_fb)
		1654	{
		1655	struct drm_device *dev = crtc->dev;
		1656	struct radeon_device *rdev = dev->dev_private;
		1657
1430	serge	1658	if (ASIC_IS_DCE4(rdev))
1963	serge	1659	return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1430	serge	1660	else if (ASIC_IS_AVIVO(rdev))
1963	serge	1661	return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1404	serge	1662	else
1963	serge	1663	return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1404	serge	1664	}
		1665
1963	serge	1666	int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
		1667	struct drm_framebuffer *fb,
		1668	int x, int y, enum mode_set_atomic state)
		1669	{
		1670	struct drm_device *dev = crtc->dev;
		1671	struct radeon_device *rdev = dev->dev_private;
		1672
		1673	if (ASIC_IS_DCE4(rdev))
		1674	return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
		1675	else if (ASIC_IS_AVIVO(rdev))
		1676	return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
		1677	else
		1678	return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
		1679	}
		1680
1404	serge	1681	/* properly set additional regs when using atombios */
		1682	static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
		1683	{
		1684	struct drm_device *dev = crtc->dev;
		1685	struct radeon_device *rdev = dev->dev_private;
		1686	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1687	u32 disp_merge_cntl;
		1688
		1689	switch (radeon_crtc->crtc_id) {
		1690	case 0:
		1691	disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		1692	disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		1693	WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		1694	break;
		1695	case 1:
		1696	disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		1697	disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		1698	WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
		1699	WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		1700	WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		1701	break;
		1702	}
		1703	}
		1704
2997	Serge	1705	/**
		1706	* radeon_get_pll_use_mask - look up a mask of which pplls are in use
		1707	*
		1708	* @crtc: drm crtc
		1709	*
		1710	* Returns the mask of which PPLLs (Pixel PLLs) are in use.
		1711	*/
		1712	static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
		1713	{
		1714	struct drm_device *dev = crtc->dev;
		1715	struct drm_crtc *test_crtc;
		1716	struct radeon_crtc *test_radeon_crtc;
		1717	u32 pll_in_use = 0;
		1718
		1719	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1720	if (crtc == test_crtc)
		1721	continue;
		1722
		1723	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1724	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1725	pll_in_use \|= (1 << test_radeon_crtc->pll_id);
		1726	}
		1727	return pll_in_use;
		1728	}
		1729
		1730	/**
		1731	* radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
		1732	*
		1733	* @crtc: drm crtc
		1734	*
		1735	* Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
		1736	* also in DP mode. For DP, a single PPLL can be used for all DP
		1737	* crtcs/encoders.
		1738	*/
		1739	static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
		1740	{
		1741	struct drm_device *dev = crtc->dev;
6661	serge	1742	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1743	struct drm_crtc *test_crtc;
		1744	struct radeon_crtc *test_radeon_crtc;
		1745
		1746	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1747	if (crtc == test_crtc)
		1748	continue;
		1749	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1750	if (test_radeon_crtc->encoder &&
		1751	ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
6661	serge	1752	/* PPLL2 is exclusive to UNIPHYA on DCE61 */
		1753	if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
		1754	test_radeon_crtc->pll_id == ATOM_PPLL2)
		1755	continue;
2997	Serge	1756	/* for DP use the same PLL for all */
		1757	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1758	return test_radeon_crtc->pll_id;
		1759	}
		1760	}
		1761	return ATOM_PPLL_INVALID;
		1762	}
		1763
		1764	/**
		1765	* radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
		1766	*
		1767	* @crtc: drm crtc
		1768	* @encoder: drm encoder
		1769	*
		1770	* Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
		1771	* be shared (i.e., same clock).
		1772	*/
		1773	static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
		1774	{
		1775	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1776	struct drm_device *dev = crtc->dev;
6661	serge	1777	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1778	struct drm_crtc *test_crtc;
		1779	struct radeon_crtc *test_radeon_crtc;
		1780	u32 adjusted_clock, test_adjusted_clock;
		1781
		1782	adjusted_clock = radeon_crtc->adjusted_clock;
		1783
		1784	if (adjusted_clock == 0)
		1785	return ATOM_PPLL_INVALID;
		1786
		1787	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		1788	if (crtc == test_crtc)
		1789	continue;
		1790	test_radeon_crtc = to_radeon_crtc(test_crtc);
		1791	if (test_radeon_crtc->encoder &&
		1792	!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
6661	serge	1793	/* PPLL2 is exclusive to UNIPHYA on DCE61 */
		1794	if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
		1795	test_radeon_crtc->pll_id == ATOM_PPLL2)
		1796	continue;
2997	Serge	1797	/* check if we are already driving this connector with another crtc */
		1798	if (test_radeon_crtc->connector == radeon_crtc->connector) {
		1799	/* if we are, return that pll */
		1800	if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
		1801	return test_radeon_crtc->pll_id;
		1802	}
		1803	/* for non-DP check the clock */
		1804	test_adjusted_clock = test_radeon_crtc->adjusted_clock;
		1805	if ((crtc->mode.clock == test_crtc->mode.clock) &&
		1806	(adjusted_clock == test_adjusted_clock) &&
		1807	(radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
		1808	(test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
		1809	return test_radeon_crtc->pll_id;
		1810	}
		1811	}
		1812	return ATOM_PPLL_INVALID;
		1813	}
		1814
		1815	/**
		1816	* radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
		1817	*
		1818	* @crtc: drm crtc
		1819	*
		1820	* Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
		1821	* a single PPLL can be used for all DP crtcs/encoders. For non-DP
		1822	* monitors a dedicated PPLL must be used. If a particular board has
		1823	* an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
		1824	* as there is no need to program the PLL itself. If we are not able to
		1825	* allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
		1826	* avoid messing up an existing monitor.
		1827	*
		1828	* Asic specific PLL information
		1829	*
5078	serge	1830	* DCE 8.x
		1831	* KB/KV
		1832	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
		1833	* CI
		1834	* - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1835	*
2997	Serge	1836	* DCE 6.1
		1837	* - PPLL2 is only available to UNIPHYA (both DP and non-DP)
		1838	* - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
		1839	*
		1840	* DCE 6.0
		1841	* - PPLL0 is available to all UNIPHY (DP only)
		1842	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1843	*
		1844	* DCE 5.0
		1845	* - DCPLL is available to all UNIPHY (DP only)
		1846	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1847	*
		1848	* DCE 3.0/4.0/4.1
		1849	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
		1850	*
		1851	*/
1430	serge	1852	static int radeon_atom_pick_pll(struct drm_crtc *crtc)
		1853	{
		1854	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1855	struct drm_device *dev = crtc->dev;
		1856	struct radeon_device *rdev = dev->dev_private;
2997	Serge	1857	struct radeon_encoder *radeon_encoder =
		1858	to_radeon_encoder(radeon_crtc->encoder);
		1859	u32 pll_in_use;
		1860	int pll;
1430	serge	1861
5078	serge	1862	if (ASIC_IS_DCE8(rdev)) {
		1863	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1864	if (rdev->clock.dp_extclk)
		1865	/* skip PPLL programming if using ext clock */
		1866	return ATOM_PPLL_INVALID;
		1867	else {
		1868	/* use the same PPLL for all DP monitors */
		1869	pll = radeon_get_shared_dp_ppll(crtc);
		1870	if (pll != ATOM_PPLL_INVALID)
		1871	return pll;
		1872	}
		1873	} else {
		1874	/* use the same PPLL for all monitors with the same clock */
		1875	pll = radeon_get_shared_nondp_ppll(crtc);
		1876	if (pll != ATOM_PPLL_INVALID)
		1877	return pll;
		1878	}
		1879	/* otherwise, pick one of the plls */
6104	serge	1880	if ((rdev->family == CHIP_KABINI) \|\|
5078	serge	1881	(rdev->family == CHIP_MULLINS)) {
6104	serge	1882	/* KB/ML has PPLL1 and PPLL2 */
5078	serge	1883	pll_in_use = radeon_get_pll_use_mask(crtc);
		1884	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1885	return ATOM_PPLL2;
		1886	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1887	return ATOM_PPLL1;
		1888	DRM_ERROR("unable to allocate a PPLL\n");
		1889	return ATOM_PPLL_INVALID;
		1890	} else {
6104	serge	1891	/* CI/KV has PPLL0, PPLL1, and PPLL2 */
5078	serge	1892	pll_in_use = radeon_get_pll_use_mask(crtc);
		1893	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1894	return ATOM_PPLL2;
		1895	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1896	return ATOM_PPLL1;
		1897	if (!(pll_in_use & (1 << ATOM_PPLL0)))
		1898	return ATOM_PPLL0;
		1899	DRM_ERROR("unable to allocate a PPLL\n");
		1900	return ATOM_PPLL_INVALID;
		1901	}
		1902	} else if (ASIC_IS_DCE61(rdev)) {
3031	serge	1903	struct radeon_encoder_atom_dig *dig =
2997	Serge	1904	radeon_encoder->enc_priv;
		1905
		1906	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
		1907	(dig->linkb == false))
		1908	/* UNIPHY A uses PPLL2 */
3031	serge	1909	return ATOM_PPLL2;
2997	Serge	1910	else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1911	/* UNIPHY B/C/D/E/F */
		1912	if (rdev->clock.dp_extclk)
		1913	/* skip PPLL programming if using ext clock */
		1914	return ATOM_PPLL_INVALID;
		1915	else {
		1916	/* use the same PPLL for all DP monitors */
		1917	pll = radeon_get_shared_dp_ppll(crtc);
		1918	if (pll != ATOM_PPLL_INVALID)
		1919	return pll;
		1920	}
		1921	} else {
		1922	/* use the same PPLL for all monitors with the same clock */
		1923	pll = radeon_get_shared_nondp_ppll(crtc);
		1924	if (pll != ATOM_PPLL_INVALID)
		1925	return pll;
		1926	}
		1927	/* UNIPHY B/C/D/E/F */
		1928	pll_in_use = radeon_get_pll_use_mask(crtc);
		1929	if (!(pll_in_use & (1 << ATOM_PPLL0)))
		1930	return ATOM_PPLL0;
		1931	if (!(pll_in_use & (1 << ATOM_PPLL1)))
3031	serge	1932	return ATOM_PPLL1;
2997	Serge	1933	DRM_ERROR("unable to allocate a PPLL\n");
		1934	return ATOM_PPLL_INVALID;
5078	serge	1935	} else if (ASIC_IS_DCE41(rdev)) {
		1936	/* Don't share PLLs on DCE4.1 chips */
		1937	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
		1938	if (rdev->clock.dp_extclk)
		1939	/* skip PPLL programming if using ext clock */
		1940	return ATOM_PPLL_INVALID;
		1941	}
		1942	pll_in_use = radeon_get_pll_use_mask(crtc);
		1943	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1944	return ATOM_PPLL1;
		1945	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1946	return ATOM_PPLL2;
		1947	DRM_ERROR("unable to allocate a PPLL\n");
		1948	return ATOM_PPLL_INVALID;
2997	Serge	1949	} else if (ASIC_IS_DCE4(rdev)) {
3031	serge	1950	/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
		1951	* depending on the asic:
		1952	* DCE4: PPLL or ext clock
2997	Serge	1953	* DCE5: PPLL, DCPLL, or ext clock
		1954	* DCE6: PPLL, PPLL0, or ext clock
3031	serge	1955	*
		1956	* Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
		1957	* PPLL/DCPLL programming and only program the DP DTO for the
		1958	* crtc virtual pixel clock.
		1959	*/
2997	Serge	1960	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
3031	serge	1961	if (rdev->clock.dp_extclk)
2997	Serge	1962	/* skip PPLL programming if using ext clock */
3031	serge	1963	return ATOM_PPLL_INVALID;
		1964	else if (ASIC_IS_DCE6(rdev))
2997	Serge	1965	/* use PPLL0 for all DP */
3031	serge	1966	return ATOM_PPLL0;
		1967	else if (ASIC_IS_DCE5(rdev))
2997	Serge	1968	/* use DCPLL for all DP */
3031	serge	1969	return ATOM_DCPLL;
2997	Serge	1970	else {
		1971	/* use the same PPLL for all DP monitors */
		1972	pll = radeon_get_shared_dp_ppll(crtc);
		1973	if (pll != ATOM_PPLL_INVALID)
		1974	return pll;
3031	serge	1975	}
2997	Serge	1976	} else {
		1977	/* use the same PPLL for all monitors with the same clock */
		1978	pll = radeon_get_shared_nondp_ppll(crtc);
		1979	if (pll != ATOM_PPLL_INVALID)
		1980	return pll;
3031	serge	1981	}
2997	Serge	1982	/* all other cases */
		1983	pll_in_use = radeon_get_pll_use_mask(crtc);
		1984	if (!(pll_in_use & (1 << ATOM_PPLL1)))
		1985	return ATOM_PPLL1;
		1986	if (!(pll_in_use & (1 << ATOM_PPLL2)))
		1987	return ATOM_PPLL2;
		1988	DRM_ERROR("unable to allocate a PPLL\n");
		1989	return ATOM_PPLL_INVALID;
6104	serge	1990	} else {
3120	serge	1991	/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
		1992	/* some atombios (observed in some DCE2/DCE3) code have a bug,
		1993	* the matching btw pll and crtc is done through
		1994	* PCLK_CRTC[1\|2]_CNTL (0x480/0x484) but atombios code use the
		1995	* pll (1 or 2) to select which register to write. ie if using
		1996	* pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
		1997	* it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
		1998	* choose which value to write. Which is reverse order from
		1999	* register logic. So only case that works is when pllid is
		2000	* same as crtcid or when both pll and crtc are enabled and
		2001	* both use same clock.
		2002	*
		2003	* So just return crtc id as if crtc and pll were hard linked
		2004	* together even if they aren't
3031	serge	2005	*/
1430	serge	2006	return radeon_crtc->crtc_id;
2997	Serge	2007	}
		2008	}
1430	serge	2009
2997	Serge	2010	void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
		2011	{
		2012	/* always set DCPLL */
		2013	if (ASIC_IS_DCE6(rdev))
		2014	atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
		2015	else if (ASIC_IS_DCE4(rdev)) {
		2016	struct radeon_atom_ss ss;
		2017	bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
		2018	ASIC_INTERNAL_SS_ON_DCPLL,
		2019	rdev->clock.default_dispclk);
		2020	if (ss_enabled)
		2021	atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
		2022	/* XXX: DCE5, make sure voltage, dispclk is high enough */
		2023	atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
		2024	if (ss_enabled)
		2025	atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
		2026	}
		2027
1430	serge	2028	}
		2029
1123	serge	2030	int atombios_crtc_mode_set(struct drm_crtc *crtc,
		2031	struct drm_display_mode *mode,
		2032	struct drm_display_mode *adjusted_mode,
		2033	int x, int y, struct drm_framebuffer *old_fb)
		2034	{
		2035	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		2036	struct drm_device *dev = crtc->dev;
		2037	struct radeon_device *rdev = dev->dev_private;
2997	Serge	2038	struct radeon_encoder *radeon_encoder =
		2039	to_radeon_encoder(radeon_crtc->encoder);
1963	serge	2040	bool is_tvcv = false;
1123	serge	2041
3031	serge	2042	if (radeon_encoder->active_device &
		2043	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		2044	is_tvcv = true;
1123	serge	2045
5078	serge	2046	if (!radeon_crtc->adjusted_clock)
		2047	return -EINVAL;
		2048
1123	serge	2049	atombios_crtc_set_pll(crtc, adjusted_mode);
1430	serge	2050
		2051	if (ASIC_IS_DCE4(rdev))
		2052	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1963	serge	2053	else if (ASIC_IS_AVIVO(rdev)) {
		2054	if (is_tvcv)
		2055	atombios_crtc_set_timing(crtc, adjusted_mode);
		2056	else
		2057	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
		2058	} else {
1430	serge	2059	atombios_crtc_set_timing(crtc, adjusted_mode);
1268	serge	2060	if (radeon_crtc->crtc_id == 0)
		2061	atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1404	serge	2062	radeon_legacy_atom_fixup(crtc);
1123	serge	2063	}
1430	serge	2064	atombios_crtc_set_base(crtc, x, y, old_fb);
6104	serge	2065	atombios_overscan_setup(crtc, mode, adjusted_mode);
		2066	atombios_scaler_setup(crtc);
		2067	// radeon_cursor_reset(crtc);
5078	serge	2068	/* update the hw version fpr dpm */
		2069	radeon_crtc->hw_mode = *adjusted_mode;
		2070
1123	serge	2071	return 0;
		2072	}
		2073
		2074	static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2997	Serge	2075	const struct drm_display_mode *mode,
1123	serge	2076	struct drm_display_mode *adjusted_mode)
		2077	{
2997	Serge	2078	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	2079	struct drm_device *dev = crtc->dev;
2997	Serge	2080	struct drm_encoder *encoder;
1963	serge	2081
2997	Serge	2082	/* assign the encoder to the radeon crtc to avoid repeated lookups later */
		2083	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		2084	if (encoder->crtc == crtc) {
		2085	radeon_crtc->encoder = encoder;
		2086	radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
		2087	break;
		2088	}
		2089	}
		2090	if ((radeon_crtc->encoder == NULL) \|\| (radeon_crtc->connector == NULL)) {
		2091	radeon_crtc->encoder = NULL;
		2092	radeon_crtc->connector = NULL;
		2093	return false;
		2094	}
6104	serge	2095	if (radeon_crtc->encoder) {
		2096	struct radeon_encoder *radeon_encoder =
		2097	to_radeon_encoder(radeon_crtc->encoder);
		2098
		2099	radeon_crtc->output_csc = radeon_encoder->output_csc;
		2100	}
1179	serge	2101	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		2102	return false;
2997	Serge	2103	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
		2104	return false;
		2105	/* pick pll */
		2106	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
		2107	/* if we can't get a PPLL for a non-DP encoder, fail */
		2108	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
		2109	!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
		2110	return false;
		2111
1123	serge	2112	return true;
		2113	}
		2114
		2115	static void atombios_crtc_prepare(struct drm_crtc *crtc)
		2116	{
2997	Serge	2117	struct drm_device *dev = crtc->dev;
		2118	struct radeon_device *rdev = dev->dev_private;
1963	serge	2119
2997	Serge	2120	/* disable crtc pair power gating before programming */
		2121	if (ASIC_IS_DCE6(rdev))
		2122	atombios_powergate_crtc(crtc, ATOM_DISABLE);
		2123
1430	serge	2124	atombios_lock_crtc(crtc, ATOM_ENABLE);
1123	serge	2125	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
		2126	}
		2127
		2128	static void atombios_crtc_commit(struct drm_crtc *crtc)
		2129	{
		2130	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1430	serge	2131	atombios_lock_crtc(crtc, ATOM_DISABLE);
1123	serge	2132	}
		2133
1963	serge	2134	static void atombios_crtc_disable(struct drm_crtc *crtc)
		2135	{
		2136	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2997	Serge	2137	struct drm_device *dev = crtc->dev;
		2138	struct radeon_device *rdev = dev->dev_private;
1963	serge	2139	struct radeon_atom_ss ss;
2997	Serge	2140	int i;
1963	serge	2141
		2142	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
5078	serge	2143	if (crtc->primary->fb) {
		2144	int r;
		2145	struct radeon_framebuffer *radeon_fb;
		2146	struct radeon_bo *rbo;
		2147
		2148	radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
		2149	rbo = gem_to_radeon_bo(radeon_fb->obj);
		2150	r = radeon_bo_reserve(rbo, false);
		2151	if (unlikely(r))
		2152	DRM_ERROR("failed to reserve rbo before unpin\n");
		2153	else {
		2154	radeon_bo_unpin(rbo);
		2155	radeon_bo_unreserve(rbo);
		2156	}
		2157	}
		2158	/* disable the GRPH */
		2159	if (ASIC_IS_DCE4(rdev))
		2160	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
		2161	else if (ASIC_IS_AVIVO(rdev))
		2162	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
		2163
3764	Serge	2164	if (ASIC_IS_DCE6(rdev))
		2165	atombios_powergate_crtc(crtc, ATOM_ENABLE);
1963	serge	2166
2997	Serge	2167	for (i = 0; i < rdev->num_crtc; i++) {
		2168	if (rdev->mode_info.crtcs[i] &&
		2169	rdev->mode_info.crtcs[i]->enabled &&
		2170	i != radeon_crtc->crtc_id &&
		2171	radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
		2172	/* one other crtc is using this pll don't turn
		2173	* off the pll
		2174	*/
		2175	goto done;
		2176	}
		2177	}
		2178
1963	serge	2179	switch (radeon_crtc->pll_id) {
		2180	case ATOM_PPLL1:
		2181	case ATOM_PPLL2:
		2182	/* disable the ppll */
		2183	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
		2184	0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
		2185	break;
2997	Serge	2186	case ATOM_PPLL0:
		2187	/* disable the ppll */
5078	serge	2188	if ((rdev->family == CHIP_ARUBA) \|\|
6104	serge	2189	(rdev->family == CHIP_KAVERI) \|\|
5078	serge	2190	(rdev->family == CHIP_BONAIRE) \|\|
		2191	(rdev->family == CHIP_HAWAII))
2997	Serge	2192	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
		2193	0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
		2194	break;
1963	serge	2195	default:
		2196	break;
		2197	}
2997	Serge	2198	done:
		2199	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
		2200	radeon_crtc->adjusted_clock = 0;
		2201	radeon_crtc->encoder = NULL;
		2202	radeon_crtc->connector = NULL;
1963	serge	2203	}
		2204
1123	serge	2205	static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
		2206	.dpms = atombios_crtc_dpms,
		2207	.mode_fixup = atombios_crtc_mode_fixup,
		2208	.mode_set = atombios_crtc_mode_set,
		2209	.mode_set_base = atombios_crtc_set_base,
1963	serge	2210	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
1123	serge	2211	.prepare = atombios_crtc_prepare,
		2212	.commit = atombios_crtc_commit,
1221	serge	2213	.load_lut = radeon_crtc_load_lut,
1963	serge	2214	.disable = atombios_crtc_disable,
1123	serge	2215	};
		2216
		2217	void radeon_atombios_init_crtc(struct drm_device *dev,
		2218	struct radeon_crtc *radeon_crtc)
		2219	{
1430	serge	2220	struct radeon_device *rdev = dev->dev_private;
		2221
		2222	if (ASIC_IS_DCE4(rdev)) {
		2223	switch (radeon_crtc->crtc_id) {
		2224	case 0:
		2225	default:
		2226	radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
		2227	break;
		2228	case 1:
		2229	radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
		2230	break;
		2231	case 2:
		2232	radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
		2233	break;
		2234	case 3:
		2235	radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
		2236	break;
		2237	case 4:
		2238	radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
		2239	break;
		2240	case 5:
		2241	radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
		2242	break;
		2243	}
		2244	} else {
3031	serge	2245	if (radeon_crtc->crtc_id == 1)
		2246	radeon_crtc->crtc_offset =
		2247	AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1430	serge	2248	else
		2249	radeon_crtc->crtc_offset = 0;
		2250	}
2997	Serge	2251	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
		2252	radeon_crtc->adjusted_clock = 0;
		2253	radeon_crtc->encoder = NULL;
		2254	radeon_crtc->connector = NULL;
1123	serge	2255	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
		2256	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/atombios_crtc.c – Rev 6661