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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1179 | serge | 26 | #include |
27 | #include |
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28 | #include |
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1963 | serge | 29 | #include |
1123 | serge | 30 | #include "radeon.h" |
31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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33 | |||
1179 | serge | 34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
35 | struct drm_display_mode *mode, |
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36 | struct drm_display_mode *adjusted_mode) |
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37 | { |
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38 | struct drm_device *dev = crtc->dev; |
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39 | struct radeon_device *rdev = dev->dev_private; |
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40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
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42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
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43 | int a1, a2; |
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44 | |||
45 | memset(&args, 0, sizeof(args)); |
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46 | |||
47 | args.ucCRTC = radeon_crtc->crtc_id; |
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48 | |||
49 | switch (radeon_crtc->rmx_type) { |
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50 | case RMX_CENTER: |
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1963 | serge | 51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
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53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
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54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
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1179 | serge | 55 | break; |
56 | case RMX_ASPECT: |
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57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
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58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
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59 | |||
60 | if (a1 > a2) { |
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1963 | serge | 61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
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1179 | serge | 63 | } else if (a2 > a1) { |
1963 | serge | 64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
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1179 | serge | 66 | } |
67 | break; |
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68 | case RMX_FULL: |
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69 | default: |
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1963 | serge | 70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
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72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
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73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
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1179 | serge | 74 | break; |
75 | } |
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1963 | serge | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1179 | serge | 77 | } |
78 | |||
79 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
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80 | { |
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81 | struct drm_device *dev = crtc->dev; |
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82 | struct radeon_device *rdev = dev->dev_private; |
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83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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84 | ENABLE_SCALER_PS_ALLOCATION args; |
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85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
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2997 | Serge | 86 | struct radeon_encoder *radeon_encoder = |
87 | to_radeon_encoder(radeon_crtc->encoder); |
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1179 | serge | 88 | /* fixme - fill in enc_priv for atom dac */ |
89 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
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90 | bool is_tv = false, is_cv = false; |
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91 | |||
92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
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93 | return; |
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94 | |||
3031 | serge | 95 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
96 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
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97 | tv_std = tv_dac->tv_std; |
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98 | is_tv = true; |
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99 | } |
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1179 | serge | 100 | |
101 | memset(&args, 0, sizeof(args)); |
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102 | |||
103 | args.ucScaler = radeon_crtc->crtc_id; |
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104 | |||
105 | if (is_tv) { |
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106 | switch (tv_std) { |
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107 | case TV_STD_NTSC: |
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108 | default: |
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109 | args.ucTVStandard = ATOM_TV_NTSC; |
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110 | break; |
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111 | case TV_STD_PAL: |
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112 | args.ucTVStandard = ATOM_TV_PAL; |
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113 | break; |
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114 | case TV_STD_PAL_M: |
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115 | args.ucTVStandard = ATOM_TV_PALM; |
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116 | break; |
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117 | case TV_STD_PAL_60: |
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118 | args.ucTVStandard = ATOM_TV_PAL60; |
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119 | break; |
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120 | case TV_STD_NTSC_J: |
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121 | args.ucTVStandard = ATOM_TV_NTSCJ; |
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122 | break; |
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123 | case TV_STD_SCART_PAL: |
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124 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
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125 | break; |
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126 | case TV_STD_SECAM: |
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127 | args.ucTVStandard = ATOM_TV_SECAM; |
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128 | break; |
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129 | case TV_STD_PAL_CN: |
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130 | args.ucTVStandard = ATOM_TV_PALCN; |
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131 | break; |
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132 | } |
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133 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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134 | } else if (is_cv) { |
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135 | args.ucTVStandard = ATOM_TV_CV; |
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136 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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137 | } else { |
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138 | switch (radeon_crtc->rmx_type) { |
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139 | case RMX_FULL: |
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140 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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141 | break; |
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142 | case RMX_CENTER: |
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143 | args.ucEnable = ATOM_SCALER_CENTER; |
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144 | break; |
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145 | case RMX_ASPECT: |
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146 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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147 | break; |
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148 | default: |
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149 | if (ASIC_IS_AVIVO(rdev)) |
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150 | args.ucEnable = ATOM_SCALER_DISABLE; |
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151 | else |
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152 | args.ucEnable = ATOM_SCALER_CENTER; |
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153 | break; |
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154 | } |
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155 | } |
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156 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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157 | if ((is_tv || is_cv) |
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158 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
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159 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
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160 | } |
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161 | } |
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162 | |||
1123 | serge | 163 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
164 | { |
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165 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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166 | struct drm_device *dev = crtc->dev; |
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167 | struct radeon_device *rdev = dev->dev_private; |
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168 | int index = |
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169 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
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170 | ENABLE_CRTC_PS_ALLOCATION args; |
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171 | |||
172 | memset(&args, 0, sizeof(args)); |
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173 | |||
174 | args.ucCRTC = radeon_crtc->crtc_id; |
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175 | args.ucEnable = lock; |
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176 | |||
177 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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178 | } |
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179 | |||
180 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
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181 | { |
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182 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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183 | struct drm_device *dev = crtc->dev; |
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184 | struct radeon_device *rdev = dev->dev_private; |
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185 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
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186 | ENABLE_CRTC_PS_ALLOCATION args; |
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187 | |||
188 | memset(&args, 0, sizeof(args)); |
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189 | |||
190 | args.ucCRTC = radeon_crtc->crtc_id; |
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191 | args.ucEnable = state; |
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192 | |||
193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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194 | } |
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195 | |||
196 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
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197 | { |
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198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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199 | struct drm_device *dev = crtc->dev; |
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200 | struct radeon_device *rdev = dev->dev_private; |
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201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
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202 | ENABLE_CRTC_PS_ALLOCATION args; |
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203 | |||
204 | memset(&args, 0, sizeof(args)); |
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205 | |||
206 | args.ucCRTC = radeon_crtc->crtc_id; |
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207 | args.ucEnable = state; |
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208 | |||
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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210 | } |
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211 | |||
212 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
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213 | { |
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214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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215 | struct drm_device *dev = crtc->dev; |
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216 | struct radeon_device *rdev = dev->dev_private; |
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217 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
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218 | BLANK_CRTC_PS_ALLOCATION args; |
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219 | |||
220 | memset(&args, 0, sizeof(args)); |
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221 | |||
222 | args.ucCRTC = radeon_crtc->crtc_id; |
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223 | args.ucBlanking = state; |
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224 | |||
225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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226 | } |
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227 | |||
2997 | Serge | 228 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
229 | { |
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230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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231 | struct drm_device *dev = crtc->dev; |
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232 | struct radeon_device *rdev = dev->dev_private; |
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233 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); |
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234 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; |
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235 | |||
236 | memset(&args, 0, sizeof(args)); |
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237 | |||
238 | args.ucDispPipeId = radeon_crtc->crtc_id; |
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239 | args.ucEnable = state; |
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240 | |||
241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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242 | } |
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243 | |||
1123 | serge | 244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
245 | { |
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246 | struct drm_device *dev = crtc->dev; |
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247 | struct radeon_device *rdev = dev->dev_private; |
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1321 | serge | 248 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 249 | |
250 | switch (mode) { |
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251 | case DRM_MODE_DPMS_ON: |
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1963 | serge | 252 | radeon_crtc->enabled = true; |
253 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
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254 | radeon_pm_compute_clocks(rdev); |
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1430 | serge | 255 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
2997 | Serge | 256 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
1430 | serge | 257 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
258 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
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3031 | serge | 259 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
1321 | serge | 260 | radeon_crtc_load_lut(crtc); |
1123 | serge | 261 | break; |
262 | case DRM_MODE_DPMS_STANDBY: |
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263 | case DRM_MODE_DPMS_SUSPEND: |
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264 | case DRM_MODE_DPMS_OFF: |
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3031 | serge | 265 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
1963 | serge | 266 | if (radeon_crtc->enabled) |
3031 | serge | 267 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
2997 | Serge | 268 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
1430 | serge | 269 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
270 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
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1963 | serge | 271 | radeon_crtc->enabled = false; |
272 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
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273 | radeon_pm_compute_clocks(rdev); |
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1123 | serge | 274 | break; |
275 | } |
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276 | } |
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277 | |||
278 | static void |
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279 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
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1268 | serge | 280 | struct drm_display_mode *mode) |
1123 | serge | 281 | { |
1268 | serge | 282 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 283 | struct drm_device *dev = crtc->dev; |
284 | struct radeon_device *rdev = dev->dev_private; |
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1268 | serge | 285 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
1123 | serge | 286 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
1268 | serge | 287 | u16 misc = 0; |
1123 | serge | 288 | |
1268 | serge | 289 | memset(&args, 0, sizeof(args)); |
1963 | serge | 290 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
1268 | serge | 291 | args.usH_Blanking_Time = |
1963 | serge | 292 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
293 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
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1268 | serge | 294 | args.usV_Blanking_Time = |
1963 | serge | 295 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
1268 | serge | 296 | args.usH_SyncOffset = |
1963 | serge | 297 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
1268 | serge | 298 | args.usH_SyncWidth = |
299 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
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300 | args.usV_SyncOffset = |
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1963 | serge | 301 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
1268 | serge | 302 | args.usV_SyncWidth = |
303 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
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1963 | serge | 304 | args.ucH_Border = radeon_crtc->h_border; |
305 | args.ucV_Border = radeon_crtc->v_border; |
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1123 | serge | 306 | |
1268 | serge | 307 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
308 | misc |= ATOM_VSYNC_POLARITY; |
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309 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
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310 | misc |= ATOM_HSYNC_POLARITY; |
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311 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
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312 | misc |= ATOM_COMPOSITESYNC; |
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313 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
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314 | misc |= ATOM_INTERLACE; |
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315 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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316 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
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317 | |||
318 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
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319 | args.ucCRTC = radeon_crtc->crtc_id; |
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320 | |||
321 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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1123 | serge | 322 | } |
323 | |||
1268 | serge | 324 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
325 | struct drm_display_mode *mode) |
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1123 | serge | 326 | { |
1268 | serge | 327 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 328 | struct drm_device *dev = crtc->dev; |
329 | struct radeon_device *rdev = dev->dev_private; |
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1268 | serge | 330 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
1123 | serge | 331 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
1268 | serge | 332 | u16 misc = 0; |
1123 | serge | 333 | |
1268 | serge | 334 | memset(&args, 0, sizeof(args)); |
335 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
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336 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
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337 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
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338 | args.usH_SyncWidth = |
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339 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
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340 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
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341 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
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342 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
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343 | args.usV_SyncWidth = |
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344 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
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1123 | serge | 345 | |
1963 | serge | 346 | args.ucOverscanRight = radeon_crtc->h_border; |
347 | args.ucOverscanLeft = radeon_crtc->h_border; |
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348 | args.ucOverscanBottom = radeon_crtc->v_border; |
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349 | args.ucOverscanTop = radeon_crtc->v_border; |
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350 | |||
1268 | serge | 351 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
352 | misc |= ATOM_VSYNC_POLARITY; |
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353 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
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354 | misc |= ATOM_HSYNC_POLARITY; |
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355 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
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356 | misc |= ATOM_COMPOSITESYNC; |
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357 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
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358 | misc |= ATOM_INTERLACE; |
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359 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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360 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
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361 | |||
362 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
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363 | args.ucCRTC = radeon_crtc->crtc_id; |
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364 | |||
365 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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1123 | serge | 366 | } |
367 | |||
2997 | Serge | 368 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
1963 | serge | 369 | { |
370 | u32 ss_cntl; |
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371 | |||
372 | if (ASIC_IS_DCE4(rdev)) { |
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2997 | Serge | 373 | switch (pll_id) { |
1963 | serge | 374 | case ATOM_PPLL1: |
375 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
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376 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
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377 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
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378 | break; |
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379 | case ATOM_PPLL2: |
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380 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
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381 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
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382 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
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383 | break; |
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384 | case ATOM_DCPLL: |
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385 | case ATOM_PPLL_INVALID: |
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386 | return; |
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387 | } |
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388 | } else if (ASIC_IS_AVIVO(rdev)) { |
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2997 | Serge | 389 | switch (pll_id) { |
1963 | serge | 390 | case ATOM_PPLL1: |
391 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
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392 | ss_cntl &= ~1; |
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393 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
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394 | break; |
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395 | case ATOM_PPLL2: |
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396 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
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397 | ss_cntl &= ~1; |
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398 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
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399 | break; |
||
400 | case ATOM_DCPLL: |
||
401 | case ATOM_PPLL_INVALID: |
||
402 | return; |
||
403 | } |
||
404 | } |
||
405 | } |
||
406 | |||
407 | |||
1430 | serge | 408 | union atom_enable_ss { |
1963 | serge | 409 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
410 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
||
1430 | serge | 411 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
1963 | serge | 412 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
413 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
||
1430 | serge | 414 | }; |
415 | |||
2997 | Serge | 416 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
1963 | serge | 417 | int enable, |
418 | int pll_id, |
||
2997 | Serge | 419 | int crtc_id, |
1963 | serge | 420 | struct radeon_atom_ss *ss) |
1268 | serge | 421 | { |
2997 | Serge | 422 | unsigned i; |
1268 | serge | 423 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
1430 | serge | 424 | union atom_enable_ss args; |
1268 | serge | 425 | |
2997 | Serge | 426 | if (!enable) { |
427 | for (i = 0; i < rdev->num_crtc; i++) { |
||
428 | if (rdev->mode_info.crtcs[i] && |
||
429 | rdev->mode_info.crtcs[i]->enabled && |
||
430 | i != crtc_id && |
||
431 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
||
432 | /* one other crtc is using this pll don't turn |
||
433 | * off spread spectrum as it might turn off |
||
434 | * display on active crtc |
||
435 | */ |
||
436 | return; |
||
437 | } |
||
438 | } |
||
439 | } |
||
440 | |||
1963 | serge | 441 | memset(&args, 0, sizeof(args)); |
1430 | serge | 442 | |
1963 | serge | 443 | if (ASIC_IS_DCE5(rdev)) { |
444 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
||
445 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
||
446 | switch (pll_id) { |
||
447 | case ATOM_PPLL1: |
||
448 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
||
449 | break; |
||
450 | case ATOM_PPLL2: |
||
451 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
||
452 | break; |
||
453 | case ATOM_DCPLL: |
||
454 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
||
455 | break; |
||
456 | case ATOM_PPLL_INVALID: |
||
457 | return; |
||
458 | } |
||
2997 | Serge | 459 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
460 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
||
1963 | serge | 461 | args.v3.ucEnable = enable; |
2997 | Serge | 462 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) |
1963 | serge | 463 | args.v3.ucEnable = ATOM_DISABLE; |
464 | } else if (ASIC_IS_DCE4(rdev)) { |
||
465 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
||
466 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
||
467 | switch (pll_id) { |
||
468 | case ATOM_PPLL1: |
||
469 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
||
470 | break; |
||
471 | case ATOM_PPLL2: |
||
472 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
||
473 | break; |
||
474 | case ATOM_DCPLL: |
||
475 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
||
476 | break; |
||
477 | case ATOM_PPLL_INVALID: |
||
3031 | serge | 478 | return; |
1963 | serge | 479 | } |
2997 | Serge | 480 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
481 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
||
1963 | serge | 482 | args.v2.ucEnable = enable; |
2997 | Serge | 483 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) |
1963 | serge | 484 | args.v2.ucEnable = ATOM_DISABLE; |
485 | } else if (ASIC_IS_DCE3(rdev)) { |
||
486 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
||
487 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
||
488 | args.v1.ucSpreadSpectrumStep = ss->step; |
||
489 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
||
490 | args.v1.ucSpreadSpectrumRange = ss->range; |
||
491 | args.v1.ucPpll = pll_id; |
||
492 | args.v1.ucEnable = enable; |
||
493 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
494 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
||
495 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
||
2997 | Serge | 496 | atombios_disable_ss(rdev, pll_id); |
3031 | serge | 497 | return; |
1268 | serge | 498 | } |
1963 | serge | 499 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
500 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
||
501 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
||
502 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
||
503 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
||
504 | args.lvds_ss_2.ucEnable = enable; |
||
1268 | serge | 505 | } else { |
1963 | serge | 506 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
507 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
||
2997 | Serge | 508 | atombios_disable_ss(rdev, pll_id); |
1963 | serge | 509 | return; |
3031 | serge | 510 | } |
1963 | serge | 511 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
512 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
||
513 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
||
514 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
||
515 | args.lvds_ss.ucEnable = enable; |
||
516 | } |
||
1430 | serge | 517 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1268 | serge | 518 | } |
519 | |||
1404 | serge | 520 | union adjust_pixel_clock { |
521 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
||
1430 | serge | 522 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
1404 | serge | 523 | }; |
524 | |||
525 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
||
2997 | Serge | 526 | struct drm_display_mode *mode) |
1123 | serge | 527 | { |
2997 | Serge | 528 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 529 | struct drm_device *dev = crtc->dev; |
530 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 531 | struct drm_encoder *encoder = radeon_crtc->encoder; |
532 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
533 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
||
1404 | serge | 534 | u32 adjusted_clock = mode->clock; |
2997 | Serge | 535 | int encoder_mode = atombios_get_encoder_mode(encoder); |
1963 | serge | 536 | u32 dp_clock = mode->clock; |
2997 | Serge | 537 | int bpc = radeon_get_monitor_bpc(connector); |
538 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
||
1123 | serge | 539 | |
1404 | serge | 540 | /* reset the pll flags */ |
2997 | Serge | 541 | radeon_crtc->pll_flags = 0; |
1123 | serge | 542 | |
543 | if (ASIC_IS_AVIVO(rdev)) { |
||
1179 | serge | 544 | if ((rdev->family == CHIP_RS600) || |
545 | (rdev->family == CHIP_RS690) || |
||
546 | (rdev->family == CHIP_RS740)) |
||
2997 | Serge | 547 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
3031 | serge | 548 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
1179 | serge | 549 | |
1123 | serge | 550 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
2997 | Serge | 551 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
1123 | serge | 552 | else |
2997 | Serge | 553 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
1963 | serge | 554 | |
555 | if (rdev->family < CHIP_RV770) |
||
2997 | Serge | 556 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
557 | /* use frac fb div on APUs */ |
||
558 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) |
||
559 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
||
3764 | Serge | 560 | /* use frac fb div on RS780/RS880 */ |
561 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
||
562 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
||
3192 | Serge | 563 | if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) |
564 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
||
1123 | serge | 565 | } else { |
2997 | Serge | 566 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
1123 | serge | 567 | |
568 | if (mode->clock > 200000) /* range limits??? */ |
||
2997 | Serge | 569 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
1123 | serge | 570 | else |
2997 | Serge | 571 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
1123 | serge | 572 | } |
573 | |||
3031 | serge | 574 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
575 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
||
576 | if (connector) { |
||
577 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
||
578 | struct radeon_connector_atom_dig *dig_connector = |
||
579 | radeon_connector->con_priv; |
||
1963 | serge | 580 | |
3031 | serge | 581 | dp_clock = dig_connector->dp_clock; |
582 | } |
||
583 | } |
||
1963 | serge | 584 | |
3031 | serge | 585 | /* use recommended ref_div for ss */ |
586 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
||
2997 | Serge | 587 | if (radeon_crtc->ss_enabled) { |
588 | if (radeon_crtc->ss.refdiv) { |
||
589 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
||
590 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; |
||
3031 | serge | 591 | if (ASIC_IS_AVIVO(rdev)) |
2997 | Serge | 592 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
1963 | serge | 593 | } |
3031 | serge | 594 | } |
595 | } |
||
1963 | serge | 596 | |
3031 | serge | 597 | if (ASIC_IS_AVIVO(rdev)) { |
598 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
||
599 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
||
600 | adjusted_clock = mode->clock * 2; |
||
601 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
||
2997 | Serge | 602 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
3031 | serge | 603 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
2997 | Serge | 604 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; |
3031 | serge | 605 | } else { |
606 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
||
2997 | Serge | 607 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
3031 | serge | 608 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
2997 | Serge | 609 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
1123 | serge | 610 | } |
611 | |||
1268 | serge | 612 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
613 | * accordingly based on the encoder/transmitter to work around |
||
614 | * special hw requirements. |
||
615 | */ |
||
616 | if (ASIC_IS_DCE3(rdev)) { |
||
1404 | serge | 617 | union adjust_pixel_clock args; |
618 | u8 frev, crev; |
||
619 | int index; |
||
1268 | serge | 620 | |
1404 | serge | 621 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
1963 | serge | 622 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
623 | &crev)) |
||
624 | return adjusted_clock; |
||
1268 | serge | 625 | |
1404 | serge | 626 | memset(&args, 0, sizeof(args)); |
627 | |||
628 | switch (frev) { |
||
629 | case 1: |
||
630 | switch (crev) { |
||
631 | case 1: |
||
632 | case 2: |
||
633 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
||
634 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
||
1430 | serge | 635 | args.v1.ucEncodeMode = encoder_mode; |
2997 | Serge | 636 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
3031 | serge | 637 | args.v1.ucConfig |= |
638 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
||
1404 | serge | 639 | |
3031 | serge | 640 | atom_execute_table(rdev->mode_info.atom_context, |
1404 | serge | 641 | index, (uint32_t *)&args); |
642 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
||
643 | break; |
||
1430 | serge | 644 | case 3: |
645 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
||
646 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
||
647 | args.v3.sInput.ucEncodeMode = encoder_mode; |
||
648 | args.v3.sInput.ucDispPllConfig = 0; |
||
2997 | Serge | 649 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
1963 | serge | 650 | args.v3.sInput.ucDispPllConfig |= |
651 | DISPPLL_CONFIG_SS_ENABLE; |
||
2997 | Serge | 652 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
3031 | serge | 653 | args.v3.sInput.ucDispPllConfig |= |
654 | DISPPLL_CONFIG_COHERENT_MODE; |
||
655 | /* 16200 or 27000 */ |
||
656 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
||
2997 | Serge | 657 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
658 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
||
659 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
||
3031 | serge | 660 | /* deep color support */ |
661 | args.v3.sInput.usPixelClock = |
||
662 | cpu_to_le16((mode->clock * bpc / 8) / 10); |
||
663 | if (dig->coherent_mode) |
||
664 | args.v3.sInput.ucDispPllConfig |= |
||
665 | DISPPLL_CONFIG_COHERENT_MODE; |
||
2997 | Serge | 666 | if (is_duallink) |
3031 | serge | 667 | args.v3.sInput.ucDispPllConfig |= |
668 | DISPPLL_CONFIG_DUAL_LINK; |
||
669 | } |
||
2997 | Serge | 670 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
671 | ENCODER_OBJECT_ID_NONE) |
||
672 | args.v3.sInput.ucExtTransmitterID = |
||
673 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
||
674 | else |
||
1986 | serge | 675 | args.v3.sInput.ucExtTransmitterID = 0; |
676 | |||
1430 | serge | 677 | atom_execute_table(rdev->mode_info.atom_context, |
678 | index, (uint32_t *)&args); |
||
679 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
||
680 | if (args.v3.sOutput.ucRefDiv) { |
||
2997 | Serge | 681 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
682 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
||
683 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; |
||
1430 | serge | 684 | } |
685 | if (args.v3.sOutput.ucPostDiv) { |
||
2997 | Serge | 686 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
687 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; |
||
688 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; |
||
1430 | serge | 689 | } |
690 | break; |
||
1404 | serge | 691 | default: |
692 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
693 | return adjusted_clock; |
||
694 | } |
||
695 | break; |
||
696 | default: |
||
697 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
698 | return adjusted_clock; |
||
699 | } |
||
1268 | serge | 700 | } |
1404 | serge | 701 | return adjusted_clock; |
702 | } |
||
1268 | serge | 703 | |
1404 | serge | 704 | union set_pixel_clock { |
705 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
||
706 | PIXEL_CLOCK_PARAMETERS v1; |
||
707 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
||
708 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
||
1430 | serge | 709 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
1963 | serge | 710 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
1404 | serge | 711 | }; |
712 | |||
1963 | serge | 713 | /* on DCE5, make sure the voltage is high enough to support the |
714 | * required disp clk. |
||
715 | */ |
||
2997 | Serge | 716 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
1963 | serge | 717 | u32 dispclk) |
1404 | serge | 718 | { |
1430 | serge | 719 | u8 frev, crev; |
720 | int index; |
||
721 | union set_pixel_clock args; |
||
722 | |||
723 | memset(&args, 0, sizeof(args)); |
||
724 | |||
725 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
||
1963 | serge | 726 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
727 | &crev)) |
||
728 | return; |
||
1430 | serge | 729 | |
730 | switch (frev) { |
||
731 | case 1: |
||
732 | switch (crev) { |
||
733 | case 5: |
||
734 | /* if the default dcpll clock is specified, |
||
735 | * SetPixelClock provides the dividers |
||
736 | */ |
||
737 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
||
1963 | serge | 738 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
1430 | serge | 739 | args.v5.ucPpll = ATOM_DCPLL; |
740 | break; |
||
1963 | serge | 741 | case 6: |
742 | /* if the default dcpll clock is specified, |
||
743 | * SetPixelClock provides the dividers |
||
744 | */ |
||
745 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
||
2997 | Serge | 746 | if (ASIC_IS_DCE61(rdev)) |
747 | args.v6.ucPpll = ATOM_EXT_PLL1; |
||
748 | else if (ASIC_IS_DCE6(rdev)) |
||
749 | args.v6.ucPpll = ATOM_PPLL0; |
||
750 | else |
||
3031 | serge | 751 | args.v6.ucPpll = ATOM_DCPLL; |
1963 | serge | 752 | break; |
1430 | serge | 753 | default: |
754 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
755 | return; |
||
756 | } |
||
757 | break; |
||
758 | default: |
||
759 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
760 | return; |
||
761 | } |
||
762 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
763 | } |
||
764 | |||
1963 | serge | 765 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
2160 | serge | 766 | u32 crtc_id, |
1963 | serge | 767 | int pll_id, |
768 | u32 encoder_mode, |
||
769 | u32 encoder_id, |
||
770 | u32 clock, |
||
771 | u32 ref_div, |
||
772 | u32 fb_div, |
||
773 | u32 frac_fb_div, |
||
774 | u32 post_div, |
||
775 | int bpc, |
||
776 | bool ss_enabled, |
||
777 | struct radeon_atom_ss *ss) |
||
1430 | serge | 778 | { |
1404 | serge | 779 | struct drm_device *dev = crtc->dev; |
780 | struct radeon_device *rdev = dev->dev_private; |
||
781 | u8 frev, crev; |
||
1963 | serge | 782 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
1404 | serge | 783 | union set_pixel_clock args; |
784 | |||
785 | memset(&args, 0, sizeof(args)); |
||
786 | |||
1963 | serge | 787 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
788 | &crev)) |
||
1404 | serge | 789 | return; |
790 | |||
1123 | serge | 791 | switch (frev) { |
792 | case 1: |
||
793 | switch (crev) { |
||
794 | case 1: |
||
1963 | serge | 795 | if (clock == ATOM_DISABLE) |
796 | return; |
||
797 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
||
1404 | serge | 798 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
799 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
||
800 | args.v1.ucFracFbDiv = frac_fb_div; |
||
801 | args.v1.ucPostDiv = post_div; |
||
1963 | serge | 802 | args.v1.ucPpll = pll_id; |
803 | args.v1.ucCRTC = crtc_id; |
||
1404 | serge | 804 | args.v1.ucRefDivSrc = 1; |
1123 | serge | 805 | break; |
806 | case 2: |
||
1963 | serge | 807 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
1404 | serge | 808 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
809 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
||
810 | args.v2.ucFracFbDiv = frac_fb_div; |
||
811 | args.v2.ucPostDiv = post_div; |
||
1963 | serge | 812 | args.v2.ucPpll = pll_id; |
813 | args.v2.ucCRTC = crtc_id; |
||
1404 | serge | 814 | args.v2.ucRefDivSrc = 1; |
1123 | serge | 815 | break; |
816 | case 3: |
||
1963 | serge | 817 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
1404 | serge | 818 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
819 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
||
820 | args.v3.ucFracFbDiv = frac_fb_div; |
||
821 | args.v3.ucPostDiv = post_div; |
||
1963 | serge | 822 | args.v3.ucPpll = pll_id; |
2997 | Serge | 823 | if (crtc_id == ATOM_CRTC2) |
824 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; |
||
825 | else |
||
826 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; |
||
1963 | serge | 827 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
828 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
||
829 | args.v3.ucTransmitterId = encoder_id; |
||
1430 | serge | 830 | args.v3.ucEncoderMode = encoder_mode; |
1123 | serge | 831 | break; |
1430 | serge | 832 | case 5: |
1963 | serge | 833 | args.v5.ucCRTC = crtc_id; |
834 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
||
1430 | serge | 835 | args.v5.ucRefDiv = ref_div; |
836 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
||
837 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
||
838 | args.v5.ucPostDiv = post_div; |
||
839 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
||
1963 | serge | 840 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
841 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
||
842 | switch (bpc) { |
||
843 | case 8: |
||
844 | default: |
||
845 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
||
846 | break; |
||
847 | case 10: |
||
848 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
||
849 | break; |
||
850 | } |
||
851 | args.v5.ucTransmitterID = encoder_id; |
||
1430 | serge | 852 | args.v5.ucEncoderMode = encoder_mode; |
1963 | serge | 853 | args.v5.ucPpll = pll_id; |
1430 | serge | 854 | break; |
1963 | serge | 855 | case 6: |
2160 | serge | 856 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
1963 | serge | 857 | args.v6.ucRefDiv = ref_div; |
858 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
||
859 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
||
860 | args.v6.ucPostDiv = post_div; |
||
861 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
||
862 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
||
863 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
||
864 | switch (bpc) { |
||
865 | case 8: |
||
866 | default: |
||
867 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
||
868 | break; |
||
869 | case 10: |
||
870 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; |
||
871 | break; |
||
872 | case 12: |
||
873 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; |
||
874 | break; |
||
875 | case 16: |
||
876 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
||
877 | break; |
||
878 | } |
||
879 | args.v6.ucTransmitterID = encoder_id; |
||
880 | args.v6.ucEncoderMode = encoder_mode; |
||
881 | args.v6.ucPpll = pll_id; |
||
882 | break; |
||
1123 | serge | 883 | default: |
884 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
885 | return; |
||
886 | } |
||
887 | break; |
||
888 | default: |
||
889 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
890 | return; |
||
891 | } |
||
892 | |||
893 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
894 | } |
||
895 | |||
2997 | Serge | 896 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
1430 | serge | 897 | { |
898 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
899 | struct drm_device *dev = crtc->dev; |
||
900 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 901 | struct radeon_encoder *radeon_encoder = |
902 | to_radeon_encoder(radeon_crtc->encoder); |
||
903 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
||
1963 | serge | 904 | |
2997 | Serge | 905 | radeon_crtc->bpc = 8; |
906 | radeon_crtc->ss_enabled = false; |
||
1963 | serge | 907 | |
2997 | Serge | 908 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
909 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
||
1963 | serge | 910 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
911 | struct drm_connector *connector = |
||
2997 | Serge | 912 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
1963 | serge | 913 | struct radeon_connector *radeon_connector = |
914 | to_radeon_connector(connector); |
||
915 | struct radeon_connector_atom_dig *dig_connector = |
||
916 | radeon_connector->con_priv; |
||
917 | int dp_clock; |
||
2997 | Serge | 918 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
1963 | serge | 919 | |
920 | switch (encoder_mode) { |
||
2997 | Serge | 921 | case ATOM_ENCODER_MODE_DP_MST: |
1963 | serge | 922 | case ATOM_ENCODER_MODE_DP: |
923 | /* DP/eDP */ |
||
924 | dp_clock = dig_connector->dp_clock / 10; |
||
3031 | serge | 925 | if (ASIC_IS_DCE4(rdev)) |
2997 | Serge | 926 | radeon_crtc->ss_enabled = |
927 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
||
3031 | serge | 928 | ASIC_INTERNAL_SS_ON_DP, |
929 | dp_clock); |
||
930 | else { |
||
931 | if (dp_clock == 16200) { |
||
2997 | Serge | 932 | radeon_crtc->ss_enabled = |
933 | radeon_atombios_get_ppll_ss_info(rdev, |
||
934 | &radeon_crtc->ss, |
||
3031 | serge | 935 | ATOM_DP_SS_ID2); |
2997 | Serge | 936 | if (!radeon_crtc->ss_enabled) |
937 | radeon_crtc->ss_enabled = |
||
938 | radeon_atombios_get_ppll_ss_info(rdev, |
||
939 | &radeon_crtc->ss, |
||
3031 | serge | 940 | ATOM_DP_SS_ID1); |
941 | } else |
||
2997 | Serge | 942 | radeon_crtc->ss_enabled = |
943 | radeon_atombios_get_ppll_ss_info(rdev, |
||
944 | &radeon_crtc->ss, |
||
3031 | serge | 945 | ATOM_DP_SS_ID1); |
946 | } |
||
1963 | serge | 947 | break; |
948 | case ATOM_ENCODER_MODE_LVDS: |
||
949 | if (ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 950 | radeon_crtc->ss_enabled = |
951 | radeon_atombios_get_asic_ss_info(rdev, |
||
952 | &radeon_crtc->ss, |
||
3031 | serge | 953 | dig->lcd_ss_id, |
954 | mode->clock / 10); |
||
1963 | serge | 955 | else |
2997 | Serge | 956 | radeon_crtc->ss_enabled = |
957 | radeon_atombios_get_ppll_ss_info(rdev, |
||
958 | &radeon_crtc->ss, |
||
3031 | serge | 959 | dig->lcd_ss_id); |
1963 | serge | 960 | break; |
961 | case ATOM_ENCODER_MODE_DVI: |
||
962 | if (ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 963 | radeon_crtc->ss_enabled = |
964 | radeon_atombios_get_asic_ss_info(rdev, |
||
965 | &radeon_crtc->ss, |
||
1963 | serge | 966 | ASIC_INTERNAL_SS_ON_TMDS, |
967 | mode->clock / 10); |
||
968 | break; |
||
969 | case ATOM_ENCODER_MODE_HDMI: |
||
970 | if (ASIC_IS_DCE4(rdev)) |
||
2997 | Serge | 971 | radeon_crtc->ss_enabled = |
972 | radeon_atombios_get_asic_ss_info(rdev, |
||
973 | &radeon_crtc->ss, |
||
1963 | serge | 974 | ASIC_INTERNAL_SS_ON_HDMI, |
975 | mode->clock / 10); |
||
976 | break; |
||
977 | default: |
||
978 | break; |
||
979 | } |
||
980 | } |
||
981 | |||
982 | /* adjust pixel clock as needed */ |
||
2997 | Serge | 983 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
1963 | serge | 984 | |
2997 | Serge | 985 | return true; |
986 | } |
||
987 | |||
988 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
989 | { |
||
990 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
991 | struct drm_device *dev = crtc->dev; |
||
992 | struct radeon_device *rdev = dev->dev_private; |
||
993 | struct radeon_encoder *radeon_encoder = |
||
994 | to_radeon_encoder(radeon_crtc->encoder); |
||
995 | u32 pll_clock = mode->clock; |
||
996 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
||
997 | struct radeon_pll *pll; |
||
998 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
||
999 | |||
1000 | switch (radeon_crtc->pll_id) { |
||
1001 | case ATOM_PPLL1: |
||
1002 | pll = &rdev->clock.p1pll; |
||
1003 | break; |
||
1004 | case ATOM_PPLL2: |
||
1005 | pll = &rdev->clock.p2pll; |
||
1006 | break; |
||
1007 | case ATOM_DCPLL: |
||
1008 | case ATOM_PPLL_INVALID: |
||
1009 | default: |
||
1010 | pll = &rdev->clock.dcpll; |
||
1011 | break; |
||
1012 | } |
||
1013 | |||
1014 | /* update pll params */ |
||
1015 | pll->flags = radeon_crtc->pll_flags; |
||
1016 | pll->reference_div = radeon_crtc->pll_reference_div; |
||
1017 | pll->post_div = radeon_crtc->pll_post_div; |
||
1018 | |||
1963 | serge | 1019 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1020 | /* TV seems to prefer the legacy algo on some boards */ |
||
2997 | Serge | 1021 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1022 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
||
1963 | serge | 1023 | else if (ASIC_IS_AVIVO(rdev)) |
2997 | Serge | 1024 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1025 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
||
1963 | serge | 1026 | else |
2997 | Serge | 1027 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1028 | &fb_div, &frac_fb_div, &ref_div, &post_div); |
||
1963 | serge | 1029 | |
2997 | Serge | 1030 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1031 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
||
1963 | serge | 1032 | |
1033 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
||
1034 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
||
2997 | Serge | 1035 | ref_div, fb_div, frac_fb_div, post_div, |
1036 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); |
||
1963 | serge | 1037 | |
2997 | Serge | 1038 | if (radeon_crtc->ss_enabled) { |
1963 | serge | 1039 | /* calculate ss amount and step size */ |
1040 | if (ASIC_IS_DCE4(rdev)) { |
||
1041 | u32 step_size; |
||
2997 | Serge | 1042 | u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; |
1043 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
||
1044 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
||
1963 | serge | 1045 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
2997 | Serge | 1046 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1047 | step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
||
1963 | serge | 1048 | (125 * 25 * pll->reference_freq / 100); |
1049 | else |
||
2997 | Serge | 1050 | step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
1963 | serge | 1051 | (125 * 25 * pll->reference_freq / 100); |
2997 | Serge | 1052 | radeon_crtc->ss.step = step_size; |
1963 | serge | 1053 | } |
1054 | |||
2997 | Serge | 1055 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1056 | radeon_crtc->crtc_id, &radeon_crtc->ss); |
||
1963 | serge | 1057 | } |
1058 | } |
||
1059 | |||
1060 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
||
3031 | serge | 1061 | struct drm_framebuffer *fb, |
1062 | int x, int y, int atomic) |
||
1963 | serge | 1063 | { |
1064 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1065 | struct drm_device *dev = crtc->dev; |
||
1066 | struct radeon_device *rdev = dev->dev_private; |
||
1430 | serge | 1067 | struct radeon_framebuffer *radeon_fb; |
1963 | serge | 1068 | struct drm_framebuffer *target_fb; |
1430 | serge | 1069 | struct drm_gem_object *obj; |
1070 | struct radeon_bo *rbo; |
||
1071 | uint64_t fb_location; |
||
1072 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
||
2997 | Serge | 1073 | unsigned bankw, bankh, mtaspect, tile_split; |
1963 | serge | 1074 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
1075 | u32 tmp, viewport_w, viewport_h; |
||
1430 | serge | 1076 | int r; |
1077 | |||
1078 | /* no fb bound */ |
||
1963 | serge | 1079 | if (!atomic && !crtc->fb) { |
1080 | DRM_DEBUG_KMS("No FB bound\n"); |
||
1430 | serge | 1081 | return 0; |
1082 | } |
||
1083 | |||
1963 | serge | 1084 | if (atomic) { |
1085 | radeon_fb = to_radeon_framebuffer(fb); |
||
1086 | target_fb = fb; |
||
1087 | } |
||
1088 | else { |
||
3031 | serge | 1089 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1963 | serge | 1090 | target_fb = crtc->fb; |
1091 | } |
||
1430 | serge | 1092 | |
1963 | serge | 1093 | /* If atomic, assume fb object is pinned & idle & fenced and |
1094 | * just update base pointers |
||
1095 | */ |
||
1430 | serge | 1096 | obj = radeon_fb->obj; |
1963 | serge | 1097 | rbo = gem_to_radeon_bo(obj); |
1430 | serge | 1098 | r = radeon_bo_reserve(rbo, false); |
1099 | if (unlikely(r != 0)) |
||
1100 | return r; |
||
1963 | serge | 1101 | |
1102 | if (atomic) |
||
1103 | fb_location = radeon_bo_gpu_offset(rbo); |
||
1104 | else { |
||
3031 | serge | 1105 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1106 | if (unlikely(r != 0)) { |
||
1107 | radeon_bo_unreserve(rbo); |
||
1108 | return -EINVAL; |
||
1109 | } |
||
1430 | serge | 1110 | } |
1963 | serge | 1111 | |
1430 | serge | 1112 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1113 | radeon_bo_unreserve(rbo); |
||
1114 | |||
1963 | serge | 1115 | switch (target_fb->bits_per_pixel) { |
1430 | serge | 1116 | case 8: |
1117 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
||
1118 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
||
1119 | break; |
||
1120 | case 15: |
||
1121 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
||
1122 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
||
1123 | break; |
||
1124 | case 16: |
||
1125 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
||
1126 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
||
1963 | serge | 1127 | #ifdef __BIG_ENDIAN |
1128 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
||
1129 | #endif |
||
1430 | serge | 1130 | break; |
1131 | case 24: |
||
1132 | case 32: |
||
1133 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
||
1134 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
||
1963 | serge | 1135 | #ifdef __BIG_ENDIAN |
1136 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
||
1137 | #endif |
||
1430 | serge | 1138 | break; |
1139 | default: |
||
1140 | DRM_ERROR("Unsupported screen depth %d\n", |
||
1963 | serge | 1141 | target_fb->bits_per_pixel); |
1430 | serge | 1142 | return -EINVAL; |
1143 | } |
||
1144 | |||
2997 | Serge | 1145 | if (tiling_flags & RADEON_TILING_MACRO) { |
1146 | if (rdev->family >= CHIP_TAHITI) |
||
1147 | tmp = rdev->config.si.tile_config; |
||
1148 | else if (rdev->family >= CHIP_CAYMAN) |
||
1149 | tmp = rdev->config.cayman.tile_config; |
||
1150 | else |
||
1151 | tmp = rdev->config.evergreen.tile_config; |
||
1152 | |||
1153 | switch ((tmp & 0xf0) >> 4) { |
||
1154 | case 0: /* 4 banks */ |
||
1155 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); |
||
1156 | break; |
||
1157 | case 1: /* 8 banks */ |
||
1158 | default: |
||
1159 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); |
||
1160 | break; |
||
1161 | case 2: /* 16 banks */ |
||
1162 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
||
1163 | break; |
||
1164 | } |
||
1165 | |||
1963 | serge | 1166 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
2997 | Serge | 1167 | |
1168 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
||
1169 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
||
1170 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
||
1171 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
||
1172 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
||
1173 | } else if (tiling_flags & RADEON_TILING_MICRO) |
||
1963 | serge | 1174 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1175 | |||
2997 | Serge | 1176 | if ((rdev->family == CHIP_TAHITI) || |
1177 | (rdev->family == CHIP_PITCAIRN)) |
||
1178 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); |
||
1179 | else if (rdev->family == CHIP_VERDE) |
||
1180 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
||
1181 | |||
1430 | serge | 1182 | switch (radeon_crtc->crtc_id) { |
1183 | case 0: |
||
1184 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
||
1185 | break; |
||
1186 | case 1: |
||
1187 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
||
1188 | break; |
||
1189 | case 2: |
||
1190 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
||
1191 | break; |
||
1192 | case 3: |
||
1193 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
||
1194 | break; |
||
1195 | case 4: |
||
1196 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
||
1197 | break; |
||
1198 | case 5: |
||
1199 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
||
1200 | break; |
||
1201 | default: |
||
1202 | break; |
||
1203 | } |
||
1204 | |||
1205 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
||
1206 | upper_32_bits(fb_location)); |
||
1207 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
||
1208 | upper_32_bits(fb_location)); |
||
1209 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
||
1210 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
||
1211 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
||
1212 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
||
1213 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
||
1963 | serge | 1214 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
1430 | serge | 1215 | |
1216 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
||
1217 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
||
1218 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
||
1219 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
||
1963 | serge | 1220 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1221 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
||
1430 | serge | 1222 | |
2997 | Serge | 1223 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1430 | serge | 1224 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1225 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
||
1226 | |||
1227 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
||
2997 | Serge | 1228 | target_fb->height); |
1430 | serge | 1229 | x &= ~3; |
1230 | y &= ~1; |
||
1231 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
||
1232 | (x << 16) | y); |
||
1963 | serge | 1233 | viewport_w = crtc->mode.hdisplay; |
1234 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
||
1430 | serge | 1235 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1963 | serge | 1236 | (viewport_w << 16) | viewport_h); |
1430 | serge | 1237 | |
1963 | serge | 1238 | /* pageflip setup */ |
1239 | /* make sure flip is at vb rather than hb */ |
||
1240 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
||
1241 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
||
1242 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
||
1430 | serge | 1243 | |
1963 | serge | 1244 | /* set pageflip to happen anywhere in vblank interval */ |
1245 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
||
1246 | |||
1247 | if (!atomic && fb && fb != crtc->fb) { |
||
1248 | radeon_fb = to_radeon_framebuffer(fb); |
||
1249 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
||
1430 | serge | 1250 | r = radeon_bo_reserve(rbo, false); |
1251 | if (unlikely(r != 0)) |
||
1252 | return r; |
||
1253 | radeon_bo_unpin(rbo); |
||
1254 | radeon_bo_unreserve(rbo); |
||
1255 | } |
||
1256 | |||
1257 | /* Bytes per pixel may have changed */ |
||
1258 | radeon_bandwidth_update(rdev); |
||
1259 | |||
1260 | return 0; |
||
1261 | } |
||
1262 | |||
1963 | serge | 1263 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1264 | struct drm_framebuffer *fb, |
||
1265 | int x, int y, int atomic) |
||
1123 | serge | 1266 | { |
1267 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1268 | struct drm_device *dev = crtc->dev; |
||
1269 | struct radeon_device *rdev = dev->dev_private; |
||
1270 | struct radeon_framebuffer *radeon_fb; |
||
1271 | struct drm_gem_object *obj; |
||
1321 | serge | 1272 | struct radeon_bo *rbo; |
1963 | serge | 1273 | struct drm_framebuffer *target_fb; |
1123 | serge | 1274 | uint64_t fb_location; |
1179 | serge | 1275 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1963 | serge | 1276 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
1277 | u32 tmp, viewport_w, viewport_h; |
||
1321 | serge | 1278 | int r; |
1123 | serge | 1279 | |
1321 | serge | 1280 | /* no fb bound */ |
1963 | serge | 1281 | if (!atomic && !crtc->fb) { |
1282 | DRM_DEBUG_KMS("No FB bound\n"); |
||
1321 | serge | 1283 | return 0; |
1284 | } |
||
1123 | serge | 1285 | |
1963 | serge | 1286 | if (atomic) { |
1287 | radeon_fb = to_radeon_framebuffer(fb); |
||
1288 | target_fb = fb; |
||
1289 | } |
||
1290 | else { |
||
3031 | serge | 1291 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1963 | serge | 1292 | target_fb = crtc->fb; |
1293 | } |
||
1123 | serge | 1294 | |
1295 | obj = radeon_fb->obj; |
||
1963 | serge | 1296 | rbo = gem_to_radeon_bo(obj); |
1404 | serge | 1297 | r = radeon_bo_reserve(rbo, false); |
1298 | if (unlikely(r != 0)) |
||
1299 | return r; |
||
1963 | serge | 1300 | |
1301 | /* If atomic, assume fb object is pinned & idle & fenced and |
||
1302 | * just update base pointers |
||
1303 | */ |
||
1304 | if (atomic) |
||
1305 | fb_location = radeon_bo_gpu_offset(rbo); |
||
1306 | else { |
||
3031 | serge | 1307 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
1308 | if (unlikely(r != 0)) { |
||
1309 | radeon_bo_unreserve(rbo); |
||
1310 | return -EINVAL; |
||
1311 | } |
||
1404 | serge | 1312 | } |
1313 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
||
1314 | radeon_bo_unreserve(rbo); |
||
1123 | serge | 1315 | |
1963 | serge | 1316 | switch (target_fb->bits_per_pixel) { |
1179 | serge | 1317 | case 8: |
1318 | fb_format = |
||
1319 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
||
1320 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
||
1321 | break; |
||
1123 | serge | 1322 | case 15: |
1323 | fb_format = |
||
1324 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
1325 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
||
1326 | break; |
||
1327 | case 16: |
||
1328 | fb_format = |
||
1329 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
1330 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
||
1963 | serge | 1331 | #ifdef __BIG_ENDIAN |
1332 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
||
1333 | #endif |
||
1123 | serge | 1334 | break; |
1335 | case 24: |
||
1336 | case 32: |
||
1337 | fb_format = |
||
1338 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
||
1339 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
||
1963 | serge | 1340 | #ifdef __BIG_ENDIAN |
1341 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
||
1342 | #endif |
||
1123 | serge | 1343 | break; |
1344 | default: |
||
1345 | DRM_ERROR("Unsupported screen depth %d\n", |
||
1963 | serge | 1346 | target_fb->bits_per_pixel); |
1123 | serge | 1347 | return -EINVAL; |
1348 | } |
||
1349 | |||
1963 | serge | 1350 | if (rdev->family >= CHIP_R600) { |
1351 | if (tiling_flags & RADEON_TILING_MACRO) |
||
1352 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
||
1353 | else if (tiling_flags & RADEON_TILING_MICRO) |
||
1354 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
||
1355 | } else { |
||
3031 | serge | 1356 | if (tiling_flags & RADEON_TILING_MACRO) |
1357 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
||
1179 | serge | 1358 | |
3031 | serge | 1359 | if (tiling_flags & RADEON_TILING_MICRO) |
1360 | fb_format |= AVIVO_D1GRPH_TILED; |
||
1963 | serge | 1361 | } |
1179 | serge | 1362 | |
1123 | serge | 1363 | if (radeon_crtc->crtc_id == 0) |
1364 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
||
1365 | else |
||
1366 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
||
1268 | serge | 1367 | |
1368 | if (rdev->family >= CHIP_RV770) { |
||
1369 | if (radeon_crtc->crtc_id) { |
||
1963 | serge | 1370 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1371 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
||
1268 | serge | 1372 | } else { |
1963 | serge | 1373 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1374 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
||
1268 | serge | 1375 | } |
1376 | } |
||
1123 | serge | 1377 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1378 | (u32) fb_location); |
||
1379 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
||
1380 | radeon_crtc->crtc_offset, (u32) fb_location); |
||
1381 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
||
1963 | serge | 1382 | if (rdev->family >= CHIP_R600) |
1383 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
||
1123 | serge | 1384 | |
1385 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
||
1386 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
||
1387 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
||
1388 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
||
1963 | serge | 1389 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1390 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
||
1123 | serge | 1391 | |
2997 | Serge | 1392 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1123 | serge | 1393 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1394 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
||
1395 | |||
1396 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
||
2997 | Serge | 1397 | target_fb->height); |
1123 | serge | 1398 | x &= ~3; |
1399 | y &= ~1; |
||
1400 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
||
1401 | (x << 16) | y); |
||
1963 | serge | 1402 | viewport_w = crtc->mode.hdisplay; |
1403 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
||
1123 | serge | 1404 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
1963 | serge | 1405 | (viewport_w << 16) | viewport_h); |
1123 | serge | 1406 | |
1963 | serge | 1407 | /* pageflip setup */ |
1408 | /* make sure flip is at vb rather than hb */ |
||
1409 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
||
1410 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
||
1411 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
||
1123 | serge | 1412 | |
1963 | serge | 1413 | /* set pageflip to happen anywhere in vblank interval */ |
1414 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
||
1415 | |||
1416 | if (!atomic && fb && fb != crtc->fb) { |
||
1417 | radeon_fb = to_radeon_framebuffer(fb); |
||
1418 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
||
1404 | serge | 1419 | r = radeon_bo_reserve(rbo, false); |
1420 | if (unlikely(r != 0)) |
||
1421 | return r; |
||
1422 | radeon_bo_unpin(rbo); |
||
1423 | radeon_bo_unreserve(rbo); |
||
1424 | } |
||
1246 | serge | 1425 | |
1268 | serge | 1426 | /* Bytes per pixel may have changed */ |
1427 | radeon_bandwidth_update(rdev); |
||
1428 | |||
1123 | serge | 1429 | return 0; |
1430 | } |
||
1431 | |||
1404 | serge | 1432 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1433 | struct drm_framebuffer *old_fb) |
||
1434 | { |
||
1435 | struct drm_device *dev = crtc->dev; |
||
1436 | struct radeon_device *rdev = dev->dev_private; |
||
1437 | |||
1430 | serge | 1438 | if (ASIC_IS_DCE4(rdev)) |
1963 | serge | 1439 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1430 | serge | 1440 | else if (ASIC_IS_AVIVO(rdev)) |
1963 | serge | 1441 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1404 | serge | 1442 | else |
1963 | serge | 1443 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
1404 | serge | 1444 | } |
1445 | |||
1963 | serge | 1446 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
1447 | struct drm_framebuffer *fb, |
||
1448 | int x, int y, enum mode_set_atomic state) |
||
1449 | { |
||
1450 | struct drm_device *dev = crtc->dev; |
||
1451 | struct radeon_device *rdev = dev->dev_private; |
||
1452 | |||
1453 | if (ASIC_IS_DCE4(rdev)) |
||
1454 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
||
1455 | else if (ASIC_IS_AVIVO(rdev)) |
||
1456 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
||
1457 | else |
||
1458 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
||
1459 | } |
||
1460 | |||
1404 | serge | 1461 | /* properly set additional regs when using atombios */ |
1462 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
||
1463 | { |
||
1464 | struct drm_device *dev = crtc->dev; |
||
1465 | struct radeon_device *rdev = dev->dev_private; |
||
1466 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1467 | u32 disp_merge_cntl; |
||
1468 | |||
1469 | switch (radeon_crtc->crtc_id) { |
||
1470 | case 0: |
||
1471 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
||
1472 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
||
1473 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
||
1474 | break; |
||
1475 | case 1: |
||
1476 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
||
1477 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
||
1478 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
||
1479 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
||
1480 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
||
1481 | break; |
||
1482 | } |
||
1483 | } |
||
1484 | |||
2997 | Serge | 1485 | /** |
1486 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use |
||
1487 | * |
||
1488 | * @crtc: drm crtc |
||
1489 | * |
||
1490 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. |
||
1491 | */ |
||
1492 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) |
||
1493 | { |
||
1494 | struct drm_device *dev = crtc->dev; |
||
1495 | struct drm_crtc *test_crtc; |
||
1496 | struct radeon_crtc *test_radeon_crtc; |
||
1497 | u32 pll_in_use = 0; |
||
1498 | |||
1499 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
||
1500 | if (crtc == test_crtc) |
||
1501 | continue; |
||
1502 | |||
1503 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
||
1504 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
||
1505 | pll_in_use |= (1 << test_radeon_crtc->pll_id); |
||
1506 | } |
||
1507 | return pll_in_use; |
||
1508 | } |
||
1509 | |||
1510 | /** |
||
1511 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP |
||
1512 | * |
||
1513 | * @crtc: drm crtc |
||
1514 | * |
||
1515 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is |
||
1516 | * also in DP mode. For DP, a single PPLL can be used for all DP |
||
1517 | * crtcs/encoders. |
||
1518 | */ |
||
1519 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) |
||
1520 | { |
||
1521 | struct drm_device *dev = crtc->dev; |
||
1522 | struct drm_crtc *test_crtc; |
||
1523 | struct radeon_crtc *test_radeon_crtc; |
||
1524 | |||
1525 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
||
1526 | if (crtc == test_crtc) |
||
1527 | continue; |
||
1528 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
||
1529 | if (test_radeon_crtc->encoder && |
||
1530 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
||
1531 | /* for DP use the same PLL for all */ |
||
1532 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
||
1533 | return test_radeon_crtc->pll_id; |
||
1534 | } |
||
1535 | } |
||
1536 | return ATOM_PPLL_INVALID; |
||
1537 | } |
||
1538 | |||
1539 | /** |
||
1540 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc |
||
1541 | * |
||
1542 | * @crtc: drm crtc |
||
1543 | * @encoder: drm encoder |
||
1544 | * |
||
1545 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can |
||
1546 | * be shared (i.e., same clock). |
||
1547 | */ |
||
1548 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
||
1549 | { |
||
1550 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1551 | struct drm_device *dev = crtc->dev; |
||
1552 | struct drm_crtc *test_crtc; |
||
1553 | struct radeon_crtc *test_radeon_crtc; |
||
1554 | u32 adjusted_clock, test_adjusted_clock; |
||
1555 | |||
1556 | adjusted_clock = radeon_crtc->adjusted_clock; |
||
1557 | |||
1558 | if (adjusted_clock == 0) |
||
1559 | return ATOM_PPLL_INVALID; |
||
1560 | |||
1561 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
||
1562 | if (crtc == test_crtc) |
||
1563 | continue; |
||
1564 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
||
1565 | if (test_radeon_crtc->encoder && |
||
1566 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { |
||
1567 | /* check if we are already driving this connector with another crtc */ |
||
1568 | if (test_radeon_crtc->connector == radeon_crtc->connector) { |
||
1569 | /* if we are, return that pll */ |
||
1570 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) |
||
1571 | return test_radeon_crtc->pll_id; |
||
1572 | } |
||
1573 | /* for non-DP check the clock */ |
||
1574 | test_adjusted_clock = test_radeon_crtc->adjusted_clock; |
||
1575 | if ((crtc->mode.clock == test_crtc->mode.clock) && |
||
1576 | (adjusted_clock == test_adjusted_clock) && |
||
1577 | (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && |
||
1578 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) |
||
1579 | return test_radeon_crtc->pll_id; |
||
1580 | } |
||
1581 | } |
||
1582 | return ATOM_PPLL_INVALID; |
||
1583 | } |
||
1584 | |||
1585 | /** |
||
1586 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. |
||
1587 | * |
||
1588 | * @crtc: drm crtc |
||
1589 | * |
||
1590 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
||
1591 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
||
1592 | * monitors a dedicated PPLL must be used. If a particular board has |
||
1593 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
||
1594 | * as there is no need to program the PLL itself. If we are not able to |
||
1595 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
||
1596 | * avoid messing up an existing monitor. |
||
1597 | * |
||
1598 | * Asic specific PLL information |
||
1599 | * |
||
1600 | * DCE 6.1 |
||
1601 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) |
||
1602 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) |
||
1603 | * |
||
1604 | * DCE 6.0 |
||
1605 | * - PPLL0 is available to all UNIPHY (DP only) |
||
1606 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
||
1607 | * |
||
1608 | * DCE 5.0 |
||
1609 | * - DCPLL is available to all UNIPHY (DP only) |
||
1610 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
||
1611 | * |
||
1612 | * DCE 3.0/4.0/4.1 |
||
1613 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
||
1614 | * |
||
1615 | */ |
||
1430 | serge | 1616 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1617 | { |
||
1618 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1619 | struct drm_device *dev = crtc->dev; |
||
1620 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 1621 | struct radeon_encoder *radeon_encoder = |
1622 | to_radeon_encoder(radeon_crtc->encoder); |
||
1623 | u32 pll_in_use; |
||
1624 | int pll; |
||
1430 | serge | 1625 | |
2997 | Serge | 1626 | if (ASIC_IS_DCE61(rdev)) { |
3031 | serge | 1627 | struct radeon_encoder_atom_dig *dig = |
2997 | Serge | 1628 | radeon_encoder->enc_priv; |
1629 | |||
1630 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
||
1631 | (dig->linkb == false)) |
||
1632 | /* UNIPHY A uses PPLL2 */ |
||
3031 | serge | 1633 | return ATOM_PPLL2; |
2997 | Serge | 1634 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
1635 | /* UNIPHY B/C/D/E/F */ |
||
1636 | if (rdev->clock.dp_extclk) |
||
1637 | /* skip PPLL programming if using ext clock */ |
||
1638 | return ATOM_PPLL_INVALID; |
||
1639 | else { |
||
1640 | /* use the same PPLL for all DP monitors */ |
||
1641 | pll = radeon_get_shared_dp_ppll(crtc); |
||
1642 | if (pll != ATOM_PPLL_INVALID) |
||
1643 | return pll; |
||
1644 | } |
||
1645 | } else { |
||
1646 | /* use the same PPLL for all monitors with the same clock */ |
||
1647 | pll = radeon_get_shared_nondp_ppll(crtc); |
||
1648 | if (pll != ATOM_PPLL_INVALID) |
||
1649 | return pll; |
||
1650 | } |
||
1651 | /* UNIPHY B/C/D/E/F */ |
||
1652 | pll_in_use = radeon_get_pll_use_mask(crtc); |
||
1653 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
||
1654 | return ATOM_PPLL0; |
||
1655 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
||
3031 | serge | 1656 | return ATOM_PPLL1; |
2997 | Serge | 1657 | DRM_ERROR("unable to allocate a PPLL\n"); |
1658 | return ATOM_PPLL_INVALID; |
||
1659 | } else if (ASIC_IS_DCE4(rdev)) { |
||
3031 | serge | 1660 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1661 | * depending on the asic: |
||
1662 | * DCE4: PPLL or ext clock |
||
2997 | Serge | 1663 | * DCE5: PPLL, DCPLL, or ext clock |
1664 | * DCE6: PPLL, PPLL0, or ext clock |
||
3031 | serge | 1665 | * |
1666 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
||
1667 | * PPLL/DCPLL programming and only program the DP DTO for the |
||
1668 | * crtc virtual pixel clock. |
||
1669 | */ |
||
2997 | Serge | 1670 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { |
3031 | serge | 1671 | if (rdev->clock.dp_extclk) |
2997 | Serge | 1672 | /* skip PPLL programming if using ext clock */ |
3031 | serge | 1673 | return ATOM_PPLL_INVALID; |
1674 | else if (ASIC_IS_DCE6(rdev)) |
||
2997 | Serge | 1675 | /* use PPLL0 for all DP */ |
3031 | serge | 1676 | return ATOM_PPLL0; |
1677 | else if (ASIC_IS_DCE5(rdev)) |
||
2997 | Serge | 1678 | /* use DCPLL for all DP */ |
3031 | serge | 1679 | return ATOM_DCPLL; |
2997 | Serge | 1680 | else { |
1681 | /* use the same PPLL for all DP monitors */ |
||
1682 | pll = radeon_get_shared_dp_ppll(crtc); |
||
1683 | if (pll != ATOM_PPLL_INVALID) |
||
1684 | return pll; |
||
3031 | serge | 1685 | } |
2997 | Serge | 1686 | } else { |
1687 | /* use the same PPLL for all monitors with the same clock */ |
||
1688 | pll = radeon_get_shared_nondp_ppll(crtc); |
||
1689 | if (pll != ATOM_PPLL_INVALID) |
||
1690 | return pll; |
||
3031 | serge | 1691 | } |
2997 | Serge | 1692 | /* all other cases */ |
1693 | pll_in_use = radeon_get_pll_use_mask(crtc); |
||
1694 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
||
1695 | return ATOM_PPLL1; |
||
1696 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
||
1697 | return ATOM_PPLL2; |
||
1698 | DRM_ERROR("unable to allocate a PPLL\n"); |
||
1699 | return ATOM_PPLL_INVALID; |
||
3031 | serge | 1700 | } else { |
3120 | serge | 1701 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ |
1702 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
||
1703 | * the matching btw pll and crtc is done through |
||
1704 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the |
||
1705 | * pll (1 or 2) to select which register to write. ie if using |
||
1706 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 |
||
1707 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to |
||
1708 | * choose which value to write. Which is reverse order from |
||
1709 | * register logic. So only case that works is when pllid is |
||
1710 | * same as crtcid or when both pll and crtc are enabled and |
||
1711 | * both use same clock. |
||
1712 | * |
||
1713 | * So just return crtc id as if crtc and pll were hard linked |
||
1714 | * together even if they aren't |
||
3031 | serge | 1715 | */ |
1430 | serge | 1716 | return radeon_crtc->crtc_id; |
2997 | Serge | 1717 | } |
1718 | } |
||
1430 | serge | 1719 | |
2997 | Serge | 1720 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
1721 | { |
||
1722 | /* always set DCPLL */ |
||
1723 | if (ASIC_IS_DCE6(rdev)) |
||
1724 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
||
1725 | else if (ASIC_IS_DCE4(rdev)) { |
||
1726 | struct radeon_atom_ss ss; |
||
1727 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
||
1728 | ASIC_INTERNAL_SS_ON_DCPLL, |
||
1729 | rdev->clock.default_dispclk); |
||
1730 | if (ss_enabled) |
||
1731 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
||
1732 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
||
1733 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
||
1734 | if (ss_enabled) |
||
1735 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
||
1736 | } |
||
1737 | |||
1430 | serge | 1738 | } |
1739 | |||
1123 | serge | 1740 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1741 | struct drm_display_mode *mode, |
||
1742 | struct drm_display_mode *adjusted_mode, |
||
1743 | int x, int y, struct drm_framebuffer *old_fb) |
||
1744 | { |
||
1745 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1746 | struct drm_device *dev = crtc->dev; |
||
1747 | struct radeon_device *rdev = dev->dev_private; |
||
2997 | Serge | 1748 | struct radeon_encoder *radeon_encoder = |
1749 | to_radeon_encoder(radeon_crtc->encoder); |
||
1963 | serge | 1750 | bool is_tvcv = false; |
1123 | serge | 1751 | |
3031 | serge | 1752 | if (radeon_encoder->active_device & |
1753 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
||
1754 | is_tvcv = true; |
||
1123 | serge | 1755 | |
1756 | atombios_crtc_set_pll(crtc, adjusted_mode); |
||
1430 | serge | 1757 | |
1758 | if (ASIC_IS_DCE4(rdev)) |
||
1759 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
||
1963 | serge | 1760 | else if (ASIC_IS_AVIVO(rdev)) { |
1761 | if (is_tvcv) |
||
1762 | atombios_crtc_set_timing(crtc, adjusted_mode); |
||
1763 | else |
||
1764 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
||
1765 | } else { |
||
1430 | serge | 1766 | atombios_crtc_set_timing(crtc, adjusted_mode); |
1268 | serge | 1767 | if (radeon_crtc->crtc_id == 0) |
1768 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
||
1404 | serge | 1769 | radeon_legacy_atom_fixup(crtc); |
1123 | serge | 1770 | } |
1430 | serge | 1771 | atombios_crtc_set_base(crtc, x, y, old_fb); |
1179 | serge | 1772 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1773 | atombios_scaler_setup(crtc); |
||
1123 | serge | 1774 | return 0; |
1775 | } |
||
1776 | |||
1777 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
||
2997 | Serge | 1778 | const struct drm_display_mode *mode, |
1123 | serge | 1779 | struct drm_display_mode *adjusted_mode) |
1780 | { |
||
2997 | Serge | 1781 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1963 | serge | 1782 | struct drm_device *dev = crtc->dev; |
2997 | Serge | 1783 | struct drm_encoder *encoder; |
1963 | serge | 1784 | |
2997 | Serge | 1785 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ |
1786 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
1787 | if (encoder->crtc == crtc) { |
||
1788 | radeon_crtc->encoder = encoder; |
||
1789 | radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); |
||
1790 | break; |
||
1791 | } |
||
1792 | } |
||
1793 | if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { |
||
1794 | radeon_crtc->encoder = NULL; |
||
1795 | radeon_crtc->connector = NULL; |
||
1796 | return false; |
||
1797 | } |
||
1179 | serge | 1798 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1799 | return false; |
||
2997 | Serge | 1800 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
1801 | return false; |
||
1802 | /* pick pll */ |
||
1803 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
||
1804 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
||
1805 | if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && |
||
1806 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) |
||
1807 | return false; |
||
1808 | |||
1123 | serge | 1809 | return true; |
1810 | } |
||
1811 | |||
1812 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
||
1813 | { |
||
2997 | Serge | 1814 | struct drm_device *dev = crtc->dev; |
1815 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | serge | 1816 | |
2997 | Serge | 1817 | /* disable crtc pair power gating before programming */ |
1818 | if (ASIC_IS_DCE6(rdev)) |
||
1819 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
||
1820 | |||
1430 | serge | 1821 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
1123 | serge | 1822 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1823 | } |
||
1824 | |||
1825 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
||
1826 | { |
||
1827 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
||
1430 | serge | 1828 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
1123 | serge | 1829 | } |
1830 | |||
1963 | serge | 1831 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
1832 | { |
||
1833 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
2997 | Serge | 1834 | struct drm_device *dev = crtc->dev; |
1835 | struct radeon_device *rdev = dev->dev_private; |
||
1963 | serge | 1836 | struct radeon_atom_ss ss; |
2997 | Serge | 1837 | int i; |
1963 | serge | 1838 | |
1839 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
||
3764 | Serge | 1840 | if (ASIC_IS_DCE6(rdev)) |
1841 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
||
1963 | serge | 1842 | |
2997 | Serge | 1843 | for (i = 0; i < rdev->num_crtc; i++) { |
1844 | if (rdev->mode_info.crtcs[i] && |
||
1845 | rdev->mode_info.crtcs[i]->enabled && |
||
1846 | i != radeon_crtc->crtc_id && |
||
1847 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { |
||
1848 | /* one other crtc is using this pll don't turn |
||
1849 | * off the pll |
||
1850 | */ |
||
1851 | goto done; |
||
1852 | } |
||
1853 | } |
||
1854 | |||
1963 | serge | 1855 | switch (radeon_crtc->pll_id) { |
1856 | case ATOM_PPLL1: |
||
1857 | case ATOM_PPLL2: |
||
1858 | /* disable the ppll */ |
||
1859 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
||
1860 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
||
1861 | break; |
||
2997 | Serge | 1862 | case ATOM_PPLL0: |
1863 | /* disable the ppll */ |
||
1864 | if (ASIC_IS_DCE61(rdev)) |
||
1865 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
||
1866 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
||
1867 | break; |
||
1963 | serge | 1868 | default: |
1869 | break; |
||
1870 | } |
||
2997 | Serge | 1871 | done: |
1872 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
||
1873 | radeon_crtc->adjusted_clock = 0; |
||
1874 | radeon_crtc->encoder = NULL; |
||
1875 | radeon_crtc->connector = NULL; |
||
1963 | serge | 1876 | } |
1877 | |||
1123 | serge | 1878 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
1879 | .dpms = atombios_crtc_dpms, |
||
1880 | .mode_fixup = atombios_crtc_mode_fixup, |
||
1881 | .mode_set = atombios_crtc_mode_set, |
||
1882 | .mode_set_base = atombios_crtc_set_base, |
||
1963 | serge | 1883 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
1123 | serge | 1884 | .prepare = atombios_crtc_prepare, |
1885 | .commit = atombios_crtc_commit, |
||
1221 | serge | 1886 | .load_lut = radeon_crtc_load_lut, |
1963 | serge | 1887 | .disable = atombios_crtc_disable, |
1123 | serge | 1888 | }; |
1889 | |||
1890 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
1891 | struct radeon_crtc *radeon_crtc) |
||
1892 | { |
||
1430 | serge | 1893 | struct radeon_device *rdev = dev->dev_private; |
1894 | |||
1895 | if (ASIC_IS_DCE4(rdev)) { |
||
1896 | switch (radeon_crtc->crtc_id) { |
||
1897 | case 0: |
||
1898 | default: |
||
1899 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
||
1900 | break; |
||
1901 | case 1: |
||
1902 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
||
1903 | break; |
||
1904 | case 2: |
||
1905 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
||
1906 | break; |
||
1907 | case 3: |
||
1908 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
||
1909 | break; |
||
1910 | case 4: |
||
1911 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
||
1912 | break; |
||
1913 | case 5: |
||
1914 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
||
1915 | break; |
||
1916 | } |
||
1917 | } else { |
||
3031 | serge | 1918 | if (radeon_crtc->crtc_id == 1) |
1919 | radeon_crtc->crtc_offset = |
||
1920 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
||
1430 | serge | 1921 | else |
1922 | radeon_crtc->crtc_offset = 0; |
||
1923 | } |
||
2997 | Serge | 1924 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
1925 | radeon_crtc->adjusted_clock = 0; |
||
1926 | radeon_crtc->encoder = NULL; |
||
1927 | radeon_crtc->connector = NULL; |
||
1123 | serge | 1928 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1929 | }>><>><>><>><>><>><>><>><>><>><>><>>><>><>>=> |