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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1123 | serge | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: Dave Airlie |
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| 24 | * Alex Deucher |
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| 25 | */ |
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| 1179 | serge | 26 | #include |
| 27 | #include |
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| 28 | #include |
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| 1123 | serge | 29 | #include "radeon_fixed.h" |
| 30 | #include "radeon.h" |
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| 31 | #include "atom.h" |
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| 32 | #include "atom-bits.h" |
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| 33 | |||
| 1179 | serge | 34 | /* evil but including atombios.h is much worse */ |
| 35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
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| 36 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
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| 37 | int32_t *pixel_clock); |
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| 38 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
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| 39 | struct drm_display_mode *mode, |
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| 40 | struct drm_display_mode *adjusted_mode) |
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| 41 | { |
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| 42 | struct drm_device *dev = crtc->dev; |
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| 43 | struct radeon_device *rdev = dev->dev_private; |
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| 44 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 45 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
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| 46 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
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| 47 | int a1, a2; |
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| 48 | |||
| 49 | memset(&args, 0, sizeof(args)); |
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| 50 | |||
| 51 | args.usOverscanRight = 0; |
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| 52 | args.usOverscanLeft = 0; |
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| 53 | args.usOverscanBottom = 0; |
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| 54 | args.usOverscanTop = 0; |
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| 55 | args.ucCRTC = radeon_crtc->crtc_id; |
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| 56 | |||
| 57 | switch (radeon_crtc->rmx_type) { |
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| 58 | case RMX_CENTER: |
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| 59 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
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| 60 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
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| 61 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
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| 62 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
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| 63 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 64 | break; |
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| 65 | case RMX_ASPECT: |
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| 66 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
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| 67 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
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| 68 | |||
| 69 | if (a1 > a2) { |
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| 70 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
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| 71 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
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| 72 | } else if (a2 > a1) { |
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| 73 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
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| 74 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
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| 75 | } |
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| 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 77 | break; |
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| 78 | case RMX_FULL: |
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| 79 | default: |
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| 80 | args.usOverscanRight = 0; |
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| 81 | args.usOverscanLeft = 0; |
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| 82 | args.usOverscanBottom = 0; |
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| 83 | args.usOverscanTop = 0; |
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| 84 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 85 | break; |
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| 86 | } |
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| 87 | } |
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| 88 | |||
| 89 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
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| 90 | { |
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| 91 | struct drm_device *dev = crtc->dev; |
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| 92 | struct radeon_device *rdev = dev->dev_private; |
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| 93 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 94 | ENABLE_SCALER_PS_ALLOCATION args; |
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| 95 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
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| 96 | |||
| 97 | /* fixme - fill in enc_priv for atom dac */ |
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| 98 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
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| 99 | bool is_tv = false, is_cv = false; |
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| 100 | struct drm_encoder *encoder; |
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| 101 | |||
| 102 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
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| 103 | return; |
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| 104 | |||
| 105 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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| 106 | /* find tv std */ |
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| 107 | if (encoder->crtc == crtc) { |
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| 108 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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| 109 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
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| 110 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
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| 111 | tv_std = tv_dac->tv_std; |
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| 112 | is_tv = true; |
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| 113 | } |
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| 114 | } |
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| 115 | } |
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| 116 | |||
| 117 | memset(&args, 0, sizeof(args)); |
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| 118 | |||
| 119 | args.ucScaler = radeon_crtc->crtc_id; |
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| 120 | |||
| 121 | if (is_tv) { |
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| 122 | switch (tv_std) { |
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| 123 | case TV_STD_NTSC: |
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| 124 | default: |
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| 125 | args.ucTVStandard = ATOM_TV_NTSC; |
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| 126 | break; |
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| 127 | case TV_STD_PAL: |
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| 128 | args.ucTVStandard = ATOM_TV_PAL; |
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| 129 | break; |
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| 130 | case TV_STD_PAL_M: |
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| 131 | args.ucTVStandard = ATOM_TV_PALM; |
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| 132 | break; |
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| 133 | case TV_STD_PAL_60: |
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| 134 | args.ucTVStandard = ATOM_TV_PAL60; |
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| 135 | break; |
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| 136 | case TV_STD_NTSC_J: |
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| 137 | args.ucTVStandard = ATOM_TV_NTSCJ; |
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| 138 | break; |
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| 139 | case TV_STD_SCART_PAL: |
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| 140 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
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| 141 | break; |
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| 142 | case TV_STD_SECAM: |
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| 143 | args.ucTVStandard = ATOM_TV_SECAM; |
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| 144 | break; |
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| 145 | case TV_STD_PAL_CN: |
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| 146 | args.ucTVStandard = ATOM_TV_PALCN; |
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| 147 | break; |
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| 148 | } |
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| 149 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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| 150 | } else if (is_cv) { |
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| 151 | args.ucTVStandard = ATOM_TV_CV; |
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| 152 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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| 153 | } else { |
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| 154 | switch (radeon_crtc->rmx_type) { |
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| 155 | case RMX_FULL: |
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| 156 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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| 157 | break; |
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| 158 | case RMX_CENTER: |
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| 159 | args.ucEnable = ATOM_SCALER_CENTER; |
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| 160 | break; |
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| 161 | case RMX_ASPECT: |
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| 162 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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| 163 | break; |
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| 164 | default: |
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| 165 | if (ASIC_IS_AVIVO(rdev)) |
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| 166 | args.ucEnable = ATOM_SCALER_DISABLE; |
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| 167 | else |
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| 168 | args.ucEnable = ATOM_SCALER_CENTER; |
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| 169 | break; |
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| 170 | } |
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| 171 | } |
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| 172 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 173 | if ((is_tv || is_cv) |
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| 174 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
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| 175 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
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| 176 | } |
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| 177 | } |
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| 178 | |||
| 1123 | serge | 179 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
| 180 | { |
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| 181 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 182 | struct drm_device *dev = crtc->dev; |
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| 183 | struct radeon_device *rdev = dev->dev_private; |
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| 184 | int index = |
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| 185 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
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| 186 | ENABLE_CRTC_PS_ALLOCATION args; |
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| 187 | |||
| 188 | memset(&args, 0, sizeof(args)); |
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| 189 | |||
| 190 | args.ucCRTC = radeon_crtc->crtc_id; |
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| 191 | args.ucEnable = lock; |
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| 192 | |||
| 193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 194 | } |
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| 195 | |||
| 196 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
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| 197 | { |
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| 198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 199 | struct drm_device *dev = crtc->dev; |
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| 200 | struct radeon_device *rdev = dev->dev_private; |
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| 201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
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| 202 | ENABLE_CRTC_PS_ALLOCATION args; |
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| 203 | |||
| 204 | memset(&args, 0, sizeof(args)); |
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| 205 | |||
| 206 | args.ucCRTC = radeon_crtc->crtc_id; |
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| 207 | args.ucEnable = state; |
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| 208 | |||
| 209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 210 | } |
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| 211 | |||
| 212 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
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| 213 | { |
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| 214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 215 | struct drm_device *dev = crtc->dev; |
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| 216 | struct radeon_device *rdev = dev->dev_private; |
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| 217 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
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| 218 | ENABLE_CRTC_PS_ALLOCATION args; |
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| 219 | |||
| 220 | memset(&args, 0, sizeof(args)); |
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| 221 | |||
| 222 | args.ucCRTC = radeon_crtc->crtc_id; |
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| 223 | args.ucEnable = state; |
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| 224 | |||
| 225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 226 | } |
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| 227 | |||
| 228 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
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| 229 | { |
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| 230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 231 | struct drm_device *dev = crtc->dev; |
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| 232 | struct radeon_device *rdev = dev->dev_private; |
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| 233 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
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| 234 | BLANK_CRTC_PS_ALLOCATION args; |
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| 235 | |||
| 236 | memset(&args, 0, sizeof(args)); |
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| 237 | |||
| 238 | args.ucCRTC = radeon_crtc->crtc_id; |
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| 239 | args.ucBlanking = state; |
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| 240 | |||
| 241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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| 242 | } |
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| 243 | |||
| 244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
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| 245 | { |
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| 246 | struct drm_device *dev = crtc->dev; |
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| 247 | struct radeon_device *rdev = dev->dev_private; |
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| 248 | |||
| 249 | switch (mode) { |
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| 250 | case DRM_MODE_DPMS_ON: |
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| 251 | if (ASIC_IS_DCE3(rdev)) |
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| 252 | atombios_enable_crtc_memreq(crtc, 1); |
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| 253 | atombios_enable_crtc(crtc, 1); |
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| 254 | atombios_blank_crtc(crtc, 0); |
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| 255 | break; |
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| 256 | case DRM_MODE_DPMS_STANDBY: |
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| 257 | case DRM_MODE_DPMS_SUSPEND: |
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| 258 | case DRM_MODE_DPMS_OFF: |
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| 259 | atombios_blank_crtc(crtc, 1); |
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| 260 | atombios_enable_crtc(crtc, 0); |
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| 261 | if (ASIC_IS_DCE3(rdev)) |
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| 262 | atombios_enable_crtc_memreq(crtc, 0); |
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| 263 | break; |
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| 264 | } |
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| 265 | |||
| 266 | if (mode != DRM_MODE_DPMS_OFF) { |
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| 267 | radeon_crtc_load_lut(crtc); |
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| 268 | } |
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| 269 | } |
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| 270 | |||
| 271 | static void |
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| 272 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
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| 273 | SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) |
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| 274 | { |
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| 275 | struct drm_device *dev = crtc->dev; |
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| 276 | struct radeon_device *rdev = dev->dev_private; |
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| 277 | SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; |
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| 278 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
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| 279 | |||
| 280 | conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); |
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| 281 | conv_param.usH_Blanking_Time = |
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| 282 | cpu_to_le16(crtc_param->usH_Blanking_Time); |
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| 283 | conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); |
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| 284 | conv_param.usV_Blanking_Time = |
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| 285 | cpu_to_le16(crtc_param->usV_Blanking_Time); |
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| 286 | conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); |
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| 287 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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| 288 | conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); |
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| 289 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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| 290 | conv_param.susModeMiscInfo.usAccess = |
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| 291 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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| 292 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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| 293 | |||
| 294 | printk("executing set crtc dtd timing\n"); |
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| 295 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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| 296 | } |
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| 297 | |||
| 298 | void atombios_crtc_set_timing(struct drm_crtc *crtc, |
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| 299 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * |
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| 300 | crtc_param) |
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| 301 | { |
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| 302 | struct drm_device *dev = crtc->dev; |
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| 303 | struct radeon_device *rdev = dev->dev_private; |
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| 304 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; |
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| 305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
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| 306 | |||
| 307 | conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); |
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| 308 | conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); |
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| 309 | conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); |
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| 310 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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| 311 | conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); |
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| 312 | conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); |
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| 313 | conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); |
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| 314 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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| 315 | conv_param.susModeMiscInfo.usAccess = |
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| 316 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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| 317 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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| 318 | conv_param.ucOverscanRight = crtc_param->ucOverscanRight; |
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| 319 | conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; |
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| 320 | conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; |
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| 321 | conv_param.ucOverscanTop = crtc_param->ucOverscanTop; |
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| 322 | conv_param.ucReserved = crtc_param->ucReserved; |
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| 323 | |||
| 324 | printk("executing set crtc timing\n"); |
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| 325 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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| 326 | } |
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| 327 | |||
| 328 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
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| 329 | { |
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| 330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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| 331 | struct drm_device *dev = crtc->dev; |
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| 332 | struct radeon_device *rdev = dev->dev_private; |
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| 333 | struct drm_encoder *encoder = NULL; |
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| 334 | struct radeon_encoder *radeon_encoder = NULL; |
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| 335 | uint8_t frev, crev; |
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| 336 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
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| 337 | SET_PIXEL_CLOCK_PS_ALLOCATION args; |
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| 338 | PIXEL_CLOCK_PARAMETERS *spc1_ptr; |
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| 339 | PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; |
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| 340 | PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; |
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| 341 | uint32_t sclock = mode->clock; |
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| 342 | uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
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| 343 | struct radeon_pll *pll; |
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| 344 | int pll_flags = 0; |
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| 345 | |||
| 346 | memset(&args, 0, sizeof(args)); |
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| 347 | |||
| 348 | if (ASIC_IS_AVIVO(rdev)) { |
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| 349 | uint32_t ss_cntl; |
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| 350 | |||
| 1179 | serge | 351 | if ((rdev->family == CHIP_RS600) || |
| 352 | (rdev->family == CHIP_RS690) || |
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| 353 | (rdev->family == CHIP_RS740)) |
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| 354 | pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | |
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| 355 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
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| 356 | |||
| 1123 | serge | 357 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
| 358 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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| 359 | else |
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| 360 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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| 361 | |||
| 362 | /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ |
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| 363 | if (radeon_crtc->crtc_id == 0) { |
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| 364 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
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| 365 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1); |
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| 366 | } else { |
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| 367 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
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| 368 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1); |
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| 369 | } |
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| 370 | } else { |
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| 371 | pll_flags |= RADEON_PLL_LEGACY; |
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| 372 | |||
| 373 | if (mode->clock > 200000) /* range limits??? */ |
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| 374 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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| 375 | else |
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| 376 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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| 377 | |||
| 378 | } |
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| 379 | |||
| 380 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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| 381 | if (encoder->crtc == crtc) { |
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| 382 | if (!ASIC_IS_AVIVO(rdev)) { |
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| 383 | if (encoder->encoder_type != |
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| 384 | DRM_MODE_ENCODER_DAC) |
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| 385 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
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| 386 | if (!ASIC_IS_AVIVO(rdev) |
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| 387 | && (encoder->encoder_type == |
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| 388 | DRM_MODE_ENCODER_LVDS)) |
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| 389 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
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| 390 | } |
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| 391 | radeon_encoder = to_radeon_encoder(encoder); |
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| 1179 | serge | 392 | break; |
| 1123 | serge | 393 | } |
| 394 | } |
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| 395 | |||
| 396 | if (radeon_crtc->crtc_id == 0) |
||
| 397 | pll = &rdev->clock.p1pll; |
||
| 398 | else |
||
| 399 | pll = &rdev->clock.p2pll; |
||
| 400 | |||
| 401 | radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, |
||
| 402 | &ref_div, &post_div, pll_flags); |
||
| 403 | |||
| 404 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
||
| 405 | &crev); |
||
| 406 | |||
| 407 | switch (frev) { |
||
| 408 | case 1: |
||
| 409 | switch (crev) { |
||
| 410 | case 1: |
||
| 411 | spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; |
||
| 412 | spc1_ptr->usPixelClock = cpu_to_le16(sclock); |
||
| 413 | spc1_ptr->usRefDiv = cpu_to_le16(ref_div); |
||
| 414 | spc1_ptr->usFbDiv = cpu_to_le16(fb_div); |
||
| 415 | spc1_ptr->ucFracFbDiv = frac_fb_div; |
||
| 416 | spc1_ptr->ucPostDiv = post_div; |
||
| 417 | spc1_ptr->ucPpll = |
||
| 418 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
| 419 | spc1_ptr->ucCRTC = radeon_crtc->crtc_id; |
||
| 420 | spc1_ptr->ucRefDivSrc = 1; |
||
| 421 | break; |
||
| 422 | case 2: |
||
| 423 | spc2_ptr = |
||
| 424 | (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; |
||
| 425 | spc2_ptr->usPixelClock = cpu_to_le16(sclock); |
||
| 426 | spc2_ptr->usRefDiv = cpu_to_le16(ref_div); |
||
| 427 | spc2_ptr->usFbDiv = cpu_to_le16(fb_div); |
||
| 428 | spc2_ptr->ucFracFbDiv = frac_fb_div; |
||
| 429 | spc2_ptr->ucPostDiv = post_div; |
||
| 430 | spc2_ptr->ucPpll = |
||
| 431 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
| 432 | spc2_ptr->ucCRTC = radeon_crtc->crtc_id; |
||
| 433 | spc2_ptr->ucRefDivSrc = 1; |
||
| 434 | break; |
||
| 435 | case 3: |
||
| 436 | if (!encoder) |
||
| 437 | return; |
||
| 438 | spc3_ptr = |
||
| 439 | (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; |
||
| 440 | spc3_ptr->usPixelClock = cpu_to_le16(sclock); |
||
| 441 | spc3_ptr->usRefDiv = cpu_to_le16(ref_div); |
||
| 442 | spc3_ptr->usFbDiv = cpu_to_le16(fb_div); |
||
| 443 | spc3_ptr->ucFracFbDiv = frac_fb_div; |
||
| 444 | spc3_ptr->ucPostDiv = post_div; |
||
| 445 | spc3_ptr->ucPpll = |
||
| 446 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
| 447 | spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); |
||
| 448 | spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; |
||
| 449 | spc3_ptr->ucEncoderMode = |
||
| 450 | atombios_get_encoder_mode(encoder); |
||
| 451 | break; |
||
| 452 | default: |
||
| 453 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
| 454 | return; |
||
| 455 | } |
||
| 456 | break; |
||
| 457 | default: |
||
| 458 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
| 459 | return; |
||
| 460 | } |
||
| 461 | |||
| 462 | printk("executing set pll\n"); |
||
| 463 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
| 464 | } |
||
| 465 | |||
| 466 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
| 467 | struct drm_framebuffer *old_fb) |
||
| 468 | { |
||
| 1246 | serge | 469 | ENTER(); |
| 470 | |||
| 1123 | serge | 471 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 472 | struct drm_device *dev = crtc->dev; |
||
| 473 | struct radeon_device *rdev = dev->dev_private; |
||
| 474 | struct radeon_framebuffer *radeon_fb; |
||
| 475 | struct drm_gem_object *obj; |
||
| 476 | struct drm_radeon_gem_object *obj_priv; |
||
| 477 | uint64_t fb_location; |
||
| 1179 | serge | 478 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
| 1123 | serge | 479 | |
| 480 | if (!crtc->fb) |
||
| 481 | return -EINVAL; |
||
| 482 | |||
| 483 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
||
| 484 | |||
| 485 | obj = radeon_fb->obj; |
||
| 486 | obj_priv = obj->driver_private; |
||
| 487 | |||
| 1179 | serge | 488 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
| 489 | // return -EINVAL; |
||
| 490 | // } |
||
| 1123 | serge | 491 | |
| 1246 | serge | 492 | fb_location = rdev->mc.vram_location; |
| 1126 | serge | 493 | |
| 1123 | serge | 494 | switch (crtc->fb->bits_per_pixel) { |
| 1179 | serge | 495 | case 8: |
| 496 | fb_format = |
||
| 497 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
||
| 498 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
||
| 499 | break; |
||
| 1123 | serge | 500 | case 15: |
| 501 | fb_format = |
||
| 502 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
| 503 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
||
| 504 | break; |
||
| 505 | case 16: |
||
| 506 | fb_format = |
||
| 507 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
| 508 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
||
| 509 | break; |
||
| 510 | case 24: |
||
| 511 | case 32: |
||
| 512 | fb_format = |
||
| 513 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
||
| 514 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
||
| 515 | break; |
||
| 516 | default: |
||
| 517 | DRM_ERROR("Unsupported screen depth %d\n", |
||
| 518 | crtc->fb->bits_per_pixel); |
||
| 519 | return -EINVAL; |
||
| 520 | } |
||
| 521 | |||
| 1179 | serge | 522 | // radeon_object_get_tiling_flags(obj->driver_private, |
| 523 | // &tiling_flags, NULL); |
||
| 524 | // if (tiling_flags & RADEON_TILING_MACRO) |
||
| 525 | // fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
||
| 526 | |||
| 527 | // if (tiling_flags & RADEON_TILING_MICRO) |
||
| 528 | // fb_format |= AVIVO_D1GRPH_TILED; |
||
| 529 | |||
| 1123 | serge | 530 | if (radeon_crtc->crtc_id == 0) |
| 531 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
||
| 532 | else |
||
| 533 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
||
| 534 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
||
| 535 | (u32) fb_location); |
||
| 536 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
||
| 537 | radeon_crtc->crtc_offset, (u32) fb_location); |
||
| 538 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
||
| 539 | |||
| 540 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
||
| 541 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
||
| 542 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
||
| 543 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
||
| 544 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
||
| 545 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
||
| 546 | |||
| 547 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
||
| 548 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
||
| 549 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
||
| 550 | |||
| 551 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
||
| 552 | crtc->mode.vdisplay); |
||
| 553 | x &= ~3; |
||
| 554 | y &= ~1; |
||
| 555 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
||
| 556 | (x << 16) | y); |
||
| 557 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
||
| 558 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
||
| 559 | |||
| 560 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
||
| 561 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
||
| 562 | AVIVO_D1MODE_INTERLEAVE_EN); |
||
| 563 | else |
||
| 564 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
||
| 565 | |||
| 1246 | serge | 566 | // if (old_fb && old_fb != crtc->fb) { |
| 1179 | serge | 567 | // radeon_fb = to_radeon_framebuffer(old_fb); |
| 1123 | serge | 568 | // radeon_gem_object_unpin(radeon_fb->obj); |
| 1246 | serge | 569 | // } |
| 570 | |||
| 571 | LEAVE(); |
||
| 572 | |||
| 1123 | serge | 573 | return 0; |
| 574 | } |
||
| 575 | |||
| 576 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
||
| 577 | struct drm_display_mode *mode, |
||
| 578 | struct drm_display_mode *adjusted_mode, |
||
| 579 | int x, int y, struct drm_framebuffer *old_fb) |
||
| 580 | { |
||
| 581 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
| 582 | struct drm_device *dev = crtc->dev; |
||
| 583 | struct radeon_device *rdev = dev->dev_private; |
||
| 584 | struct drm_encoder *encoder; |
||
| 585 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
||
| 1179 | serge | 586 | int need_tv_timings = 0; |
| 587 | bool ret; |
||
| 1123 | serge | 588 | |
| 589 | /* TODO color tiling */ |
||
| 590 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
||
| 591 | |||
| 592 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
| 1179 | serge | 593 | /* find tv std */ |
| 594 | if (encoder->crtc == crtc) { |
||
| 595 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
| 1123 | serge | 596 | |
| 1179 | serge | 597 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
| 598 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
||
| 599 | if (tv_dac) { |
||
| 600 | if (tv_dac->tv_std == TV_STD_NTSC || |
||
| 601 | tv_dac->tv_std == TV_STD_NTSC_J || |
||
| 602 | tv_dac->tv_std == TV_STD_PAL_M) |
||
| 603 | need_tv_timings = 1; |
||
| 604 | else |
||
| 605 | need_tv_timings = 2; |
||
| 606 | break; |
||
| 607 | } |
||
| 608 | } |
||
| 609 | } |
||
| 1123 | serge | 610 | } |
| 611 | |||
| 612 | crtc_timing.ucCRTC = radeon_crtc->crtc_id; |
||
| 1179 | serge | 613 | if (need_tv_timings) { |
| 614 | ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, |
||
| 615 | &crtc_timing, &adjusted_mode->clock); |
||
| 616 | if (ret == false) |
||
| 617 | need_tv_timings = 0; |
||
| 618 | } |
||
| 619 | |||
| 620 | if (!need_tv_timings) { |
||
| 1123 | serge | 621 | crtc_timing.usH_Total = adjusted_mode->crtc_htotal; |
| 622 | crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; |
||
| 623 | crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; |
||
| 624 | crtc_timing.usH_SyncWidth = |
||
| 625 | adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
||
| 626 | |||
| 627 | crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; |
||
| 628 | crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; |
||
| 629 | crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; |
||
| 630 | crtc_timing.usV_SyncWidth = |
||
| 631 | adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
||
| 632 | |||
| 633 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
| 634 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; |
||
| 635 | |||
| 636 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
| 637 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; |
||
| 638 | |||
| 639 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
||
| 640 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; |
||
| 641 | |||
| 642 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
| 643 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; |
||
| 644 | |||
| 645 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
| 646 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; |
||
| 1179 | serge | 647 | } |
| 1123 | serge | 648 | |
| 649 | atombios_crtc_set_pll(crtc, adjusted_mode); |
||
| 650 | atombios_crtc_set_timing(crtc, &crtc_timing); |
||
| 651 | |||
| 652 | if (ASIC_IS_AVIVO(rdev)) |
||
| 653 | atombios_crtc_set_base(crtc, x, y, old_fb); |
||
| 654 | else { |
||
| 655 | if (radeon_crtc->crtc_id == 0) { |
||
| 656 | SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; |
||
| 657 | memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); |
||
| 658 | |||
| 659 | /* setup FP shadow regs on R4xx */ |
||
| 660 | crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; |
||
| 661 | crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay; |
||
| 662 | crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay; |
||
| 663 | crtc_dtd_timing.usH_Blanking_Time = |
||
| 664 | adjusted_mode->crtc_hblank_end - |
||
| 665 | adjusted_mode->crtc_hdisplay; |
||
| 666 | crtc_dtd_timing.usV_Blanking_Time = |
||
| 667 | adjusted_mode->crtc_vblank_end - |
||
| 668 | adjusted_mode->crtc_vdisplay; |
||
| 669 | crtc_dtd_timing.usH_SyncOffset = |
||
| 670 | adjusted_mode->crtc_hsync_start - |
||
| 671 | adjusted_mode->crtc_hdisplay; |
||
| 672 | crtc_dtd_timing.usV_SyncOffset = |
||
| 673 | adjusted_mode->crtc_vsync_start - |
||
| 674 | adjusted_mode->crtc_vdisplay; |
||
| 675 | crtc_dtd_timing.usH_SyncWidth = |
||
| 676 | adjusted_mode->crtc_hsync_end - |
||
| 677 | adjusted_mode->crtc_hsync_start; |
||
| 678 | crtc_dtd_timing.usV_SyncWidth = |
||
| 679 | adjusted_mode->crtc_vsync_end - |
||
| 680 | adjusted_mode->crtc_vsync_start; |
||
| 681 | /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */ |
||
| 682 | /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */ |
||
| 683 | |||
| 684 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
| 685 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
| 686 | ATOM_VSYNC_POLARITY; |
||
| 687 | |||
| 688 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
| 689 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
| 690 | ATOM_HSYNC_POLARITY; |
||
| 691 | |||
| 692 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
||
| 693 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
| 694 | ATOM_COMPOSITESYNC; |
||
| 695 | |||
| 696 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
| 697 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
| 698 | ATOM_INTERLACE; |
||
| 699 | |||
| 700 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
| 701 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
| 702 | ATOM_DOUBLE_CLOCK_MODE; |
||
| 703 | |||
| 704 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
||
| 705 | } |
||
| 706 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
| 707 | radeon_legacy_atom_set_surface(crtc); |
||
| 708 | } |
||
| 1179 | serge | 709 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
| 710 | atombios_scaler_setup(crtc); |
||
| 711 | radeon_bandwidth_update(rdev); |
||
| 1123 | serge | 712 | return 0; |
| 713 | } |
||
| 714 | |||
| 715 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
||
| 716 | struct drm_display_mode *mode, |
||
| 717 | struct drm_display_mode *adjusted_mode) |
||
| 718 | { |
||
| 1179 | serge | 719 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 720 | return false; |
||
| 1123 | serge | 721 | return true; |
| 722 | } |
||
| 723 | |||
| 724 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
||
| 725 | { |
||
| 726 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
||
| 727 | atombios_lock_crtc(crtc, 1); |
||
| 728 | } |
||
| 729 | |||
| 730 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
||
| 731 | { |
||
| 732 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
||
| 733 | atombios_lock_crtc(crtc, 0); |
||
| 734 | } |
||
| 735 | |||
| 736 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
||
| 737 | .dpms = atombios_crtc_dpms, |
||
| 738 | .mode_fixup = atombios_crtc_mode_fixup, |
||
| 739 | .mode_set = atombios_crtc_mode_set, |
||
| 740 | .mode_set_base = atombios_crtc_set_base, |
||
| 741 | .prepare = atombios_crtc_prepare, |
||
| 742 | .commit = atombios_crtc_commit, |
||
| 1221 | serge | 743 | .load_lut = radeon_crtc_load_lut, |
| 1123 | serge | 744 | }; |
| 745 | |||
| 746 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
| 747 | struct radeon_crtc *radeon_crtc) |
||
| 748 | { |
||
| 749 | if (radeon_crtc->crtc_id == 1) |
||
| 750 | radeon_crtc->crtc_offset = |
||
| 751 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
||
| 752 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
||
| 753 | } |