Rev 1125 | Go to most recent revision | Details | Last modification | View Log | RSS feed
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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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26 | #include |
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27 | #include |
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28 | #include "radeon_drm.h" |
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29 | #include "radeon_fixed.h" |
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30 | #include "radeon.h" |
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31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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33 | |||
34 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
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35 | { |
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36 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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37 | struct drm_device *dev = crtc->dev; |
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38 | struct radeon_device *rdev = dev->dev_private; |
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39 | int index = |
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40 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
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41 | ENABLE_CRTC_PS_ALLOCATION args; |
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42 | |||
43 | memset(&args, 0, sizeof(args)); |
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44 | |||
45 | args.ucCRTC = radeon_crtc->crtc_id; |
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46 | args.ucEnable = lock; |
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47 | |||
48 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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49 | } |
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50 | |||
51 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
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52 | { |
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53 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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54 | struct drm_device *dev = crtc->dev; |
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55 | struct radeon_device *rdev = dev->dev_private; |
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56 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
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57 | ENABLE_CRTC_PS_ALLOCATION args; |
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58 | |||
59 | memset(&args, 0, sizeof(args)); |
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60 | |||
61 | args.ucCRTC = radeon_crtc->crtc_id; |
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62 | args.ucEnable = state; |
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63 | |||
64 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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65 | } |
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66 | |||
67 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
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68 | { |
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69 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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70 | struct drm_device *dev = crtc->dev; |
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71 | struct radeon_device *rdev = dev->dev_private; |
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72 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
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73 | ENABLE_CRTC_PS_ALLOCATION args; |
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74 | |||
75 | memset(&args, 0, sizeof(args)); |
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76 | |||
77 | args.ucCRTC = radeon_crtc->crtc_id; |
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78 | args.ucEnable = state; |
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79 | |||
80 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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81 | } |
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82 | |||
83 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
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84 | { |
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85 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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86 | struct drm_device *dev = crtc->dev; |
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87 | struct radeon_device *rdev = dev->dev_private; |
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88 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
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89 | BLANK_CRTC_PS_ALLOCATION args; |
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90 | |||
91 | memset(&args, 0, sizeof(args)); |
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92 | |||
93 | args.ucCRTC = radeon_crtc->crtc_id; |
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94 | args.ucBlanking = state; |
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95 | |||
96 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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97 | } |
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98 | |||
99 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
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100 | { |
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101 | struct drm_device *dev = crtc->dev; |
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102 | struct radeon_device *rdev = dev->dev_private; |
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103 | |||
104 | switch (mode) { |
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105 | case DRM_MODE_DPMS_ON: |
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106 | if (ASIC_IS_DCE3(rdev)) |
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107 | atombios_enable_crtc_memreq(crtc, 1); |
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108 | atombios_enable_crtc(crtc, 1); |
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109 | atombios_blank_crtc(crtc, 0); |
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110 | break; |
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111 | case DRM_MODE_DPMS_STANDBY: |
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112 | case DRM_MODE_DPMS_SUSPEND: |
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113 | case DRM_MODE_DPMS_OFF: |
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114 | atombios_blank_crtc(crtc, 1); |
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115 | atombios_enable_crtc(crtc, 0); |
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116 | if (ASIC_IS_DCE3(rdev)) |
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117 | atombios_enable_crtc_memreq(crtc, 0); |
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118 | break; |
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119 | } |
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120 | |||
121 | if (mode != DRM_MODE_DPMS_OFF) { |
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122 | radeon_crtc_load_lut(crtc); |
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123 | } |
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124 | } |
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125 | |||
126 | static void |
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127 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
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128 | SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) |
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129 | { |
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130 | struct drm_device *dev = crtc->dev; |
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131 | struct radeon_device *rdev = dev->dev_private; |
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132 | SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; |
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133 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
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134 | |||
135 | conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); |
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136 | conv_param.usH_Blanking_Time = |
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137 | cpu_to_le16(crtc_param->usH_Blanking_Time); |
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138 | conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); |
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139 | conv_param.usV_Blanking_Time = |
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140 | cpu_to_le16(crtc_param->usV_Blanking_Time); |
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141 | conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); |
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142 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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143 | conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); |
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144 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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145 | conv_param.susModeMiscInfo.usAccess = |
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146 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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147 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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148 | |||
149 | printk("executing set crtc dtd timing\n"); |
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150 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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151 | } |
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152 | |||
153 | void atombios_crtc_set_timing(struct drm_crtc *crtc, |
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154 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * |
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155 | crtc_param) |
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156 | { |
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157 | struct drm_device *dev = crtc->dev; |
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158 | struct radeon_device *rdev = dev->dev_private; |
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159 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; |
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160 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
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161 | |||
162 | conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); |
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163 | conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); |
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164 | conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); |
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165 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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166 | conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); |
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167 | conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); |
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168 | conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); |
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169 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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170 | conv_param.susModeMiscInfo.usAccess = |
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171 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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172 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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173 | conv_param.ucOverscanRight = crtc_param->ucOverscanRight; |
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174 | conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; |
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175 | conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; |
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176 | conv_param.ucOverscanTop = crtc_param->ucOverscanTop; |
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177 | conv_param.ucReserved = crtc_param->ucReserved; |
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178 | |||
179 | printk("executing set crtc timing\n"); |
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180 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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181 | } |
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182 | |||
183 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
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184 | { |
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185 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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186 | struct drm_device *dev = crtc->dev; |
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187 | struct radeon_device *rdev = dev->dev_private; |
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188 | struct drm_encoder *encoder = NULL; |
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189 | struct radeon_encoder *radeon_encoder = NULL; |
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190 | uint8_t frev, crev; |
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191 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
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192 | SET_PIXEL_CLOCK_PS_ALLOCATION args; |
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193 | PIXEL_CLOCK_PARAMETERS *spc1_ptr; |
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194 | PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; |
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195 | PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; |
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196 | uint32_t sclock = mode->clock; |
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197 | uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
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198 | struct radeon_pll *pll; |
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199 | int pll_flags = 0; |
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200 | |||
201 | memset(&args, 0, sizeof(args)); |
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202 | |||
203 | if (ASIC_IS_AVIVO(rdev)) { |
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204 | uint32_t ss_cntl; |
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205 | |||
206 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
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207 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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208 | else |
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209 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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210 | |||
211 | /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ |
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212 | if (radeon_crtc->crtc_id == 0) { |
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213 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
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214 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1); |
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215 | } else { |
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216 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
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217 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1); |
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218 | } |
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219 | } else { |
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220 | pll_flags |= RADEON_PLL_LEGACY; |
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221 | |||
222 | if (mode->clock > 200000) /* range limits??? */ |
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223 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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224 | else |
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225 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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226 | |||
227 | } |
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228 | |||
229 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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230 | if (encoder->crtc == crtc) { |
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231 | if (!ASIC_IS_AVIVO(rdev)) { |
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232 | if (encoder->encoder_type != |
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233 | DRM_MODE_ENCODER_DAC) |
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234 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
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235 | if (!ASIC_IS_AVIVO(rdev) |
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236 | && (encoder->encoder_type == |
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237 | DRM_MODE_ENCODER_LVDS)) |
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238 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
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239 | } |
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240 | radeon_encoder = to_radeon_encoder(encoder); |
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241 | } |
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242 | } |
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243 | |||
244 | if (radeon_crtc->crtc_id == 0) |
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245 | pll = &rdev->clock.p1pll; |
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246 | else |
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247 | pll = &rdev->clock.p2pll; |
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248 | |||
249 | radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, |
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250 | &ref_div, &post_div, pll_flags); |
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251 | |||
252 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
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253 | &crev); |
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254 | |||
255 | switch (frev) { |
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256 | case 1: |
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257 | switch (crev) { |
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258 | case 1: |
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259 | spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; |
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260 | spc1_ptr->usPixelClock = cpu_to_le16(sclock); |
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261 | spc1_ptr->usRefDiv = cpu_to_le16(ref_div); |
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262 | spc1_ptr->usFbDiv = cpu_to_le16(fb_div); |
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263 | spc1_ptr->ucFracFbDiv = frac_fb_div; |
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264 | spc1_ptr->ucPostDiv = post_div; |
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265 | spc1_ptr->ucPpll = |
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266 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
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267 | spc1_ptr->ucCRTC = radeon_crtc->crtc_id; |
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268 | spc1_ptr->ucRefDivSrc = 1; |
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269 | break; |
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270 | case 2: |
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271 | spc2_ptr = |
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272 | (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; |
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273 | spc2_ptr->usPixelClock = cpu_to_le16(sclock); |
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274 | spc2_ptr->usRefDiv = cpu_to_le16(ref_div); |
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275 | spc2_ptr->usFbDiv = cpu_to_le16(fb_div); |
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276 | spc2_ptr->ucFracFbDiv = frac_fb_div; |
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277 | spc2_ptr->ucPostDiv = post_div; |
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278 | spc2_ptr->ucPpll = |
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279 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
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280 | spc2_ptr->ucCRTC = radeon_crtc->crtc_id; |
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281 | spc2_ptr->ucRefDivSrc = 1; |
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282 | break; |
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283 | case 3: |
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284 | if (!encoder) |
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285 | return; |
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286 | spc3_ptr = |
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287 | (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; |
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288 | spc3_ptr->usPixelClock = cpu_to_le16(sclock); |
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289 | spc3_ptr->usRefDiv = cpu_to_le16(ref_div); |
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290 | spc3_ptr->usFbDiv = cpu_to_le16(fb_div); |
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291 | spc3_ptr->ucFracFbDiv = frac_fb_div; |
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292 | spc3_ptr->ucPostDiv = post_div; |
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293 | spc3_ptr->ucPpll = |
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294 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
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295 | spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); |
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296 | spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; |
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297 | spc3_ptr->ucEncoderMode = |
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298 | atombios_get_encoder_mode(encoder); |
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299 | break; |
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300 | default: |
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301 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
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302 | return; |
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303 | } |
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304 | break; |
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305 | default: |
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306 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
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307 | return; |
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308 | } |
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309 | |||
310 | printk("executing set pll\n"); |
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311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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312 | } |
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313 | |||
314 | |||
315 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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316 | struct drm_framebuffer *old_fb) |
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317 | { |
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318 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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319 | struct drm_device *dev = crtc->dev; |
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320 | struct radeon_device *rdev = dev->dev_private; |
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321 | struct radeon_framebuffer *radeon_fb; |
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322 | struct drm_gem_object *obj; |
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323 | struct drm_radeon_gem_object *obj_priv; |
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324 | uint64_t fb_location; |
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325 | uint32_t fb_format, fb_pitch_pixels; |
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326 | |||
327 | if (!crtc->fb) |
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328 | return -EINVAL; |
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329 | |||
330 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
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331 | |||
332 | obj = radeon_fb->obj; |
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333 | obj_priv = obj->driver_private; |
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334 | |||
335 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
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336 | // return -EINVAL; |
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337 | // } |
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338 | |||
339 | switch (crtc->fb->bits_per_pixel) { |
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340 | case 15: |
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341 | fb_format = |
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342 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
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343 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
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344 | break; |
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345 | case 16: |
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346 | fb_format = |
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347 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
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348 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
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349 | break; |
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350 | case 24: |
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351 | case 32: |
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352 | fb_format = |
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353 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
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354 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
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355 | break; |
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356 | default: |
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357 | DRM_ERROR("Unsupported screen depth %d\n", |
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358 | crtc->fb->bits_per_pixel); |
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359 | return -EINVAL; |
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360 | } |
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361 | |||
362 | /* TODO tiling */ |
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363 | if (radeon_crtc->crtc_id == 0) |
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364 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
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365 | else |
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366 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
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367 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
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368 | (u32) fb_location); |
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369 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
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370 | radeon_crtc->crtc_offset, (u32) fb_location); |
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371 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
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372 | |||
373 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
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374 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
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375 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
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376 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
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377 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
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378 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
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379 | |||
380 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
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381 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
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382 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
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383 | |||
384 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
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385 | crtc->mode.vdisplay); |
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386 | x &= ~3; |
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387 | y &= ~1; |
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388 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
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389 | (x << 16) | y); |
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390 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
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391 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
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392 | |||
393 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
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394 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
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395 | AVIVO_D1MODE_INTERLEAVE_EN); |
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396 | else |
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397 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
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398 | |||
399 | if (old_fb && old_fb != crtc->fb) { |
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400 | radeon_fb = to_radeon_framebuffer(old_fb); |
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401 | // radeon_gem_object_unpin(radeon_fb->obj); |
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402 | } |
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403 | return 0; |
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404 | } |
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405 | |||
406 | |||
407 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
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408 | struct drm_display_mode *mode, |
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409 | struct drm_display_mode *adjusted_mode, |
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410 | int x, int y, struct drm_framebuffer *old_fb) |
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411 | { |
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412 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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413 | struct drm_device *dev = crtc->dev; |
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414 | struct radeon_device *rdev = dev->dev_private; |
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415 | struct drm_encoder *encoder; |
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416 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
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417 | |||
418 | /* TODO color tiling */ |
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419 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
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420 | |||
421 | /* TODO tv */ |
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422 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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423 | |||
424 | } |
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425 | |||
426 | crtc_timing.ucCRTC = radeon_crtc->crtc_id; |
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427 | crtc_timing.usH_Total = adjusted_mode->crtc_htotal; |
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428 | crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; |
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429 | crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; |
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430 | crtc_timing.usH_SyncWidth = |
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431 | adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
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432 | |||
433 | crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; |
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434 | crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; |
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435 | crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; |
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436 | crtc_timing.usV_SyncWidth = |
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437 | adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
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438 | |||
439 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
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440 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; |
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441 | |||
442 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
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443 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; |
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444 | |||
445 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
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446 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; |
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447 | |||
448 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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449 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; |
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450 | |||
451 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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452 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; |
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453 | |||
454 | atombios_crtc_set_pll(crtc, adjusted_mode); |
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455 | atombios_crtc_set_timing(crtc, &crtc_timing); |
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456 | |||
457 | if (ASIC_IS_AVIVO(rdev)) |
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458 | atombios_crtc_set_base(crtc, x, y, old_fb); |
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459 | else { |
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460 | if (radeon_crtc->crtc_id == 0) { |
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461 | SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; |
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462 | memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); |
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463 | |||
464 | /* setup FP shadow regs on R4xx */ |
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465 | crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; |
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466 | crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay; |
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467 | crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay; |
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468 | crtc_dtd_timing.usH_Blanking_Time = |
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469 | adjusted_mode->crtc_hblank_end - |
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470 | adjusted_mode->crtc_hdisplay; |
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471 | crtc_dtd_timing.usV_Blanking_Time = |
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472 | adjusted_mode->crtc_vblank_end - |
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473 | adjusted_mode->crtc_vdisplay; |
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474 | crtc_dtd_timing.usH_SyncOffset = |
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475 | adjusted_mode->crtc_hsync_start - |
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476 | adjusted_mode->crtc_hdisplay; |
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477 | crtc_dtd_timing.usV_SyncOffset = |
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478 | adjusted_mode->crtc_vsync_start - |
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479 | adjusted_mode->crtc_vdisplay; |
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480 | crtc_dtd_timing.usH_SyncWidth = |
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481 | adjusted_mode->crtc_hsync_end - |
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482 | adjusted_mode->crtc_hsync_start; |
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483 | crtc_dtd_timing.usV_SyncWidth = |
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484 | adjusted_mode->crtc_vsync_end - |
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485 | adjusted_mode->crtc_vsync_start; |
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486 | /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */ |
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487 | /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */ |
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488 | |||
489 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
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490 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
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491 | ATOM_VSYNC_POLARITY; |
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492 | |||
493 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
494 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
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495 | ATOM_HSYNC_POLARITY; |
||
496 | |||
497 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
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498 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
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499 | ATOM_COMPOSITESYNC; |
||
500 | |||
501 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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502 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
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503 | ATOM_INTERLACE; |
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504 | |||
505 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
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506 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
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507 | ATOM_DOUBLE_CLOCK_MODE; |
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508 | |||
509 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
||
510 | } |
||
511 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
512 | radeon_legacy_atom_set_surface(crtc); |
||
513 | } |
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514 | return 0; |
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515 | } |
||
516 | |||
517 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
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518 | struct drm_display_mode *mode, |
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519 | struct drm_display_mode *adjusted_mode) |
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520 | { |
||
521 | return true; |
||
522 | } |
||
523 | |||
524 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
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525 | { |
||
526 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
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527 | atombios_lock_crtc(crtc, 1); |
||
528 | } |
||
529 | |||
530 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
||
531 | { |
||
532 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
||
533 | atombios_lock_crtc(crtc, 0); |
||
534 | } |
||
535 | |||
536 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
||
537 | .dpms = atombios_crtc_dpms, |
||
538 | .mode_fixup = atombios_crtc_mode_fixup, |
||
539 | .mode_set = atombios_crtc_mode_set, |
||
540 | .mode_set_base = atombios_crtc_set_base, |
||
541 | .prepare = atombios_crtc_prepare, |
||
542 | .commit = atombios_crtc_commit, |
||
543 | }; |
||
544 | |||
545 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
546 | struct radeon_crtc *radeon_crtc) |
||
547 | { |
||
548 | if (radeon_crtc->crtc_id == 1) |
||
549 | radeon_crtc->crtc_offset = |
||
550 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
||
551 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
||
552 | } |
||
553 | |||
554 | void radeon_init_disp_bw_avivo(struct drm_device *dev, |
||
555 | struct drm_display_mode *mode1, |
||
556 | uint32_t pixel_bytes1, |
||
557 | struct drm_display_mode *mode2, |
||
558 | uint32_t pixel_bytes2) |
||
559 | { |
||
560 | struct radeon_device *rdev = dev->dev_private; |
||
561 | fixed20_12 min_mem_eff; |
||
562 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; |
||
563 | fixed20_12 sclk_ff, mclk_ff; |
||
564 | uint32_t dc_lb_memory_split, temp; |
||
565 | |||
566 | min_mem_eff.full = rfixed_const_8(0); |
||
567 | if (rdev->disp_priority == 2) { |
||
568 | uint32_t mc_init_misc_lat_timer = 0; |
||
569 | if (rdev->family == CHIP_RV515) |
||
570 | mc_init_misc_lat_timer = |
||
571 | RREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER); |
||
572 | else if (rdev->family == CHIP_RS690) |
||
573 | mc_init_misc_lat_timer = |
||
574 | RREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER); |
||
575 | |||
576 | mc_init_misc_lat_timer &= |
||
577 | ~(R300_MC_DISP1R_INIT_LAT_MASK << |
||
578 | R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
579 | mc_init_misc_lat_timer &= |
||
580 | ~(R300_MC_DISP0R_INIT_LAT_MASK << |
||
581 | R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
582 | |||
583 | if (mode2) |
||
584 | mc_init_misc_lat_timer |= |
||
585 | (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
||
586 | if (mode1) |
||
587 | mc_init_misc_lat_timer |= |
||
588 | (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
||
589 | |||
590 | if (rdev->family == CHIP_RV515) |
||
591 | WREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER, |
||
592 | mc_init_misc_lat_timer); |
||
593 | else if (rdev->family == CHIP_RS690) |
||
594 | WREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER, |
||
595 | mc_init_misc_lat_timer); |
||
596 | } |
||
597 | |||
598 | /* |
||
599 | * determine is there is enough bw for current mode |
||
600 | */ |
||
601 | temp_ff.full = rfixed_const(100); |
||
602 | mclk_ff.full = rfixed_const(rdev->clock.default_mclk); |
||
603 | mclk_ff.full = rfixed_div(mclk_ff, temp_ff); |
||
604 | sclk_ff.full = rfixed_const(rdev->clock.default_sclk); |
||
605 | sclk_ff.full = rfixed_div(sclk_ff, temp_ff); |
||
606 | |||
607 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
||
608 | temp_ff.full = rfixed_const(temp); |
||
609 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); |
||
610 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); |
||
611 | |||
612 | pix_clk.full = 0; |
||
613 | pix_clk2.full = 0; |
||
614 | peak_disp_bw.full = 0; |
||
615 | if (mode1) { |
||
616 | temp_ff.full = rfixed_const(1000); |
||
617 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ |
||
618 | pix_clk.full = rfixed_div(pix_clk, temp_ff); |
||
619 | temp_ff.full = rfixed_const(pixel_bytes1); |
||
620 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); |
||
621 | } |
||
622 | if (mode2) { |
||
623 | temp_ff.full = rfixed_const(1000); |
||
624 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ |
||
625 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); |
||
626 | temp_ff.full = rfixed_const(pixel_bytes2); |
||
627 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); |
||
628 | } |
||
629 | |||
630 | if (peak_disp_bw.full >= mem_bw.full) { |
||
631 | DRM_ERROR |
||
632 | ("You may not have enough display bandwidth for current mode\n" |
||
633 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
||
634 | printk("peak disp bw %d, mem_bw %d\n", |
||
635 | rfixed_trunc(peak_disp_bw), rfixed_trunc(mem_bw)); |
||
636 | } |
||
637 | |||
638 | /* |
||
639 | * Line Buffer Setup |
||
640 | * There is a single line buffer shared by both display controllers. |
||
641 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display |
||
642 | * controllers. The paritioning can either be done manually or via one of four |
||
643 | * preset allocations specified in bits 1:0: |
||
644 | * 0 - line buffer is divided in half and shared between each display controller |
||
645 | * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 |
||
646 | * 2 - D1 gets the whole buffer |
||
647 | * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 |
||
648 | * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode. |
||
649 | * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits |
||
650 | * 14:4; D2 allocation follows D1. |
||
651 | */ |
||
652 | |||
653 | /* is auto or manual better ? */ |
||
654 | dc_lb_memory_split = |
||
655 | RREG32(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK; |
||
656 | dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; |
||
657 | #if 1 |
||
658 | /* auto */ |
||
659 | if (mode1 && mode2) { |
||
660 | if (mode1->hdisplay > mode2->hdisplay) { |
||
661 | if (mode1->hdisplay > 2560) |
||
662 | dc_lb_memory_split |= |
||
663 | AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
||
664 | else |
||
665 | dc_lb_memory_split |= |
||
666 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
||
667 | } else if (mode2->hdisplay > mode1->hdisplay) { |
||
668 | if (mode2->hdisplay > 2560) |
||
669 | dc_lb_memory_split |= |
||
670 | AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
||
671 | else |
||
672 | dc_lb_memory_split |= |
||
673 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
||
674 | } else |
||
675 | dc_lb_memory_split |= |
||
676 | AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
||
677 | } else if (mode1) { |
||
678 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY; |
||
679 | } else if (mode2) { |
||
680 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
||
681 | } |
||
682 | #else |
||
683 | /* manual */ |
||
684 | dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; |
||
685 | dc_lb_memory_split &= |
||
686 | ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << |
||
687 | AVIVO_DC_LB_DISP1_END_ADR_SHIFT); |
||
688 | if (mode1) { |
||
689 | dc_lb_memory_split |= |
||
690 | ((((mode1->hdisplay / 2) + 64) & AVIVO_DC_LB_DISP1_END_ADR_MASK) |
||
691 | << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); |
||
692 | } else if (mode2) { |
||
693 | dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); |
||
694 | } |
||
695 | #endif |
||
696 | WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); |
||
697 | }><>><> |