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#include 

#include 

#include 

#include 

#include 

#include 

#include 

extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);

static LIST_HEAD(devices);

/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */

#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */

#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)

#define IORESOURCE_ROM_COPY             (1<<2)  /* ROM is alloc'd copy, resource field overlaid */

#define IORESOURCE_ROM_BIOS_COPY        (1<<3)  /* ROM is BIOS copy, resource field overlaid */

/*

 * Translate the low bits of the PCI base

 * to the resource type

 */

static inline unsigned int pci_calc_resource_flags(unsigned int flags)

{

    if (flags & PCI_BASE_ADDRESS_SPACE_IO)

        return IORESOURCE_IO;

    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)

        return IORESOURCE_MEM | IORESOURCE_PREFETCH;

    return IORESOURCE_MEM;

}

static u32 pci_size(u32 base, u32 maxbase, u32 mask)

{

    u32 size = mask & maxbase;      /* Find the significant bits */

    if (!size)

        return 0;

    /* Get the lowest of them to find the decode size, and

       from that the extent.  */

    size = (size & ~(size-1)) - 1;

    /* base == maxbase can be valid only if the BAR has

       already been programmed with all 1s.  */

    if (base == maxbase && ((base | size) & mask) != mask)

        return 0;

    return size;

}

static u64 pci_size64(u64 base, u64 maxbase, u64 mask)

{

    u64 size = mask & maxbase;      /* Find the significant bits */

    if (!size)

        return 0;

    /* Get the lowest of them to find the decode size, and

       from that the extent.  */

    size = (size & ~(size-1)) - 1;

    /* base == maxbase can be valid only if the BAR has

       already been programmed with all 1s.  */

    if (base == maxbase && ((base | size) & mask) != mask)

        return 0;

    return size;

}

static inline int is_64bit_memory(u32 mask)

{

    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==

        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))

        return 1;

    return 0;

}

static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)

{

    u32  pos, reg, next;

    u32  l, sz;

    struct resource *res;

    for(pos=0; pos < howmany; pos = next)

    {

        u64  l64;

        u64  sz64;

        u32  raw_sz;

        next = pos + 1;

        res  = &dev->resource[pos];

        reg = PCI_BASE_ADDRESS_0 + (pos << 2);

        l = PciRead32(dev->busnr, dev->devfn, reg);

        PciWrite32(dev->busnr, dev->devfn, reg, ~0);

        sz = PciRead32(dev->busnr, dev->devfn, reg);

        PciWrite32(dev->busnr, dev->devfn, reg, l);

        if (!sz || sz == 0xffffffff)

            continue;

        if (l == 0xffffffff)

            l = 0;

        raw_sz = sz;

        if ((l & PCI_BASE_ADDRESS_SPACE) ==

                        PCI_BASE_ADDRESS_SPACE_MEMORY)

        {

            sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);

            /*

             * For 64bit prefetchable memory sz could be 0, if the

             * real size is bigger than 4G, so we need to check

             * szhi for that.

             */

            if (!is_64bit_memory(l) && !sz)

                    continue;

            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;

            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;

        }

        else {

            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);

            if (!sz)

                continue;

            res->start = l & PCI_BASE_ADDRESS_IO_MASK;

            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;

        }

        res->end = res->start + (unsigned long) sz;

        res->flags |= pci_calc_resource_flags(l);

        if (is_64bit_memory(l))

        {

            u32 szhi, lhi;

            lhi = PciRead32(dev->busnr, dev->devfn, reg+4);

            PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);

            szhi = PciRead32(dev->busnr, dev->devfn, reg+4);

            PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);

            sz64 = ((u64)szhi << 32) | raw_sz;

            l64 = ((u64)lhi << 32) | l;

            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);

            next++;

#if BITS_PER_LONG == 64

            if (!sz64) {

                res->start = 0;

                res->end = 0;

                res->flags = 0;

                continue;

            }

            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;

            res->end = res->start + sz64;

#else

            if (sz64 > 0x100000000ULL) {

                printk(KERN_ERR "PCI: Unable to handle 64-bit "

                                "BAR for device %s\n", pci_name(dev));

                res->start = 0;

                res->flags = 0;

            }

            else if (lhi)

            {

                /* 64-bit wide address, treat as disabled */

                PciWrite32(dev->busnr, dev->devfn, reg,

                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);

                PciWrite32(dev->busnr, dev->devfn, reg+4, 0);

                res->start = 0;

                res->end = sz;

            }

#endif

        }

    }

    if ( rom )

    {

        dev->rom_base_reg = rom;

        res = &dev->resource[PCI_ROM_RESOURCE];

        l = PciRead32(dev->busnr, dev->devfn, rom);

        PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);

        sz = PciRead32(dev->busnr, dev->devfn, rom);

        PciWrite32(dev->busnr, dev->devfn, rom, l);

        if (l == 0xffffffff)

            l = 0;

        if (sz && sz != 0xffffffff)

        {

            sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);

            if (sz)

            {

                res->flags = (l & IORESOURCE_ROM_ENABLE) |

                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |

                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;

                res->start = l & PCI_ROM_ADDRESS_MASK;

                res->end = res->start + (unsigned long) sz;

            }

        }

    }

}

static void pci_read_irq(struct pci_dev *dev)

{

    u8 irq;

    irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);

    dev->pin = irq;

    if (irq)

        irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);

    dev->irq = irq;

};

int pci_setup_device(struct pci_dev *dev)

{

    u32  class;

    class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);

    dev->revision = class & 0xff;

    class >>= 8;                                /* upper 3 bytes */

    dev->class = class;

    /* "Unknown power state" */

//    dev->current_state = PCI_UNKNOWN;

    /* Early fixups, before probing the BARs */

 //   pci_fixup_device(pci_fixup_early, dev);

    class = dev->class >> 8;

    switch (dev->hdr_type)

    {

        case PCI_HEADER_TYPE_NORMAL:                /* standard header */

            if (class == PCI_CLASS_BRIDGE_PCI)

                goto bad;