WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/main.c

Rev	Author	Line No.	Line
6084	serge	1	#include
		2
3031	serge	3	#include
		4	#include
2338	Serge	5	#include "i915_drv.h"
		6
2325	Serge	7	#include
		8	#include
		9	#include
		10	#include
		11
6088	serge	12	#include "getopt.h"
		13
2342	Serge	14	#include "bitmap.h"
6088	serge	15	#include "i915_kos32.h"
2340	Serge	16
6084	serge	17	#define DRV_NAME "i915 v4.4"
		18
5060	serge	19	#define I915_DEV_CLOSE 0
		20	#define I915_DEV_INIT 1
		21	#define I915_DEV_READY 2
		22
6088	serge	23	static int my_atoi(char **cmd);
		24	static char* parse_mode(char p, videomode_t mode);
5354	serge	25	void cpu_detect1();
		26	int kmap_init();
2344	Serge	27
5060	serge	28	unsigned long volatile jiffies;
6088	serge	29	int oops_in_progress;
		30	int x86_clflush_size;
		31	unsigned int tsc_khz;
3482	Serge	32	struct workqueue_struct *system_wq;
3764	Serge	33	int driver_wq_state;
6088	serge	34	struct drm_device *main_device;
		35	struct drm_file *drm_file_handlers[256];
		36	videomode_t usermode;
		37	extern int __getopt_initialized;
3482	Serge	38
4126	Serge	39	void i915_driver_thread()
		40	{
5060	serge	41	struct drm_i915_private *dev_priv = NULL;
		42	struct workqueue_struct *cwq = NULL;
4126	Serge	43	static int dpms = 1;
		44	static int dpms_lock = 0;
		45	oskey_t key;
		46	unsigned long irqflags;
		47	int tmp;
		48
		49	printf("%s\n",__FUNCTION__);
		50
5060	serge	51	while(driver_wq_state == I915_DEV_INIT)
		52	{
6084	serge	53	jiffies = GetClockNs() / 10000000;
5060	serge	54	delay(1);
		55	};
		56
6084	serge	57	if( driver_wq_state == I915_DEV_CLOSE)
		58	{
		59	asm volatile ("int $0x40"::"a"(-1));
		60	};
		61
5060	serge	62	dev_priv = main_device->dev_private;
		63	cwq = dev_priv->wq;
		64
4126	Serge	65	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
		66	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
		67	asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
		68
5060	serge	69	while(driver_wq_state != I915_DEV_CLOSE)
4126	Serge	70	{
6084	serge	71	jiffies = GetClockNs() / 10000000;
5060	serge	72
4126	Serge	73	key = get_key();
		74
		75	if( (key.val != 1) && (key.state == 0x02))
		76	{
		77	if(key.code == 0x46 && dpms_lock == 0)
		78	{
		79	dpms_lock = 1;
		80	if(dpms == 1)
		81	{
		82	i915_dpms(main_device, DRM_MODE_DPMS_OFF);
		83	printf("dpms off\n");
		84	}
		85	else
		86	{
		87	i915_dpms(main_device, DRM_MODE_DPMS_ON);
		88	printf("dpms on\n");
		89	};
		90	dpms ^= 1;
		91	}
		92	else if(key.code == 0xC6)
		93	dpms_lock = 0;
		94	};
		95
		96	spin_lock_irqsave(&cwq->lock, irqflags);
		97
		98	while (!list_empty(&cwq->worklist))
		99	{
		100	struct work_struct *work = list_entry(cwq->worklist.next,
		101	struct work_struct, entry);
		102	work_func_t f = work->func;
		103	list_del_init(cwq->worklist.next);
		104
		105	spin_unlock_irqrestore(&cwq->lock, irqflags);
		106	f(work);
		107	spin_lock_irqsave(&cwq->lock, irqflags);
		108	}
		109
		110	spin_unlock_irqrestore(&cwq->lock, irqflags);
		111
		112	delay(1);
		113	};
		114
		115	asm volatile ("int $0x40"::"a"(-1));
		116	}
		117
5354	serge	118	u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
2325	Serge	119	{
5060	serge	120	static pci_dev_t device;
		121	const struct pci_device_id *ent;
6088	serge	122	char *safecmdline;
4104	Serge	123	int err = 0;
2325	Serge	124
		125	if(action != 1)
3764	Serge	126	{
5060	serge	127	driver_wq_state = I915_DEV_CLOSE;
2325	Serge	128	return 0;
3764	Serge	129	};
2325	Serge	130
		131	if( GetService("DISPLAY") != 0 )
		132	return 0;
		133
6084	serge	134	printf("\n%s build %s %s\nusage: i915 [options]\n"
6088	serge	135	"-f\n"
		136	"--fbsize <0-9> Set framebuffer size in megabytes (default: 16)\n",
6084	serge	137	DRV_NAME, __DATE__, __TIME__);
		138
6088	serge	139	printf("--rc6 <-1,0-7> Enable power-saving render C-state 6.\n"
		140	" Different stages can be selected via bitmask values\n"
		141	" (0 = disable; 1 = enable rc6; 2 = enable deep rc6;\n"
		142	" 4 = enable deepest rc6).\n"
		143	" For example, 3 would enable rc6 and deep rc6,\n"
		144	" and 7 would enable everything.\n"
		145	" default: -1 (use per-chip default)\n");
		146	printf("--fbc <-1,0,1> Enable frame buffer compression for power savings\n"
		147	" (default: -1 (use per-chip default))\n");
		148	printf("-l\n"
		149	"--log path to log file\n");
		150	printf("-m\n"
		151	"--mode set videomode\n");
		152	printf("-v\n"
		153	"--video :x[M][R][-][@][i][m][eDd]\n"
		154	" set videomode for CONNECTOR\n");
6084	serge	155
2340	Serge	156	if( cmdline && *cmdline )
6088	serge	157	{
		158	int argc, i, c;
		159	char **argv;
2325	Serge	160
6088	serge	161	safecmdline = __builtin_strdup(cmdline);
		162	printf("cmdline %s\n", safecmdline);
		163
		164	argc = split_cmdline(safecmdline, NULL);
		165	argv = __builtin_malloc((argc+1)sizeof(char));
		166	split_cmdline(safecmdline, argv);
		167	argv[argc] = NULL;
		168
		169	while(1)
		170	{
		171	static struct option long_options[] =
		172	{
		173	{"log", required_argument, 0, 'l'},
		174	{"mode", required_argument, 0, 'm'},
		175	{"fbsize",required_argument, 0, 'f'},
		176	{"video", required_argument, 0, 'v'},
		177	{"rc6", required_argument, 0, OPTION_RC6},
		178	{"fbc", required_argument, 0, OPTION_FBC},
		179	{0, 0, 0, 0}
		180	};
		181
		182	int option_index = 0;
		183
		184	c = getopt_long (argc, argv, "f:l:m:v:",
		185	long_options, &option_index);
		186
		187	if (c == -1)
		188	break;
		189
		190	switch(c)
		191	{
		192	case OPTION_RC6:
		193	i915.enable_rc6 = my_atoi(&optarg);
		194	printf("i915.rc6 = %d\n",i915.enable_rc6);
		195	break;
		196
		197	case OPTION_FBC:
		198	i915.enable_fbc = my_atoi(&optarg);
		199	printf("i915.fbc = %d\n",i915.enable_fbc);
		200	break;
		201
		202	case 'f':
		203	i915.fbsize = my_atoi(&optarg);
		204	printf("i915.fbsize =%d\n",i915.fbsize);
		205	break;
		206
		207	case 'l':
		208	i915.log_file = optarg;
		209	break;
		210
		211	case 'm':
		212	parse_mode(optarg, &usermode);
		213	break;
		214
		215	case 'v':
		216	i915.cmdline_mode = optarg;
		217	printf("i915.cmdline_mode =%s\n",i915.cmdline_mode);
		218	break;
		219	}
		220	}
		221	};
		222
		223	if( i915.log_file && !dbg_open(i915.log_file))
6084	serge	224	{
6088	serge	225	printf("Can't open %s\nExit\n", i915.log_file);
6084	serge	226	return 0;
2325	Serge	227	}
6084	serge	228	else
		229	{
		230	dbgprintf("\nLOG: %s build %s %s\n",DRV_NAME,__DATE__, __TIME__);
		231	}
2325	Serge	232
5354	serge	233	cpu_detect1();
2351	Serge	234
5060	serge	235	err = enum_pci_devices();
		236	if( unlikely(err != 0) )
		237	{
		238	dbgprintf("Device enumeration failed\n");
		239	return 0;
		240	}
2325	Serge	241
5354	serge	242	err = kmap_init();
		243	if( unlikely(err != 0) )
		244	{
		245	dbgprintf("kmap initialization failed\n");
		246	return 0;
		247	}
		248
5097	serge	249	dmi_scan_machine();
		250
5060	serge	251	driver_wq_state = I915_DEV_INIT;
		252	CreateKernelThread(i915_driver_thread);
		253
2325	Serge	254	err = i915_init();
5060	serge	255	if(unlikely(err!= 0))
2338	Serge	256	{
5060	serge	257	driver_wq_state = I915_DEV_CLOSE;
3298	Serge	258	dbgprintf("Epic Fail :(\n");
6084	serge	259	delay(100);
3298	Serge	260	return 0;
2338	Serge	261	};
2325	Serge	262
5060	serge	263	driver_wq_state = I915_DEV_READY;
		264
4280	Serge	265	init_display_kms(main_device, &usermode);
		266
2338	Serge	267	err = RegService("DISPLAY", display_handler);
2325	Serge	268
2338	Serge	269	if( err != 0)
		270	dbgprintf("Set DISPLAY handler\n");
		271
2325	Serge	272	return err;
		273	};
		274
6088	serge	275	int do_command_line(const char* usercmd)
		276	{
		277	char *cmdline;
		278	int argc, i, c;
		279	char **argv;
6103	serge	280	int retval = 0;
3480	Serge	281
6088	serge	282	if( (usercmd == NULL) \|\| (*usercmd == 0) )
		283	return 1;
		284
		285	cmdline = __builtin_strdup(usercmd);
		286	printf("cmdline %s\n", cmdline);
		287
		288	argc = split_cmdline(cmdline, NULL);
		289	argv = __builtin_malloc((argc+1)sizeof(char));
		290	split_cmdline(cmdline, argv);
		291	argv[argc] = NULL;
		292
		293	__getopt_initialized = 0;
		294
		295	while(1)
		296	{
		297	static struct option long_options[] =
		298	{
6103	serge	299	{"list-connectors", no_argument, 0, OPTION_CONNECTORS},
		300	{"list-connector-modes", required_argument, 0, OPTION_CONN_MODES},
		301	{"video", required_argument, 0, 'v'},
6088	serge	302	{0, 0, 0, 0}
		303	};
		304
		305	int option_index = 0;
		306
		307	c = getopt_long (argc, argv, "v:",
		308	long_options, &option_index);
		309
		310	if (c == -1)
		311	break;
		312
		313	switch(c)
		314	{
		315	case 'v':
		316	printf("cmdline_mode %s\n",optarg);
6103	serge	317	retval = set_cmdline_mode_ext(main_device, optarg);
6088	serge	318	break;
6103	serge	319
		320	case OPTION_CONNECTORS:
		321	list_connectors(main_device);
		322	break;
		323
		324	case OPTION_CONN_MODES:
		325	retval = list_connector_modes(main_device, optarg);
		326	break;
6088	serge	327	}
		328	}
		329	__builtin_free(argv);
		330	__builtin_free(cmdline);
		331
6103	serge	332	return retval;
6088	serge	333	};
		334
2344	Serge	335	#define CURRENT_API 0x0200 /* 2.00 */
		336	#define COMPATIBLE_API 0x0100 /* 1.00 */
2338	Serge	337
2344	Serge	338	#define API_VERSION (COMPATIBLE_API << 16) \| CURRENT_API
2351	Serge	339	#define DISPLAY_VERSION API_VERSION
2338	Serge	340
		341
6084	serge	342	#define SRV_GETVERSION 0
		343	#define SRV_ENUM_MODES 1
		344	#define SRV_SET_MODE 2
		345	#define SRV_GET_CAPS 3
6088	serge	346	#define SRV_CMDLINE 4
2342	Serge	347
6084	serge	348	#define SRV_GET_PCI_INFO 20
4246	Serge	349	#define SRV_I915_GET_PARAM 21
6084	serge	350	#define SRV_I915_GEM_CREATE 22
		351	#define SRV_DRM_GEM_CLOSE 23
4246	Serge	352	#define SRV_DRM_GEM_FLINK 24
		353	#define SRV_DRM_GEM_OPEN 25
		354	#define SRV_I915_GEM_PIN 26
		355	#define SRV_I915_GEM_UNPIN 27
5367	serge	356	#define SRV_I915_GEM_GET_CACHING 28
		357	#define SRV_I915_GEM_SET_CACHING 29
		358	#define SRV_I915_GEM_PWRITE 30
		359	#define SRV_I915_GEM_BUSY 31
		360	#define SRV_I915_GEM_SET_DOMAIN 32
		361	#define SRV_I915_GEM_MMAP 33
		362	#define SRV_I915_GEM_SET_TILING 34
		363	#define SRV_I915_GEM_GET_TILING 35
		364	#define SRV_I915_GEM_GET_APERTURE 36
		365	#define SRV_I915_GEM_MMAP_GTT 37
		366	#define SRV_I915_GEM_THROTTLE 38
		367	#define SRV_I915_GEM_EXECBUFFER2 39
		368	#define SRV_I915_GEM_WAIT 40
		369	#define SRV_I915_GEM_CONTEXT_CREATE 41
		370	#define SRV_I915_GEM_CONTEXT_DESTROY 42
		371	#define SRV_I915_REG_READ 43
3260	Serge	372
5367	serge	373	#define SRV_FBINFO 44
		374	#define SRV_MASK_UPDATE 45
		375	#define SRV_MASK_UPDATE_EX 46
3263	Serge	376
2338	Serge	377	#define check_input(size) \
		378	if( unlikely((inp==NULL)\|\|(io->inp_size != (size))) ) \
		379	break;
		380
		381	#define check_output(size) \
		382	if( unlikely((outp==NULL)\|\|(io->out_size != (size))) ) \
		383	break;
		384
		385	int _stdcall display_handler(ioctl_t *io)
		386	{
3255	Serge	387	struct drm_file *file;
		388
6084	serge	389	int retval = -1;
5354	serge	390	u32 *inp;
		391	u32 *outp;
2338	Serge	392
		393	inp = io->input;
		394	outp = io->output;
		395
3255	Serge	396	file = drm_file_handlers[0];
		397
2338	Serge	398	switch(io->io_code)
		399	{
		400	case SRV_GETVERSION:
		401	check_output(4);
2344	Serge	402	*outp = DISPLAY_VERSION;
2338	Serge	403	retval = 0;
		404	break;
		405
		406	case SRV_ENUM_MODES:
3031	serge	407	// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		408	// inp, io->inp_size, io->out_size );
2340	Serge	409	check_output(4);
2338	Serge	410	// check_input(outp sizeof(videomode_t));
6088	serge	411	retval = get_videomodes((videomode_t*)inp, outp);
2338	Serge	412	break;
		413
		414	case SRV_SET_MODE:
3031	serge	415	// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		416	// inp, io->inp_size);
2338	Serge	417	check_input(sizeof(videomode_t));
6088	serge	418	retval = set_user_mode((videomode_t*)inp);
2338	Serge	419	break;
3033	serge	420
2351	Serge	421	case SRV_GET_CAPS:
		422	retval = get_driver_caps((hwcaps_t*)inp);
		423	break;
		424
6088	serge	425	case SRV_CMDLINE:
		426	retval = do_command_line((char*)inp);
		427	break;
		428
3260	Serge	429	case SRV_GET_PCI_INFO:
3255	Serge	430	get_pci_info((struct pci_device *)inp);
2338	Serge	431	retval = 0;
		432	break;
3031	serge	433
4246	Serge	434	case SRV_I915_GET_PARAM:
		435	retval = i915_getparam(main_device, inp, file);
3255	Serge	436	break;
		437
		438	case SRV_I915_GEM_CREATE:
		439	retval = i915_gem_create_ioctl(main_device, inp, file);
		440	break;
		441
		442	case SRV_DRM_GEM_CLOSE:
		443	retval = drm_gem_close_ioctl(main_device, inp, file);
		444	break;
		445
4246	Serge	446	case SRV_DRM_GEM_FLINK:
		447	retval = drm_gem_flink_ioctl(main_device, inp, file);
		448	break;
		449
		450	case SRV_DRM_GEM_OPEN:
		451	retval = drm_gem_open_ioctl(main_device, inp, file);
		452	break;
		453
5367	serge	454	case SRV_I915_GEM_GET_CACHING:
		455	retval = i915_gem_get_caching_ioctl(main_device, inp, file);
		456	break;
		457
4246	Serge	458	case SRV_I915_GEM_SET_CACHING:
		459	retval = i915_gem_set_caching_ioctl(main_device, inp, file);
3260	Serge	460	break;
		461
		462	case SRV_I915_GEM_PWRITE:
		463	retval = i915_gem_pwrite_ioctl(main_device, inp, file);
		464	break;
		465
		466	case SRV_I915_GEM_BUSY:
		467	retval = i915_gem_busy_ioctl(main_device, inp, file);
		468	break;
		469
		470	case SRV_I915_GEM_SET_DOMAIN:
		471	retval = i915_gem_set_domain_ioctl(main_device, inp, file);
		472	break;
		473
3263	Serge	474	case SRV_I915_GEM_MMAP:
		475	retval = i915_gem_mmap_ioctl(main_device, inp, file);
		476	break;
		477
4246	Serge	478	case SRV_I915_GEM_SET_TILING:
		479	retval = i915_gem_set_tiling(main_device, inp, file);
		480	break;
		481
		482	case SRV_I915_GEM_GET_TILING:
		483	retval = i915_gem_get_tiling(main_device, inp, file);
		484	break;
		485
		486	case SRV_I915_GEM_GET_APERTURE:
		487	// printf("SRV_I915_GEM_GET_APERTURE ");
		488	retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
		489	// printf(" retval=%d\n", retval);
		490	break;
		491
3480	Serge	492	case SRV_I915_GEM_MMAP_GTT:
		493	retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
		494	break;
		495
4246	Serge	496	case SRV_I915_GEM_THROTTLE:
		497	retval = i915_gem_throttle_ioctl(main_device, inp, file);
3263	Serge	498	break;
		499
		500	case SRV_I915_GEM_EXECBUFFER2:
4246	Serge	501	// printf("SRV_I915_GEM_EXECBUFFER2\n");
3263	Serge	502	retval = i915_gem_execbuffer2(main_device, inp, file);
		503	break;
		504
4246	Serge	505	case SRV_I915_GEM_WAIT:
		506	retval = i915_gem_wait_ioctl(main_device, inp, file);
		507	break;
		508
		509	case SRV_I915_GEM_CONTEXT_CREATE:
		510	retval = i915_gem_context_create_ioctl(main_device, inp, file);
		511	break;
		512
		513	case SRV_I915_GEM_CONTEXT_DESTROY:
		514	retval = i915_gem_context_destroy_ioctl(main_device, inp, file);
		515	break;
		516
		517	case SRV_I915_REG_READ:
		518	retval = i915_reg_read_ioctl(main_device, inp, file);
		519	break;
		520
		521	case SRV_FBINFO:
		522	retval = i915_fbinfo(inp);
		523	break;
		524
3290	Serge	525	case SRV_MASK_UPDATE:
		526	retval = i915_mask_update(main_device, inp, file);
		527	break;
4539	Serge	528
		529	case SRV_MASK_UPDATE_EX:
		530	retval = i915_mask_update_ex(main_device, inp, file);
		531	break;
2338	Serge	532	};
		533
		534	return retval;
		535	}
		536
		537
2325	Serge	538	#define PCI_CLASS_REVISION 0x08
		539	#define PCI_CLASS_DISPLAY_VGA 0x0300
		540	#define PCI_CLASS_BRIDGE_HOST 0x0600
2326	Serge	541	#define PCI_CLASS_BRIDGE_ISA 0x0601
2325	Serge	542
5354	serge	543	int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
2325	Serge	544	{
5354	serge	545	u16 vendor, device;
		546	u32 class;
2325	Serge	547	int ret = 0;
		548
		549	vendor = id & 0xffff;
		550	device = (id >> 16) & 0xffff;
		551
		552	if(vendor == 0x8086)
		553	{
		554	class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
		555	class >>= 16;
		556
		557	if( (class == PCI_CLASS_DISPLAY_VGA) \|\|
2326	Serge	558	(class == PCI_CLASS_BRIDGE_HOST) \|\|
		559	(class == PCI_CLASS_BRIDGE_ISA))
2325	Serge	560	ret = 1;
		561	}
		562	return ret;
		563	};
2340	Serge	564
		565
5060	serge	566	struct mtrr
		567	{
5354	serge	568	u64 base;
		569	u64 mask;
5060	serge	570	};
		571
		572	struct cpuinfo
		573	{
5354	serge	574	u64 caps;
		575	u64 def_mtrr;
		576	u64 mtrr_cap;
5060	serge	577	int var_mtrr_count;
		578	int fix_mtrr_count;
		579	struct mtrr var_mtrr[9];
		580	char model_name[64];
		581	};
		582
		583	#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
		584	#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
		585
		586	#define MSR_MTRRdefType 0x000002ff
		587
		588	#define IA32_MTRRCAP 0xFE
		589	#define IA32_CR_PAT_MSR 0x277
		590
		591	#define PAT_TYPE_UC 0
		592	#define PAT_TYPE_WC 1
		593	#define PAT_TYPE_WB 6
		594	#define PAT_TYPE_UCM 7
		595
		596
		597	#define MTRR_UC 0
		598	#define MTRR_WC 1
		599	#define MTRR_WB 6
		600
5354	serge	601	static inline u64 read_msr(u32 msr)
5060	serge	602	{
		603	union {
5354	serge	604	u64 val;
5060	serge	605	struct {
5354	serge	606	u32 low;
		607	u32 high;
5060	serge	608	};
		609	}tmp;
		610
		611	asm volatile (
		612	"rdmsr"
		613	: "=a" (tmp.low), "=d" (tmp.high)
		614	: "c" (msr));
		615	return tmp.val;
		616	}
		617
5354	serge	618	static inline void write_msr(u32 msr, u64 val)
5060	serge	619	{
		620	union {
5354	serge	621	u64 val;
5060	serge	622	struct {
5354	serge	623	u32 low;
		624	u32 high;
5060	serge	625	};
		626	}tmp;
		627
		628	tmp.val = val;
		629
		630	asm volatile (
		631	"wrmsr"
		632	:: "a" (tmp.low), "d" (tmp.high), "c" (msr));
		633	}
		634
		635	#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
		636
		637	static void set_mtrr(unsigned int reg, unsigned long base,
		638	unsigned long size, int type)
		639	{
		640	unsigned int base_lo, base_hi, mask_lo, mask_hi;
		641	u64 size_or_mask, size_and_mask;
		642
		643	size_or_mask = SIZE_OR_MASK_BITS(36);
		644	size_and_mask = 0x00f00000;
		645
		646	if (size == 0) {
		647	/*
		648	* The invalid bit is kept in the mask, so we simply
		649	* clear the relevant mask register to disable a range.
		650	*/
		651	native_write_msr(MTRRphysMask_MSR(reg), 0, 0);
		652	}
		653	else {
		654	base_lo = base << PAGE_SHIFT \| type;
		655	base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
		656	mask_lo = -size << PAGE_SHIFT \| 0x800;
		657	mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
		658
		659	native_write_msr(MTRRphysBase_MSR(reg), base_lo, base_hi);
		660	native_write_msr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
		661	};
		662	}
		663
		664
		665	static u32 deftype_lo, deftype_hi;
		666
5354	serge	667	void cpu_detect1()
2344	Serge	668	{
5060	serge	669	struct cpuinfo cpuinfo;
		670
2344	Serge	671	u32 junk, tfms, cap0, misc;
5060	serge	672	int i;
5354	serge	673
2344	Serge	674	cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
		675
		676	if (cap0 & (1<<19))
		677	{
		678	x86_clflush_size = ((misc >> 8) & 0xff) * 8;
		679	}
3482	Serge	680
5354	serge	681	#if 0
5060	serge	682	cpuid(0x80000002, (unsigned int)&cpuinfo.model_name[0], (unsigned int)&cpuinfo.model_name[4],
		683	(unsigned int)&cpuinfo.model_name[8], (unsigned int)&cpuinfo.model_name[12]);
		684	cpuid(0x80000003, (unsigned int)&cpuinfo.model_name[16], (unsigned int)&cpuinfo.model_name[20],
		685	(unsigned int)&cpuinfo.model_name[24], (unsigned int)&cpuinfo.model_name[28]);
		686	cpuid(0x80000004, (unsigned int)&cpuinfo.model_name[32], (unsigned int)&cpuinfo.model_name[36],
		687	(unsigned int)&cpuinfo.model_name[40], (unsigned int)&cpuinfo.model_name[44]);
		688
		689	printf("\n%s\n\n",cpuinfo.model_name);
		690
		691	cpuinfo.def_mtrr = read_msr(MSR_MTRRdefType);
		692	cpuinfo.mtrr_cap = read_msr(IA32_MTRRCAP);
		693
		694	printf("MSR_MTRRdefType %016llx\n\n", cpuinfo.def_mtrr);
		695
		696	cpuinfo.var_mtrr_count = (u8_t)cpuinfo.mtrr_cap;
		697
		698	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		699	{
		700	u64_t mtrr_base;
		701	u64_t mtrr_mask;
		702
		703	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		704	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		705
		706	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		707	cpuinfo.var_mtrr[i].base,
		708	cpuinfo.var_mtrr[i].mask);
		709	};
		710
		711	unsigned int cr0, cr3, cr4, eflags;
		712
		713	eflags = safe_cli();
		714
		715	/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
		716	cr0 = read_cr0() \| (1<<30);
		717	write_cr0(cr0);
		718	wbinvd();
		719
		720	cr4 = read_cr4();
		721	write_cr4(cr4 & ~(1<<7));
		722
		723	cr3 = read_cr3();
		724	write_cr3(cr3);
		725
		726	/* Save MTRR state */
		727	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		728
		729	/* Disable MTRRs, and set the default type to uncached */
		730	native_write_msr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
		731	wbinvd();
		732
		733	i = 0;
		734	set_mtrr(i++,0,0x80000000>>12,MTRR_WB);
		735	set_mtrr(i++,0x80000000>>12,0x40000000>>12,MTRR_WB);
		736	set_mtrr(i++,0xC0000000>>12,0x20000000>>12,MTRR_WB);
		737	set_mtrr(i++,0xdb800000>>12,0x00800000>>12,MTRR_UC);
		738	set_mtrr(i++,0xdc000000>>12,0x04000000>>12,MTRR_UC);
		739	set_mtrr(i++,0xE0000000>>12,0x10000000>>12,MTRR_WC);
		740
		741	for(; i < cpuinfo.var_mtrr_count; i++)
		742	set_mtrr(i,0,0,0);
		743
		744	write_cr3(cr3);
		745
		746	/* Intel (P6) standard MTRRs */
		747	native_write_msr(MSR_MTRRdefType, deftype_lo, deftype_hi);
		748
		749	/* Enable caches */
		750	write_cr0(read_cr0() & ~(1<<30));
		751
		752	/* Restore value of CR4 */
		753	write_cr4(cr4);
		754
		755	safe_sti(eflags);
		756
		757	printf("\nnew MTRR map\n\n");
		758
		759	for(i = 0; i < cpuinfo.var_mtrr_count; i++)
		760	{
		761	u64_t mtrr_base;
		762	u64_t mtrr_mask;
		763
		764	cpuinfo.var_mtrr[i].base = read_msr(MTRRphysBase_MSR(i));
		765	cpuinfo.var_mtrr[i].mask = read_msr(MTRRphysMask_MSR(i));
		766
		767	printf("MTRR_%d base: %016llx mask: %016llx\n", i,
		768	cpuinfo.var_mtrr[i].base,
		769	cpuinfo.var_mtrr[i].mask);
		770	};
		771	#endif
		772
3482	Serge	773	tsc_khz = (unsigned int)(GetCpuFreq()/1000);
2344	Serge	774	}
		775
3243	Serge	776
		777	int get_driver_caps(hwcaps_t *caps)
		778	{
		779	int ret = 0;
		780
		781	switch(caps->idx)
		782	{
		783	case 0:
		784	caps->opt[0] = 0;
		785	caps->opt[1] = 0;
		786	break;
		787
		788	case 1:
		789	caps->cap1.max_tex_width = 4096;
		790	caps->cap1.max_tex_height = 4096;
		791	break;
		792	default:
		793	ret = 1;
		794	};
		795	caps->idx = 1;
		796	return ret;
		797	}
		798
3255	Serge	799
		800	void get_pci_info(struct pci_device *dev)
		801	{
		802	struct pci_dev *pdev = main_device->pdev;
		803
		804	memset(dev, sizeof(*dev), 0);
		805
		806	dev->domain = 0;
		807	dev->bus = pdev->busnr;
		808	dev->dev = pdev->devfn >> 3;
		809	dev->func = pdev->devfn & 7;
		810	dev->vendor_id = pdev->vendor;
		811	dev->device_id = pdev->device;
		812	dev->revision = pdev->revision;
		813	};
4246	Serge	814
		815
		816
4280	Serge	817	char strstr(const char cs, const char *ct);
		818
		819	static int my_atoi(char **cmd)
		820	{
		821	char* p = *cmd;
		822	int val = 0;
		823	int sign = 1;
		824
		825	if(*p == '-')
		826	{
		827	sign = -1;
		828	p++;
		829	};
		830
		831	for (;; *p++) {
		832	switch (*p) {
		833	case '0' ... '9':
		834	val = 10val+(p-'0');
		835	break;
		836	default:
		837	*cmd = p;
		838	return val*sign;
		839	}
		840	}
		841	}
		842
6088	serge	843	static char* parse_mode(char p, videomode_t mode)
4280	Serge	844	{
		845	char c;
		846
		847	while( (c = *p++) == ' ');
		848
		849	if( c )
		850	{
		851	p--;
		852
		853	mode->width = my_atoi(&p);
		854	if(*p == 'x') p++;
		855
		856	mode->height = my_atoi(&p);
		857	if(*p == 'x') p++;
		858
		859	mode->bpp = 32;
		860
		861	mode->freq = my_atoi(&p);
		862
		863	if( mode->freq == 0 )
		864	mode->freq = 60;
		865	}
		866
		867	return p;
		868	};
		869

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