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2340 Serge 1
 
2
3
 
2338 Serge 4
#include "drm.h"
5
#include "i915_drm.h"
6
#include "i915_drv.h"
7
#include "intel_drv.h"
8
9
 
10
#include 
11
#include 
12
#include 
13
#include 
14
15
 
16
17
 
3033 serge 18
#include "bitmap.h"
2340 Serge 19
2338 Serge 20
 
2351 Serge 21
2338 Serge 22
 
2351 Serge 23
 
2338 Serge 24
{
25
    kobj_t     header;
26
27
 
28
    uint32_t   hot_x;
29
    uint32_t   hot_y;
30
31
 
32
    struct drm_i915_gem_object  *cobj;
33
}cursor_t;
34
35
 
36
#define CURSOR_HEIGHT 64
37
38
 
39
 
40
{
41
    int  x;
42
    int  y;
43
    int  width;
44
    int  height;
45
    int  bpp;
46
    int  vrefresh;
47
    int  pitch;
48
    int  lfb;
49
50
 
51
    struct drm_device    *ddev;
52
    struct drm_connector *connector;
53
    struct drm_crtc      *crtc;
54
55
 
56
57
 
58
    int       (*init_cursor)(cursor_t*);
59
    cursor_t* (__stdcall *select_cursor)(cursor_t*);
60
    void      (*show_cursor)(int show);
61
    void      (__stdcall *move_cursor)(cursor_t *cursor, int x, int y);
62
    void      (__stdcall *restore_cursor)(int x, int y);
63
    void      (*disable_mouse)(void);
64
    u32  mask_seqno;
2361 Serge 65
    u32  check_mouse;
3031 serge 66
    u32  check_m_pixel;
67
68
 
2338 Serge 69
70
 
71
 
72
73
 
2340 Serge 74
u32_t cmd_offset;
75
76
 
2351 Serge 77
int  sna_init();
78
79
 
2338 Serge 80
static cursor_t*  __stdcall select_cursor_kms(cursor_t *cursor);
81
static void       __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
82
83
 
84
{};
85
86
 
87
{};
88
89
 
3031 serge 90
{
91
    static char name[4];
92
93
 
94
    name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@';
95
    name[2] = (x[1] & 0x1F) + '@';
96
    name[3] = 0;
97
98
 
99
}
100
101
 
102
              videomode_t *reqmode, bool strict)
103
{
104
    drm_i915_private_t      *dev_priv   = dev->dev_private;
105
    struct drm_fb_helper    *fb_helper  = &dev_priv->fbdev->helper;
106
107
 
108
    struct drm_display_mode *mode       = NULL, *tmpmode;
109
    struct drm_framebuffer  *fb         = NULL;
110
    struct drm_crtc         *crtc;
111
    struct drm_encoder      *encoder;
112
    struct drm_mode_set     set;
113
    char *con_name;
114
    char *enc_name;
115
    unsigned hdisplay, vdisplay;
116
    int ret;
117
118
 
119
120
 
121
    {
122
        if( (drm_mode_width(tmpmode)    == reqmode->width)  &&
123
            (drm_mode_height(tmpmode)   == reqmode->height) &&
124
            (drm_mode_vrefresh(tmpmode) == reqmode->freq) )
125
        {
126
            mode = tmpmode;
127
            goto do_set;
128
        }
129
    };
130
131
 
132
    {
133
        list_for_each_entry(tmpmode, &connector->modes, head)
134
        {
135
            if( (drm_mode_width(tmpmode)  == reqmode->width)  &&
136
                (drm_mode_height(tmpmode) == reqmode->height) )
137
            {
138
                mode = tmpmode;
139
                goto do_set;
140
            }
141
        };
142
    };
143
144
 
3037 serge 145
3031 serge 146
 
147
148
 
149
150
 
151
 
152
    crtc = encoder->crtc;
153
154
 
155
    enc_name = drm_get_encoder_name(encoder);
156
157
 
158
              reqmode->width, reqmode->height, crtc->base.id,
159
              con_name, enc_name);
160
161
 
162
163
 
164
    vdisplay = mode->vdisplay;
165
166
 
167
        swap(hdisplay, vdisplay);
168
169
 
170
171
 
172
    fb->height = reqmode->height;
173
    fb->pitches[0]  = ALIGN(reqmode->width * 4, 64);
174
    fb->pitches[1]  = ALIGN(reqmode->width * 4, 64);
175
    fb->pitches[2]  = ALIGN(reqmode->width * 4, 64);
176
    fb->pitches[3]  = ALIGN(reqmode->width * 4, 64);
177
178
 
179
    fb->depth = 24;
180
181
 
182
    crtc->enabled = true;
183
    os_display->crtc = crtc;
184
185
 
186
    set.x = 0;
187
    set.y = 0;
188
    set.mode = mode;
189
    set.connectors = &connector;
190
    set.num_connectors = 1;
191
    set.fb = fb;
192
    ret = crtc->funcs->set_config(&set);
193
    mutex_unlock(&dev->mode_config.mutex);
194
195
 
196
    {
197
        os_display->width    = fb->width;
198
        os_display->height   = fb->height;
199
        os_display->pitch    = fb->pitches[0];
200
        os_display->vrefresh = drm_mode_vrefresh(mode);
201
202
 
203
204
 
3037 serge 205
                       fb->width, fb->height, fb->pitches[0]);
3031 serge 206
    }
207
    else
208
        DRM_ERROR("failed to set mode %d_%d on crtc %p\n",
209
                   fb->width, fb->height, crtc);
210
211
 
212
 
213
}
214
215
 
2338 Serge 216
{
217
    struct drm_display_mode  *mode;
218
    int count = 0;
219
220
 
221
    {
222
        count++;
223
    };
224
    return count;
225
};
226
227
 
3031 serge 228
{
229
    struct drm_connector  *connector;
230
    struct drm_connector_helper_funcs *connector_funcs;
231
232
 
233
234
 
235
    {
236
        struct drm_encoder  *encoder;
237
        struct drm_crtc     *crtc;
238
239
 
240
            continue;
241
242
 
243
        encoder = connector_funcs->best_encoder(connector);
244
        if( encoder == NULL)
245
            continue;
246
247
 
248
249
 
250
251
 
3037 serge 252
                   connector, connector->base.id,
3031 serge 253
                   connector->status, connector->encoder,
254
                   crtc);
255
256
 
257
//            continue;
258
259
 
260
261
 
262
    };
263
264
 
265
};
266
267
 
268
 
2338 Serge 269
{
270
    struct drm_connector    *connector;
271
    struct drm_connector_helper_funcs *connector_funcs;
272
    struct drm_encoder      *encoder;
273
    struct drm_crtc         *crtc = NULL;
274
    struct drm_framebuffer  *fb;
275
276
 
277
    u32_t      ifl;
278
    int        err;
3033 serge 279
2338 Serge 280
 
281
    {
282
        if( connector->status != connector_status_connected)
283
            continue;
284
285
 
286
        encoder = connector_funcs->best_encoder(connector);
287
        if( encoder == NULL)
288
        {
289
            DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n",
3037 serge 290
                      connector, connector->base.id);
2338 Serge 291
            continue;
292
        }
293
        connector->encoder = encoder;
294
        crtc = encoder->crtc;
3031 serge 295
2338 Serge 296
 
3037 serge 297
               connector, connector->base.id,
2338 Serge 298
               connector->status, connector->encoder,
299
               crtc, crtc->base.id );
3031 serge 300
2338 Serge 301
 
302
    };
303
304
 
305
    {
306
        DRM_ERROR("No active connectors!\n");
3037 serge 307
        return -1;
2338 Serge 308
    };
309
310
 
311
    {
312
        struct drm_crtc *tmp_crtc;
313
        int crtc_mask = 1;
314
315
 
316
        {
317
            if (encoder->possible_crtcs & crtc_mask)
318
            {
319
                crtc = tmp_crtc;
320
                encoder->crtc = crtc;
321
                break;
322
            };
323
            crtc_mask <<= 1;
324
        };
325
    };
326
327
 
328
    {
329
        DRM_ERROR("No CRTC for encoder %d\n", encoder->base.id);
3037 serge 330
        return -1;
2338 Serge 331
    };
332
333
 
334
 
335
336
 
337
    os_display->ddev = dev;
338
    os_display->connector = connector;
339
    os_display->crtc = crtc;
340
341
 
342
343
 
344
 
345
    {
346
        struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
347
348
 
349
        {
350
            init_cursor(cursor);
351
        };
352
353
 
354
        os_display->init_cursor    = init_cursor;
355
        os_display->select_cursor  = select_cursor_kms;
356
        os_display->show_cursor    = NULL;
357
        os_display->move_cursor    = move_cursor_kms;
358
        os_display->restore_cursor = restore_cursor;
359
        os_display->disable_mouse  = disable_mouse;
360
361
 
362
        intel_crtc->cursor_y = os_display->height/2;
363
364
 
365
    };
366
    safe_sti(ifl);
367
368
 
2351 Serge 369
370
 
2342 Serge 371
2340 Serge 372
 
2338 Serge 373
};
374
375
 
376
 
377
{
378
    int err = -1;
379
380
 
3031 serge 381
2338 Serge 382
 
383
    {
384
        *count = os_display->supported_modes;
385
        err = 0;
386
    }
387
    else if( mode != NULL )
388
    {
389
        struct drm_display_mode  *drmmode;
390
        int i = 0;
391
392
 
393
            *count = os_display->supported_modes;
394
395
 
396
        {
397
            if( i < *count)
398
            {
399
                mode->width  = drm_mode_width(drmmode);
400
                mode->height = drm_mode_height(drmmode);
401
                mode->bpp    = 32;
402
                mode->freq   = drm_mode_vrefresh(drmmode);
403
                i++;
404
                mode++;
405
            }
406
            else break;
407
        };
408
        *count = i;
409
        err = 0;
410
    };
411
    return err;
412
};
413
414
 
415
{
416
    int err = -1;
417
418
 
3031 serge 419
//               mode->width, mode->height, mode->freq);
420
2338 Serge 421
 
422
        (mode->height != 0)  &&
423
        (mode->freq   != 0 ) &&
424
        ( (mode->width   != os_display->width)  ||
425
          (mode->height  != os_display->height) ||
426
          (mode->freq    != os_display->vrefresh) ) )
427
    {
428
        if( set_mode(os_display->ddev, os_display->connector, mode, true) )
429
            err = 0;
430
    };
431
432
 
433
};
434
435
 
436
{
437
    list_del(&cursor->list);
3037 serge 438
2342 Serge 439
 
3037 serge 440
441
 
442
    drm_gem_object_unreference(&cursor->cobj->base);
443
    mutex_unlock(&main_device->struct_mutex);
444
445
 
2338 Serge 446
};
447
448
 
449
{
450
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
451
    struct drm_i915_gem_object *obj;
452
    uint32_t *bits;
453
    uint32_t *src;
454
    void     *mapped;
3037 serge 455
2338 Serge 456
 
457
    int       ret;
458
459
 
460
    {
461
        bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);
462
        if (unlikely(bits == NULL))
463
            return ENOMEM;
464
        cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits);
465
    }
466
    else
467
    {
468
        obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4);
469
        if (unlikely(obj == NULL))
470
            return -ENOMEM;
471
472
 
3031 serge 473
        if (ret) {
2338 Serge 474
            drm_gem_object_unreference(&obj->base);
2344 Serge 475
            return ret;
2338 Serge 476
        }
477
478
 
479
 * GTT space is continuous. I guarantee it.                           */
480
481
 
3037 serge 482
                    CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);
2338 Serge 483
484
 
485
        {
486
            i915_gem_object_unpin(obj);
2344 Serge 487
            drm_gem_object_unreference(&obj->base);
488
            return -ENOMEM;
2338 Serge 489
        };
490
        cursor->cobj = obj;
491
    };
492
493
 
494
495
 
496
    {
497
        for(j = 0; j < 32; j++)
498
            *bits++ = *src++;
499
        for(j = 32; j < CURSOR_WIDTH; j++)
500
            *bits++ = 0;
501
    }
502
    for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
503
        *bits++ = 0;
504
505
 
3037 serge 506
507
 
2338 Serge 508
509
 
2340 Serge 510
2338 Serge 511
 
512
513
 
514
515
 
516
}
517
518
 
519
 
520
{
521
    struct drm_device *dev = crtc->dev;
522
    struct drm_i915_private *dev_priv = dev->dev_private;
523
    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
524
    int pipe = intel_crtc->pipe;
525
    bool visible = base != 0;
526
527
 
528
        uint32_t cntl = I915_READ(CURCNTR(pipe));
529
        if (base) {
530
            cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
531
            cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
532
            cntl |= pipe << 28; /* Connect to correct pipe */
533
        } else {
534
            cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
535
            cntl |= CURSOR_MODE_DISABLE;
536
        }
537
        I915_WRITE(CURCNTR(pipe), cntl);
538
539
 
540
    }
541
    /* and commit changes on next vblank */
542
    I915_WRITE(CURBASE(pipe), base);
543
}
544
545
 
546
{
547
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
548
    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
549
    u32 base, pos;
550
    bool visible;
551
552
 
553
554
 
555
    intel_crtc->cursor_y = y;
556
557
 
558
    y = y - cursor->hot_y;
559
560
 
561
 
562
563
 
564
    if (x >= os_display->width)
565
        base = 0;
566
567
 
568
        base = 0;
569
570
 
571
    {
572
        if (x + intel_crtc->cursor_width < 0)
573
            base = 0;
574
575
 
576
        x = -x;
577
    }
578
    pos |= x << CURSOR_X_SHIFT;
579
580
 
581
    {
582
        if (y + intel_crtc->cursor_height < 0)
583
            base = 0;
584
585
 
586
        y = -y;
587
    }
588
    pos |= y << CURSOR_Y_SHIFT;
589
590
 
591
    if (!visible && !intel_crtc->cursor_visible)
592
        return;
593
594
 
595
//    if (IS_845G(dev) || IS_I865G(dev))
596
//        i845_update_cursor(crtc, base);
597
//    else
598
        i9xx_update_cursor(os_display->crtc, base);
599
600
 
601
602
 
603
 
604
{
605
    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
606
    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
607
    cursor_t *old;
608
609
 
610
    os_display->cursor = cursor;
611
612
 
613
       intel_crtc->cursor_addr = cursor->cobj->gtt_offset;
614
    else
615
        intel_crtc->cursor_addr = (addr_t)cursor->cobj;
2352 Serge 616
2338 Serge 617
 
618
    intel_crtc->cursor_height = 32;
619
620
 
621
    return old;
622
};
623
624
 
2340 Serge 625
 
626
 
2342 Serge 627
 
3033 serge 628
 
629
630
 
631
 
2342 Serge 632
{
2338 Serge 633
    int left;
2342 Serge 634
    int top;
635
    int right;
636
    int bottom;
637
}rect_t;
638
2338 Serge 639
 
2342 Serge 640
 
641
642
 
643
644
 
645
646
 
647
{
648
    u32_t   addr;
649
650
 
651
    addr+= sizeof(display_t);            /*  shoot me  */
652
    return *(u32_t*)addr;
653
}
654
655
 
3033 serge 656
#define XY_SRC_COPY_BLT_CMD         ((2<<29)|(0x53<<22)|6)
657
#define XY_SRC_COPY_CHROMA_CMD     ((2<<29)|(0x73<<22)|8)
2342 Serge 658
#define ROP_COPY_SRC               0xCC
659
#define FORMAT8888                 3
660
661
 
3033 serge 662
#define BLT_WRITE_RGB               (1<<20)
663
664
 
665
 
666
 
2342 Serge 667
668
 
669
 
3037 serge 670
 
3033 serge 671
i915_gem_execbuffer_retire_commands(struct drm_device *dev,
672
                    struct drm_file *file,
3037 serge 673
                    struct intel_ring_buffer *ring)
3033 serge 674
{
675
    /* Unconditionally force add_request to emit a full flush. */
3037 serge 676
    ring->gpu_caches_dirty = true;
677
3033 serge 678
 
679
    (void)i915_add_request(ring, file, NULL);
3037 serge 680
}
3033 serge 681
682
 
3120 serge 683
               int src_x, int src_y, u32 w, u32 h)
2342 Serge 684
{
685
    drm_i915_private_t *dev_priv = main_device->dev_private;
2340 Serge 686
    struct intel_ring_buffer *ring;
687
    struct context *context;
3033 serge 688
2338 Serge 689
 
2342 Serge 690
    rect_t     winrc;
691
    clip_t     dst_clip;
692
    clip_t     src_clip;
693
    u32_t      width;
694
    u32_t      height;
695
2338 Serge 696
 
2342 Serge 697
    u32_t      offset;
698
    u8         slot;
699
    int      n=0;
2340 Serge 700
    int        ret;
3037 serge 701
2338 Serge 702
 
2342 Serge 703
        return -1;
704
2338 Serge 705
 
3033 serge 706
2338 Serge 707
 
2342 Serge 708
        return -1;
709
2338 Serge 710
 
3033 serge 711
    if(unlikely(context == NULL))
712
        return -1;
713
2338 Serge 714
 
2342 Serge 715
    {
3120 serge 716
        static warn_count;
717
2338 Serge 718
 
3120 serge 719
        {
720
            printf("left %d top %d right %d bottom %d\n",
721
                    winrc.left, winrc.top, winrc.right, winrc.bottom);
722
            printf("bitmap width %d height %d\n", w, h);
723
            warn_count++;
724
        };
725
    };
726
727
 
728
 
2342 Serge 729
    dst_clip.ymin   = 0;
730
    dst_clip.xmax   = winrc.right-winrc.left;
3039 serge 731
    dst_clip.ymax   = winrc.bottom -winrc.top;
732
2338 Serge 733
 
2342 Serge 734
    src_clip.ymin   = 0;
735
    src_clip.xmax   = bitmap->width  - 1;
736
    src_clip.ymax   = bitmap->height - 1;
737
2338 Serge 738
 
2342 Serge 739
    height = h;
740
2338 Serge 741
 
2342 Serge 742
                  &src_clip, &src_x, &src_y,
743
                  &width, &height) )
744
        return 0;
745
2340 Serge 746
 
2342 Serge 747
    dst_y+= winrc.top;
748
2340 Serge 749
 
2342 Serge 750
2340 Serge 751
 
2342 Serge 752
2340 Serge 753
 
2342 Serge 754
#if 0
755
        static v4si write_mask = {0xFF000000, 0xFF000000,
756
                                  0xFF000000, 0xFF000000};
757
2340 Serge 758
 
2342 Serge 759
        u8* dst_offset;
760
2340 Serge 761
 
2342 Serge 762
        src_offset += (u32)bitmap->uaddr;
763
2340 Serge 764
 
2342 Serge 765
        dst_offset+= get_display_map();
766
2340 Serge 767
 
2342 Serge 768
2340 Serge 769
 
2342 Serge 770
        "movdqa     %[write_mask],  %%xmm7    \n"
771
        "movd       %[slot_mask],   %%xmm6    \n"
772
        "punpckldq  %%xmm6, %%xmm6            \n"
773
        "punpcklqdq %%xmm6, %%xmm6            \n"
774
        :: [write_mask] "m" (write_mask),
775
           [slot_mask]  "g" (slot_mask)
776
        :"xmm7", "xmm6");
777
2340 Serge 778
 
2342 Serge 779
        {
780
            u32_t tmp_w = width;
781
2340 Serge 782
 
2342 Serge 783
            u8* tmp_dst = dst_offset;
784
2340 Serge 785
 
2342 Serge 786
            dst_offset+= os_display->width;
787
2340 Serge 788
 
2342 Serge 789
            {
790
                __asm__ __volatile__ (
791
                "movq       (%0),   %%xmm0            \n"
792
                "punpcklbw  %%xmm0, %%xmm0            \n"
793
                "movdqa     %%xmm0, %%xmm1            \n"
794
                "punpcklwd  %%xmm0, %%xmm0            \n"
795
                "punpckhwd  %%xmm1, %%xmm1            \n"
796
                "pcmpeqb    %%xmm6, %%xmm0            \n"
797
                "pcmpeqb    %%xmm6, %%xmm1            \n"
798
                "maskmovdqu %%xmm7, %%xmm0            \n"
799
                "addl       $16, %%edi                \n"
800
                "maskmovdqu %%xmm7, %%xmm1            \n"
801
                :: "r" (tmp_dst), "D" (tmp_src)
802
                :"xmm0", "xmm1");
803
                __asm__ __volatile__ ("":::"edi");
804
                tmp_w -= 8;
805
                tmp_src += 32;
806
                tmp_dst += 8;
807
            };
808
2340 Serge 809
 
2342 Serge 810
            {
811
                __asm__ __volatile__ (
812
                "movd       (%0),   %%xmm0            \n"
813
                "punpcklbw  %%xmm0, %%xmm0            \n"
814
                "punpcklwd  %%xmm0, %%xmm0            \n"
815
                "pcmpeqb    %%xmm6, %%xmm0            \n"
816
                "maskmovdqu %%xmm7, %%xmm0            \n"
817
                :: "r" (tmp_dst), "D" (tmp_src)
818
                :"xmm0");
819
                tmp_w -= 4;
820
                tmp_src += 16;
821
                tmp_dst += 4;
822
            };
823
2340 Serge 824
 
2342 Serge 825
            {
826
                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
827
                tmp_src+=4;
828
                tmp_dst++;
829
            };
830
        };
831
#else
832
        u8* src_offset;
833
        u8* dst_offset;
834
        u32 ifl;
2351 Serge 835
2340 Serge 836
 
2342 Serge 837
        src_offset += (u32)bitmap->uaddr;
838
2340 Serge 839
 
2342 Serge 840
        dst_offset+= get_display_map();
841
842
 
843
844
 
2351 Serge 845
        while( tmp_h--)
2342 Serge 846
        {
847
            u32_t tmp_w = width;
848
849
 
850
            u8* tmp_dst = dst_offset;
851
852
 
853
            dst_offset+= os_display->width;
854
855
 
856
            {
857
                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
858
                tmp_src+=4;
859
                tmp_dst++;
860
            };
861
        };
862
      safe_sti(ifl);
2351 Serge 863
    }
2342 Serge 864
#endif
865
866
 
3120 serge 867
        static warn_count;
868
869
 
870
        {
871
            printf("blit width %d height %d\n",
872
                    width, height);
873
            warn_count++;
874
        };
875
    };
876
877
 
878
 
3033 serge 879
        context->cmd_buffer&= 0xFFFFF000;
880
2342 Serge 881
 
3033 serge 882
2342 Serge 883
 
3033 serge 884
2342 Serge 885
 
886
    cmd |= 3 << 17;
887
888
 
2340 Serge 889
    br13|= ROP_COPY_SRC << 16;
2342 Serge 890
    br13|= FORMAT8888   << 24;
891
2340 Serge 892
 
893
    b[n++] = br13;
894
    b[n++] = (dst_y << 16) | dst_x;                   // left, top
2342 Serge 895
    b[n++] = ((dst_y+height)<< 16)|(dst_x+width); // bottom, right
3039 serge 896
    b[n++] = 0;                          // destination
2342 Serge 897
    b[n++] = (src_y << 16) | src_x;      // source left & top
898
    b[n++] = bitmap->pitch;              // source pitch
899
    b[n++] = bitmap->gaddr;              // source
900
2340 Serge 901
 
2342 Serge 902
    b[n++] = 0x00FFFFFF;                 // Transparency Color High
903
2340 Serge 904
 
905
    if( n & 1)
906
        b[n++] = MI_NOOP;
907
908
 
3033 serge 909
2340 Serge 910
 
3037 serge 911
3033 serge 912
 
3037 serge 913
 
914
915
 
916
917
 
2342 Serge 918
    {
2351 Serge 919
        u32 seqno;
3037 serge 920
        int i;
921
2351 Serge 922
 
2342 Serge 923
//        printf("dispatch...  ");
3033 serge 924
3037 serge 925
 
926
        intel_ring_invalidate_all_caches(ring);
927
928
 
929
//        printf("seqno = %d\n", seqno);
930
931
 
932
            if (seqno < ring->sync_seqno[i]) {
933
            /* The GPU can not handle its semaphore value wrapping,
934
             * so every billion or so execbuffers, we need to stall
935
             * the GPU in order to reset the counters.
936
             */
937
                DRM_DEBUG("wrap seqno\n");
938
939
 
940
                if (ret)
941
                    goto fail;
942
                i915_gem_retire_requests(main_device);
943
944
 
945
            }
946
        }
947
948
 
949
        if (ret)
950
            goto fail;
951
//        printf("done\n");
3033 serge 952
2351 Serge 953
 
3037 serge 954
        bitmap->obj->base.write_domain = bitmap->obj->base.pending_write_domain;
955
        bitmap->obj->fenced_gpu_access = bitmap->obj->pending_fenced_gpu_access;
956
957
 
958
959
 
960
//        printf("retire\n");
3033 serge 961
    }
2351 Serge 962
    else
2342 Serge 963
    {
2351 Serge 964
        ring = &dev_priv->ring[RCS];
2342 Serge 965
        ring->dispatch_execbuffer(ring, offset, n*4);
3033 serge 966
        ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER);
2351 Serge 967
    };
968
2342 Serge 969
 
3037 serge 970
//    bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
971
2340 Serge 972
 
3037 serge 973
fail:
2351 Serge 974
    return ret;
3037 serge 975
};
2351 Serge 976
2340 Serge 977
 
2344 Serge 978
 
3033 serge 979
980
 
981
/* For display hotplug interrupt */
2351 Serge 982
static void
983
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
984
{
985
    if ((dev_priv->irq_mask & mask) != 0) {
986
        dev_priv->irq_mask &= ~mask;
987
        I915_WRITE(DEIMR, dev_priv->irq_mask);
988
        POSTING_READ(DEIMR);
989
    }
990
}
991
2340 Serge 992
 
2351 Serge 993
{
994
    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
995
    unsigned long irqflags;
996
997
 
998
//        return -EINVAL;
999
1000
 
1001
    ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1002
                    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1003
    spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1004
1005
 
2340 Serge 1006
}
2351 Serge 1007
1008
 
1009
 
1010
 
1011
{
1012
    drm_i915_private_t *dev_priv = dev->dev_private;
1013
    int ret, i, pipe;
1014
1015
 
1016
        dbgprintf("Interrupt enable:    %08x\n",
1017
               I915_READ(IER));
1018
        dbgprintf("Interrupt identity:  %08x\n",
1019
               I915_READ(IIR));
1020
        dbgprintf("Interrupt mask:      %08x\n",
1021
               I915_READ(IMR));
1022
        for_each_pipe(pipe)
1023
            dbgprintf("Pipe %c stat:         %08x\n",
1024
                   pipe_name(pipe),
1025
                   I915_READ(PIPESTAT(pipe)));
1026
    } else {
1027
        dbgprintf("North Display Interrupt enable:      %08x\n",
1028
           I915_READ(DEIER));
1029
        dbgprintf("North Display Interrupt identity:    %08x\n",
1030
           I915_READ(DEIIR));
1031
        dbgprintf("North Display Interrupt mask:        %08x\n",
1032
           I915_READ(DEIMR));
1033
        dbgprintf("South Display Interrupt enable:      %08x\n",
1034
           I915_READ(SDEIER));
1035
        dbgprintf("South Display Interrupt identity:    %08x\n",
1036
           I915_READ(SDEIIR));
1037
        dbgprintf("South Display Interrupt mask:        %08x\n",
1038
           I915_READ(SDEIMR));
1039
        dbgprintf("Graphics Interrupt enable:           %08x\n",
1040
           I915_READ(GTIER));
1041
        dbgprintf("Graphics Interrupt identity:         %08x\n",
1042
           I915_READ(GTIIR));
1043
        dbgprintf("Graphics Interrupt mask:             %08x\n",
1044
               I915_READ(GTIMR));
1045
    }
1046
    dbgprintf("Interrupts received: %d\n",
1047
           atomic_read(&dev_priv->irq_received));
1048
    for (i = 0; i < I915_NUM_RINGS; i++) {
1049
        if (IS_GEN6(dev) || IS_GEN7(dev)) {
1050
            printf("Graphics Interrupt mask (%s):       %08x\n",
1051
                   dev_priv->ring[i].name,
1052
                   I915_READ_IMR(&dev_priv->ring[i]));
1053
        }
1054
//        i915_ring_seqno_info(m, &dev_priv->ring[i]);
1055
    }
1056
1057
 
1058
}
1059
1060
 
1061
                     int size)
1062
{
1063
    struct intel_ring_buffer *ring;
1064
    drm_i915_private_t *dev_priv = main_device->dev_private;
1065
    u32 invalidate;
1066
    u32 seqno = 2;
1067
1068
 
1069
//    dbgprintf("execute %x size %d\n", offset, size);
1070
1071
 
1072
//    "mfence \n"
1073
//    "wbinvd \n"
1074
//    "mfence  \n"
1075
//    :::"memory");
1076
1077
 
1078
    ring->dispatch_execbuffer(ring, offset, size);
1079
1080
 
1081
    if (INTEL_INFO(main_device)->gen >= 4)
1082
        invalidate |= I915_GEM_DOMAIN_SAMPLER;
1083
    if (ring->flush(ring, invalidate, 0))
1084
        i915_gem_next_request_seqno(ring);
1085
1086
 
1087
1088
 
1089
1090
 
1091
1092
 
2340 Serge 1093
2351 Serge 1094
 
1095
 
1096
               int src_x, int src_y, u32 w, u32 h)
1097
{
1098
    drm_i915_private_t *dev_priv = main_device->dev_private;
1099
1100
 
1101
    bitmap_t   screen;
1102
1103
 
1104
1105
 
1106
//              hbitmap, dst_x, dst_y, src_x, src_y, w, h);
1107
1108
 
1109
        return -1;
1110
1111
 
1112
//    dbgprintf("bitmap %x\n", src_bitmap);
1113
1114
 
1115
        return -1;
1116
1117
 
1118
1119
 
1120
    screen.gaddr  = 0;
1121
    screen.width  = os_display->width;
1122
    screen.height = os_display->height;
1123
    screen.obj    = (void*)-1;
1124
1125
 
1126
1127
 
1128
    dst_y+= winrc.top;
1129
1130
 
1131
1132
 
1133
1134
 
2361 Serge 1135
                  int w, int h, bitmap_t *src_bitmap, int src_x, int src_y,
1136
                  bitmap_t *mask_bitmap);
1137
2360 Serge 1138
 
2361 Serge 1139
 
1140
             int src_x, int src_y, u32 w, u32 h)
1141
{
1142
    drm_i915_private_t *dev_priv = main_device->dev_private;
1143
    struct context *ctx;
1144
1145
 
1146
    bitmap_t   screen;
1147
    int        ret;
1148
1149
 
1150
    rect_t     winrc;
1151
1152
 
1153
//              hbitmap, dst_x, dst_y, src_x, src_y, w, h);
1154
1155
 
1156
        return -1;
1157
1158
 
1159
//    dbgprintf("bitmap %x\n", src_bitmap);
1160
1161
 
1162
        return -1;
1163
1164
 
1165
    if(unlikely(ctx==NULL))
1166
    {
1167
        ret = create_context();
1168
        if(ret!=0)
1169
            return -1;
1170
1171
 
1172
    };
1173
1174
 
1175
1176
 
1177
    dst_x+= winrc.left;
1178
    dst_y+= winrc.top;
1179
1180
 
1181
 
1182
    {
1183
        u8* src_offset;
1184
        u8* dst_offset;
1185
        u32 slot;
3031 serge 1186
        u32 ifl;
2361 Serge 1187
1188
 
1189
        if(ret !=0 )
1190
        {
1191
            dbgprintf("%s fail\n", __FUNCTION__);
1192
            return ret;
1193
        };
1194
1195
 
3031 serge 1196
2361 Serge 1197
 
1198
        mask_bitmap->height = winrc.bottom;
1199
        mask_bitmap->pitch =  ALIGN(w,64);
1200
1201
 
3031 serge 1202
//        slot = 0x01;
1203
1204
 
2361 Serge 1205
1206
 
1207
 
1208
        "movd       %[slot],   %%xmm6    \n"
1209
        "punpckldq  %%xmm6, %%xmm6            \n"
1210
        "punpcklqdq %%xmm6, %%xmm6            \n"
1211
        :: [slot]  "m" (slot)
3031 serge 1212
        :"xmm6");
2361 Serge 1213
1214
 
1215
1216
 
1217
        dst_offset+= get_display_map();
1218
1219
 
1220
1221
 
1222
        while( tmp_h--)
1223
        {
1224
            int tmp_w = mask_bitmap->width;
1225
1226
 
1227
            u8* tmp_dst = dst_offset;
1228
1229
 
1230
            dst_offset+= os_display->width;
1231
1232
 
1233
//            {
1234
//                *(tmp_src) = (*tmp_dst==slot)?0x1:0x00;
1235
//                tmp_src++;
1236
//                tmp_dst++;
1237
//            };
1238
            while(tmp_w >= 64)
1239
            {
1240
                __asm__ __volatile__ (
1241
                "movdqu     (%0),   %%xmm0            \n"
1242
                "movdqu   16(%0),   %%xmm1            \n"
1243
                "movdqu   32(%0),   %%xmm2            \n"
1244
                "movdqu   48(%0),   %%xmm3            \n"
1245
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1246
                "pcmpeqb    %%xmm6, %%xmm1            \n"
1247
                "pcmpeqb    %%xmm6, %%xmm2            \n"
1248
                "pcmpeqb    %%xmm6, %%xmm3            \n"
1249
                "movdqa     %%xmm0,   (%%edi)         \n"
1250
                "movdqa     %%xmm1, 16(%%edi)         \n"
1251
                "movdqa     %%xmm2, 32(%%edi)         \n"
1252
                "movdqa     %%xmm3, 48(%%edi)         \n"
1253
1254
 
1255
                :"xmm0","xmm1","xmm2","xmm3");
1256
                tmp_w -= 64;
1257
                tmp_src += 64;
1258
                tmp_dst += 64;
1259
            }
1260
1261
 
1262
            {
1263
                __asm__ __volatile__ (
1264
                "movdqu     (%0),   %%xmm0            \n"
1265
                "movdqu   16(%0),   %%xmm1            \n"
1266
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1267
                "pcmpeqb    %%xmm6, %%xmm1            \n"
1268
                "movdqa     %%xmm0,   (%%edi)         \n"
1269
                "movdqa     %%xmm1, 16(%%edi)         \n"
1270
1271
 
1272
                :"xmm0","xmm1");
1273
                tmp_w -= 32;
1274
                tmp_src += 32;
1275
                tmp_dst += 32;
1276
            }
1277
1278
 
1279
            {
1280
                __asm__ __volatile__ (
1281
                "movdqu     (%0),   %%xmm0            \n"
1282
                "pcmpeqb    %%xmm6, %%xmm0            \n"
1283
                "movdqa     %%xmm0,   (%%edi)         \n"
1284
                :: "r" (tmp_dst), "D" (tmp_src)
1285
                :"xmm0");
1286
                tmp_w -= 16;
1287
                tmp_src += 16;
1288
                tmp_dst += 16;
1289
            }
1290
        };
1291
      safe_sti(ifl);
1292
      ctx->seqno = os_display->mask_seqno;
1293
    }
1294
1295
 
1296
    screen.gaddr  = 0;
1297
    screen.width  = os_display->width;
1298
    screen.height = os_display->height;
1299
    screen.obj    = (void*)-1;
1300
1301
 
1302
1303
 
1304
 
1305
                 mask_bitmap);
1306
1307
 
1308
};
1309
1310
 
1311
 
3031 serge 1312
2361 Serge 1313
 
1314
 
1315
 
1316
 
1317
 
1318
 
1319
 
1320
 
2360 Serge 1321
{
1322
    unsigned long irqflags;
1323
1324
 
1325
//               cwq, &cwq->worklist, cwq->worklist.next);
1326
1327
 
1328
1329
 
1330
    {
1331
        struct work_struct *work = list_entry(cwq->worklist.next,
1332
                                        struct work_struct, entry);
1333
        work_func_t f = work->func;
1334
        list_del_init(cwq->worklist.next);
1335
//        dbgprintf("head %x, next %x\n",
1336
//                  &cwq->worklist, cwq->worklist.next);
1337
1338
 
1339
        f(work);
1340
        spin_lock_irqsave(&cwq->lock, irqflags);
1341
    }
1342
1343
 
1344
}
1345
1346
 
1347
 
1348
int __queue_work(struct workqueue_struct *wq,
1349
                         struct work_struct *work)
1350
{
1351
    unsigned long flags;
1352
1353
 
1354
//               wq, work );
1355
1356
 
1357
        return 0;
1358
1359
 
1360
1361
 
1362
        TimerHs(0,0, run_workqueue, wq);
1363
1364
 
1365
1366
 
1367
//    dbgprintf("wq: %x head %x, next %x\n",
1368
//               wq, &wq->worklist, wq->worklist.next);
1369
1370
 
1371
};
1372
1373
 
1374
{
1375
    struct delayed_work *dwork = (struct delayed_work *)__data;
1376
    struct workqueue_struct *wq = dwork->work.data;
1377
1378
 
1379
//               wq, &dwork->work );
1380
1381
 
1382
}
1383
1384
 
1385
 
1386
                        struct delayed_work *dwork, unsigned long delay)
1387
{
1388
    struct work_struct *work = &dwork->work;
1389
1390
 
1391
    TimerHs(0,0, delayed_work_timer_fn, dwork);
1392
    return 1;
1393
}
1394
1395
 
1396
                        struct delayed_work *dwork, unsigned long delay)
1397
{
1398
    u32  flags;
1399
1400
 
1401
//               wq, &dwork->work );
1402
1403
 
1404
        return __queue_work(wq, &dwork->work);
1405
1406
 
1407
}
1408
1409
 
1410
 
1411
                           unsigned int flags,
1412
                           int max_active)
1413
{
1414
    struct workqueue_struct *wq;
1415
1416
 
1417
    if (!wq)
1418
        goto err;
1419
1420
 
1421
1422
 
1423
err:
1424
    return NULL;
1425
}
1426
1427
 
3031 serge 1428
2360 Serge 1429
 
3031 serge 1430
{
1431
    u32 tmp = GetTimerTicks();
1432
2360 Serge 1433
 
3031 serge 1434
    ts->tv_nsec = (tmp - ts->tv_sec*100)*10000000;
1435
}
1436
2360 Serge 1437
 
3031 serge 1438
{
1439
        while (nsec >= NSEC_PER_SEC) {
1440
                nsec -= NSEC_PER_SEC;
1441
                ++sec;
1442
        }
1443
        while (nsec < 0) {
1444
                nsec += NSEC_PER_SEC;
1445
                --sec;
1446
        }
1447
        ts->tv_sec = sec;
1448
        ts->tv_nsec = nsec;
1449
}
1450
2360 Serge 1451
 
3031 serge 1452
 
1453