Subversion Repositories Kolibri OS

#include "drm.h"

#include "i915_drm.h"

#include "i915_drv.h"

#include "intel_drv.h"

#include 

#include 

#include 

#include 

#include "bitmap.h"

{

    kobj_t     header;

    uint32_t   hot_x;

    uint32_t   hot_y;

    struct drm_i915_gem_object  *cobj;

}cursor_t;

#define CURSOR_HEIGHT 64

{

    int  x;

    int  y;

    int  width;

    int  height;

    int  bpp;

    int  vrefresh;

    int  pitch;

    int  lfb;

    struct drm_device    *ddev;

    struct drm_connector *connector;

    struct drm_crtc      *crtc;

    int       (*init_cursor)(cursor_t*);

    cursor_t* (__stdcall *select_cursor)(cursor_t*);

    void      (*show_cursor)(int show);

    void      (__stdcall *move_cursor)(cursor_t *cursor, int x, int y);

    void      (__stdcall *restore_cursor)(int x, int y);

    void      (*disable_mouse)(void);

    u32  mask_seqno;

    u32  check_mouse;

    u32  check_m_pixel;

u32_t cmd_offset;

int  sna_init();

static cursor_t*  __stdcall select_cursor_kms(cursor_t *cursor);

static void       __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);

{};

{};

{

    static char name[4];

    name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@';

    name[2] = (x[1] & 0x1F) + '@';

    name[3] = 0;

}

              videomode_t *reqmode, bool strict)

{

    drm_i915_private_t      *dev_priv   = dev->dev_private;

    struct drm_fb_helper    *fb_helper  = &dev_priv->fbdev->helper;

    struct drm_display_mode *mode       = NULL, *tmpmode;

    struct drm_framebuffer  *fb         = NULL;

    struct drm_crtc         *crtc;

    struct drm_encoder      *encoder;

    struct drm_mode_set     set;

    char *con_name;

    char *enc_name;

    unsigned hdisplay, vdisplay;

    int ret;

    {

        if( (drm_mode_width(tmpmode)    == reqmode->width)  &&

            (drm_mode_height(tmpmode)   == reqmode->height) &&

            (drm_mode_vrefresh(tmpmode) == reqmode->freq) )

        {

            mode = tmpmode;

            goto do_set;

        }

    };

    {

        list_for_each_entry(tmpmode, &connector->modes, head)

        {

            if( (drm_mode_width(tmpmode)  == reqmode->width)  &&

                (drm_mode_height(tmpmode) == reqmode->height) )

            {

                mode = tmpmode;

                goto do_set;

            }

        };

    };

    crtc = encoder->crtc;

    enc_name = drm_get_encoder_name(encoder);

              reqmode->width, reqmode->height, crtc->base.id,

              con_name, enc_name);

    vdisplay = mode->vdisplay;

        swap(hdisplay, vdisplay);

    fb->height = reqmode->height;

    fb->pitches[0]  = ALIGN(reqmode->width * 4, 64);

    fb->pitches[1]  = ALIGN(reqmode->width * 4, 64);

    fb->pitches[2]  = ALIGN(reqmode->width * 4, 64);

    fb->pitches[3]  = ALIGN(reqmode->width * 4, 64);

    fb->depth = 24;

    crtc->enabled = true;

    os_display->crtc = crtc;

    set.x = 0;

    set.y = 0;

    set.mode = mode;

    set.connectors = &connector;

    set.num_connectors = 1;

    set.fb = fb;

    ret = crtc->funcs->set_config(&set);

    mutex_unlock(&dev->mode_config.mutex);

    {

        os_display->width    = fb->width;

        os_display->height   = fb->height;

        os_display->pitch    = fb->pitches[0];

        os_display->vrefresh = drm_mode_vrefresh(mode);

                       fb->width, fb->height, fb->pitches[0]);

    }

    else

        DRM_ERROR("failed to set mode %d_%d on crtc %p\n",

                   fb->width, fb->height, crtc);

}

{

    struct drm_display_mode  *mode;

    int count = 0;

    {

        count++;

    };

    return count;

};

{

    struct drm_connector  *connector;

    struct drm_connector_helper_funcs *connector_funcs;

    {

        struct drm_encoder  *encoder;

        struct drm_crtc     *crtc;

            continue;

        encoder = connector_funcs->best_encoder(connector);

        if( encoder == NULL)

            continue;

                   connector, connector->base.id,

                   connector->status, connector->encoder,

                   crtc);

//            continue;

    };

};

{

    struct drm_connector    *connector;

    struct drm_connector_helper_funcs *connector_funcs;

    struct drm_encoder      *encoder;

    struct drm_crtc         *crtc = NULL;

    struct drm_framebuffer  *fb;

    u32_t      ifl;

    int        err;

    {

        if( connector->status != connector_status_connected)

            continue;

        encoder = connector_funcs->best_encoder(connector);

        if( encoder == NULL)

        {

            DRM_DEBUG_KMS("CONNECTOR %x ID: %d no active encoders\n",

                      connector, connector->base.id);

            continue;

        }

        connector->encoder = encoder;

        crtc = encoder->crtc;

               connector, connector->base.id,

               connector->status, connector->encoder,

               crtc, crtc->base.id );

    };

    {

        DRM_ERROR("No active connectors!\n");

        return -1;

    };

    {

        struct drm_crtc *tmp_crtc;

        int crtc_mask = 1;

        {

            if (encoder->possible_crtcs & crtc_mask)

            {

                crtc = tmp_crtc;

                encoder->crtc = crtc;

                break;

            };

            crtc_mask <<= 1;

        };

    };

    {

        DRM_ERROR("No CRTC for encoder %d\n", encoder->base.id);

        return -1;

    };

    os_display->ddev = dev;

    os_display->connector = connector;

    os_display->crtc = crtc;

    {

        struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

        {

            init_cursor(cursor);

        };

        os_display->init_cursor    = init_cursor;

        os_display->select_cursor  = select_cursor_kms;

        os_display->show_cursor    = NULL;

        os_display->move_cursor    = move_cursor_kms;

        os_display->restore_cursor = restore_cursor;

        os_display->disable_mouse  = disable_mouse;

        intel_crtc->cursor_y = os_display->height/2;

    };

    safe_sti(ifl);

};

{

    int err = -1;

    {

        *count = os_display->supported_modes;

        err = 0;

    }

    else if( mode != NULL )

    {

        struct drm_display_mode  *drmmode;

        int i = 0;

            *count = os_display->supported_modes;

        {

            if( i < *count)

            {

                mode->width  = drm_mode_width(drmmode);

                mode->height = drm_mode_height(drmmode);

                mode->bpp    = 32;

                mode->freq   = drm_mode_vrefresh(drmmode);

                i++;

                mode++;

            }

            else break;

        };

        *count = i;

        err = 0;

    };

    return err;

};

{

    int err = -1;

//               mode->width, mode->height, mode->freq);

        (mode->height != 0)  &&

        (mode->freq   != 0 ) &&

        ( (mode->width   != os_display->width)  ||

          (mode->height  != os_display->height) ||

          (mode->freq    != os_display->vrefresh) ) )

    {

        if( set_mode(os_display->ddev, os_display->connector, mode, true) )

            err = 0;

    };

};

{

    list_del(&cursor->list);

    drm_gem_object_unreference(&cursor->cobj->base);

    mutex_unlock(&main_device->struct_mutex);

};

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct drm_i915_gem_object *obj;

    uint32_t *bits;

    uint32_t *src;

    void     *mapped;

    int       ret;

    {

        bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);

        if (unlikely(bits == NULL))

            return ENOMEM;

        cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits);

    }

    else

    {

        obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4);

        if (unlikely(obj == NULL))

            return -ENOMEM;

        if (ret) {

            drm_gem_object_unreference(&obj->base);

            return ret;

        }

 * GTT space is continuous. I guarantee it.                           */

                    CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);

        {

            i915_gem_object_unpin(obj);

            drm_gem_object_unreference(&obj->base);

            return -ENOMEM;

        };

        cursor->cobj = obj;

    };

    {

        for(j = 0; j < 32; j++)

            *bits++ = *src++;

        for(j = 32; j < CURSOR_WIDTH; j++)

            *bits++ = 0;

    }

    for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)

        *bits++ = 0;

}

{

    struct drm_device *dev = crtc->dev;

    struct drm_i915_private *dev_priv = dev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

    int pipe = intel_crtc->pipe;

    bool visible = base != 0;

        uint32_t cntl = I915_READ(CURCNTR(pipe));

        if (base) {

            cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);

            cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

            cntl |= pipe << 28; /* Connect to correct pipe */

        } else {

            cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

            cntl |= CURSOR_MODE_DISABLE;

        }

        I915_WRITE(CURCNTR(pipe), cntl);

    }

    /* and commit changes on next vblank */

    I915_WRITE(CURBASE(pipe), base);

}

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

    u32 base, pos;

    bool visible;

    intel_crtc->cursor_y = y;

    y = y - cursor->hot_y;

    if (x >= os_display->width)

        base = 0;

        base = 0;

    {

        if (x + intel_crtc->cursor_width < 0)

            base = 0;

        x = -x;

    }

    pos |= x << CURSOR_X_SHIFT;

    {

        if (y + intel_crtc->cursor_height < 0)

            base = 0;

        y = -y;

    }

    pos |= y << CURSOR_Y_SHIFT;

    if (!visible && !intel_crtc->cursor_visible)

        return;

//    if (IS_845G(dev) || IS_I865G(dev))

//        i845_update_cursor(crtc, base);

//    else

        i9xx_update_cursor(os_display->crtc, base);

{

    struct drm_i915_private *dev_priv = os_display->ddev->dev_private;

    struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);

    cursor_t *old;

    os_display->cursor = cursor;

       intel_crtc->cursor_addr = cursor->cobj->gtt_offset;

    else

        intel_crtc->cursor_addr = (addr_t)cursor->cobj;

    intel_crtc->cursor_height = 32;

    return old;

};

{

    int left;

    int top;

    int right;

    int bottom;

}rect_t;

{

    u32_t   addr;

    addr+= sizeof(display_t);            /*  shoot me  */

    return *(u32_t*)addr;

}

#define XY_SRC_COPY_BLT_CMD         ((2<<29)|(0x53<<22)|6)

#define XY_SRC_COPY_CHROMA_CMD     ((2<<29)|(0x73<<22)|8)

#define ROP_COPY_SRC               0xCC

#define FORMAT8888                 3

#define BLT_WRITE_RGB               (1<<20)

i915_gem_execbuffer_retire_commands(struct drm_device *dev,

                    struct drm_file *file,

                    struct intel_ring_buffer *ring)

{

    /* Unconditionally force add_request to emit a full flush. */

    ring->gpu_caches_dirty = true;

    (void)i915_add_request(ring, file, NULL);

}

               int src_x, int src_y, u32 w, u32 h)

{

    drm_i915_private_t *dev_priv = main_device->dev_private;

    struct intel_ring_buffer *ring;

    struct context *context;

    rect_t     winrc;

    clip_t     dst_clip;

    clip_t     src_clip;

    u32_t      width;

    u32_t      height;

    u32_t      offset;

    u8         slot;

    int      n=0;

    int        ret;

        return -1;

        return -1;

    if(unlikely(context == NULL))

        return -1;

    dst_clip.ymin   = 0;

    dst_clip.xmax   = winrc.right-winrc.left-1;

    dst_clip.ymax   = winrc.bottom -winrc.top-1;

    src_clip.ymin   = 0;

    src_clip.xmax   = bitmap->width  - 1;

    src_clip.ymax   = bitmap->height - 1;

    height = h;

                  &src_clip, &src_x, &src_y,

                  &width, &height) )

        return 0;

    dst_y+= winrc.top;

#if 0

        static v4si write_mask = {0xFF000000, 0xFF000000,

                                  0xFF000000, 0xFF000000};

        u8* dst_offset;

        src_offset += (u32)bitmap->uaddr;

        dst_offset+= get_display_map();

        "movdqa     %[write_mask],  %%xmm7    \n"

        "movd       %[slot_mask],   %%xmm6    \n"

        "punpckldq  %%xmm6, %%xmm6            \n"

        "punpcklqdq %%xmm6, %%xmm6            \n"

        :: [write_mask] "m" (write_mask),

           [slot_mask]  "g" (slot_mask)

        :"xmm7", "xmm6");

        {

            u32_t tmp_w = width;

            u8* tmp_dst = dst_offset;

            dst_offset+= os_display->width;

            {

                __asm__ __volatile__ (

                "movq       (%0),   %%xmm0            \n"

                "punpcklbw  %%xmm0, %%xmm0            \n"

                "movdqa     %%xmm0, %%xmm1            \n"

                "punpcklwd  %%xmm0, %%xmm0            \n"

                "punpckhwd  %%xmm1, %%xmm1            \n"

                "pcmpeqb    %%xmm6, %%xmm0            \n"

                "pcmpeqb    %%xmm6, %%xmm1            \n"

                "maskmovdqu %%xmm7, %%xmm0            \n"

                "addl       $16, %%edi                \n"

                "maskmovdqu %%xmm7, %%xmm1            \n"

                :: "r" (tmp_dst), "D" (tmp_src)

                :"xmm0", "xmm1");

                __asm__ __volatile__ ("":::"edi");

                tmp_w -= 8;

                tmp_src += 32;

                tmp_dst += 8;

            };

            {

                __asm__ __volatile__ (

                "movd       (%0),   %%xmm0            \n"

                "punpcklbw  %%xmm0, %%xmm0            \n"

                "punpcklwd  %%xmm0, %%xmm0            \n"

                "pcmpeqb    %%xmm6, %%xmm0            \n"

                "maskmovdqu %%xmm7, %%xmm0            \n"

                :: "r" (tmp_dst), "D" (tmp_src)

                :"xmm0");

                tmp_w -= 4;

                tmp_src += 16;

                tmp_dst += 4;

            };

            {

                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;

                tmp_src+=4;

                tmp_dst++;

            };

        };

#else

        u8* src_offset;

        u8* dst_offset;

        u32 ifl;

        src_offset += (u32)bitmap->uaddr;

        dst_offset+= get_display_map();

        while( tmp_h--)

        {

            u32_t tmp_w = width;

            u8* tmp_dst = dst_offset;

            dst_offset+= os_display->width;

            {

                *(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;

                tmp_src+=4;

                tmp_dst++;

            };

        };

      safe_sti(ifl);

    }

#endif

        context->cmd_buffer&= 0xFFFFF000;

    cmd |= 3 << 17;

    br13|= ROP_COPY_SRC << 16;

    br13|= FORMAT8888   << 24;

    b[n++] = br13;

    b[n++] = (dst_y << 16) | dst_x;                   // left, top

    b[n++] = ((dst_y+height-1)<< 16)|(dst_x+width-1); // bottom, right

    b[n++] = 0;                          // destination

    b[n++] = (src_y << 16) | src_x;      // source left & top

    b[n++] = bitmap->pitch;              // source pitch

    b[n++] = bitmap->gaddr;              // source

    b[n++] = 0x00FFFFFF;                 // Transparency Color High

    if( n & 1)

        b[n++] = MI_NOOP;

    {

        u32 seqno;

        int i;

//        printf("dispatch...  ");

        intel_ring_invalidate_all_caches(ring);

//        printf("seqno = %d\n", seqno);

            if (seqno < ring->sync_seqno[i]) {

            /* The GPU can not handle its semaphore value wrapping,

             * so every billion or so execbuffers, we need to stall

             * the GPU in order to reset the counters.

             */

                DRM_DEBUG("wrap seqno\n");

                if (ret)

                    goto fail;

                i915_gem_retire_requests(main_device);

            }

        }

        if (ret)

            goto fail;

//        printf("done\n");

        bitmap->obj->base.write_domain = bitmap->obj->base.pending_write_domain;

        bitmap->obj->fenced_gpu_access = bitmap->obj->pending_fenced_gpu_access;

//        printf("retire\n");

    }

    else

    {

        ring = &dev_priv->ring[RCS];

        ring->dispatch_execbuffer(ring, offset, n*4);

        ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER);

    };

//    bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;

fail:

    return ret;

};

/* For display hotplug interrupt */

static void

ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)

{

    if ((dev_priv->irq_mask & mask) != 0) {

        dev_priv->irq_mask &= ~mask;

        I915_WRITE(DEIMR, dev_priv->irq_mask);

        POSTING_READ(DEIMR);

    }

}

{

    drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

    unsigned long irqflags;

//        return -EINVAL;

    ironlake_enable_display_irq(dev_priv, (pipe == 0) ?

                    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);

    spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

}

{

    drm_i915_private_t *dev_priv = dev->dev_private;

    int ret, i, pipe;

        dbgprintf("Interrupt enable:    %08x\n",

               I915_READ(IER));

        dbgprintf("Interrupt identity:  %08x\n",

               I915_READ(IIR));

        dbgprintf("Interrupt mask:      %08x\n",

               I915_READ(IMR));

        for_each_pipe(pipe)

            dbgprintf("Pipe %c stat:         %08x\n",

                   pipe_name(pipe),

                   I915_READ(PIPESTAT(pipe)));

    } else {

        dbgprintf("North Display Interrupt enable:      %08x\n",

           I915_READ(DEIER));

        dbgprintf("North Display Interrupt identity:    %08x\n",

           I915_READ(DEIIR));

        dbgprintf("North Display Interrupt mask:        %08x\n",

           I915_READ(DEIMR));

        dbgprintf("South Display Interrupt enable:      %08x\n",

           I915_READ(SDEIER));

        dbgprintf("South Display Interrupt identity:    %08x\n",

           I915_READ(SDEIIR));

        dbgprintf("South Display Interrupt mask:        %08x\n",

           I915_READ(SDEIMR));

        dbgprintf("Graphics Interrupt enable:           %08x\n",

           I915_READ(GTIER));

        dbgprintf("Graphics Interrupt identity:         %08x\n",

           I915_READ(GTIIR));

        dbgprintf("Graphics Interrupt mask:             %08x\n",

               I915_READ(GTIMR));

    }

    dbgprintf("Interrupts received: %d\n",

           atomic_read(&dev_priv->irq_received));

    for (i = 0; i < I915_NUM_RINGS; i++) {

        if (IS_GEN6(dev) || IS_GEN7(dev)) {

            printf("Graphics Interrupt mask (%s):       %08x\n",

                   dev_priv->ring[i].name,

                   I915_READ_IMR(&dev_priv->ring[i]));

        }

//        i915_ring_seqno_info(m, &dev_priv->ring[i]);

    }

}

                     int size)

{

    struct intel_ring_buffer *ring;

    drm_i915_private_t *dev_priv = main_device->dev_private;

    u32 invalidate;

    u32 seqno = 2;

//    dbgprintf("execute %x size %d\n", offset, size);

//    "mfence \n"

//    "wbinvd \n"

//    "mfence  \n"

//    :::"memory");

    ring->dispatch_execbuffer(ring, offset, size);

    if (INTEL_INFO(main_device)->gen >= 4)

        invalidate |= I915_GEM_DOMAIN_SAMPLER;

    if (ring->flush(ring, invalidate, 0))

        i915_gem_next_request_seqno(ring);

               int src_x, int src_y, u32 w, u32 h)

{

    drm_i915_private_t *dev_priv = main_device->dev_private;

    bitmap_t   screen;

//              hbitmap, dst_x, dst_y, src_x, src_y, w, h);

        return -1;

//    dbgprintf("bitmap %x\n", src_bitmap);

        return -1;

    screen.gaddr  = 0;

    screen.width  = os_display->width;

    screen.height = os_display->height;

    screen.obj    = (void*)-1;