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Rev | Author | Line No. | Line |
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2340 | Serge | 1 | |
2 | |||
3 | |||
2338 | Serge | 4 | #include "drm.h" |
5 | #include "i915_drm.h" |
||
6 | #include "i915_drv.h" |
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7 | #include "intel_drv.h" |
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8 | |||
9 | |||
10 | #include |
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11 | #include |
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12 | #include |
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13 | #include |
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14 | |||
15 | |||
16 | |||
17 | |||
2340 | Serge | 18 | |
2338 | Serge | 19 | |
20 | |||
21 | { |
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22 | kobj_t header; |
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23 | |||
24 | |||
25 | uint32_t hot_x; |
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26 | uint32_t hot_y; |
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27 | |||
28 | |||
29 | struct drm_i915_gem_object *cobj; |
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30 | }cursor_t; |
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31 | |||
32 | |||
33 | #define CURSOR_HEIGHT 64 |
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34 | |||
35 | |||
36 | |||
37 | { |
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38 | int x; |
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39 | int y; |
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40 | int width; |
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41 | int height; |
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42 | int bpp; |
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43 | int vrefresh; |
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44 | int pitch; |
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45 | int lfb; |
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46 | |||
47 | |||
48 | struct drm_device *ddev; |
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49 | struct drm_connector *connector; |
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50 | struct drm_crtc *crtc; |
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51 | |||
52 | |||
53 | |||
54 | |||
55 | int (*init_cursor)(cursor_t*); |
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56 | cursor_t* (__stdcall *select_cursor)(cursor_t*); |
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57 | void (*show_cursor)(int show); |
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58 | void (__stdcall *move_cursor)(cursor_t *cursor, int x, int y); |
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59 | void (__stdcall *restore_cursor)(int x, int y); |
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60 | void (*disable_mouse)(void); |
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61 | }; |
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62 | |||
63 | |||
64 | |||
65 | |||
66 | |||
2340 | Serge | 67 | u32_t cmd_offset; |
68 | |||
69 | |||
2338 | Serge | 70 | static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor); |
71 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
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72 | |||
73 | |||
74 | {}; |
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75 | |||
76 | |||
77 | {}; |
||
78 | |||
79 | |||
80 | { |
||
81 | struct drm_display_mode *mode; |
||
82 | int count = 0; |
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83 | |||
84 | |||
85 | { |
||
86 | count++; |
||
87 | }; |
||
88 | return count; |
||
89 | }; |
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90 | |||
91 | |||
92 | { |
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93 | struct drm_connector *connector; |
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94 | struct drm_connector_helper_funcs *connector_funcs; |
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95 | struct drm_encoder *encoder; |
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96 | struct drm_crtc *crtc = NULL; |
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97 | struct drm_framebuffer *fb; |
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98 | |||
99 | |||
100 | u32_t ifl; |
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101 | |||
102 | |||
103 | |||
104 | |||
105 | { |
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106 | if( connector->status != connector_status_connected) |
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107 | continue; |
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108 | |||
109 | |||
110 | encoder = connector_funcs->best_encoder(connector); |
||
111 | if( encoder == NULL) |
||
112 | { |
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113 | dbgprintf("CONNECTOR %x ID: %d no active encoders\n", |
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114 | connector, connector->base.id); |
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115 | continue; |
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116 | } |
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117 | connector->encoder = encoder; |
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118 | |||
119 | |||
120 | connector, connector->base.id, |
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121 | connector->status, connector->encoder, |
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122 | encoder->crtc); |
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123 | |||
124 | |||
125 | break; |
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126 | }; |
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127 | |||
128 | |||
129 | { |
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130 | dbgprintf("No active connectors!\n"); |
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131 | return -1; |
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132 | }; |
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133 | |||
134 | |||
135 | { |
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136 | struct drm_crtc *tmp_crtc; |
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137 | int crtc_mask = 1; |
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138 | |||
139 | |||
140 | { |
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141 | if (encoder->possible_crtcs & crtc_mask) |
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142 | { |
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143 | crtc = tmp_crtc; |
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144 | encoder->crtc = crtc; |
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145 | break; |
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146 | }; |
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147 | crtc_mask <<= 1; |
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148 | }; |
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149 | }; |
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150 | |||
151 | |||
152 | { |
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153 | dbgprintf("No CRTC for encoder %d\n", encoder->base.id); |
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154 | return -1; |
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155 | }; |
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156 | |||
157 | |||
158 | |||
159 | |||
160 | |||
161 | |||
162 | |||
163 | os_display->connector = connector; |
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164 | os_display->crtc = crtc; |
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165 | |||
166 | |||
167 | |||
168 | |||
169 | |||
170 | { |
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171 | struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc); |
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172 | |||
173 | |||
174 | { |
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175 | init_cursor(cursor); |
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176 | }; |
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177 | |||
178 | |||
179 | os_display->init_cursor = init_cursor; |
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180 | os_display->select_cursor = select_cursor_kms; |
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181 | os_display->show_cursor = NULL; |
||
182 | os_display->move_cursor = move_cursor_kms; |
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183 | os_display->restore_cursor = restore_cursor; |
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184 | os_display->disable_mouse = disable_mouse; |
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185 | |||
186 | |||
187 | intel_crtc->cursor_y = os_display->height/2; |
||
188 | |||
189 | |||
190 | }; |
||
191 | safe_sti(ifl); |
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192 | |||
193 | |||
2340 | Serge | 194 | #define XY_COLOR_BLT ((2<<29)|(0x50<<22)|(0x4)) |
195 | #define BLT_WRITE_ALPHA (1<<21) |
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196 | #define BLT_WRITE_RGB (1<<20) |
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197 | |||
2338 | Serge | 198 | |
2340 | Serge | 199 | struct drm_i915_gem_object *obj; |
200 | struct intel_ring_buffer *ring; |
||
201 | |||
202 | |||
203 | |||
204 | |||
205 | |||
206 | |||
207 | br13 = os_display->pitch; |
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208 | br13 |= 0xF0 << 16; |
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209 | br13 |= 3 << 24; |
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210 | |||
211 | |||
212 | i915_gem_object_pin(obj, 4096, true); |
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213 | |||
214 | |||
215 | cmd_offset = obj->gtt_offset; |
||
216 | |||
217 | |||
218 | b[n++] = cmd; |
||
219 | b[n++] = br13; |
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220 | b[n++] = 0; // top, left |
||
221 | b[n++] = (128 << 16) | 128; // bottom, right |
||
222 | b[n++] = 0; // dst |
||
223 | b[n++] = 0x0000FF00; |
||
224 | b[n++] = MI_BATCH_BUFFER_END; |
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225 | if( n & 1) |
||
226 | b[n++] = MI_NOOP; |
||
227 | |||
228 | |||
229 | // i915_gem_object_set_to_gtt_domain(obj, false); |
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230 | |||
231 | |||
232 | |||
233 | ring->dispatch_execbuffer(ring,cmd_offset, n*4); |
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234 | |||
235 | |||
236 | |||
237 | |||
2338 | Serge | 238 | |
239 | |||
240 | }; |
||
241 | |||
242 | |||
243 | |||
244 | videomode_t *reqmode, bool strict) |
||
245 | { |
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246 | struct drm_display_mode *mode = NULL, *tmpmode; |
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247 | drm_i915_private_t *dev_priv = dev->dev_private; |
||
248 | struct drm_fb_helper *fb_helper = &dev_priv->fbdev->helper; |
||
249 | |||
250 | |||
251 | |||
252 | |||
253 | |||
254 | |||
255 | reqmode->width, reqmode->height, reqmode->freq); |
||
256 | |||
257 | |||
258 | { |
||
259 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
||
260 | (drm_mode_height(tmpmode) == reqmode->height) && |
||
261 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
||
262 | { |
||
263 | mode = tmpmode; |
||
264 | goto do_set; |
||
265 | } |
||
266 | }; |
||
267 | |||
268 | |||
269 | { |
||
270 | list_for_each_entry(tmpmode, &connector->modes, head) |
||
271 | { |
||
272 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
||
273 | (drm_mode_height(tmpmode) == reqmode->height) ) |
||
274 | { |
||
275 | mode = tmpmode; |
||
276 | goto do_set; |
||
277 | } |
||
278 | }; |
||
279 | }; |
||
280 | |||
281 | |||
282 | |||
283 | |||
284 | { |
||
285 | struct drm_framebuffer *fb; |
||
286 | struct drm_encoder *encoder; |
||
287 | struct drm_crtc *crtc; |
||
288 | |||
289 | |||
290 | char *enc_name; |
||
291 | |||
292 | |||
293 | crtc = encoder->crtc; |
||
294 | |||
295 | |||
296 | enc_name = drm_get_encoder_name(encoder); |
||
297 | |||
298 | |||
299 | reqmode->width, reqmode->height, con_name, enc_name); |
||
300 | |||
301 | |||
302 | |||
303 | |||
304 | fb->height = reqmode->height; |
||
305 | fb->pitch = ALIGN(reqmode->width * 4, 64); |
||
306 | fb->bits_per_pixel = 32; |
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307 | fb->depth == 24; |
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308 | |||
309 | |||
310 | crtc->enabled = true; |
||
311 | os_display->crtc = crtc; |
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312 | |||
313 | |||
314 | |||
315 | |||
316 | // radeon_show_cursor_kms(crtc); |
||
317 | |||
318 | |||
319 | { |
||
320 | os_display->width = fb->width; |
||
321 | os_display->height = fb->height; |
||
322 | os_display->pitch = fb->pitch; |
||
323 | os_display->vrefresh = drm_mode_vrefresh(mode); |
||
324 | |||
325 | |||
326 | |||
327 | |||
328 | fb->width, fb->height, fb->pitch); |
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329 | } |
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330 | else |
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331 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
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332 | fb->width, fb->height, crtc); |
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333 | } |
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334 | |||
335 | |||
336 | return ret; |
||
337 | }; |
||
338 | |||
339 | |||
340 | |||
341 | |||
342 | { |
||
343 | int err = -1; |
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344 | |||
345 | |||
346 | |||
347 | |||
348 | |||
349 | |||
350 | { |
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351 | *count = os_display->supported_modes; |
||
352 | err = 0; |
||
353 | } |
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354 | else if( mode != NULL ) |
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355 | { |
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356 | struct drm_display_mode *drmmode; |
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357 | int i = 0; |
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358 | |||
359 | |||
360 | *count = os_display->supported_modes; |
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361 | |||
362 | |||
363 | { |
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364 | if( i < *count) |
||
365 | { |
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366 | mode->width = drm_mode_width(drmmode); |
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367 | mode->height = drm_mode_height(drmmode); |
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368 | mode->bpp = 32; |
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369 | mode->freq = drm_mode_vrefresh(drmmode); |
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370 | i++; |
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371 | mode++; |
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372 | } |
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373 | else break; |
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374 | }; |
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375 | *count = i; |
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376 | err = 0; |
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377 | }; |
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378 | LEAVE(); |
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379 | return err; |
||
380 | }; |
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381 | |||
382 | |||
383 | { |
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384 | int err = -1; |
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385 | |||
386 | |||
387 | |||
388 | |||
389 | mode->width, mode->height, mode->freq); |
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390 | |||
391 | |||
392 | (mode->height != 0) && |
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393 | (mode->freq != 0 ) && |
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394 | ( (mode->width != os_display->width) || |
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395 | (mode->height != os_display->height) || |
||
396 | (mode->freq != os_display->vrefresh) ) ) |
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397 | { |
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398 | if( set_mode(os_display->ddev, os_display->connector, mode, true) ) |
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399 | err = 0; |
||
400 | }; |
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401 | |||
402 | |||
403 | return err; |
||
404 | }; |
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405 | |||
406 | |||
407 | { |
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408 | list_del(&cursor->list); |
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409 | // radeon_bo_unpin(cursor->robj); |
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410 | // KernelFree(cursor->data); |
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411 | __DestroyObject(cursor); |
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412 | }; |
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413 | |||
414 | |||
415 | { |
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416 | struct drm_i915_private *dev_priv = os_display->ddev->dev_private; |
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417 | struct drm_i915_gem_object *obj; |
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418 | uint32_t *bits; |
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419 | uint32_t *src; |
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420 | |||
421 | |||
422 | int ret; |
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423 | |||
424 | |||
425 | |||
426 | |||
427 | { |
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428 | bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4); |
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429 | if (unlikely(bits == NULL)) |
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430 | return ENOMEM; |
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431 | cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits); |
||
432 | } |
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433 | else |
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434 | { |
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435 | obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4); |
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436 | if (unlikely(obj == NULL)) |
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437 | return -ENOMEM; |
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438 | |||
439 | |||
440 | if (ret) { |
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441 | // drm_gem_object_unreference(&obj->base); |
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442 | return ret; |
||
443 | } |
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444 | |||
445 | |||
446 | * GTT space is continuous. I guarantee it. */ |
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447 | |||
448 | |||
449 | CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW); |
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450 | |||
451 | |||
452 | { |
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453 | // i915_gem_object_unpin(obj); |
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454 | // drm_gem_object_unreference(&obj->base); |
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455 | return -ENOMEM; |
||
456 | }; |
||
457 | cursor->cobj = obj; |
||
458 | }; |
||
459 | |||
460 | |||
461 | |||
462 | |||
463 | { |
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464 | for(j = 0; j < 32; j++) |
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465 | *bits++ = *src++; |
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466 | for(j = 32; j < CURSOR_WIDTH; j++) |
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467 | *bits++ = 0; |
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468 | } |
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469 | for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++) |
||
470 | *bits++ = 0; |
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471 | |||
472 | |||
473 | |||
474 | |||
2340 | Serge | 475 | |
2338 | Serge | 476 | |
477 | |||
478 | |||
479 | LEAVE(); |
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480 | |||
481 | |||
482 | } |
||
483 | |||
484 | |||
485 | |||
486 | { |
||
487 | struct drm_device *dev = crtc->dev; |
||
488 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
490 | int pipe = intel_crtc->pipe; |
||
491 | bool visible = base != 0; |
||
492 | |||
493 | |||
494 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
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495 | if (base) { |
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496 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
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497 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
||
498 | cntl |= pipe << 28; /* Connect to correct pipe */ |
||
499 | } else { |
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500 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
||
501 | cntl |= CURSOR_MODE_DISABLE; |
||
502 | } |
||
503 | I915_WRITE(CURCNTR(pipe), cntl); |
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504 | |||
505 | |||
506 | } |
||
507 | /* and commit changes on next vblank */ |
||
508 | I915_WRITE(CURBASE(pipe), base); |
||
509 | } |
||
510 | |||
511 | |||
512 | { |
||
513 | struct drm_i915_private *dev_priv = os_display->ddev->dev_private; |
||
514 | struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc); |
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515 | u32 base, pos; |
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516 | bool visible; |
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517 | |||
518 | |||
519 | |||
520 | |||
521 | intel_crtc->cursor_y = y; |
||
522 | |||
523 | |||
524 | y = y - cursor->hot_y; |
||
525 | |||
526 | |||
527 | |||
528 | |||
529 | |||
530 | if (x >= os_display->width) |
||
531 | base = 0; |
||
532 | |||
533 | |||
534 | base = 0; |
||
535 | |||
536 | |||
537 | { |
||
538 | if (x + intel_crtc->cursor_width < 0) |
||
539 | base = 0; |
||
540 | |||
541 | |||
542 | x = -x; |
||
543 | } |
||
544 | pos |= x << CURSOR_X_SHIFT; |
||
545 | |||
546 | |||
547 | { |
||
548 | if (y + intel_crtc->cursor_height < 0) |
||
549 | base = 0; |
||
550 | |||
551 | |||
552 | y = -y; |
||
553 | } |
||
554 | pos |= y << CURSOR_Y_SHIFT; |
||
555 | |||
556 | |||
557 | if (!visible && !intel_crtc->cursor_visible) |
||
558 | return; |
||
559 | |||
560 | |||
561 | // if (IS_845G(dev) || IS_I865G(dev)) |
||
562 | // i845_update_cursor(crtc, base); |
||
563 | // else |
||
564 | i9xx_update_cursor(os_display->crtc, base); |
||
565 | |||
566 | |||
567 | |||
568 | |||
569 | |||
570 | { |
||
571 | struct drm_i915_private *dev_priv = os_display->ddev->dev_private; |
||
572 | struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc); |
||
573 | cursor_t *old; |
||
574 | |||
575 | |||
576 | os_display->cursor = cursor; |
||
577 | |||
578 | |||
579 | intel_crtc->cursor_addr = cursor->cobj->gtt_offset; |
||
580 | else |
||
581 | intel_crtc->cursor_addr = cursor->cobj; |
||
582 | |||
583 | |||
584 | intel_crtc->cursor_height = 32; |
||
585 | |||
586 | |||
587 | return old; |
||
588 | }; |
||
589 | |||
590 | |||
2340 | Serge | 591 | |
592 | |||
593 | |||
594 | |||
595 | int w, int h, int pitch) |
||
596 | { |
||
2338 | Serge | 597 | |
598 | |||
2340 | Serge | 599 | struct intel_ring_buffer *ring; |
600 | |||
2338 | Serge | 601 | |
2340 | Serge | 602 | u32_t offset; |
603 | |||
2338 | Serge | 604 | |
2340 | Serge | 605 | |
2338 | Serge | 606 | |
2340 | Serge | 607 | // cmd_buffer&= 0xFFFFF000; |
608 | |||
2338 | Serge | 609 | |
2340 | Serge | 610 | |
2338 | Serge | 611 | |
2340 | Serge | 612 | |
2338 | Serge | 613 | |
2340 | Serge | 614 | |
2338 | Serge | 615 | |
2340 | Serge | 616 | br13 = os_display->pitch; |
617 | br13 |= 0xCC << 16; |
||
618 | br13 |= 3 << 24; |
||
619 | |||
2338 | Serge | 620 | |
2340 | Serge | 621 | b[n++] = br13; |
622 | b[n++] = (y << 16) | x; |
||
623 | b[n++] = ( (y+h) << 16) | (x+w); // bottom, right |
||
624 | b[n++] = 0; // dst_offset |
||
625 | b[n++] = 0; //src_top|src_left |
||
626 | |||
2338 | Serge | 627 | |
2340 | Serge | 628 | b[n++] = (u32_t)src_offset; |
629 | |||
2338 | Serge | 630 | |
2340 | Serge | 631 | if( n & 1) |
632 | b[n++] = MI_NOOP; |
||
633 | |||
2338 | Serge | 634 | |
2340 | Serge | 635 | |
636 | |||
637 | ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
||
638 | |||
639 | |||
640 | // if (ret) |
||
641 | // return ret; |
||
642 | |||
643 | |||
644 | // if (invalidate & I915_GEM_GPU_DOMAINS) |
||
645 | // cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
||
646 | intel_ring_emit(ring, MI_FLUSH_DW); |
||
647 | intel_ring_emit(ring, 0); |
||
648 | intel_ring_emit(ring, 0); |
||
649 | intel_ring_emit(ring, MI_NOOP); |
||
650 | intel_ring_advance(ring); |
||
651 | |||
652 | |||
653 | |||
654 | return -1; |
||
655 | }; |
||
656 | |||
657 | |||
658 | |||
659 | int src_x, int src_y, u32 w, u32 h) |
||
660 | { |
||
661 | drm_i915_private_t *dev_priv = main_device->dev_private; |
||
662 | struct intel_ring_buffer *ring; |
||
663 | |||
664 | |||
665 | u32_t br13, cmd, *b; |
||
666 | u32_t offset; |
||
667 | |||
668 | |||
669 | |||
670 | |||
671 | return -1; |
||
672 | |||
673 | |||
674 | |||
675 | |||
676 | return -1; |
||
677 | |||
678 | |||
679 | // cmd_buffer&= 0xFFFFF000; |
||
680 | |||
681 | |||
682 | |||
683 | |||
684 | |||
685 | |||
686 | |||
687 | |||
688 | br13 = os_display->pitch; |
||
689 | br13 |= 0xCC << 16; |
||
690 | br13 |= 3 << 24; |
||
691 | |||
692 | |||
693 | b[n++] = br13; |
||
694 | b[n++] = (dst_y << 16) | dst_x; |
||
695 | b[n++] = ( (dst_y+h) << 16) | (dst_x+w); // bottom, right |
||
696 | b[n++] = 0; // dst_offset |
||
697 | b[n++] = (src_y << 16) | src_x; |
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698 | |||
699 | |||
700 | b[n++] = bitmap->gaddr; |
||
701 | |||
702 | |||
703 | if( n & 1) |
||
704 | b[n++] = MI_NOOP; |
||
705 | |||
706 | |||
707 | |||
708 | |||
709 | ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
||
710 | |||
711 | |||
712 | // if (ret) |
||
713 | // return ret; |
||
714 | |||
715 | |||
716 | intel_ring_emit(ring, 0); |
||
717 | intel_ring_emit(ring, 0); |
||
718 | intel_ring_emit(ring, MI_NOOP); |
||
719 | intel_ring_advance(ring); |
||
720 | |||
721 | |||
722 | fail: |
||
723 | return -1; |
||
724 | };><>><>><>><>><>><>><>><>><>22)|6) |
||
725 |