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/*

 * Copyright © 2013 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 */

#include "i915_drv.h"

#include "intel_drv.h"

#define FORCEWAKE_ACK_TIMEOUT_MS 2

#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))

#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))

#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))

#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))

#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))

#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)

static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)

{

	u32 gt_thread_status_mask;

	if (IS_HASWELL(dev_priv->dev))

		gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;

	else

		gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;

	/* w/a for a sporadic read returning 0 by waiting for the GT

	 * thread to wake up.

	 */

	if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))

		DRM_ERROR("GT thread status wait timed out\n");

}

static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE, 0);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

}

static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE, 1);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");

	/* WaRsForcewakeWaitTC0:snb */

	__gen6_gt_wait_for_thread_c0(dev_priv);

}

static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

}

static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)

{

	u32 forcewake_ack;

	if (IS_HASWELL(dev_priv->dev))

		forcewake_ack = FORCEWAKE_ACK_HSW;

	else

		forcewake_ack = FORCEWAKE_MT_ACK;

	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE_MT,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

	if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");

	/* WaRsForcewakeWaitTC0:ivb,hsw */

	__gen6_gt_wait_for_thread_c0(dev_priv);

}

static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)

{

	u32 gtfifodbg;

	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);

	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,

	     "MMIO read or write has been dropped %x\n", gtfifodbg))

		__raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);

}

static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE, 0);

	/* something from same cacheline, but !FORCEWAKE */

	__raw_posting_read(dev_priv, ECOBUS);

	gen6_gt_check_fifodbg(dev_priv);

}

static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_MT,

			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));

	/* something from same cacheline, but !FORCEWAKE_MT */

	__raw_posting_read(dev_priv, ECOBUS);

	gen6_gt_check_fifodbg(dev_priv);

}

static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int ret = 0;

	if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {

		int loop = 500;

		u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);

		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {

			udelay(10);

			fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);

		}

		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))

			++ret;

		dev_priv->uncore.fifo_count = fifo;

	}

	dev_priv->uncore.fifo_count--;

	return ret;

}

static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,

			   _MASKED_BIT_DISABLE(0xffff));

	/* something from same cacheline, but !FORCEWAKE_VLV */

	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);

}

static void vlv_force_wake_get(struct drm_i915_private *dev_priv)

{

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");

	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,

			   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");

	if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) &

			     FORCEWAKE_KERNEL),

			    FORCEWAKE_ACK_TIMEOUT_MS))

		DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");

	/* WaRsForcewakeWaitTC0:vlv */

	__gen6_gt_wait_for_thread_c0(dev_priv);

}

static void vlv_force_wake_put(struct drm_i915_private *dev_priv)

{

	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,

			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));

	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,

			   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));

	/* The below doubles as a POSTING_READ */

	gen6_gt_check_fifodbg(dev_priv);

}

void intel_uncore_early_sanitize(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_FPGA_DBG_UNCLAIMED(dev))

		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

}

void intel_uncore_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_VALLEYVIEW(dev)) {

		dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;

		dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;

	} else if (IS_HASWELL(dev)) {

		dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;

		dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;

	} else if (IS_IVYBRIDGE(dev)) {

		u32 ecobus;

		/* IVB configs may use multi-threaded forcewake */

		/* A small trick here - if the bios hasn't configured

		 * MT forcewake, and if the device is in RC6, then

		 * force_wake_mt_get will not wake the device and the

		 * ECOBUS read will return zero. Which will be

		 * (correctly) interpreted by the test below as MT

		 * forcewake being disabled.

		 */

		mutex_lock(&dev->struct_mutex);

		__gen6_gt_force_wake_mt_get(dev_priv);

		ecobus = __raw_i915_read32(dev_priv, ECOBUS);

		__gen6_gt_force_wake_mt_put(dev_priv);

		mutex_unlock(&dev->struct_mutex);

		if (ecobus & FORCEWAKE_MT_ENABLE) {

			dev_priv->uncore.funcs.force_wake_get =

				__gen6_gt_force_wake_mt_get;

			dev_priv->uncore.funcs.force_wake_put =

				__gen6_gt_force_wake_mt_put;

		} else {

			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");

			DRM_INFO("when using vblank-synced partial screen updates.\n");

			dev_priv->uncore.funcs.force_wake_get =

				__gen6_gt_force_wake_get;

			dev_priv->uncore.funcs.force_wake_put =

				__gen6_gt_force_wake_put;

		}

	} else if (IS_GEN6(dev)) {

		dev_priv->uncore.funcs.force_wake_get =

			__gen6_gt_force_wake_get;

		dev_priv->uncore.funcs.force_wake_put =

			__gen6_gt_force_wake_put;

	}