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Rev | Author | Line No. | Line |
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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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4104 | Serge | 35 | #include |
6084 | serge | 36 | #include |
37 | #include |
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2342 | Serge | 38 | #include "intel_drv.h" |
3031 | serge | 39 | #include |
2342 | Serge | 40 | #include "i915_drv.h" |
41 | |||
5354 | serge | 42 | static bool |
43 | format_is_yuv(uint32_t format) |
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44 | { |
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45 | switch (format) { |
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46 | case DRM_FORMAT_YUYV: |
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47 | case DRM_FORMAT_UYVY: |
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48 | case DRM_FORMAT_VYUY: |
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49 | case DRM_FORMAT_YVYU: |
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50 | return true; |
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51 | default: |
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52 | return false; |
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53 | } |
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54 | } |
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55 | |||
6084 | serge | 56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) |
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5060 | serge | 58 | { |
59 | /* paranoia */ |
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6084 | serge | 60 | if (!adjusted_mode->crtc_htotal) |
5060 | serge | 61 | return 1; |
62 | |||
6084 | serge | 63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); |
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5060 | serge | 65 | } |
66 | |||
5354 | serge | 67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers |
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69 | * @crtc: the crtc of which the registers are going to be updated |
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70 | * @start_vbl_count: vblank counter return pointer used for error checking |
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71 | * |
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72 | * Mark the start of an update to pipe registers that should be updated |
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73 | * atomically regarding vblank. If the next vblank will happens within |
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74 | * the next 100 us, this function waits until the vblank passes. |
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75 | * |
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76 | * After a successful call to this function, interrupts will be disabled |
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77 | * until a subsequent call to intel_pipe_update_end(). That is done to |
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78 | * avoid random delays. The value written to @start_vbl_count should be |
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79 | * supplied to intel_pipe_update_end() for error checking. |
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80 | */ |
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6084 | serge | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
5060 | serge | 82 | { |
83 | struct drm_device *dev = crtc->base.dev; |
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6084 | serge | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 85 | enum pipe pipe = crtc->pipe; |
86 | long timeout = msecs_to_jiffies_timeout(1); |
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87 | int scanline, min, max, vblank_start; |
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6103 | serge | 88 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
89 | DEFINE_WAIT(wait); |
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5060 | serge | 90 | |
6084 | serge | 91 | vblank_start = adjusted_mode->crtc_vblank_start; |
92 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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5060 | serge | 93 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
94 | |||
95 | /* FIXME needs to be calibrated sensibly */ |
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6084 | serge | 96 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
5060 | serge | 97 | max = vblank_start - 1; |
98 | |||
6103 | serge | 99 | local_irq_disable(); |
100 | |||
5060 | serge | 101 | if (min <= 0 || max <= 0) |
6084 | serge | 102 | return; |
5060 | serge | 103 | |
6103 | serge | 104 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
105 | return; |
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5060 | serge | 106 | |
6084 | serge | 107 | crtc->debug.min_vbl = min; |
108 | crtc->debug.max_vbl = max; |
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109 | trace_i915_pipe_update_start(crtc); |
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5060 | serge | 110 | |
111 | for (;;) { |
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112 | /* |
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113 | * prepare_to_wait() has a memory barrier, which guarantees |
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114 | * other CPUs can see the task state update by the time we |
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115 | * read the scanline. |
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116 | */ |
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5354 | serge | 117 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
5060 | serge | 118 | |
119 | scanline = intel_get_crtc_scanline(crtc); |
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120 | if (scanline < min || scanline > max) |
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121 | break; |
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122 | |||
123 | if (timeout <= 0) { |
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124 | DRM_ERROR("Potential atomic update failure on pipe %c\n", |
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125 | pipe_name(crtc->pipe)); |
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126 | break; |
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127 | } |
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128 | |||
6103 | serge | 129 | local_irq_enable(); |
130 | |||
131 | { |
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132 | unsigned long expire; |
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133 | expire = timeout + jiffies; |
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134 | WaitEventTimeout(wait.evnt, timeout);; |
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135 | timeout = expire - jiffies; |
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136 | timeout = timeout < 0 ? 0 : timeout; |
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137 | } |
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138 | local_irq_disable(); |
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5060 | serge | 139 | } |
140 | |||
5354 | serge | 141 | finish_wait(wq, &wait); |
5060 | serge | 142 | |
6103 | serge | 143 | drm_crtc_vblank_put(&crtc->base); |
144 | |||
6084 | serge | 145 | crtc->debug.scanline_start = scanline; |
146 | crtc->debug.start_vbl_time = ktime_get(); |
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147 | crtc->debug.start_vbl_count = |
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148 | dev->driver->get_vblank_counter(dev, pipe); |
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5060 | serge | 149 | |
6084 | serge | 150 | trace_i915_pipe_update_vblank_evaded(crtc); |
5060 | serge | 151 | } |
152 | |||
5354 | serge | 153 | /** |
154 | * intel_pipe_update_end() - end update of a set of display registers |
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155 | * @crtc: the crtc of which the registers were updated |
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156 | * @start_vbl_count: start vblank counter (used for error checking) |
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157 | * |
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158 | * Mark the end of an update started with intel_pipe_update_start(). This |
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159 | * re-enables interrupts and verifies the update was actually completed |
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160 | * before a vblank using the value of @start_vbl_count. |
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161 | */ |
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6084 | serge | 162 | void intel_pipe_update_end(struct intel_crtc *crtc) |
5060 | serge | 163 | { |
164 | struct drm_device *dev = crtc->base.dev; |
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165 | enum pipe pipe = crtc->pipe; |
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6084 | serge | 166 | int scanline_end = intel_get_crtc_scanline(crtc); |
5060 | serge | 167 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
6084 | serge | 168 | ktime_t end_vbl_time = ktime_get(); |
5060 | serge | 169 | |
6084 | serge | 170 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
5060 | serge | 171 | |
6103 | serge | 172 | local_irq_enable(); |
5060 | serge | 173 | |
6084 | serge | 174 | if (crtc->debug.start_vbl_count && |
175 | crtc->debug.start_vbl_count != end_vbl_count) { |
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176 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", |
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177 | pipe_name(pipe), crtc->debug.start_vbl_count, |
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178 | end_vbl_count, |
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179 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), |
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180 | crtc->debug.min_vbl, crtc->debug.max_vbl, |
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181 | crtc->debug.scanline_start, scanline_end); |
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182 | } |
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5060 | serge | 183 | } |
184 | |||
2342 | Serge | 185 | static void |
5354 | serge | 186 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, |
187 | struct drm_framebuffer *fb, |
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6084 | serge | 188 | int crtc_x, int crtc_y, |
5354 | serge | 189 | unsigned int crtc_w, unsigned int crtc_h, |
190 | uint32_t x, uint32_t y, |
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191 | uint32_t src_w, uint32_t src_h) |
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192 | { |
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193 | struct drm_device *dev = drm_plane->dev; |
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194 | struct drm_i915_private *dev_priv = dev->dev_private; |
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195 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
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6084 | serge | 196 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
5354 | serge | 197 | const int pipe = intel_plane->pipe; |
198 | const int plane = intel_plane->plane + 1; |
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6084 | serge | 199 | u32 plane_ctl, stride_div, stride; |
200 | const struct drm_intel_sprite_colorkey *key = |
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201 | &to_intel_plane_state(drm_plane->state)->ckey; |
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6660 | serge | 202 | u32 surf_addr; |
6084 | serge | 203 | u32 tile_height, plane_offset, plane_size; |
204 | unsigned int rotation; |
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205 | int x_offset, y_offset; |
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206 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
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207 | int scaler_id; |
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5354 | serge | 208 | |
6084 | serge | 209 | plane_ctl = PLANE_CTL_ENABLE | |
210 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
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211 | PLANE_CTL_PIPE_CSC_ENABLE; |
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5354 | serge | 212 | |
6084 | serge | 213 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
214 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
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5354 | serge | 215 | |
6084 | serge | 216 | rotation = drm_plane->state->rotation; |
217 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
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5354 | serge | 218 | |
6084 | serge | 219 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
220 | fb->pixel_format); |
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221 | |||
222 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
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223 | |||
5354 | serge | 224 | /* Sizes are 0 based */ |
225 | src_w--; |
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226 | src_h--; |
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227 | crtc_w--; |
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228 | crtc_h--; |
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229 | |||
6084 | serge | 230 | if (key->flags) { |
231 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); |
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232 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); |
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233 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); |
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234 | } |
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5354 | serge | 235 | |
6084 | serge | 236 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
237 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; |
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238 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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239 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; |
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5354 | serge | 240 | |
6084 | serge | 241 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
5354 | serge | 242 | |
6084 | serge | 243 | if (intel_rotation_90_or_270(rotation)) { |
244 | /* stride: Surface height in tiles */ |
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245 | tile_height = intel_tile_height(dev, fb->pixel_format, |
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246 | fb->modifier[0], 0); |
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247 | stride = DIV_ROUND_UP(fb->height, tile_height); |
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248 | plane_size = (src_w << 16) | src_h; |
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249 | x_offset = stride * tile_height - y - (src_h + 1); |
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250 | y_offset = x; |
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251 | } else { |
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252 | stride = fb->pitches[0] / stride_div; |
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253 | plane_size = (src_h << 16) | src_w; |
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254 | x_offset = x; |
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255 | y_offset = y; |
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256 | } |
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257 | plane_offset = y_offset << 16 | x_offset; |
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5354 | serge | 258 | |
6084 | serge | 259 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); |
260 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); |
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261 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
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5354 | serge | 262 | |
6084 | serge | 263 | /* program plane scaler */ |
264 | if (scaler_id >= 0) { |
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265 | uint32_t ps_ctrl = 0; |
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5354 | serge | 266 | |
6084 | serge | 267 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, |
268 | PS_PLANE_SEL(plane)); |
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269 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | |
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270 | crtc_state->scaler_state.scalers[scaler_id].mode; |
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271 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
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272 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
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273 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); |
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274 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), |
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275 | ((crtc_w + 1) << 16)|(crtc_h + 1)); |
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5354 | serge | 276 | |
6084 | serge | 277 | I915_WRITE(PLANE_POS(pipe, plane), 0); |
278 | } else { |
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279 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
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280 | } |
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281 | |||
5354 | serge | 282 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
6084 | serge | 283 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
284 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 285 | } |
286 | |||
287 | static void |
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6084 | serge | 288 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
5354 | serge | 289 | { |
6084 | serge | 290 | struct drm_device *dev = dplane->dev; |
5354 | serge | 291 | struct drm_i915_private *dev_priv = dev->dev_private; |
6084 | serge | 292 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
5354 | serge | 293 | const int pipe = intel_plane->pipe; |
6084 | serge | 294 | const int plane = intel_plane->plane + 1; |
5354 | serge | 295 | |
6084 | serge | 296 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
5354 | serge | 297 | |
6084 | serge | 298 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
299 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 300 | } |
301 | |||
302 | static void |
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303 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) |
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304 | { |
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305 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; |
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306 | int plane = intel_plane->plane; |
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307 | |||
308 | /* Seems RGB data bypasses the CSC always */ |
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309 | if (!format_is_yuv(format)) |
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310 | return; |
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311 | |||
312 | /* |
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313 | * BT.601 limited range YCbCr -> full range RGB |
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314 | * |
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315 | * |r| | 6537 4769 0| |cr | |
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316 | * |g| = |-3330 4769 -1605| x |y-64| |
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317 | * |b| | 0 4769 8263| |cb | |
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318 | * |
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319 | * Cb and Cr apparently come in as signed already, so no |
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320 | * need for any offset. For Y we need to remove the offset. |
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321 | */ |
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322 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); |
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323 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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324 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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325 | |||
326 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); |
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327 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); |
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328 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); |
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329 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); |
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330 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); |
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331 | |||
332 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); |
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333 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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334 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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335 | |||
336 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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337 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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338 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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339 | } |
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340 | |||
341 | static void |
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4104 | Serge | 342 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
343 | struct drm_framebuffer *fb, |
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6084 | serge | 344 | int crtc_x, int crtc_y, |
3746 | Serge | 345 | unsigned int crtc_w, unsigned int crtc_h, |
346 | uint32_t x, uint32_t y, |
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347 | uint32_t src_w, uint32_t src_h) |
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348 | { |
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349 | struct drm_device *dev = dplane->dev; |
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350 | struct drm_i915_private *dev_priv = dev->dev_private; |
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351 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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6084 | serge | 352 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3746 | Serge | 353 | int pipe = intel_plane->pipe; |
354 | int plane = intel_plane->plane; |
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355 | u32 sprctl; |
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356 | unsigned long sprsurf_offset, linear_offset; |
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357 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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6084 | serge | 358 | const struct drm_intel_sprite_colorkey *key = |
359 | &to_intel_plane_state(dplane->state)->ckey; |
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3746 | Serge | 360 | |
6084 | serge | 361 | sprctl = SP_ENABLE; |
3746 | Serge | 362 | |
363 | switch (fb->pixel_format) { |
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364 | case DRM_FORMAT_YUYV: |
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365 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
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366 | break; |
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367 | case DRM_FORMAT_YVYU: |
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368 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
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369 | break; |
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370 | case DRM_FORMAT_UYVY: |
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371 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
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372 | break; |
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373 | case DRM_FORMAT_VYUY: |
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374 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
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375 | break; |
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376 | case DRM_FORMAT_RGB565: |
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377 | sprctl |= SP_FORMAT_BGR565; |
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378 | break; |
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379 | case DRM_FORMAT_XRGB8888: |
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380 | sprctl |= SP_FORMAT_BGRX8888; |
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381 | break; |
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382 | case DRM_FORMAT_ARGB8888: |
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383 | sprctl |= SP_FORMAT_BGRA8888; |
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384 | break; |
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385 | case DRM_FORMAT_XBGR2101010: |
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386 | sprctl |= SP_FORMAT_RGBX1010102; |
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387 | break; |
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388 | case DRM_FORMAT_ABGR2101010: |
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389 | sprctl |= SP_FORMAT_RGBA1010102; |
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390 | break; |
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391 | case DRM_FORMAT_XBGR8888: |
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392 | sprctl |= SP_FORMAT_RGBX8888; |
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393 | break; |
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394 | case DRM_FORMAT_ABGR8888: |
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395 | sprctl |= SP_FORMAT_RGBA8888; |
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396 | break; |
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397 | default: |
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398 | /* |
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399 | * If we get here one of the upper layers failed to filter |
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400 | * out the unsupported plane formats |
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401 | */ |
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402 | BUG(); |
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403 | break; |
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404 | } |
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405 | |||
4560 | Serge | 406 | /* |
407 | * Enable gamma to match primary/cursor plane behaviour. |
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408 | * FIXME should be user controllable via propertiesa. |
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409 | */ |
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410 | sprctl |= SP_GAMMA_ENABLE; |
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411 | |||
3746 | Serge | 412 | if (obj->tiling_mode != I915_TILING_NONE) |
413 | sprctl |= SP_TILED; |
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414 | |||
415 | /* Sizes are 0 based */ |
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416 | src_w--; |
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417 | src_h--; |
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418 | crtc_w--; |
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419 | crtc_h--; |
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420 | |||
421 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
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6084 | serge | 422 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, |
423 | &x, &y, |
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3746 | Serge | 424 | obj->tiling_mode, |
425 | pixel_size, |
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426 | fb->pitches[0]); |
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427 | linear_offset -= sprsurf_offset; |
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428 | |||
6084 | serge | 429 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 430 | sprctl |= SP_ROTATE_180; |
431 | |||
432 | x += src_w; |
||
433 | y += src_h; |
||
434 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
435 | } |
||
436 | |||
6084 | serge | 437 | if (key->flags) { |
438 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
||
439 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
||
440 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
||
441 | } |
||
5060 | serge | 442 | |
6084 | serge | 443 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
444 | sprctl |= SP_SOURCE_KEY; |
||
5060 | serge | 445 | |
5354 | serge | 446 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
447 | chv_update_csc(intel_plane, fb->pixel_format); |
||
448 | |||
5060 | serge | 449 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
450 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
||
451 | |||
3746 | Serge | 452 | if (obj->tiling_mode != I915_TILING_NONE) |
453 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
||
454 | else |
||
455 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
||
456 | |||
5354 | serge | 457 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
458 | |||
3746 | Serge | 459 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
460 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
||
4560 | Serge | 461 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
6084 | serge | 462 | sprsurf_offset); |
463 | POSTING_READ(SPSURF(pipe, plane)); |
||
3746 | Serge | 464 | } |
465 | |||
466 | static void |
||
4104 | Serge | 467 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
3746 | Serge | 468 | { |
469 | struct drm_device *dev = dplane->dev; |
||
470 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
471 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
||
472 | int pipe = intel_plane->pipe; |
||
473 | int plane = intel_plane->plane; |
||
474 | |||
6084 | serge | 475 | I915_WRITE(SPCNTR(pipe, plane), 0); |
5060 | serge | 476 | |
4560 | Serge | 477 | I915_WRITE(SPSURF(pipe, plane), 0); |
6084 | serge | 478 | POSTING_READ(SPSURF(pipe, plane)); |
3746 | Serge | 479 | } |
480 | |||
481 | static void |
||
4104 | Serge | 482 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
483 | struct drm_framebuffer *fb, |
||
6084 | serge | 484 | int crtc_x, int crtc_y, |
2342 | Serge | 485 | unsigned int crtc_w, unsigned int crtc_h, |
486 | uint32_t x, uint32_t y, |
||
487 | uint32_t src_w, uint32_t src_h) |
||
488 | { |
||
489 | struct drm_device *dev = plane->dev; |
||
490 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
491 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 492 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
493 | enum pipe pipe = intel_plane->pipe; |
||
2342 | Serge | 494 | u32 sprctl, sprscale = 0; |
3243 | Serge | 495 | unsigned long sprsurf_offset, linear_offset; |
496 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
||
6084 | serge | 497 | const struct drm_intel_sprite_colorkey *key = |
498 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 499 | |
6084 | serge | 500 | sprctl = SPRITE_ENABLE; |
2342 | Serge | 501 | |
502 | switch (fb->pixel_format) { |
||
503 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 504 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 505 | break; |
506 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 507 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 508 | break; |
509 | case DRM_FORMAT_YUYV: |
||
510 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
||
511 | break; |
||
512 | case DRM_FORMAT_YVYU: |
||
513 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
||
514 | break; |
||
515 | case DRM_FORMAT_UYVY: |
||
516 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
||
517 | break; |
||
518 | case DRM_FORMAT_VYUY: |
||
519 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
||
520 | break; |
||
521 | default: |
||
3243 | Serge | 522 | BUG(); |
2342 | Serge | 523 | } |
524 | |||
4560 | Serge | 525 | /* |
526 | * Enable gamma to match primary/cursor plane behaviour. |
||
527 | * FIXME should be user controllable via propertiesa. |
||
528 | */ |
||
529 | sprctl |= SPRITE_GAMMA_ENABLE; |
||
530 | |||
2342 | Serge | 531 | if (obj->tiling_mode != I915_TILING_NONE) |
532 | sprctl |= SPRITE_TILED; |
||
533 | |||
4560 | Serge | 534 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4104 | Serge | 535 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
536 | else |
||
6084 | serge | 537 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
4104 | Serge | 538 | |
4560 | Serge | 539 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3480 | Serge | 540 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
541 | |||
2342 | Serge | 542 | /* Sizes are 0 based */ |
543 | src_w--; |
||
544 | src_h--; |
||
545 | crtc_w--; |
||
546 | crtc_h--; |
||
547 | |||
4560 | Serge | 548 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 549 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
550 | |||
3243 | Serge | 551 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
552 | sprsurf_offset = |
||
6084 | serge | 553 | intel_gen4_compute_page_offset(dev_priv, |
554 | &x, &y, obj->tiling_mode, |
||
555 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 556 | linear_offset -= sprsurf_offset; |
557 | |||
6084 | serge | 558 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 559 | sprctl |= SPRITE_ROTATE_180; |
560 | |||
561 | /* HSW and BDW does this automagically in hardware */ |
||
562 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
||
563 | x += src_w; |
||
564 | y += src_h; |
||
565 | linear_offset += src_h * fb->pitches[0] + |
||
566 | src_w * pixel_size; |
||
567 | } |
||
568 | } |
||
569 | |||
6084 | serge | 570 | if (key->flags) { |
571 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); |
||
572 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); |
||
573 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); |
||
574 | } |
||
5060 | serge | 575 | |
6084 | serge | 576 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
577 | sprctl |= SPRITE_DEST_KEY; |
||
578 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
579 | sprctl |= SPRITE_SOURCE_KEY; |
||
5060 | serge | 580 | |
581 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
||
582 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
||
583 | |||
3243 | Serge | 584 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
585 | * register */ |
||
4560 | Serge | 586 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3243 | Serge | 587 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
588 | else if (obj->tiling_mode != I915_TILING_NONE) |
||
2342 | Serge | 589 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 590 | else |
591 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
||
2342 | Serge | 592 | |
593 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
3243 | Serge | 594 | if (intel_plane->can_scale) |
6084 | serge | 595 | I915_WRITE(SPRSCALE(pipe), sprscale); |
2342 | Serge | 596 | I915_WRITE(SPRCTL(pipe), sprctl); |
4560 | Serge | 597 | I915_WRITE(SPRSURF(pipe), |
6084 | serge | 598 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
599 | POSTING_READ(SPRSURF(pipe)); |
||
2342 | Serge | 600 | } |
601 | |||
602 | static void |
||
4104 | Serge | 603 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 604 | { |
605 | struct drm_device *dev = plane->dev; |
||
606 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
607 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
608 | int pipe = intel_plane->pipe; |
||
609 | |||
6084 | serge | 610 | I915_WRITE(SPRCTL(pipe), 0); |
2342 | Serge | 611 | /* Can't leave the scaler enabled... */ |
3243 | Serge | 612 | if (intel_plane->can_scale) |
6084 | serge | 613 | I915_WRITE(SPRSCALE(pipe), 0); |
614 | |||
4560 | Serge | 615 | I915_WRITE(SPRSURF(pipe), 0); |
6084 | serge | 616 | POSTING_READ(SPRSURF(pipe)); |
2342 | Serge | 617 | } |
618 | |||
619 | static void |
||
4104 | Serge | 620 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
621 | struct drm_framebuffer *fb, |
||
6084 | serge | 622 | int crtc_x, int crtc_y, |
2342 | Serge | 623 | unsigned int crtc_w, unsigned int crtc_h, |
624 | uint32_t x, uint32_t y, |
||
625 | uint32_t src_w, uint32_t src_h) |
||
626 | { |
||
627 | struct drm_device *dev = plane->dev; |
||
628 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
629 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 630 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3243 | Serge | 631 | int pipe = intel_plane->pipe; |
632 | unsigned long dvssurf_offset, linear_offset; |
||
3031 | serge | 633 | u32 dvscntr, dvsscale; |
3243 | Serge | 634 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 635 | const struct drm_intel_sprite_colorkey *key = |
636 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 637 | |
6084 | serge | 638 | dvscntr = DVS_ENABLE; |
2342 | Serge | 639 | |
640 | switch (fb->pixel_format) { |
||
641 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 642 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 643 | break; |
644 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 645 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 646 | break; |
647 | case DRM_FORMAT_YUYV: |
||
648 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
||
649 | break; |
||
650 | case DRM_FORMAT_YVYU: |
||
651 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
||
652 | break; |
||
653 | case DRM_FORMAT_UYVY: |
||
654 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
||
655 | break; |
||
656 | case DRM_FORMAT_VYUY: |
||
657 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
||
658 | break; |
||
659 | default: |
||
3243 | Serge | 660 | BUG(); |
2342 | Serge | 661 | } |
662 | |||
4560 | Serge | 663 | /* |
664 | * Enable gamma to match primary/cursor plane behaviour. |
||
665 | * FIXME should be user controllable via propertiesa. |
||
666 | */ |
||
667 | dvscntr |= DVS_GAMMA_ENABLE; |
||
668 | |||
2342 | Serge | 669 | if (obj->tiling_mode != I915_TILING_NONE) |
670 | dvscntr |= DVS_TILED; |
||
671 | |||
3031 | serge | 672 | if (IS_GEN6(dev)) |
673 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
||
2342 | Serge | 674 | |
675 | /* Sizes are 0 based */ |
||
676 | src_w--; |
||
677 | src_h--; |
||
678 | crtc_w--; |
||
679 | crtc_h--; |
||
680 | |||
3031 | serge | 681 | dvsscale = 0; |
4560 | Serge | 682 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 683 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
684 | |||
3243 | Serge | 685 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
686 | dvssurf_offset = |
||
6084 | serge | 687 | intel_gen4_compute_page_offset(dev_priv, |
688 | &x, &y, obj->tiling_mode, |
||
689 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 690 | linear_offset -= dvssurf_offset; |
691 | |||
6084 | serge | 692 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 693 | dvscntr |= DVS_ROTATE_180; |
694 | |||
695 | x += src_w; |
||
696 | y += src_h; |
||
697 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
698 | } |
||
699 | |||
6084 | serge | 700 | if (key->flags) { |
701 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); |
||
702 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); |
||
703 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); |
||
704 | } |
||
5060 | serge | 705 | |
6084 | serge | 706 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
707 | dvscntr |= DVS_DEST_KEY; |
||
708 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
709 | dvscntr |= DVS_SOURCE_KEY; |
||
5060 | serge | 710 | |
711 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
||
712 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
||
713 | |||
3243 | Serge | 714 | if (obj->tiling_mode != I915_TILING_NONE) |
2342 | Serge | 715 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 716 | else |
717 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
||
2342 | Serge | 718 | |
719 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
720 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
||
721 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
||
4560 | Serge | 722 | I915_WRITE(DVSSURF(pipe), |
6084 | serge | 723 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
724 | POSTING_READ(DVSSURF(pipe)); |
||
2342 | Serge | 725 | } |
726 | |||
727 | static void |
||
4104 | Serge | 728 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 729 | { |
730 | struct drm_device *dev = plane->dev; |
||
731 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
732 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
733 | int pipe = intel_plane->pipe; |
||
734 | |||
6084 | serge | 735 | I915_WRITE(DVSCNTR(pipe), 0); |
2342 | Serge | 736 | /* Disable the scaler */ |
737 | I915_WRITE(DVSSCALE(pipe), 0); |
||
6084 | serge | 738 | |
4560 | Serge | 739 | I915_WRITE(DVSSURF(pipe), 0); |
6084 | serge | 740 | POSTING_READ(DVSSURF(pipe)); |
2342 | Serge | 741 | } |
742 | |||
743 | static int |
||
5354 | serge | 744 | intel_check_sprite_plane(struct drm_plane *plane, |
6084 | serge | 745 | struct intel_crtc_state *crtc_state, |
5354 | serge | 746 | struct intel_plane_state *state) |
2342 | Serge | 747 | { |
6084 | serge | 748 | struct drm_device *dev = plane->dev; |
749 | struct drm_crtc *crtc = state->base.crtc; |
||
750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2342 | Serge | 751 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 752 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 753 | int crtc_x, crtc_y; |
754 | unsigned int crtc_w, crtc_h; |
||
755 | uint32_t src_x, src_y, src_w, src_h; |
||
756 | struct drm_rect *src = &state->src; |
||
757 | struct drm_rect *dst = &state->dst; |
||
758 | const struct drm_rect *clip = &state->clip; |
||
4104 | Serge | 759 | int hscale, vscale; |
760 | int max_scale, min_scale; |
||
6084 | serge | 761 | bool can_scale; |
762 | int pixel_size; |
||
2342 | Serge | 763 | |
6084 | serge | 764 | if (!fb) { |
765 | state->visible = false; |
||
766 | return 0; |
||
767 | } |
||
768 | |||
4104 | Serge | 769 | /* Don't modify another pipe's plane */ |
770 | if (intel_plane->pipe != intel_crtc->pipe) { |
||
771 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
||
2342 | Serge | 772 | return -EINVAL; |
4104 | Serge | 773 | } |
2342 | Serge | 774 | |
4104 | Serge | 775 | /* FIXME check all gen limits */ |
776 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
||
777 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
||
2342 | Serge | 778 | return -EINVAL; |
4104 | Serge | 779 | } |
2342 | Serge | 780 | |
6084 | serge | 781 | /* setup can_scale, min_scale, max_scale */ |
782 | if (INTEL_INFO(dev)->gen >= 9) { |
||
783 | /* use scaler when colorkey is not required */ |
||
784 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
||
785 | can_scale = 1; |
||
786 | min_scale = 1; |
||
787 | max_scale = skl_max_scale(intel_crtc, crtc_state); |
||
788 | } else { |
||
789 | can_scale = 0; |
||
790 | min_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
791 | max_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
792 | } |
||
793 | } else { |
||
794 | can_scale = intel_plane->can_scale; |
||
795 | max_scale = intel_plane->max_downscale << 16; |
||
796 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
||
3243 | Serge | 797 | } |
798 | |||
2342 | Serge | 799 | /* |
4104 | Serge | 800 | * FIXME the following code does a bunch of fuzzy adjustments to the |
801 | * coordinates and sizes. We probably need some way to decide whether |
||
802 | * more strict checking should be done instead. |
||
2342 | Serge | 803 | */ |
5354 | serge | 804 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
6084 | serge | 805 | state->base.rotation); |
5354 | serge | 806 | |
807 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
||
4104 | Serge | 808 | BUG_ON(hscale < 0); |
809 | |||
5354 | serge | 810 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
4104 | Serge | 811 | BUG_ON(vscale < 0); |
812 | |||
6084 | serge | 813 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
4104 | Serge | 814 | |
5354 | serge | 815 | crtc_x = dst->x1; |
816 | crtc_y = dst->y1; |
||
817 | crtc_w = drm_rect_width(dst); |
||
818 | crtc_h = drm_rect_height(dst); |
||
4104 | Serge | 819 | |
5354 | serge | 820 | if (state->visible) { |
4104 | Serge | 821 | /* check again in case clipping clamped the results */ |
5354 | serge | 822 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
4104 | Serge | 823 | if (hscale < 0) { |
824 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
||
6937 | serge | 825 | drm_rect_debug_print("src: ", src, true); |
826 | drm_rect_debug_print("dst: ", dst, false); |
||
4104 | Serge | 827 | |
828 | return hscale; |
||
6084 | serge | 829 | } |
2342 | Serge | 830 | |
5354 | serge | 831 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
4104 | Serge | 832 | if (vscale < 0) { |
833 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
||
6937 | serge | 834 | drm_rect_debug_print("src: ", src, true); |
835 | drm_rect_debug_print("dst: ", dst, false); |
||
4104 | Serge | 836 | |
837 | return vscale; |
||
6084 | serge | 838 | } |
2342 | Serge | 839 | |
4104 | Serge | 840 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
5354 | serge | 841 | drm_rect_adjust_size(src, |
842 | drm_rect_width(dst) * hscale - drm_rect_width(src), |
||
843 | drm_rect_height(dst) * vscale - drm_rect_height(src)); |
||
2342 | Serge | 844 | |
5354 | serge | 845 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
6084 | serge | 846 | state->base.rotation); |
5354 | serge | 847 | |
4104 | Serge | 848 | /* sanity check to make sure the src viewport wasn't enlarged */ |
6084 | serge | 849 | WARN_ON(src->x1 < (int) state->base.src_x || |
850 | src->y1 < (int) state->base.src_y || |
||
851 | src->x2 > (int) state->base.src_x + state->base.src_w || |
||
852 | src->y2 > (int) state->base.src_y + state->base.src_h); |
||
4104 | Serge | 853 | |
6084 | serge | 854 | /* |
4104 | Serge | 855 | * Hardware doesn't handle subpixel coordinates. |
856 | * Adjust to (macro)pixel boundary, but be careful not to |
||
857 | * increase the source viewport size, because that could |
||
858 | * push the downscaling factor out of bounds. |
||
6084 | serge | 859 | */ |
5354 | serge | 860 | src_x = src->x1 >> 16; |
861 | src_w = drm_rect_width(src) >> 16; |
||
862 | src_y = src->y1 >> 16; |
||
863 | src_h = drm_rect_height(src) >> 16; |
||
3243 | Serge | 864 | |
4104 | Serge | 865 | if (format_is_yuv(fb->pixel_format)) { |
866 | src_x &= ~1; |
||
867 | src_w &= ~1; |
||
868 | |||
6084 | serge | 869 | /* |
4104 | Serge | 870 | * Must keep src and dst the |
871 | * same if we can't scale. |
||
6084 | serge | 872 | */ |
873 | if (!can_scale) |
||
4104 | Serge | 874 | crtc_w &= ~1; |
875 | |||
876 | if (crtc_w == 0) |
||
5354 | serge | 877 | state->visible = false; |
4104 | Serge | 878 | } |
879 | } |
||
880 | |||
881 | /* Check size restrictions when scaling */ |
||
5354 | serge | 882 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
4104 | Serge | 883 | unsigned int width_bytes; |
884 | |||
6084 | serge | 885 | WARN_ON(!can_scale); |
4104 | Serge | 886 | |
887 | /* FIXME interlacing min height is 6 */ |
||
888 | |||
889 | if (crtc_w < 3 || crtc_h < 3) |
||
5354 | serge | 890 | state->visible = false; |
4104 | Serge | 891 | |
892 | if (src_w < 3 || src_h < 3) |
||
5354 | serge | 893 | state->visible = false; |
4104 | Serge | 894 | |
6084 | serge | 895 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
5354 | serge | 896 | width_bytes = ((src_x * pixel_size) & 63) + |
897 | src_w * pixel_size; |
||
4104 | Serge | 898 | |
6084 | serge | 899 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
900 | width_bytes > 4096 || fb->pitches[0] > 4096)) { |
||
4104 | Serge | 901 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
6084 | serge | 902 | return -EINVAL; |
4104 | Serge | 903 | } |
904 | } |
||
2342 | Serge | 905 | |
5354 | serge | 906 | if (state->visible) { |
6084 | serge | 907 | src->x1 = src_x << 16; |
908 | src->x2 = (src_x + src_w) << 16; |
||
909 | src->y1 = src_y << 16; |
||
910 | src->y2 = (src_y + src_h) << 16; |
||
5354 | serge | 911 | } |
4104 | Serge | 912 | |
5354 | serge | 913 | dst->x1 = crtc_x; |
914 | dst->x2 = crtc_x + crtc_w; |
||
915 | dst->y1 = crtc_y; |
||
916 | dst->y2 = crtc_y + crtc_h; |
||
2342 | Serge | 917 | |
5354 | serge | 918 | return 0; |
919 | } |
||
920 | |||
921 | static void |
||
922 | intel_commit_sprite_plane(struct drm_plane *plane, |
||
923 | struct intel_plane_state *state) |
||
924 | { |
||
6084 | serge | 925 | struct drm_crtc *crtc = state->base.crtc; |
5354 | serge | 926 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 927 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 928 | |
6084 | serge | 929 | crtc = crtc ? crtc : plane->crtc; |
5354 | serge | 930 | |
6084 | serge | 931 | if (state->visible) { |
932 | intel_plane->update_plane(plane, crtc, fb, |
||
933 | state->dst.x1, state->dst.y1, |
||
934 | drm_rect_width(&state->dst), |
||
935 | drm_rect_height(&state->dst), |
||
936 | state->src.x1 >> 16, |
||
937 | state->src.y1 >> 16, |
||
938 | drm_rect_width(&state->src) >> 16, |
||
939 | drm_rect_height(&state->src) >> 16); |
||
940 | } else { |
||
4104 | Serge | 941 | intel_plane->disable_plane(plane, crtc); |
4560 | Serge | 942 | } |
5354 | serge | 943 | } |
2342 | Serge | 944 | |
945 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
946 | struct drm_file *file_priv) |
||
947 | { |
||
948 | struct drm_intel_sprite_colorkey *set = data; |
||
949 | struct drm_plane *plane; |
||
6084 | serge | 950 | struct drm_plane_state *plane_state; |
951 | struct drm_atomic_state *state; |
||
952 | struct drm_modeset_acquire_ctx ctx; |
||
2342 | Serge | 953 | int ret = 0; |
954 | |||
955 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
956 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
957 | return -EINVAL; |
||
958 | |||
6937 | serge | 959 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
6084 | serge | 960 | set->flags & I915_SET_COLORKEY_DESTINATION) |
961 | return -EINVAL; |
||
2342 | Serge | 962 | |
5060 | serge | 963 | plane = drm_plane_find(dev, set->plane_id); |
6084 | serge | 964 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
965 | return -ENOENT; |
||
2342 | Serge | 966 | |
6084 | serge | 967 | drm_modeset_acquire_init(&ctx, 0); |
2342 | Serge | 968 | |
6084 | serge | 969 | state = drm_atomic_state_alloc(plane->dev); |
970 | if (!state) { |
||
971 | ret = -ENOMEM; |
||
972 | goto out; |
||
973 | } |
||
974 | state->acquire_ctx = &ctx; |
||
2342 | Serge | 975 | |
6084 | serge | 976 | while (1) { |
977 | plane_state = drm_atomic_get_plane_state(state, plane); |
||
978 | ret = PTR_ERR_OR_ZERO(plane_state); |
||
979 | if (!ret) { |
||
980 | to_intel_plane_state(plane_state)->ckey = *set; |
||
981 | ret = drm_atomic_commit(state); |
||
982 | } |
||
2342 | Serge | 983 | |
6084 | serge | 984 | if (ret != -EDEADLK) |
985 | break; |
||
2342 | Serge | 986 | |
6084 | serge | 987 | drm_atomic_state_clear(state); |
988 | drm_modeset_backoff(&ctx); |
||
2342 | Serge | 989 | } |
990 | |||
6084 | serge | 991 | if (ret) |
992 | drm_atomic_state_free(state); |
||
2342 | Serge | 993 | |
6084 | serge | 994 | out: |
995 | drm_modeset_drop_locks(&ctx); |
||
996 | drm_modeset_acquire_fini(&ctx); |
||
2342 | Serge | 997 | return ret; |
998 | } |
||
999 | |||
6084 | serge | 1000 | static const uint32_t ilk_plane_formats[] = { |
3031 | serge | 1001 | DRM_FORMAT_XRGB8888, |
1002 | DRM_FORMAT_YUYV, |
||
1003 | DRM_FORMAT_YVYU, |
||
1004 | DRM_FORMAT_UYVY, |
||
1005 | DRM_FORMAT_VYUY, |
||
1006 | }; |
||
1007 | |||
6084 | serge | 1008 | static const uint32_t snb_plane_formats[] = { |
2342 | Serge | 1009 | DRM_FORMAT_XBGR8888, |
1010 | DRM_FORMAT_XRGB8888, |
||
1011 | DRM_FORMAT_YUYV, |
||
1012 | DRM_FORMAT_YVYU, |
||
1013 | DRM_FORMAT_UYVY, |
||
1014 | DRM_FORMAT_VYUY, |
||
1015 | }; |
||
1016 | |||
6084 | serge | 1017 | static const uint32_t vlv_plane_formats[] = { |
3746 | Serge | 1018 | DRM_FORMAT_RGB565, |
1019 | DRM_FORMAT_ABGR8888, |
||
1020 | DRM_FORMAT_ARGB8888, |
||
1021 | DRM_FORMAT_XBGR8888, |
||
1022 | DRM_FORMAT_XRGB8888, |
||
1023 | DRM_FORMAT_XBGR2101010, |
||
1024 | DRM_FORMAT_ABGR2101010, |
||
1025 | DRM_FORMAT_YUYV, |
||
1026 | DRM_FORMAT_YVYU, |
||
1027 | DRM_FORMAT_UYVY, |
||
1028 | DRM_FORMAT_VYUY, |
||
1029 | }; |
||
1030 | |||
5354 | serge | 1031 | static uint32_t skl_plane_formats[] = { |
1032 | DRM_FORMAT_RGB565, |
||
1033 | DRM_FORMAT_ABGR8888, |
||
1034 | DRM_FORMAT_ARGB8888, |
||
1035 | DRM_FORMAT_XBGR8888, |
||
1036 | DRM_FORMAT_XRGB8888, |
||
1037 | DRM_FORMAT_YUYV, |
||
1038 | DRM_FORMAT_YVYU, |
||
1039 | DRM_FORMAT_UYVY, |
||
1040 | DRM_FORMAT_VYUY, |
||
1041 | }; |
||
1042 | |||
2342 | Serge | 1043 | int |
3746 | Serge | 1044 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
2342 | Serge | 1045 | { |
1046 | struct intel_plane *intel_plane; |
||
6084 | serge | 1047 | struct intel_plane_state *state; |
2342 | Serge | 1048 | unsigned long possible_crtcs; |
3031 | serge | 1049 | const uint32_t *plane_formats; |
1050 | int num_plane_formats; |
||
2342 | Serge | 1051 | int ret; |
1052 | |||
3031 | serge | 1053 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 1054 | return -ENODEV; |
1055 | |||
4560 | Serge | 1056 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
2342 | Serge | 1057 | if (!intel_plane) |
1058 | return -ENOMEM; |
||
1059 | |||
6084 | serge | 1060 | state = intel_create_plane_state(&intel_plane->base); |
1061 | if (!state) { |
||
1062 | kfree(intel_plane); |
||
1063 | return -ENOMEM; |
||
1064 | } |
||
1065 | intel_plane->base.state = &state->base; |
||
1066 | |||
3031 | serge | 1067 | switch (INTEL_INFO(dev)->gen) { |
1068 | case 5: |
||
1069 | case 6: |
||
3243 | Serge | 1070 | intel_plane->can_scale = true; |
3031 | serge | 1071 | intel_plane->max_downscale = 16; |
1072 | intel_plane->update_plane = ilk_update_plane; |
||
1073 | intel_plane->disable_plane = ilk_disable_plane; |
||
1074 | |||
6084 | serge | 1075 | if (IS_GEN6(dev)) { |
3031 | serge | 1076 | plane_formats = snb_plane_formats; |
1077 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
1078 | } else { |
||
1079 | plane_formats = ilk_plane_formats; |
||
1080 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
1081 | } |
||
1082 | break; |
||
1083 | |||
1084 | case 7: |
||
4560 | Serge | 1085 | case 8: |
4104 | Serge | 1086 | if (IS_IVYBRIDGE(dev)) { |
1087 | intel_plane->can_scale = true; |
||
1088 | intel_plane->max_downscale = 2; |
||
1089 | } else { |
||
3243 | Serge | 1090 | intel_plane->can_scale = false; |
4104 | Serge | 1091 | intel_plane->max_downscale = 1; |
1092 | } |
||
3746 | Serge | 1093 | |
6937 | serge | 1094 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3746 | Serge | 1095 | intel_plane->update_plane = vlv_update_plane; |
1096 | intel_plane->disable_plane = vlv_disable_plane; |
||
1097 | |||
1098 | plane_formats = vlv_plane_formats; |
||
1099 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
||
1100 | } else { |
||
6084 | serge | 1101 | intel_plane->update_plane = ivb_update_plane; |
1102 | intel_plane->disable_plane = ivb_disable_plane; |
||
3031 | serge | 1103 | |
6084 | serge | 1104 | plane_formats = snb_plane_formats; |
1105 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
3746 | Serge | 1106 | } |
3031 | serge | 1107 | break; |
5354 | serge | 1108 | case 9: |
6084 | serge | 1109 | intel_plane->can_scale = true; |
5354 | serge | 1110 | intel_plane->update_plane = skl_update_plane; |
1111 | intel_plane->disable_plane = skl_disable_plane; |
||
6084 | serge | 1112 | state->scaler_id = -1; |
3031 | serge | 1113 | |
5354 | serge | 1114 | plane_formats = skl_plane_formats; |
1115 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); |
||
1116 | break; |
||
3031 | serge | 1117 | default: |
1118 | kfree(intel_plane); |
||
1119 | return -ENODEV; |
||
2342 | Serge | 1120 | } |
1121 | |||
1122 | intel_plane->pipe = pipe; |
||
3746 | Serge | 1123 | intel_plane->plane = plane; |
6084 | serge | 1124 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
1125 | intel_plane->check_plane = intel_check_sprite_plane; |
||
1126 | intel_plane->commit_plane = intel_commit_sprite_plane; |
||
2342 | Serge | 1127 | possible_crtcs = (1 << pipe); |
5354 | serge | 1128 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
6084 | serge | 1129 | &intel_plane_funcs, |
1130 | plane_formats, num_plane_formats, |
||
6937 | serge | 1131 | DRM_PLANE_TYPE_OVERLAY, NULL); |
5354 | serge | 1132 | if (ret) { |
2342 | Serge | 1133 | kfree(intel_plane); |
5354 | serge | 1134 | goto out; |
1135 | } |
||
2342 | Serge | 1136 | |
6084 | serge | 1137 | intel_create_rotation_property(dev, intel_plane); |
5354 | serge | 1138 | |
6084 | serge | 1139 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
5354 | serge | 1140 | |
6084 | serge | 1141 | out: |
2342 | Serge | 1142 | return ret; |
1143 | }><>>><>><>><>><>>>>>>>>><>><>>>>>><>><>><>><>>>->><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>>=>=> |