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Rev | Author | Line No. | Line |
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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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4104 | Serge | 35 | #include |
6084 | serge | 36 | #include |
37 | #include |
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2342 | Serge | 38 | #include "intel_drv.h" |
3031 | serge | 39 | #include |
2342 | Serge | 40 | #include "i915_drv.h" |
41 | |||
5354 | serge | 42 | static bool |
43 | format_is_yuv(uint32_t format) |
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44 | { |
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45 | switch (format) { |
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46 | case DRM_FORMAT_YUYV: |
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47 | case DRM_FORMAT_UYVY: |
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48 | case DRM_FORMAT_VYUY: |
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49 | case DRM_FORMAT_YVYU: |
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50 | return true; |
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51 | default: |
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52 | return false; |
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53 | } |
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54 | } |
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55 | |||
6084 | serge | 56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) |
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5060 | serge | 58 | { |
59 | /* paranoia */ |
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6084 | serge | 60 | if (!adjusted_mode->crtc_htotal) |
5060 | serge | 61 | return 1; |
62 | |||
6084 | serge | 63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); |
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5060 | serge | 65 | } |
66 | |||
5354 | serge | 67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers |
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69 | * @crtc: the crtc of which the registers are going to be updated |
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70 | * @start_vbl_count: vblank counter return pointer used for error checking |
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71 | * |
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72 | * Mark the start of an update to pipe registers that should be updated |
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73 | * atomically regarding vblank. If the next vblank will happens within |
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74 | * the next 100 us, this function waits until the vblank passes. |
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75 | * |
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76 | * After a successful call to this function, interrupts will be disabled |
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77 | * until a subsequent call to intel_pipe_update_end(). That is done to |
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78 | * avoid random delays. The value written to @start_vbl_count should be |
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79 | * supplied to intel_pipe_update_end() for error checking. |
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80 | */ |
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6084 | serge | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
5060 | serge | 82 | { |
83 | struct drm_device *dev = crtc->base.dev; |
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6084 | serge | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 85 | enum pipe pipe = crtc->pipe; |
86 | long timeout = msecs_to_jiffies_timeout(1); |
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87 | int scanline, min, max, vblank_start; |
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6103 | serge | 88 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
89 | DEFINE_WAIT(wait); |
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5060 | serge | 90 | |
6084 | serge | 91 | vblank_start = adjusted_mode->crtc_vblank_start; |
92 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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5060 | serge | 93 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
94 | |||
95 | /* FIXME needs to be calibrated sensibly */ |
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6084 | serge | 96 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
5060 | serge | 97 | max = vblank_start - 1; |
98 | |||
6103 | serge | 99 | local_irq_disable(); |
100 | |||
5060 | serge | 101 | if (min <= 0 || max <= 0) |
6084 | serge | 102 | return; |
5060 | serge | 103 | |
6103 | serge | 104 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
105 | return; |
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5060 | serge | 106 | |
6084 | serge | 107 | crtc->debug.min_vbl = min; |
108 | crtc->debug.max_vbl = max; |
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109 | trace_i915_pipe_update_start(crtc); |
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5060 | serge | 110 | |
111 | for (;;) { |
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112 | /* |
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113 | * prepare_to_wait() has a memory barrier, which guarantees |
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114 | * other CPUs can see the task state update by the time we |
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115 | * read the scanline. |
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116 | */ |
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5354 | serge | 117 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
5060 | serge | 118 | |
119 | scanline = intel_get_crtc_scanline(crtc); |
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120 | if (scanline < min || scanline > max) |
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121 | break; |
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122 | |||
123 | if (timeout <= 0) { |
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124 | DRM_ERROR("Potential atomic update failure on pipe %c\n", |
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125 | pipe_name(crtc->pipe)); |
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126 | break; |
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127 | } |
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128 | |||
6103 | serge | 129 | local_irq_enable(); |
130 | |||
131 | { |
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132 | unsigned long expire; |
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133 | expire = timeout + jiffies; |
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134 | WaitEventTimeout(wait.evnt, timeout);; |
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135 | timeout = expire - jiffies; |
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136 | timeout = timeout < 0 ? 0 : timeout; |
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137 | } |
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138 | local_irq_disable(); |
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5060 | serge | 139 | } |
140 | |||
5354 | serge | 141 | finish_wait(wq, &wait); |
5060 | serge | 142 | |
6103 | serge | 143 | drm_crtc_vblank_put(&crtc->base); |
144 | |||
6084 | serge | 145 | crtc->debug.scanline_start = scanline; |
146 | crtc->debug.start_vbl_time = ktime_get(); |
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147 | crtc->debug.start_vbl_count = |
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148 | dev->driver->get_vblank_counter(dev, pipe); |
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5060 | serge | 149 | |
6084 | serge | 150 | trace_i915_pipe_update_vblank_evaded(crtc); |
5060 | serge | 151 | } |
152 | |||
5354 | serge | 153 | /** |
154 | * intel_pipe_update_end() - end update of a set of display registers |
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155 | * @crtc: the crtc of which the registers were updated |
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156 | * @start_vbl_count: start vblank counter (used for error checking) |
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157 | * |
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158 | * Mark the end of an update started with intel_pipe_update_start(). This |
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159 | * re-enables interrupts and verifies the update was actually completed |
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160 | * before a vblank using the value of @start_vbl_count. |
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161 | */ |
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6084 | serge | 162 | void intel_pipe_update_end(struct intel_crtc *crtc) |
5060 | serge | 163 | { |
164 | struct drm_device *dev = crtc->base.dev; |
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165 | enum pipe pipe = crtc->pipe; |
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6084 | serge | 166 | int scanline_end = intel_get_crtc_scanline(crtc); |
5060 | serge | 167 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
6084 | serge | 168 | ktime_t end_vbl_time = ktime_get(); |
5060 | serge | 169 | |
6084 | serge | 170 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
5060 | serge | 171 | |
6103 | serge | 172 | local_irq_enable(); |
5060 | serge | 173 | |
6084 | serge | 174 | if (crtc->debug.start_vbl_count && |
175 | crtc->debug.start_vbl_count != end_vbl_count) { |
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176 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", |
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177 | pipe_name(pipe), crtc->debug.start_vbl_count, |
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178 | end_vbl_count, |
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179 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), |
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180 | crtc->debug.min_vbl, crtc->debug.max_vbl, |
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181 | crtc->debug.scanline_start, scanline_end); |
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182 | } |
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5060 | serge | 183 | } |
184 | |||
2342 | Serge | 185 | static void |
5354 | serge | 186 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, |
187 | struct drm_framebuffer *fb, |
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6084 | serge | 188 | int crtc_x, int crtc_y, |
5354 | serge | 189 | unsigned int crtc_w, unsigned int crtc_h, |
190 | uint32_t x, uint32_t y, |
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191 | uint32_t src_w, uint32_t src_h) |
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192 | { |
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193 | struct drm_device *dev = drm_plane->dev; |
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194 | struct drm_i915_private *dev_priv = dev->dev_private; |
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195 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
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6084 | serge | 196 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
5354 | serge | 197 | const int pipe = intel_plane->pipe; |
198 | const int plane = intel_plane->plane + 1; |
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6084 | serge | 199 | u32 plane_ctl, stride_div, stride; |
5354 | serge | 200 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 201 | const struct drm_intel_sprite_colorkey *key = |
202 | &to_intel_plane_state(drm_plane->state)->ckey; |
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6660 | serge | 203 | u32 surf_addr; |
6084 | serge | 204 | u32 tile_height, plane_offset, plane_size; |
205 | unsigned int rotation; |
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206 | int x_offset, y_offset; |
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207 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
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208 | int scaler_id; |
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5354 | serge | 209 | |
6084 | serge | 210 | plane_ctl = PLANE_CTL_ENABLE | |
211 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
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212 | PLANE_CTL_PIPE_CSC_ENABLE; |
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5354 | serge | 213 | |
6084 | serge | 214 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
215 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
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5354 | serge | 216 | |
6084 | serge | 217 | rotation = drm_plane->state->rotation; |
218 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
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5354 | serge | 219 | |
220 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, |
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221 | pixel_size, true, |
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222 | src_w != crtc_w || src_h != crtc_h); |
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223 | |||
6084 | serge | 224 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
225 | fb->pixel_format); |
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226 | |||
227 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
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228 | |||
5354 | serge | 229 | /* Sizes are 0 based */ |
230 | src_w--; |
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231 | src_h--; |
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232 | crtc_w--; |
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233 | crtc_h--; |
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234 | |||
6084 | serge | 235 | if (key->flags) { |
236 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); |
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237 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); |
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238 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); |
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239 | } |
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5354 | serge | 240 | |
6084 | serge | 241 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
242 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; |
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243 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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244 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; |
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5354 | serge | 245 | |
6084 | serge | 246 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
5354 | serge | 247 | |
6084 | serge | 248 | if (intel_rotation_90_or_270(rotation)) { |
249 | /* stride: Surface height in tiles */ |
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250 | tile_height = intel_tile_height(dev, fb->pixel_format, |
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251 | fb->modifier[0], 0); |
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252 | stride = DIV_ROUND_UP(fb->height, tile_height); |
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253 | plane_size = (src_w << 16) | src_h; |
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254 | x_offset = stride * tile_height - y - (src_h + 1); |
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255 | y_offset = x; |
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256 | } else { |
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257 | stride = fb->pitches[0] / stride_div; |
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258 | plane_size = (src_h << 16) | src_w; |
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259 | x_offset = x; |
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260 | y_offset = y; |
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261 | } |
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262 | plane_offset = y_offset << 16 | x_offset; |
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5354 | serge | 263 | |
6084 | serge | 264 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); |
265 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); |
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266 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
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5354 | serge | 267 | |
6084 | serge | 268 | /* program plane scaler */ |
269 | if (scaler_id >= 0) { |
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270 | uint32_t ps_ctrl = 0; |
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5354 | serge | 271 | |
6084 | serge | 272 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, |
273 | PS_PLANE_SEL(plane)); |
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274 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | |
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275 | crtc_state->scaler_state.scalers[scaler_id].mode; |
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276 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
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277 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
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278 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); |
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279 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), |
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280 | ((crtc_w + 1) << 16)|(crtc_h + 1)); |
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5354 | serge | 281 | |
6084 | serge | 282 | I915_WRITE(PLANE_POS(pipe, plane), 0); |
283 | } else { |
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284 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
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285 | } |
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286 | |||
5354 | serge | 287 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
6084 | serge | 288 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
289 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 290 | } |
291 | |||
292 | static void |
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6084 | serge | 293 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
5354 | serge | 294 | { |
6084 | serge | 295 | struct drm_device *dev = dplane->dev; |
5354 | serge | 296 | struct drm_i915_private *dev_priv = dev->dev_private; |
6084 | serge | 297 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
5354 | serge | 298 | const int pipe = intel_plane->pipe; |
6084 | serge | 299 | const int plane = intel_plane->plane + 1; |
5354 | serge | 300 | |
6084 | serge | 301 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
5354 | serge | 302 | |
6084 | serge | 303 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
304 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 305 | |
6084 | serge | 306 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
5354 | serge | 307 | } |
308 | |||
309 | static void |
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310 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) |
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311 | { |
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312 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; |
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313 | int plane = intel_plane->plane; |
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314 | |||
315 | /* Seems RGB data bypasses the CSC always */ |
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316 | if (!format_is_yuv(format)) |
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317 | return; |
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318 | |||
319 | /* |
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320 | * BT.601 limited range YCbCr -> full range RGB |
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321 | * |
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322 | * |r| | 6537 4769 0| |cr | |
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323 | * |g| = |-3330 4769 -1605| x |y-64| |
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324 | * |b| | 0 4769 8263| |cb | |
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325 | * |
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326 | * Cb and Cr apparently come in as signed already, so no |
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327 | * need for any offset. For Y we need to remove the offset. |
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328 | */ |
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329 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); |
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330 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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331 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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332 | |||
333 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); |
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334 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); |
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335 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); |
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336 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); |
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337 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); |
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338 | |||
339 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); |
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340 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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341 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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342 | |||
343 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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344 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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345 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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346 | } |
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347 | |||
348 | static void |
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4104 | Serge | 349 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
350 | struct drm_framebuffer *fb, |
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6084 | serge | 351 | int crtc_x, int crtc_y, |
3746 | Serge | 352 | unsigned int crtc_w, unsigned int crtc_h, |
353 | uint32_t x, uint32_t y, |
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354 | uint32_t src_w, uint32_t src_h) |
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355 | { |
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356 | struct drm_device *dev = dplane->dev; |
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357 | struct drm_i915_private *dev_priv = dev->dev_private; |
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358 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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6084 | serge | 359 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3746 | Serge | 360 | int pipe = intel_plane->pipe; |
361 | int plane = intel_plane->plane; |
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362 | u32 sprctl; |
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363 | unsigned long sprsurf_offset, linear_offset; |
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364 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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6084 | serge | 365 | const struct drm_intel_sprite_colorkey *key = |
366 | &to_intel_plane_state(dplane->state)->ckey; |
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3746 | Serge | 367 | |
6084 | serge | 368 | sprctl = SP_ENABLE; |
3746 | Serge | 369 | |
370 | switch (fb->pixel_format) { |
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371 | case DRM_FORMAT_YUYV: |
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372 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
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373 | break; |
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374 | case DRM_FORMAT_YVYU: |
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375 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
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376 | break; |
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377 | case DRM_FORMAT_UYVY: |
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378 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
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379 | break; |
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380 | case DRM_FORMAT_VYUY: |
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381 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
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382 | break; |
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383 | case DRM_FORMAT_RGB565: |
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384 | sprctl |= SP_FORMAT_BGR565; |
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385 | break; |
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386 | case DRM_FORMAT_XRGB8888: |
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387 | sprctl |= SP_FORMAT_BGRX8888; |
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388 | break; |
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389 | case DRM_FORMAT_ARGB8888: |
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390 | sprctl |= SP_FORMAT_BGRA8888; |
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391 | break; |
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392 | case DRM_FORMAT_XBGR2101010: |
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393 | sprctl |= SP_FORMAT_RGBX1010102; |
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394 | break; |
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395 | case DRM_FORMAT_ABGR2101010: |
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396 | sprctl |= SP_FORMAT_RGBA1010102; |
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397 | break; |
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398 | case DRM_FORMAT_XBGR8888: |
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399 | sprctl |= SP_FORMAT_RGBX8888; |
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400 | break; |
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401 | case DRM_FORMAT_ABGR8888: |
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402 | sprctl |= SP_FORMAT_RGBA8888; |
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403 | break; |
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404 | default: |
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405 | /* |
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406 | * If we get here one of the upper layers failed to filter |
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407 | * out the unsupported plane formats |
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408 | */ |
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409 | BUG(); |
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410 | break; |
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411 | } |
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412 | |||
4560 | Serge | 413 | /* |
414 | * Enable gamma to match primary/cursor plane behaviour. |
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415 | * FIXME should be user controllable via propertiesa. |
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416 | */ |
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417 | sprctl |= SP_GAMMA_ENABLE; |
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418 | |||
3746 | Serge | 419 | if (obj->tiling_mode != I915_TILING_NONE) |
420 | sprctl |= SP_TILED; |
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421 | |||
422 | /* Sizes are 0 based */ |
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423 | src_w--; |
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424 | src_h--; |
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425 | crtc_w--; |
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426 | crtc_h--; |
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427 | |||
428 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
||
6084 | serge | 429 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, |
430 | &x, &y, |
||
3746 | Serge | 431 | obj->tiling_mode, |
432 | pixel_size, |
||
433 | fb->pitches[0]); |
||
434 | linear_offset -= sprsurf_offset; |
||
435 | |||
6084 | serge | 436 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 437 | sprctl |= SP_ROTATE_180; |
438 | |||
439 | x += src_w; |
||
440 | y += src_h; |
||
441 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
442 | } |
||
443 | |||
6084 | serge | 444 | if (key->flags) { |
445 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
||
446 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
||
447 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
||
448 | } |
||
5060 | serge | 449 | |
6084 | serge | 450 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
451 | sprctl |= SP_SOURCE_KEY; |
||
5060 | serge | 452 | |
5354 | serge | 453 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
454 | chv_update_csc(intel_plane, fb->pixel_format); |
||
455 | |||
5060 | serge | 456 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
457 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
||
458 | |||
3746 | Serge | 459 | if (obj->tiling_mode != I915_TILING_NONE) |
460 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
||
461 | else |
||
462 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
||
463 | |||
5354 | serge | 464 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
465 | |||
3746 | Serge | 466 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
467 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
||
4560 | Serge | 468 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
6084 | serge | 469 | sprsurf_offset); |
470 | POSTING_READ(SPSURF(pipe, plane)); |
||
3746 | Serge | 471 | } |
472 | |||
473 | static void |
||
4104 | Serge | 474 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
3746 | Serge | 475 | { |
476 | struct drm_device *dev = dplane->dev; |
||
477 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
478 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
||
479 | int pipe = intel_plane->pipe; |
||
480 | int plane = intel_plane->plane; |
||
481 | |||
6084 | serge | 482 | I915_WRITE(SPCNTR(pipe, plane), 0); |
5060 | serge | 483 | |
4560 | Serge | 484 | I915_WRITE(SPSURF(pipe, plane), 0); |
6084 | serge | 485 | POSTING_READ(SPSURF(pipe, plane)); |
3746 | Serge | 486 | } |
487 | |||
488 | static void |
||
4104 | Serge | 489 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
490 | struct drm_framebuffer *fb, |
||
6084 | serge | 491 | int crtc_x, int crtc_y, |
2342 | Serge | 492 | unsigned int crtc_w, unsigned int crtc_h, |
493 | uint32_t x, uint32_t y, |
||
494 | uint32_t src_w, uint32_t src_h) |
||
495 | { |
||
496 | struct drm_device *dev = plane->dev; |
||
497 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
498 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 499 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
500 | enum pipe pipe = intel_plane->pipe; |
||
2342 | Serge | 501 | u32 sprctl, sprscale = 0; |
3243 | Serge | 502 | unsigned long sprsurf_offset, linear_offset; |
503 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
||
6084 | serge | 504 | const struct drm_intel_sprite_colorkey *key = |
505 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 506 | |
6084 | serge | 507 | sprctl = SPRITE_ENABLE; |
2342 | Serge | 508 | |
509 | switch (fb->pixel_format) { |
||
510 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 511 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 512 | break; |
513 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 514 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 515 | break; |
516 | case DRM_FORMAT_YUYV: |
||
517 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
||
518 | break; |
||
519 | case DRM_FORMAT_YVYU: |
||
520 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
||
521 | break; |
||
522 | case DRM_FORMAT_UYVY: |
||
523 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
||
524 | break; |
||
525 | case DRM_FORMAT_VYUY: |
||
526 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
||
527 | break; |
||
528 | default: |
||
3243 | Serge | 529 | BUG(); |
2342 | Serge | 530 | } |
531 | |||
4560 | Serge | 532 | /* |
533 | * Enable gamma to match primary/cursor plane behaviour. |
||
534 | * FIXME should be user controllable via propertiesa. |
||
535 | */ |
||
536 | sprctl |= SPRITE_GAMMA_ENABLE; |
||
537 | |||
2342 | Serge | 538 | if (obj->tiling_mode != I915_TILING_NONE) |
539 | sprctl |= SPRITE_TILED; |
||
540 | |||
4560 | Serge | 541 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4104 | Serge | 542 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
543 | else |
||
6084 | serge | 544 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
4104 | Serge | 545 | |
4560 | Serge | 546 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3480 | Serge | 547 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
548 | |||
5060 | serge | 549 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
550 | true, |
||
4104 | Serge | 551 | src_w != crtc_w || src_h != crtc_h); |
552 | |||
2342 | Serge | 553 | /* Sizes are 0 based */ |
554 | src_w--; |
||
555 | src_h--; |
||
556 | crtc_w--; |
||
557 | crtc_h--; |
||
558 | |||
4560 | Serge | 559 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 560 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
561 | |||
3243 | Serge | 562 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
563 | sprsurf_offset = |
||
6084 | serge | 564 | intel_gen4_compute_page_offset(dev_priv, |
565 | &x, &y, obj->tiling_mode, |
||
566 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 567 | linear_offset -= sprsurf_offset; |
568 | |||
6084 | serge | 569 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 570 | sprctl |= SPRITE_ROTATE_180; |
571 | |||
572 | /* HSW and BDW does this automagically in hardware */ |
||
573 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
||
574 | x += src_w; |
||
575 | y += src_h; |
||
576 | linear_offset += src_h * fb->pitches[0] + |
||
577 | src_w * pixel_size; |
||
578 | } |
||
579 | } |
||
580 | |||
6084 | serge | 581 | if (key->flags) { |
582 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); |
||
583 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); |
||
584 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); |
||
585 | } |
||
5060 | serge | 586 | |
6084 | serge | 587 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
588 | sprctl |= SPRITE_DEST_KEY; |
||
589 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
590 | sprctl |= SPRITE_SOURCE_KEY; |
||
5060 | serge | 591 | |
592 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
||
593 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
||
594 | |||
3243 | Serge | 595 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
596 | * register */ |
||
4560 | Serge | 597 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3243 | Serge | 598 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
599 | else if (obj->tiling_mode != I915_TILING_NONE) |
||
2342 | Serge | 600 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 601 | else |
602 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
||
2342 | Serge | 603 | |
604 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
3243 | Serge | 605 | if (intel_plane->can_scale) |
6084 | serge | 606 | I915_WRITE(SPRSCALE(pipe), sprscale); |
2342 | Serge | 607 | I915_WRITE(SPRCTL(pipe), sprctl); |
4560 | Serge | 608 | I915_WRITE(SPRSURF(pipe), |
6084 | serge | 609 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
610 | POSTING_READ(SPRSURF(pipe)); |
||
2342 | Serge | 611 | } |
612 | |||
613 | static void |
||
4104 | Serge | 614 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 615 | { |
616 | struct drm_device *dev = plane->dev; |
||
617 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
618 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
619 | int pipe = intel_plane->pipe; |
||
620 | |||
6084 | serge | 621 | I915_WRITE(SPRCTL(pipe), 0); |
2342 | Serge | 622 | /* Can't leave the scaler enabled... */ |
3243 | Serge | 623 | if (intel_plane->can_scale) |
6084 | serge | 624 | I915_WRITE(SPRSCALE(pipe), 0); |
625 | |||
4560 | Serge | 626 | I915_WRITE(SPRSURF(pipe), 0); |
6084 | serge | 627 | POSTING_READ(SPRSURF(pipe)); |
2342 | Serge | 628 | } |
629 | |||
630 | static void |
||
4104 | Serge | 631 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
632 | struct drm_framebuffer *fb, |
||
6084 | serge | 633 | int crtc_x, int crtc_y, |
2342 | Serge | 634 | unsigned int crtc_w, unsigned int crtc_h, |
635 | uint32_t x, uint32_t y, |
||
636 | uint32_t src_w, uint32_t src_h) |
||
637 | { |
||
638 | struct drm_device *dev = plane->dev; |
||
639 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
640 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 641 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3243 | Serge | 642 | int pipe = intel_plane->pipe; |
643 | unsigned long dvssurf_offset, linear_offset; |
||
3031 | serge | 644 | u32 dvscntr, dvsscale; |
3243 | Serge | 645 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 646 | const struct drm_intel_sprite_colorkey *key = |
647 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 648 | |
6084 | serge | 649 | dvscntr = DVS_ENABLE; |
2342 | Serge | 650 | |
651 | switch (fb->pixel_format) { |
||
652 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 653 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 654 | break; |
655 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 656 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 657 | break; |
658 | case DRM_FORMAT_YUYV: |
||
659 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
||
660 | break; |
||
661 | case DRM_FORMAT_YVYU: |
||
662 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
||
663 | break; |
||
664 | case DRM_FORMAT_UYVY: |
||
665 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
||
666 | break; |
||
667 | case DRM_FORMAT_VYUY: |
||
668 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
||
669 | break; |
||
670 | default: |
||
3243 | Serge | 671 | BUG(); |
2342 | Serge | 672 | } |
673 | |||
4560 | Serge | 674 | /* |
675 | * Enable gamma to match primary/cursor plane behaviour. |
||
676 | * FIXME should be user controllable via propertiesa. |
||
677 | */ |
||
678 | dvscntr |= DVS_GAMMA_ENABLE; |
||
679 | |||
2342 | Serge | 680 | if (obj->tiling_mode != I915_TILING_NONE) |
681 | dvscntr |= DVS_TILED; |
||
682 | |||
3031 | serge | 683 | if (IS_GEN6(dev)) |
684 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
||
2342 | Serge | 685 | |
5060 | serge | 686 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
687 | pixel_size, true, |
||
4104 | Serge | 688 | src_w != crtc_w || src_h != crtc_h); |
689 | |||
2342 | Serge | 690 | /* Sizes are 0 based */ |
691 | src_w--; |
||
692 | src_h--; |
||
693 | crtc_w--; |
||
694 | crtc_h--; |
||
695 | |||
3031 | serge | 696 | dvsscale = 0; |
4560 | Serge | 697 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 698 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
699 | |||
3243 | Serge | 700 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
701 | dvssurf_offset = |
||
6084 | serge | 702 | intel_gen4_compute_page_offset(dev_priv, |
703 | &x, &y, obj->tiling_mode, |
||
704 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 705 | linear_offset -= dvssurf_offset; |
706 | |||
6084 | serge | 707 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 708 | dvscntr |= DVS_ROTATE_180; |
709 | |||
710 | x += src_w; |
||
711 | y += src_h; |
||
712 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
713 | } |
||
714 | |||
6084 | serge | 715 | if (key->flags) { |
716 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); |
||
717 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); |
||
718 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); |
||
719 | } |
||
5060 | serge | 720 | |
6084 | serge | 721 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
722 | dvscntr |= DVS_DEST_KEY; |
||
723 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
724 | dvscntr |= DVS_SOURCE_KEY; |
||
5060 | serge | 725 | |
726 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
||
727 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
||
728 | |||
3243 | Serge | 729 | if (obj->tiling_mode != I915_TILING_NONE) |
2342 | Serge | 730 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 731 | else |
732 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
||
2342 | Serge | 733 | |
734 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
735 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
||
736 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
||
4560 | Serge | 737 | I915_WRITE(DVSSURF(pipe), |
6084 | serge | 738 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
739 | POSTING_READ(DVSSURF(pipe)); |
||
2342 | Serge | 740 | } |
741 | |||
742 | static void |
||
4104 | Serge | 743 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 744 | { |
745 | struct drm_device *dev = plane->dev; |
||
746 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
747 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
748 | int pipe = intel_plane->pipe; |
||
749 | |||
6084 | serge | 750 | I915_WRITE(DVSCNTR(pipe), 0); |
2342 | Serge | 751 | /* Disable the scaler */ |
752 | I915_WRITE(DVSSCALE(pipe), 0); |
||
6084 | serge | 753 | |
4560 | Serge | 754 | I915_WRITE(DVSSURF(pipe), 0); |
6084 | serge | 755 | POSTING_READ(DVSSURF(pipe)); |
2342 | Serge | 756 | } |
757 | |||
758 | static int |
||
5354 | serge | 759 | intel_check_sprite_plane(struct drm_plane *plane, |
6084 | serge | 760 | struct intel_crtc_state *crtc_state, |
5354 | serge | 761 | struct intel_plane_state *state) |
2342 | Serge | 762 | { |
6084 | serge | 763 | struct drm_device *dev = plane->dev; |
764 | struct drm_crtc *crtc = state->base.crtc; |
||
765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2342 | Serge | 766 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 767 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 768 | int crtc_x, crtc_y; |
769 | unsigned int crtc_w, crtc_h; |
||
770 | uint32_t src_x, src_y, src_w, src_h; |
||
771 | struct drm_rect *src = &state->src; |
||
772 | struct drm_rect *dst = &state->dst; |
||
773 | const struct drm_rect *clip = &state->clip; |
||
4104 | Serge | 774 | int hscale, vscale; |
775 | int max_scale, min_scale; |
||
6084 | serge | 776 | bool can_scale; |
777 | int pixel_size; |
||
2342 | Serge | 778 | |
6084 | serge | 779 | if (!fb) { |
780 | state->visible = false; |
||
781 | return 0; |
||
782 | } |
||
783 | |||
4104 | Serge | 784 | /* Don't modify another pipe's plane */ |
785 | if (intel_plane->pipe != intel_crtc->pipe) { |
||
786 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
||
2342 | Serge | 787 | return -EINVAL; |
4104 | Serge | 788 | } |
2342 | Serge | 789 | |
4104 | Serge | 790 | /* FIXME check all gen limits */ |
791 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
||
792 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
||
2342 | Serge | 793 | return -EINVAL; |
4104 | Serge | 794 | } |
2342 | Serge | 795 | |
6084 | serge | 796 | /* setup can_scale, min_scale, max_scale */ |
797 | if (INTEL_INFO(dev)->gen >= 9) { |
||
798 | /* use scaler when colorkey is not required */ |
||
799 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
||
800 | can_scale = 1; |
||
801 | min_scale = 1; |
||
802 | max_scale = skl_max_scale(intel_crtc, crtc_state); |
||
803 | } else { |
||
804 | can_scale = 0; |
||
805 | min_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
806 | max_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
807 | } |
||
808 | } else { |
||
809 | can_scale = intel_plane->can_scale; |
||
810 | max_scale = intel_plane->max_downscale << 16; |
||
811 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
||
3243 | Serge | 812 | } |
813 | |||
2342 | Serge | 814 | /* |
4104 | Serge | 815 | * FIXME the following code does a bunch of fuzzy adjustments to the |
816 | * coordinates and sizes. We probably need some way to decide whether |
||
817 | * more strict checking should be done instead. |
||
2342 | Serge | 818 | */ |
5354 | serge | 819 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
6084 | serge | 820 | state->base.rotation); |
5354 | serge | 821 | |
822 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
||
4104 | Serge | 823 | BUG_ON(hscale < 0); |
824 | |||
5354 | serge | 825 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
4104 | Serge | 826 | BUG_ON(vscale < 0); |
827 | |||
6084 | serge | 828 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
4104 | Serge | 829 | |
5354 | serge | 830 | crtc_x = dst->x1; |
831 | crtc_y = dst->y1; |
||
832 | crtc_w = drm_rect_width(dst); |
||
833 | crtc_h = drm_rect_height(dst); |
||
4104 | Serge | 834 | |
5354 | serge | 835 | if (state->visible) { |
4104 | Serge | 836 | /* check again in case clipping clamped the results */ |
5354 | serge | 837 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
4104 | Serge | 838 | if (hscale < 0) { |
839 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
||
5354 | serge | 840 | drm_rect_debug_print(src, true); |
841 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 842 | |
843 | return hscale; |
||
6084 | serge | 844 | } |
2342 | Serge | 845 | |
5354 | serge | 846 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
4104 | Serge | 847 | if (vscale < 0) { |
848 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
||
5354 | serge | 849 | drm_rect_debug_print(src, true); |
850 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 851 | |
852 | return vscale; |
||
6084 | serge | 853 | } |
2342 | Serge | 854 | |
4104 | Serge | 855 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
5354 | serge | 856 | drm_rect_adjust_size(src, |
857 | drm_rect_width(dst) * hscale - drm_rect_width(src), |
||
858 | drm_rect_height(dst) * vscale - drm_rect_height(src)); |
||
2342 | Serge | 859 | |
5354 | serge | 860 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
6084 | serge | 861 | state->base.rotation); |
5354 | serge | 862 | |
4104 | Serge | 863 | /* sanity check to make sure the src viewport wasn't enlarged */ |
6084 | serge | 864 | WARN_ON(src->x1 < (int) state->base.src_x || |
865 | src->y1 < (int) state->base.src_y || |
||
866 | src->x2 > (int) state->base.src_x + state->base.src_w || |
||
867 | src->y2 > (int) state->base.src_y + state->base.src_h); |
||
4104 | Serge | 868 | |
6084 | serge | 869 | /* |
4104 | Serge | 870 | * Hardware doesn't handle subpixel coordinates. |
871 | * Adjust to (macro)pixel boundary, but be careful not to |
||
872 | * increase the source viewport size, because that could |
||
873 | * push the downscaling factor out of bounds. |
||
6084 | serge | 874 | */ |
5354 | serge | 875 | src_x = src->x1 >> 16; |
876 | src_w = drm_rect_width(src) >> 16; |
||
877 | src_y = src->y1 >> 16; |
||
878 | src_h = drm_rect_height(src) >> 16; |
||
3243 | Serge | 879 | |
4104 | Serge | 880 | if (format_is_yuv(fb->pixel_format)) { |
881 | src_x &= ~1; |
||
882 | src_w &= ~1; |
||
883 | |||
6084 | serge | 884 | /* |
4104 | Serge | 885 | * Must keep src and dst the |
886 | * same if we can't scale. |
||
6084 | serge | 887 | */ |
888 | if (!can_scale) |
||
4104 | Serge | 889 | crtc_w &= ~1; |
890 | |||
891 | if (crtc_w == 0) |
||
5354 | serge | 892 | state->visible = false; |
4104 | Serge | 893 | } |
894 | } |
||
895 | |||
896 | /* Check size restrictions when scaling */ |
||
5354 | serge | 897 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
4104 | Serge | 898 | unsigned int width_bytes; |
899 | |||
6084 | serge | 900 | WARN_ON(!can_scale); |
4104 | Serge | 901 | |
902 | /* FIXME interlacing min height is 6 */ |
||
903 | |||
904 | if (crtc_w < 3 || crtc_h < 3) |
||
5354 | serge | 905 | state->visible = false; |
4104 | Serge | 906 | |
907 | if (src_w < 3 || src_h < 3) |
||
5354 | serge | 908 | state->visible = false; |
4104 | Serge | 909 | |
6084 | serge | 910 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
5354 | serge | 911 | width_bytes = ((src_x * pixel_size) & 63) + |
912 | src_w * pixel_size; |
||
4104 | Serge | 913 | |
6084 | serge | 914 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
915 | width_bytes > 4096 || fb->pitches[0] > 4096)) { |
||
4104 | Serge | 916 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
6084 | serge | 917 | return -EINVAL; |
4104 | Serge | 918 | } |
919 | } |
||
2342 | Serge | 920 | |
5354 | serge | 921 | if (state->visible) { |
6084 | serge | 922 | src->x1 = src_x << 16; |
923 | src->x2 = (src_x + src_w) << 16; |
||
924 | src->y1 = src_y << 16; |
||
925 | src->y2 = (src_y + src_h) << 16; |
||
5354 | serge | 926 | } |
4104 | Serge | 927 | |
5354 | serge | 928 | dst->x1 = crtc_x; |
929 | dst->x2 = crtc_x + crtc_w; |
||
930 | dst->y1 = crtc_y; |
||
931 | dst->y2 = crtc_y + crtc_h; |
||
2342 | Serge | 932 | |
5354 | serge | 933 | return 0; |
934 | } |
||
935 | |||
936 | static void |
||
937 | intel_commit_sprite_plane(struct drm_plane *plane, |
||
938 | struct intel_plane_state *state) |
||
939 | { |
||
6084 | serge | 940 | struct drm_crtc *crtc = state->base.crtc; |
5354 | serge | 941 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 942 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 943 | |
6084 | serge | 944 | crtc = crtc ? crtc : plane->crtc; |
5354 | serge | 945 | |
6084 | serge | 946 | if (!crtc->state->active) |
947 | return; |
||
2342 | Serge | 948 | |
6084 | serge | 949 | if (state->visible) { |
950 | intel_plane->update_plane(plane, crtc, fb, |
||
951 | state->dst.x1, state->dst.y1, |
||
952 | drm_rect_width(&state->dst), |
||
953 | drm_rect_height(&state->dst), |
||
954 | state->src.x1 >> 16, |
||
955 | state->src.y1 >> 16, |
||
956 | drm_rect_width(&state->src) >> 16, |
||
957 | drm_rect_height(&state->src) >> 16); |
||
958 | } else { |
||
4104 | Serge | 959 | intel_plane->disable_plane(plane, crtc); |
4560 | Serge | 960 | } |
5354 | serge | 961 | } |
2342 | Serge | 962 | |
963 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
964 | struct drm_file *file_priv) |
||
965 | { |
||
966 | struct drm_intel_sprite_colorkey *set = data; |
||
967 | struct drm_plane *plane; |
||
6084 | serge | 968 | struct drm_plane_state *plane_state; |
969 | struct drm_atomic_state *state; |
||
970 | struct drm_modeset_acquire_ctx ctx; |
||
2342 | Serge | 971 | int ret = 0; |
972 | |||
973 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
974 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
975 | return -EINVAL; |
||
976 | |||
6084 | serge | 977 | if (IS_VALLEYVIEW(dev) && |
978 | set->flags & I915_SET_COLORKEY_DESTINATION) |
||
979 | return -EINVAL; |
||
2342 | Serge | 980 | |
5060 | serge | 981 | plane = drm_plane_find(dev, set->plane_id); |
6084 | serge | 982 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
983 | return -ENOENT; |
||
2342 | Serge | 984 | |
6084 | serge | 985 | drm_modeset_acquire_init(&ctx, 0); |
2342 | Serge | 986 | |
6084 | serge | 987 | state = drm_atomic_state_alloc(plane->dev); |
988 | if (!state) { |
||
989 | ret = -ENOMEM; |
||
990 | goto out; |
||
991 | } |
||
992 | state->acquire_ctx = &ctx; |
||
2342 | Serge | 993 | |
6084 | serge | 994 | while (1) { |
995 | plane_state = drm_atomic_get_plane_state(state, plane); |
||
996 | ret = PTR_ERR_OR_ZERO(plane_state); |
||
997 | if (!ret) { |
||
998 | to_intel_plane_state(plane_state)->ckey = *set; |
||
999 | ret = drm_atomic_commit(state); |
||
1000 | } |
||
2342 | Serge | 1001 | |
6084 | serge | 1002 | if (ret != -EDEADLK) |
1003 | break; |
||
2342 | Serge | 1004 | |
6084 | serge | 1005 | drm_atomic_state_clear(state); |
1006 | drm_modeset_backoff(&ctx); |
||
2342 | Serge | 1007 | } |
1008 | |||
6084 | serge | 1009 | if (ret) |
1010 | drm_atomic_state_free(state); |
||
2342 | Serge | 1011 | |
6084 | serge | 1012 | out: |
1013 | drm_modeset_drop_locks(&ctx); |
||
1014 | drm_modeset_acquire_fini(&ctx); |
||
2342 | Serge | 1015 | return ret; |
1016 | } |
||
1017 | |||
6084 | serge | 1018 | static const uint32_t ilk_plane_formats[] = { |
3031 | serge | 1019 | DRM_FORMAT_XRGB8888, |
1020 | DRM_FORMAT_YUYV, |
||
1021 | DRM_FORMAT_YVYU, |
||
1022 | DRM_FORMAT_UYVY, |
||
1023 | DRM_FORMAT_VYUY, |
||
1024 | }; |
||
1025 | |||
6084 | serge | 1026 | static const uint32_t snb_plane_formats[] = { |
2342 | Serge | 1027 | DRM_FORMAT_XBGR8888, |
1028 | DRM_FORMAT_XRGB8888, |
||
1029 | DRM_FORMAT_YUYV, |
||
1030 | DRM_FORMAT_YVYU, |
||
1031 | DRM_FORMAT_UYVY, |
||
1032 | DRM_FORMAT_VYUY, |
||
1033 | }; |
||
1034 | |||
6084 | serge | 1035 | static const uint32_t vlv_plane_formats[] = { |
3746 | Serge | 1036 | DRM_FORMAT_RGB565, |
1037 | DRM_FORMAT_ABGR8888, |
||
1038 | DRM_FORMAT_ARGB8888, |
||
1039 | DRM_FORMAT_XBGR8888, |
||
1040 | DRM_FORMAT_XRGB8888, |
||
1041 | DRM_FORMAT_XBGR2101010, |
||
1042 | DRM_FORMAT_ABGR2101010, |
||
1043 | DRM_FORMAT_YUYV, |
||
1044 | DRM_FORMAT_YVYU, |
||
1045 | DRM_FORMAT_UYVY, |
||
1046 | DRM_FORMAT_VYUY, |
||
1047 | }; |
||
1048 | |||
5354 | serge | 1049 | static uint32_t skl_plane_formats[] = { |
1050 | DRM_FORMAT_RGB565, |
||
1051 | DRM_FORMAT_ABGR8888, |
||
1052 | DRM_FORMAT_ARGB8888, |
||
1053 | DRM_FORMAT_XBGR8888, |
||
1054 | DRM_FORMAT_XRGB8888, |
||
1055 | DRM_FORMAT_YUYV, |
||
1056 | DRM_FORMAT_YVYU, |
||
1057 | DRM_FORMAT_UYVY, |
||
1058 | DRM_FORMAT_VYUY, |
||
1059 | }; |
||
1060 | |||
2342 | Serge | 1061 | int |
3746 | Serge | 1062 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
2342 | Serge | 1063 | { |
1064 | struct intel_plane *intel_plane; |
||
6084 | serge | 1065 | struct intel_plane_state *state; |
2342 | Serge | 1066 | unsigned long possible_crtcs; |
3031 | serge | 1067 | const uint32_t *plane_formats; |
1068 | int num_plane_formats; |
||
2342 | Serge | 1069 | int ret; |
1070 | |||
3031 | serge | 1071 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 1072 | return -ENODEV; |
1073 | |||
4560 | Serge | 1074 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
2342 | Serge | 1075 | if (!intel_plane) |
1076 | return -ENOMEM; |
||
1077 | |||
6084 | serge | 1078 | state = intel_create_plane_state(&intel_plane->base); |
1079 | if (!state) { |
||
1080 | kfree(intel_plane); |
||
1081 | return -ENOMEM; |
||
1082 | } |
||
1083 | intel_plane->base.state = &state->base; |
||
1084 | |||
3031 | serge | 1085 | switch (INTEL_INFO(dev)->gen) { |
1086 | case 5: |
||
1087 | case 6: |
||
3243 | Serge | 1088 | intel_plane->can_scale = true; |
3031 | serge | 1089 | intel_plane->max_downscale = 16; |
1090 | intel_plane->update_plane = ilk_update_plane; |
||
1091 | intel_plane->disable_plane = ilk_disable_plane; |
||
1092 | |||
6084 | serge | 1093 | if (IS_GEN6(dev)) { |
3031 | serge | 1094 | plane_formats = snb_plane_formats; |
1095 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
1096 | } else { |
||
1097 | plane_formats = ilk_plane_formats; |
||
1098 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
1099 | } |
||
1100 | break; |
||
1101 | |||
1102 | case 7: |
||
4560 | Serge | 1103 | case 8: |
4104 | Serge | 1104 | if (IS_IVYBRIDGE(dev)) { |
1105 | intel_plane->can_scale = true; |
||
1106 | intel_plane->max_downscale = 2; |
||
1107 | } else { |
||
3243 | Serge | 1108 | intel_plane->can_scale = false; |
4104 | Serge | 1109 | intel_plane->max_downscale = 1; |
1110 | } |
||
3746 | Serge | 1111 | |
1112 | if (IS_VALLEYVIEW(dev)) { |
||
1113 | intel_plane->update_plane = vlv_update_plane; |
||
1114 | intel_plane->disable_plane = vlv_disable_plane; |
||
1115 | |||
1116 | plane_formats = vlv_plane_formats; |
||
1117 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
||
1118 | } else { |
||
6084 | serge | 1119 | intel_plane->update_plane = ivb_update_plane; |
1120 | intel_plane->disable_plane = ivb_disable_plane; |
||
3031 | serge | 1121 | |
6084 | serge | 1122 | plane_formats = snb_plane_formats; |
1123 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
3746 | Serge | 1124 | } |
3031 | serge | 1125 | break; |
5354 | serge | 1126 | case 9: |
6084 | serge | 1127 | intel_plane->can_scale = true; |
5354 | serge | 1128 | intel_plane->update_plane = skl_update_plane; |
1129 | intel_plane->disable_plane = skl_disable_plane; |
||
6084 | serge | 1130 | state->scaler_id = -1; |
3031 | serge | 1131 | |
5354 | serge | 1132 | plane_formats = skl_plane_formats; |
1133 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); |
||
1134 | break; |
||
3031 | serge | 1135 | default: |
1136 | kfree(intel_plane); |
||
1137 | return -ENODEV; |
||
2342 | Serge | 1138 | } |
1139 | |||
1140 | intel_plane->pipe = pipe; |
||
3746 | Serge | 1141 | intel_plane->plane = plane; |
6084 | serge | 1142 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
1143 | intel_plane->check_plane = intel_check_sprite_plane; |
||
1144 | intel_plane->commit_plane = intel_commit_sprite_plane; |
||
2342 | Serge | 1145 | possible_crtcs = (1 << pipe); |
5354 | serge | 1146 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
6084 | serge | 1147 | &intel_plane_funcs, |
1148 | plane_formats, num_plane_formats, |
||
5354 | serge | 1149 | DRM_PLANE_TYPE_OVERLAY); |
1150 | if (ret) { |
||
2342 | Serge | 1151 | kfree(intel_plane); |
5354 | serge | 1152 | goto out; |
1153 | } |
||
2342 | Serge | 1154 | |
6084 | serge | 1155 | intel_create_rotation_property(dev, intel_plane); |
5354 | serge | 1156 | |
6084 | serge | 1157 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
5354 | serge | 1158 | |
6084 | serge | 1159 | out: |
2342 | Serge | 1160 | return ret; |
1161 | }><>>><>><>><>><>>>>>>>>><>><>>>>>><>><>><>><>>>->><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>=>>=>=> |