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Rev | Author | Line No. | Line |
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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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4104 | Serge | 35 | #include |
6084 | serge | 36 | #include |
37 | #include |
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2342 | Serge | 38 | #include "intel_drv.h" |
3031 | serge | 39 | #include |
2342 | Serge | 40 | #include "i915_drv.h" |
41 | |||
5354 | serge | 42 | static bool |
43 | format_is_yuv(uint32_t format) |
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44 | { |
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45 | switch (format) { |
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46 | case DRM_FORMAT_YUYV: |
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47 | case DRM_FORMAT_UYVY: |
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48 | case DRM_FORMAT_VYUY: |
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49 | case DRM_FORMAT_YVYU: |
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50 | return true; |
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51 | default: |
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52 | return false; |
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53 | } |
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54 | } |
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55 | |||
6084 | serge | 56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) |
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5060 | serge | 58 | { |
59 | /* paranoia */ |
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6084 | serge | 60 | if (!adjusted_mode->crtc_htotal) |
5060 | serge | 61 | return 1; |
62 | |||
6084 | serge | 63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); |
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5060 | serge | 65 | } |
66 | |||
5354 | serge | 67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers |
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69 | * @crtc: the crtc of which the registers are going to be updated |
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70 | * @start_vbl_count: vblank counter return pointer used for error checking |
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71 | * |
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72 | * Mark the start of an update to pipe registers that should be updated |
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73 | * atomically regarding vblank. If the next vblank will happens within |
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74 | * the next 100 us, this function waits until the vblank passes. |
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75 | * |
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76 | * After a successful call to this function, interrupts will be disabled |
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77 | * until a subsequent call to intel_pipe_update_end(). That is done to |
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78 | * avoid random delays. The value written to @start_vbl_count should be |
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79 | * supplied to intel_pipe_update_end() for error checking. |
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80 | */ |
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6084 | serge | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
5060 | serge | 82 | { |
83 | struct drm_device *dev = crtc->base.dev; |
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6084 | serge | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 85 | enum pipe pipe = crtc->pipe; |
86 | long timeout = msecs_to_jiffies_timeout(1); |
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87 | int scanline, min, max, vblank_start; |
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6084 | serge | 88 | #if 0 |
89 | // wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
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90 | // DEFINE_WAIT(wait); |
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5060 | serge | 91 | |
6084 | serge | 92 | vblank_start = adjusted_mode->crtc_vblank_start; |
93 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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5060 | serge | 94 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
95 | |||
96 | /* FIXME needs to be calibrated sensibly */ |
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6084 | serge | 97 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
5060 | serge | 98 | max = vblank_start - 1; |
99 | |||
100 | if (min <= 0 || max <= 0) |
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6084 | serge | 101 | return; |
5060 | serge | 102 | |
103 | // if (WARN_ON(drm_vblank_get(dev, pipe))) |
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104 | // return false; |
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105 | |||
6084 | serge | 106 | crtc->debug.min_vbl = min; |
107 | crtc->debug.max_vbl = max; |
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108 | trace_i915_pipe_update_start(crtc); |
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5060 | serge | 109 | |
110 | for (;;) { |
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111 | /* |
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112 | * prepare_to_wait() has a memory barrier, which guarantees |
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113 | * other CPUs can see the task state update by the time we |
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114 | * read the scanline. |
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115 | */ |
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5354 | serge | 116 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
5060 | serge | 117 | |
118 | scanline = intel_get_crtc_scanline(crtc); |
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119 | if (scanline < min || scanline > max) |
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120 | break; |
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121 | |||
122 | if (timeout <= 0) { |
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123 | DRM_ERROR("Potential atomic update failure on pipe %c\n", |
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124 | pipe_name(crtc->pipe)); |
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125 | break; |
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126 | } |
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127 | |||
128 | // local_irq_enable(); |
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129 | |||
130 | schedule_timeout(timeout); |
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131 | timeout = 0; |
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132 | // local_irq_disable(); |
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133 | } |
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134 | |||
5354 | serge | 135 | finish_wait(wq, &wait); |
6084 | serge | 136 | #endif |
5060 | serge | 137 | |
6084 | serge | 138 | crtc->debug.scanline_start = scanline; |
139 | crtc->debug.start_vbl_time = ktime_get(); |
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140 | crtc->debug.start_vbl_count = |
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141 | dev->driver->get_vblank_counter(dev, pipe); |
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5060 | serge | 142 | |
6084 | serge | 143 | trace_i915_pipe_update_vblank_evaded(crtc); |
5060 | serge | 144 | } |
145 | |||
5354 | serge | 146 | /** |
147 | * intel_pipe_update_end() - end update of a set of display registers |
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148 | * @crtc: the crtc of which the registers were updated |
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149 | * @start_vbl_count: start vblank counter (used for error checking) |
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150 | * |
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151 | * Mark the end of an update started with intel_pipe_update_start(). This |
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152 | * re-enables interrupts and verifies the update was actually completed |
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153 | * before a vblank using the value of @start_vbl_count. |
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154 | */ |
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6084 | serge | 155 | void intel_pipe_update_end(struct intel_crtc *crtc) |
5060 | serge | 156 | { |
157 | struct drm_device *dev = crtc->base.dev; |
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158 | enum pipe pipe = crtc->pipe; |
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6084 | serge | 159 | int scanline_end = intel_get_crtc_scanline(crtc); |
5060 | serge | 160 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
6084 | serge | 161 | ktime_t end_vbl_time = ktime_get(); |
5060 | serge | 162 | |
6084 | serge | 163 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
5060 | serge | 164 | |
165 | // local_irq_enable(); |
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166 | |||
6084 | serge | 167 | if (crtc->debug.start_vbl_count && |
168 | crtc->debug.start_vbl_count != end_vbl_count) { |
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169 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", |
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170 | pipe_name(pipe), crtc->debug.start_vbl_count, |
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171 | end_vbl_count, |
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172 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), |
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173 | crtc->debug.min_vbl, crtc->debug.max_vbl, |
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174 | crtc->debug.scanline_start, scanline_end); |
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175 | } |
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5060 | serge | 176 | } |
177 | |||
2342 | Serge | 178 | static void |
5354 | serge | 179 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, |
180 | struct drm_framebuffer *fb, |
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6084 | serge | 181 | int crtc_x, int crtc_y, |
5354 | serge | 182 | unsigned int crtc_w, unsigned int crtc_h, |
183 | uint32_t x, uint32_t y, |
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184 | uint32_t src_w, uint32_t src_h) |
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185 | { |
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186 | struct drm_device *dev = drm_plane->dev; |
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187 | struct drm_i915_private *dev_priv = dev->dev_private; |
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188 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
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6084 | serge | 189 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
5354 | serge | 190 | const int pipe = intel_plane->pipe; |
191 | const int plane = intel_plane->plane + 1; |
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6084 | serge | 192 | u32 plane_ctl, stride_div, stride; |
5354 | serge | 193 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 194 | const struct drm_intel_sprite_colorkey *key = |
195 | &to_intel_plane_state(drm_plane->state)->ckey; |
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196 | unsigned long surf_addr; |
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197 | u32 tile_height, plane_offset, plane_size; |
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198 | unsigned int rotation; |
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199 | int x_offset, y_offset; |
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200 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
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201 | int scaler_id; |
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5354 | serge | 202 | |
6084 | serge | 203 | plane_ctl = PLANE_CTL_ENABLE | |
204 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
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205 | PLANE_CTL_PIPE_CSC_ENABLE; |
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5354 | serge | 206 | |
6084 | serge | 207 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
208 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
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5354 | serge | 209 | |
6084 | serge | 210 | rotation = drm_plane->state->rotation; |
211 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
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5354 | serge | 212 | |
213 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, |
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214 | pixel_size, true, |
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215 | src_w != crtc_w || src_h != crtc_h); |
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216 | |||
6084 | serge | 217 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
218 | fb->pixel_format); |
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219 | |||
220 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
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221 | |||
5354 | serge | 222 | /* Sizes are 0 based */ |
223 | src_w--; |
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224 | src_h--; |
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225 | crtc_w--; |
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226 | crtc_h--; |
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227 | |||
6084 | serge | 228 | if (key->flags) { |
229 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); |
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230 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); |
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231 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); |
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232 | } |
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5354 | serge | 233 | |
6084 | serge | 234 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
235 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; |
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236 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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237 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; |
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5354 | serge | 238 | |
6084 | serge | 239 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
5354 | serge | 240 | |
6084 | serge | 241 | if (intel_rotation_90_or_270(rotation)) { |
242 | /* stride: Surface height in tiles */ |
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243 | tile_height = intel_tile_height(dev, fb->pixel_format, |
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244 | fb->modifier[0], 0); |
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245 | stride = DIV_ROUND_UP(fb->height, tile_height); |
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246 | plane_size = (src_w << 16) | src_h; |
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247 | x_offset = stride * tile_height - y - (src_h + 1); |
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248 | y_offset = x; |
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249 | } else { |
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250 | stride = fb->pitches[0] / stride_div; |
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251 | plane_size = (src_h << 16) | src_w; |
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252 | x_offset = x; |
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253 | y_offset = y; |
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254 | } |
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255 | plane_offset = y_offset << 16 | x_offset; |
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5354 | serge | 256 | |
6084 | serge | 257 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); |
258 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); |
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259 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
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5354 | serge | 260 | |
6084 | serge | 261 | /* program plane scaler */ |
262 | if (scaler_id >= 0) { |
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263 | uint32_t ps_ctrl = 0; |
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5354 | serge | 264 | |
6084 | serge | 265 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, |
266 | PS_PLANE_SEL(plane)); |
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267 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | |
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268 | crtc_state->scaler_state.scalers[scaler_id].mode; |
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269 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
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270 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
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271 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); |
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272 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), |
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273 | ((crtc_w + 1) << 16)|(crtc_h + 1)); |
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5354 | serge | 274 | |
6084 | serge | 275 | I915_WRITE(PLANE_POS(pipe, plane), 0); |
276 | } else { |
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277 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
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278 | } |
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279 | |||
5354 | serge | 280 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
6084 | serge | 281 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
282 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 283 | } |
284 | |||
285 | static void |
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6084 | serge | 286 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
5354 | serge | 287 | { |
6084 | serge | 288 | struct drm_device *dev = dplane->dev; |
5354 | serge | 289 | struct drm_i915_private *dev_priv = dev->dev_private; |
6084 | serge | 290 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
5354 | serge | 291 | const int pipe = intel_plane->pipe; |
6084 | serge | 292 | const int plane = intel_plane->plane + 1; |
5354 | serge | 293 | |
6084 | serge | 294 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
5354 | serge | 295 | |
6084 | serge | 296 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
297 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 298 | |
6084 | serge | 299 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
5354 | serge | 300 | } |
301 | |||
302 | static void |
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303 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) |
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304 | { |
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305 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; |
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306 | int plane = intel_plane->plane; |
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307 | |||
308 | /* Seems RGB data bypasses the CSC always */ |
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309 | if (!format_is_yuv(format)) |
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310 | return; |
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311 | |||
312 | /* |
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313 | * BT.601 limited range YCbCr -> full range RGB |
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314 | * |
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315 | * |r| | 6537 4769 0| |cr | |
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316 | * |g| = |-3330 4769 -1605| x |y-64| |
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317 | * |b| | 0 4769 8263| |cb | |
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318 | * |
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319 | * Cb and Cr apparently come in as signed already, so no |
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320 | * need for any offset. For Y we need to remove the offset. |
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321 | */ |
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322 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); |
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323 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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324 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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325 | |||
326 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); |
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327 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); |
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328 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); |
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329 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); |
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330 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); |
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331 | |||
332 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); |
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333 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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334 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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335 | |||
336 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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337 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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338 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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339 | } |
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340 | |||
341 | static void |
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4104 | Serge | 342 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
343 | struct drm_framebuffer *fb, |
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6084 | serge | 344 | int crtc_x, int crtc_y, |
3746 | Serge | 345 | unsigned int crtc_w, unsigned int crtc_h, |
346 | uint32_t x, uint32_t y, |
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347 | uint32_t src_w, uint32_t src_h) |
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348 | { |
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349 | struct drm_device *dev = dplane->dev; |
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350 | struct drm_i915_private *dev_priv = dev->dev_private; |
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351 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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6084 | serge | 352 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3746 | Serge | 353 | int pipe = intel_plane->pipe; |
354 | int plane = intel_plane->plane; |
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355 | u32 sprctl; |
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356 | unsigned long sprsurf_offset, linear_offset; |
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357 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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6084 | serge | 358 | const struct drm_intel_sprite_colorkey *key = |
359 | &to_intel_plane_state(dplane->state)->ckey; |
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3746 | Serge | 360 | |
6084 | serge | 361 | sprctl = SP_ENABLE; |
3746 | Serge | 362 | |
363 | switch (fb->pixel_format) { |
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364 | case DRM_FORMAT_YUYV: |
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365 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
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366 | break; |
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367 | case DRM_FORMAT_YVYU: |
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368 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
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369 | break; |
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370 | case DRM_FORMAT_UYVY: |
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371 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
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372 | break; |
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373 | case DRM_FORMAT_VYUY: |
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374 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
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375 | break; |
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376 | case DRM_FORMAT_RGB565: |
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377 | sprctl |= SP_FORMAT_BGR565; |
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378 | break; |
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379 | case DRM_FORMAT_XRGB8888: |
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380 | sprctl |= SP_FORMAT_BGRX8888; |
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381 | break; |
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382 | case DRM_FORMAT_ARGB8888: |
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383 | sprctl |= SP_FORMAT_BGRA8888; |
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384 | break; |
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385 | case DRM_FORMAT_XBGR2101010: |
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386 | sprctl |= SP_FORMAT_RGBX1010102; |
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387 | break; |
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388 | case DRM_FORMAT_ABGR2101010: |
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389 | sprctl |= SP_FORMAT_RGBA1010102; |
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390 | break; |
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391 | case DRM_FORMAT_XBGR8888: |
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392 | sprctl |= SP_FORMAT_RGBX8888; |
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393 | break; |
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394 | case DRM_FORMAT_ABGR8888: |
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395 | sprctl |= SP_FORMAT_RGBA8888; |
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396 | break; |
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397 | default: |
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398 | /* |
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399 | * If we get here one of the upper layers failed to filter |
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400 | * out the unsupported plane formats |
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401 | */ |
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402 | BUG(); |
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403 | break; |
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404 | } |
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405 | |||
4560 | Serge | 406 | /* |
407 | * Enable gamma to match primary/cursor plane behaviour. |
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408 | * FIXME should be user controllable via propertiesa. |
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409 | */ |
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410 | sprctl |= SP_GAMMA_ENABLE; |
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411 | |||
3746 | Serge | 412 | if (obj->tiling_mode != I915_TILING_NONE) |
413 | sprctl |= SP_TILED; |
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414 | |||
415 | /* Sizes are 0 based */ |
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416 | src_w--; |
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417 | src_h--; |
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418 | crtc_w--; |
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419 | crtc_h--; |
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420 | |||
421 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
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6084 | serge | 422 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, |
423 | &x, &y, |
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3746 | Serge | 424 | obj->tiling_mode, |
425 | pixel_size, |
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426 | fb->pitches[0]); |
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427 | linear_offset -= sprsurf_offset; |
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428 | |||
6084 | serge | 429 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 430 | sprctl |= SP_ROTATE_180; |
431 | |||
432 | x += src_w; |
||
433 | y += src_h; |
||
434 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
435 | } |
||
436 | |||
6084 | serge | 437 | if (key->flags) { |
438 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
||
439 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
||
440 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
||
441 | } |
||
5060 | serge | 442 | |
6084 | serge | 443 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
444 | sprctl |= SP_SOURCE_KEY; |
||
5060 | serge | 445 | |
5354 | serge | 446 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
447 | chv_update_csc(intel_plane, fb->pixel_format); |
||
448 | |||
5060 | serge | 449 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
450 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
||
451 | |||
3746 | Serge | 452 | if (obj->tiling_mode != I915_TILING_NONE) |
453 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
||
454 | else |
||
455 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
||
456 | |||
5354 | serge | 457 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
458 | |||
3746 | Serge | 459 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
460 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
||
4560 | Serge | 461 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
6084 | serge | 462 | sprsurf_offset); |
463 | POSTING_READ(SPSURF(pipe, plane)); |
||
3746 | Serge | 464 | } |
465 | |||
466 | static void |
||
4104 | Serge | 467 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
3746 | Serge | 468 | { |
469 | struct drm_device *dev = dplane->dev; |
||
470 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
471 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
||
472 | int pipe = intel_plane->pipe; |
||
473 | int plane = intel_plane->plane; |
||
474 | |||
6084 | serge | 475 | I915_WRITE(SPCNTR(pipe, plane), 0); |
5060 | serge | 476 | |
4560 | Serge | 477 | I915_WRITE(SPSURF(pipe, plane), 0); |
6084 | serge | 478 | POSTING_READ(SPSURF(pipe, plane)); |
3746 | Serge | 479 | } |
480 | |||
481 | static void |
||
4104 | Serge | 482 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
483 | struct drm_framebuffer *fb, |
||
6084 | serge | 484 | int crtc_x, int crtc_y, |
2342 | Serge | 485 | unsigned int crtc_w, unsigned int crtc_h, |
486 | uint32_t x, uint32_t y, |
||
487 | uint32_t src_w, uint32_t src_h) |
||
488 | { |
||
489 | struct drm_device *dev = plane->dev; |
||
490 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
491 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 492 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
493 | enum pipe pipe = intel_plane->pipe; |
||
2342 | Serge | 494 | u32 sprctl, sprscale = 0; |
3243 | Serge | 495 | unsigned long sprsurf_offset, linear_offset; |
496 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
||
6084 | serge | 497 | const struct drm_intel_sprite_colorkey *key = |
498 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 499 | |
6084 | serge | 500 | sprctl = SPRITE_ENABLE; |
2342 | Serge | 501 | |
502 | switch (fb->pixel_format) { |
||
503 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 504 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 505 | break; |
506 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 507 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 508 | break; |
509 | case DRM_FORMAT_YUYV: |
||
510 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
||
511 | break; |
||
512 | case DRM_FORMAT_YVYU: |
||
513 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
||
514 | break; |
||
515 | case DRM_FORMAT_UYVY: |
||
516 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
||
517 | break; |
||
518 | case DRM_FORMAT_VYUY: |
||
519 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
||
520 | break; |
||
521 | default: |
||
3243 | Serge | 522 | BUG(); |
2342 | Serge | 523 | } |
524 | |||
4560 | Serge | 525 | /* |
526 | * Enable gamma to match primary/cursor plane behaviour. |
||
527 | * FIXME should be user controllable via propertiesa. |
||
528 | */ |
||
529 | sprctl |= SPRITE_GAMMA_ENABLE; |
||
530 | |||
2342 | Serge | 531 | if (obj->tiling_mode != I915_TILING_NONE) |
532 | sprctl |= SPRITE_TILED; |
||
533 | |||
4560 | Serge | 534 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4104 | Serge | 535 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
536 | else |
||
6084 | serge | 537 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
4104 | Serge | 538 | |
4560 | Serge | 539 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3480 | Serge | 540 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
541 | |||
5060 | serge | 542 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
543 | true, |
||
4104 | Serge | 544 | src_w != crtc_w || src_h != crtc_h); |
545 | |||
2342 | Serge | 546 | /* Sizes are 0 based */ |
547 | src_w--; |
||
548 | src_h--; |
||
549 | crtc_w--; |
||
550 | crtc_h--; |
||
551 | |||
4560 | Serge | 552 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 553 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
554 | |||
3243 | Serge | 555 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
556 | sprsurf_offset = |
||
6084 | serge | 557 | intel_gen4_compute_page_offset(dev_priv, |
558 | &x, &y, obj->tiling_mode, |
||
559 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 560 | linear_offset -= sprsurf_offset; |
561 | |||
6084 | serge | 562 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 563 | sprctl |= SPRITE_ROTATE_180; |
564 | |||
565 | /* HSW and BDW does this automagically in hardware */ |
||
566 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
||
567 | x += src_w; |
||
568 | y += src_h; |
||
569 | linear_offset += src_h * fb->pitches[0] + |
||
570 | src_w * pixel_size; |
||
571 | } |
||
572 | } |
||
573 | |||
6084 | serge | 574 | if (key->flags) { |
575 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); |
||
576 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); |
||
577 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); |
||
578 | } |
||
5060 | serge | 579 | |
6084 | serge | 580 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
581 | sprctl |= SPRITE_DEST_KEY; |
||
582 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
583 | sprctl |= SPRITE_SOURCE_KEY; |
||
5060 | serge | 584 | |
585 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
||
586 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
||
587 | |||
3243 | Serge | 588 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
589 | * register */ |
||
4560 | Serge | 590 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3243 | Serge | 591 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
592 | else if (obj->tiling_mode != I915_TILING_NONE) |
||
2342 | Serge | 593 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 594 | else |
595 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
||
2342 | Serge | 596 | |
597 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
3243 | Serge | 598 | if (intel_plane->can_scale) |
6084 | serge | 599 | I915_WRITE(SPRSCALE(pipe), sprscale); |
2342 | Serge | 600 | I915_WRITE(SPRCTL(pipe), sprctl); |
4560 | Serge | 601 | I915_WRITE(SPRSURF(pipe), |
6084 | serge | 602 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
603 | POSTING_READ(SPRSURF(pipe)); |
||
2342 | Serge | 604 | } |
605 | |||
606 | static void |
||
4104 | Serge | 607 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 608 | { |
609 | struct drm_device *dev = plane->dev; |
||
610 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
611 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
612 | int pipe = intel_plane->pipe; |
||
613 | |||
6084 | serge | 614 | I915_WRITE(SPRCTL(pipe), 0); |
2342 | Serge | 615 | /* Can't leave the scaler enabled... */ |
3243 | Serge | 616 | if (intel_plane->can_scale) |
6084 | serge | 617 | I915_WRITE(SPRSCALE(pipe), 0); |
618 | |||
4560 | Serge | 619 | I915_WRITE(SPRSURF(pipe), 0); |
6084 | serge | 620 | POSTING_READ(SPRSURF(pipe)); |
2342 | Serge | 621 | } |
622 | |||
623 | static void |
||
4104 | Serge | 624 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
625 | struct drm_framebuffer *fb, |
||
6084 | serge | 626 | int crtc_x, int crtc_y, |
2342 | Serge | 627 | unsigned int crtc_w, unsigned int crtc_h, |
628 | uint32_t x, uint32_t y, |
||
629 | uint32_t src_w, uint32_t src_h) |
||
630 | { |
||
631 | struct drm_device *dev = plane->dev; |
||
632 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
633 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 634 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3243 | Serge | 635 | int pipe = intel_plane->pipe; |
636 | unsigned long dvssurf_offset, linear_offset; |
||
3031 | serge | 637 | u32 dvscntr, dvsscale; |
3243 | Serge | 638 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 639 | const struct drm_intel_sprite_colorkey *key = |
640 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 641 | |
6084 | serge | 642 | dvscntr = DVS_ENABLE; |
2342 | Serge | 643 | |
644 | switch (fb->pixel_format) { |
||
645 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 646 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 647 | break; |
648 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 649 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 650 | break; |
651 | case DRM_FORMAT_YUYV: |
||
652 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
||
653 | break; |
||
654 | case DRM_FORMAT_YVYU: |
||
655 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
||
656 | break; |
||
657 | case DRM_FORMAT_UYVY: |
||
658 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
||
659 | break; |
||
660 | case DRM_FORMAT_VYUY: |
||
661 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
||
662 | break; |
||
663 | default: |
||
3243 | Serge | 664 | BUG(); |
2342 | Serge | 665 | } |
666 | |||
4560 | Serge | 667 | /* |
668 | * Enable gamma to match primary/cursor plane behaviour. |
||
669 | * FIXME should be user controllable via propertiesa. |
||
670 | */ |
||
671 | dvscntr |= DVS_GAMMA_ENABLE; |
||
672 | |||
2342 | Serge | 673 | if (obj->tiling_mode != I915_TILING_NONE) |
674 | dvscntr |= DVS_TILED; |
||
675 | |||
3031 | serge | 676 | if (IS_GEN6(dev)) |
677 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
||
2342 | Serge | 678 | |
5060 | serge | 679 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
680 | pixel_size, true, |
||
4104 | Serge | 681 | src_w != crtc_w || src_h != crtc_h); |
682 | |||
2342 | Serge | 683 | /* Sizes are 0 based */ |
684 | src_w--; |
||
685 | src_h--; |
||
686 | crtc_w--; |
||
687 | crtc_h--; |
||
688 | |||
3031 | serge | 689 | dvsscale = 0; |
4560 | Serge | 690 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 691 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
692 | |||
3243 | Serge | 693 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
694 | dvssurf_offset = |
||
6084 | serge | 695 | intel_gen4_compute_page_offset(dev_priv, |
696 | &x, &y, obj->tiling_mode, |
||
697 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 698 | linear_offset -= dvssurf_offset; |
699 | |||
6084 | serge | 700 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 701 | dvscntr |= DVS_ROTATE_180; |
702 | |||
703 | x += src_w; |
||
704 | y += src_h; |
||
705 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
706 | } |
||
707 | |||
6084 | serge | 708 | if (key->flags) { |
709 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); |
||
710 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); |
||
711 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); |
||
712 | } |
||
5060 | serge | 713 | |
6084 | serge | 714 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
715 | dvscntr |= DVS_DEST_KEY; |
||
716 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
717 | dvscntr |= DVS_SOURCE_KEY; |
||
5060 | serge | 718 | |
719 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
||
720 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
||
721 | |||
3243 | Serge | 722 | if (obj->tiling_mode != I915_TILING_NONE) |
2342 | Serge | 723 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 724 | else |
725 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
||
2342 | Serge | 726 | |
727 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
728 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
||
729 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
||
4560 | Serge | 730 | I915_WRITE(DVSSURF(pipe), |
6084 | serge | 731 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
732 | POSTING_READ(DVSSURF(pipe)); |
||
2342 | Serge | 733 | } |
734 | |||
735 | static void |
||
4104 | Serge | 736 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 737 | { |
738 | struct drm_device *dev = plane->dev; |
||
739 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
740 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
741 | int pipe = intel_plane->pipe; |
||
742 | |||
6084 | serge | 743 | I915_WRITE(DVSCNTR(pipe), 0); |
2342 | Serge | 744 | /* Disable the scaler */ |
745 | I915_WRITE(DVSSCALE(pipe), 0); |
||
6084 | serge | 746 | |
4560 | Serge | 747 | I915_WRITE(DVSSURF(pipe), 0); |
6084 | serge | 748 | POSTING_READ(DVSSURF(pipe)); |
2342 | Serge | 749 | } |
750 | |||
751 | static int |
||
5354 | serge | 752 | intel_check_sprite_plane(struct drm_plane *plane, |
6084 | serge | 753 | struct intel_crtc_state *crtc_state, |
5354 | serge | 754 | struct intel_plane_state *state) |
2342 | Serge | 755 | { |
6084 | serge | 756 | struct drm_device *dev = plane->dev; |
757 | struct drm_crtc *crtc = state->base.crtc; |
||
758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2342 | Serge | 759 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 760 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 761 | int crtc_x, crtc_y; |
762 | unsigned int crtc_w, crtc_h; |
||
763 | uint32_t src_x, src_y, src_w, src_h; |
||
764 | struct drm_rect *src = &state->src; |
||
765 | struct drm_rect *dst = &state->dst; |
||
766 | const struct drm_rect *clip = &state->clip; |
||
4104 | Serge | 767 | int hscale, vscale; |
768 | int max_scale, min_scale; |
||
6084 | serge | 769 | bool can_scale; |
770 | int pixel_size; |
||
2342 | Serge | 771 | |
6084 | serge | 772 | if (!fb) { |
773 | state->visible = false; |
||
774 | return 0; |
||
775 | } |
||
776 | |||
4104 | Serge | 777 | /* Don't modify another pipe's plane */ |
778 | if (intel_plane->pipe != intel_crtc->pipe) { |
||
779 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
||
2342 | Serge | 780 | return -EINVAL; |
4104 | Serge | 781 | } |
2342 | Serge | 782 | |
4104 | Serge | 783 | /* FIXME check all gen limits */ |
784 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
||
785 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
||
2342 | Serge | 786 | return -EINVAL; |
4104 | Serge | 787 | } |
2342 | Serge | 788 | |
6084 | serge | 789 | /* setup can_scale, min_scale, max_scale */ |
790 | if (INTEL_INFO(dev)->gen >= 9) { |
||
791 | /* use scaler when colorkey is not required */ |
||
792 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
||
793 | can_scale = 1; |
||
794 | min_scale = 1; |
||
795 | max_scale = skl_max_scale(intel_crtc, crtc_state); |
||
796 | } else { |
||
797 | can_scale = 0; |
||
798 | min_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
799 | max_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
800 | } |
||
801 | } else { |
||
802 | can_scale = intel_plane->can_scale; |
||
803 | max_scale = intel_plane->max_downscale << 16; |
||
804 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
||
3243 | Serge | 805 | } |
806 | |||
2342 | Serge | 807 | /* |
4104 | Serge | 808 | * FIXME the following code does a bunch of fuzzy adjustments to the |
809 | * coordinates and sizes. We probably need some way to decide whether |
||
810 | * more strict checking should be done instead. |
||
2342 | Serge | 811 | */ |
5354 | serge | 812 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
6084 | serge | 813 | state->base.rotation); |
5354 | serge | 814 | |
815 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
||
4104 | Serge | 816 | BUG_ON(hscale < 0); |
817 | |||
5354 | serge | 818 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
4104 | Serge | 819 | BUG_ON(vscale < 0); |
820 | |||
6084 | serge | 821 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
4104 | Serge | 822 | |
5354 | serge | 823 | crtc_x = dst->x1; |
824 | crtc_y = dst->y1; |
||
825 | crtc_w = drm_rect_width(dst); |
||
826 | crtc_h = drm_rect_height(dst); |
||
4104 | Serge | 827 | |
5354 | serge | 828 | if (state->visible) { |
4104 | Serge | 829 | /* check again in case clipping clamped the results */ |
5354 | serge | 830 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
4104 | Serge | 831 | if (hscale < 0) { |
832 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
||
5354 | serge | 833 | drm_rect_debug_print(src, true); |
834 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 835 | |
836 | return hscale; |
||
6084 | serge | 837 | } |
2342 | Serge | 838 | |
5354 | serge | 839 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
4104 | Serge | 840 | if (vscale < 0) { |
841 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
||
5354 | serge | 842 | drm_rect_debug_print(src, true); |
843 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 844 | |
845 | return vscale; |
||
6084 | serge | 846 | } |
2342 | Serge | 847 | |
4104 | Serge | 848 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
5354 | serge | 849 | drm_rect_adjust_size(src, |
850 | drm_rect_width(dst) * hscale - drm_rect_width(src), |
||
851 | drm_rect_height(dst) * vscale - drm_rect_height(src)); |
||
2342 | Serge | 852 | |
5354 | serge | 853 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
6084 | serge | 854 | state->base.rotation); |
5354 | serge | 855 | |
4104 | Serge | 856 | /* sanity check to make sure the src viewport wasn't enlarged */ |
6084 | serge | 857 | WARN_ON(src->x1 < (int) state->base.src_x || |
858 | src->y1 < (int) state->base.src_y || |
||
859 | src->x2 > (int) state->base.src_x + state->base.src_w || |
||
860 | src->y2 > (int) state->base.src_y + state->base.src_h); |
||
4104 | Serge | 861 | |
6084 | serge | 862 | /* |
4104 | Serge | 863 | * Hardware doesn't handle subpixel coordinates. |
864 | * Adjust to (macro)pixel boundary, but be careful not to |
||
865 | * increase the source viewport size, because that could |
||
866 | * push the downscaling factor out of bounds. |
||
6084 | serge | 867 | */ |
5354 | serge | 868 | src_x = src->x1 >> 16; |
869 | src_w = drm_rect_width(src) >> 16; |
||
870 | src_y = src->y1 >> 16; |
||
871 | src_h = drm_rect_height(src) >> 16; |
||
3243 | Serge | 872 | |
4104 | Serge | 873 | if (format_is_yuv(fb->pixel_format)) { |
874 | src_x &= ~1; |
||
875 | src_w &= ~1; |
||
876 | |||
6084 | serge | 877 | /* |
4104 | Serge | 878 | * Must keep src and dst the |
879 | * same if we can't scale. |
||
6084 | serge | 880 | */ |
881 | if (!can_scale) |
||
4104 | Serge | 882 | crtc_w &= ~1; |
883 | |||
884 | if (crtc_w == 0) |
||
5354 | serge | 885 | state->visible = false; |
4104 | Serge | 886 | } |
887 | } |
||
888 | |||
889 | /* Check size restrictions when scaling */ |
||
5354 | serge | 890 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
4104 | Serge | 891 | unsigned int width_bytes; |
892 | |||
6084 | serge | 893 | WARN_ON(!can_scale); |
4104 | Serge | 894 | |
895 | /* FIXME interlacing min height is 6 */ |
||
896 | |||
897 | if (crtc_w < 3 || crtc_h < 3) |
||
5354 | serge | 898 | state->visible = false; |
4104 | Serge | 899 | |
900 | if (src_w < 3 || src_h < 3) |
||
5354 | serge | 901 | state->visible = false; |
4104 | Serge | 902 | |
6084 | serge | 903 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
5354 | serge | 904 | width_bytes = ((src_x * pixel_size) & 63) + |
905 | src_w * pixel_size; |
||
4104 | Serge | 906 | |
6084 | serge | 907 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
908 | width_bytes > 4096 || fb->pitches[0] > 4096)) { |
||
4104 | Serge | 909 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
6084 | serge | 910 | return -EINVAL; |
4104 | Serge | 911 | } |
912 | } |
||
2342 | Serge | 913 | |
5354 | serge | 914 | if (state->visible) { |
6084 | serge | 915 | src->x1 = src_x << 16; |
916 | src->x2 = (src_x + src_w) << 16; |
||
917 | src->y1 = src_y << 16; |
||
918 | src->y2 = (src_y + src_h) << 16; |
||
5354 | serge | 919 | } |
4104 | Serge | 920 | |
5354 | serge | 921 | dst->x1 = crtc_x; |
922 | dst->x2 = crtc_x + crtc_w; |
||
923 | dst->y1 = crtc_y; |
||
924 | dst->y2 = crtc_y + crtc_h; |
||
2342 | Serge | 925 | |
5354 | serge | 926 | return 0; |
927 | } |
||
928 | |||
929 | static void |
||
930 | intel_commit_sprite_plane(struct drm_plane *plane, |
||
931 | struct intel_plane_state *state) |
||
932 | { |
||
6084 | serge | 933 | struct drm_crtc *crtc = state->base.crtc; |
5354 | serge | 934 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 935 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 936 | |
6084 | serge | 937 | crtc = crtc ? crtc : plane->crtc; |
5354 | serge | 938 | |
6084 | serge | 939 | if (!crtc->state->active) |
940 | return; |
||
2342 | Serge | 941 | |
6084 | serge | 942 | if (state->visible) { |
943 | intel_plane->update_plane(plane, crtc, fb, |
||
944 | state->dst.x1, state->dst.y1, |
||
945 | drm_rect_width(&state->dst), |
||
946 | drm_rect_height(&state->dst), |
||
947 | state->src.x1 >> 16, |
||
948 | state->src.y1 >> 16, |
||
949 | drm_rect_width(&state->src) >> 16, |
||
950 | drm_rect_height(&state->src) >> 16); |
||
951 | } else { |
||
4104 | Serge | 952 | intel_plane->disable_plane(plane, crtc); |
4560 | Serge | 953 | } |
5354 | serge | 954 | } |
2342 | Serge | 955 | |
956 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
957 | struct drm_file *file_priv) |
||
958 | { |
||
959 | struct drm_intel_sprite_colorkey *set = data; |
||
960 | struct drm_plane *plane; |
||
6084 | serge | 961 | struct drm_plane_state *plane_state; |
962 | struct drm_atomic_state *state; |
||
963 | struct drm_modeset_acquire_ctx ctx; |
||
2342 | Serge | 964 | int ret = 0; |
965 | |||
966 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
967 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
968 | return -EINVAL; |
||
969 | |||
6084 | serge | 970 | if (IS_VALLEYVIEW(dev) && |
971 | set->flags & I915_SET_COLORKEY_DESTINATION) |
||
972 | return -EINVAL; |
||
2342 | Serge | 973 | |
5060 | serge | 974 | plane = drm_plane_find(dev, set->plane_id); |
6084 | serge | 975 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
976 | return -ENOENT; |
||
2342 | Serge | 977 | |
6084 | serge | 978 | drm_modeset_acquire_init(&ctx, 0); |
2342 | Serge | 979 | |
6084 | serge | 980 | state = drm_atomic_state_alloc(plane->dev); |
981 | if (!state) { |
||
982 | ret = -ENOMEM; |
||
983 | goto out; |
||
984 | } |
||
985 | state->acquire_ctx = &ctx; |
||
2342 | Serge | 986 | |
6084 | serge | 987 | while (1) { |
988 | plane_state = drm_atomic_get_plane_state(state, plane); |
||
989 | ret = PTR_ERR_OR_ZERO(plane_state); |
||
990 | if (!ret) { |
||
991 | to_intel_plane_state(plane_state)->ckey = *set; |
||
992 | ret = drm_atomic_commit(state); |
||
993 | } |
||
2342 | Serge | 994 | |
6084 | serge | 995 | if (ret != -EDEADLK) |
996 | break; |
||
2342 | Serge | 997 | |
6084 | serge | 998 | drm_atomic_state_clear(state); |
999 | drm_modeset_backoff(&ctx); |
||
2342 | Serge | 1000 | } |
1001 | |||
6084 | serge | 1002 | if (ret) |
1003 | drm_atomic_state_free(state); |
||
2342 | Serge | 1004 | |
6084 | serge | 1005 | out: |
1006 | drm_modeset_drop_locks(&ctx); |
||
1007 | drm_modeset_acquire_fini(&ctx); |
||
2342 | Serge | 1008 | return ret; |
1009 | } |
||
1010 | |||
6084 | serge | 1011 | static const uint32_t ilk_plane_formats[] = { |
3031 | serge | 1012 | DRM_FORMAT_XRGB8888, |
1013 | DRM_FORMAT_YUYV, |
||
1014 | DRM_FORMAT_YVYU, |
||
1015 | DRM_FORMAT_UYVY, |
||
1016 | DRM_FORMAT_VYUY, |
||
1017 | }; |
||
1018 | |||
6084 | serge | 1019 | static const uint32_t snb_plane_formats[] = { |
2342 | Serge | 1020 | DRM_FORMAT_XBGR8888, |
1021 | DRM_FORMAT_XRGB8888, |
||
1022 | DRM_FORMAT_YUYV, |
||
1023 | DRM_FORMAT_YVYU, |
||
1024 | DRM_FORMAT_UYVY, |
||
1025 | DRM_FORMAT_VYUY, |
||
1026 | }; |
||
1027 | |||
6084 | serge | 1028 | static const uint32_t vlv_plane_formats[] = { |
3746 | Serge | 1029 | DRM_FORMAT_RGB565, |
1030 | DRM_FORMAT_ABGR8888, |
||
1031 | DRM_FORMAT_ARGB8888, |
||
1032 | DRM_FORMAT_XBGR8888, |
||
1033 | DRM_FORMAT_XRGB8888, |
||
1034 | DRM_FORMAT_XBGR2101010, |
||
1035 | DRM_FORMAT_ABGR2101010, |
||
1036 | DRM_FORMAT_YUYV, |
||
1037 | DRM_FORMAT_YVYU, |
||
1038 | DRM_FORMAT_UYVY, |
||
1039 | DRM_FORMAT_VYUY, |
||
1040 | }; |
||
1041 | |||
5354 | serge | 1042 | static uint32_t skl_plane_formats[] = { |
1043 | DRM_FORMAT_RGB565, |
||
1044 | DRM_FORMAT_ABGR8888, |
||
1045 | DRM_FORMAT_ARGB8888, |
||
1046 | DRM_FORMAT_XBGR8888, |
||
1047 | DRM_FORMAT_XRGB8888, |
||
1048 | DRM_FORMAT_YUYV, |
||
1049 | DRM_FORMAT_YVYU, |
||
1050 | DRM_FORMAT_UYVY, |
||
1051 | DRM_FORMAT_VYUY, |
||
1052 | }; |
||
1053 | |||
2342 | Serge | 1054 | int |
3746 | Serge | 1055 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
2342 | Serge | 1056 | { |
1057 | struct intel_plane *intel_plane; |
||
6084 | serge | 1058 | struct intel_plane_state *state; |
2342 | Serge | 1059 | unsigned long possible_crtcs; |
3031 | serge | 1060 | const uint32_t *plane_formats; |
1061 | int num_plane_formats; |
||
2342 | Serge | 1062 | int ret; |
1063 | |||
3031 | serge | 1064 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 1065 | return -ENODEV; |
1066 | |||
4560 | Serge | 1067 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
2342 | Serge | 1068 | if (!intel_plane) |
1069 | return -ENOMEM; |
||
1070 | |||
6084 | serge | 1071 | state = intel_create_plane_state(&intel_plane->base); |
1072 | if (!state) { |
||
1073 | kfree(intel_plane); |
||
1074 | return -ENOMEM; |
||
1075 | } |
||
1076 | intel_plane->base.state = &state->base; |
||
1077 | |||
3031 | serge | 1078 | switch (INTEL_INFO(dev)->gen) { |
1079 | case 5: |
||
1080 | case 6: |
||
3243 | Serge | 1081 | intel_plane->can_scale = true; |
3031 | serge | 1082 | intel_plane->max_downscale = 16; |
1083 | intel_plane->update_plane = ilk_update_plane; |
||
1084 | intel_plane->disable_plane = ilk_disable_plane; |
||
1085 | |||
6084 | serge | 1086 | if (IS_GEN6(dev)) { |
3031 | serge | 1087 | plane_formats = snb_plane_formats; |
1088 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
1089 | } else { |
||
1090 | plane_formats = ilk_plane_formats; |
||
1091 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
1092 | } |
||
1093 | break; |
||
1094 | |||
1095 | case 7: |
||
4560 | Serge | 1096 | case 8: |
4104 | Serge | 1097 | if (IS_IVYBRIDGE(dev)) { |
1098 | intel_plane->can_scale = true; |
||
1099 | intel_plane->max_downscale = 2; |
||
1100 | } else { |
||
3243 | Serge | 1101 | intel_plane->can_scale = false; |
4104 | Serge | 1102 | intel_plane->max_downscale = 1; |
1103 | } |
||
3746 | Serge | 1104 | |
1105 | if (IS_VALLEYVIEW(dev)) { |
||
1106 | intel_plane->update_plane = vlv_update_plane; |
||
1107 | intel_plane->disable_plane = vlv_disable_plane; |
||
1108 | |||
1109 | plane_formats = vlv_plane_formats; |
||
1110 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
||
1111 | } else { |
||
6084 | serge | 1112 | intel_plane->update_plane = ivb_update_plane; |
1113 | intel_plane->disable_plane = ivb_disable_plane; |
||
3031 | serge | 1114 | |
6084 | serge | 1115 | plane_formats = snb_plane_formats; |
1116 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
3746 | Serge | 1117 | } |
3031 | serge | 1118 | break; |
5354 | serge | 1119 | case 9: |
6084 | serge | 1120 | intel_plane->can_scale = true; |
5354 | serge | 1121 | intel_plane->update_plane = skl_update_plane; |
1122 | intel_plane->disable_plane = skl_disable_plane; |
||
6084 | serge | 1123 | state->scaler_id = -1; |
3031 | serge | 1124 | |
5354 | serge | 1125 | plane_formats = skl_plane_formats; |
1126 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); |
||
1127 | break; |
||
3031 | serge | 1128 | default: |
1129 | kfree(intel_plane); |
||
1130 | return -ENODEV; |
||
2342 | Serge | 1131 | } |
1132 | |||
1133 | intel_plane->pipe = pipe; |
||
3746 | Serge | 1134 | intel_plane->plane = plane; |
6084 | serge | 1135 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
1136 | intel_plane->check_plane = intel_check_sprite_plane; |
||
1137 | intel_plane->commit_plane = intel_commit_sprite_plane; |
||
2342 | Serge | 1138 | possible_crtcs = (1 << pipe); |
5354 | serge | 1139 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
6084 | serge | 1140 | &intel_plane_funcs, |
1141 | plane_formats, num_plane_formats, |
||
5354 | serge | 1142 | DRM_PLANE_TYPE_OVERLAY); |
1143 | if (ret) { |
||
2342 | Serge | 1144 | kfree(intel_plane); |
5354 | serge | 1145 | goto out; |
1146 | } |
||
2342 | Serge | 1147 | |
6084 | serge | 1148 | intel_create_rotation_property(dev, intel_plane); |
5354 | serge | 1149 | |
6084 | serge | 1150 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
5354 | serge | 1151 | |
6084 | serge | 1152 | out: |
2342 | Serge | 1153 | return ret; |
1154 | }><>>><>><>><>><>>>>>>>>><>><>>>>>><>><>><>><>>>->><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>>=>=> |