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Rev | Author | Line No. | Line |
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2342 | Serge | 1 | /* |
2 | * Copyright © 2011 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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21 | * SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Jesse Barnes |
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25 | * |
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26 | * New plane/sprite handling. |
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27 | * |
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28 | * The older chips had a separate interface for programming plane related |
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29 | * registers; newer ones are much simpler and we can use the new DRM plane |
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30 | * support. |
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31 | */ |
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3031 | serge | 32 | #include |
33 | #include |
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34 | #include |
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4104 | Serge | 35 | #include |
6084 | serge | 36 | #include |
37 | #include |
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2342 | Serge | 38 | #include "intel_drv.h" |
3031 | serge | 39 | #include |
2342 | Serge | 40 | #include "i915_drv.h" |
41 | |||
5354 | serge | 42 | static bool |
43 | format_is_yuv(uint32_t format) |
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44 | { |
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45 | switch (format) { |
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46 | case DRM_FORMAT_YUYV: |
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47 | case DRM_FORMAT_UYVY: |
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48 | case DRM_FORMAT_VYUY: |
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49 | case DRM_FORMAT_YVYU: |
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50 | return true; |
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51 | default: |
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52 | return false; |
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53 | } |
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54 | } |
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55 | |||
6084 | serge | 56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) |
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5060 | serge | 58 | { |
59 | /* paranoia */ |
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6084 | serge | 60 | if (!adjusted_mode->crtc_htotal) |
5060 | serge | 61 | return 1; |
62 | |||
6084 | serge | 63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); |
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5060 | serge | 65 | } |
66 | |||
5354 | serge | 67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers |
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69 | * @crtc: the crtc of which the registers are going to be updated |
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70 | * @start_vbl_count: vblank counter return pointer used for error checking |
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71 | * |
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72 | * Mark the start of an update to pipe registers that should be updated |
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73 | * atomically regarding vblank. If the next vblank will happens within |
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74 | * the next 100 us, this function waits until the vblank passes. |
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75 | * |
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76 | * After a successful call to this function, interrupts will be disabled |
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77 | * until a subsequent call to intel_pipe_update_end(). That is done to |
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78 | * avoid random delays. The value written to @start_vbl_count should be |
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79 | * supplied to intel_pipe_update_end() for error checking. |
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80 | */ |
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6084 | serge | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
5060 | serge | 82 | { |
6084 | serge | 83 | ENTER(); |
5060 | serge | 84 | struct drm_device *dev = crtc->base.dev; |
6084 | serge | 85 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
5060 | serge | 86 | enum pipe pipe = crtc->pipe; |
87 | long timeout = msecs_to_jiffies_timeout(1); |
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88 | int scanline, min, max, vblank_start; |
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6084 | serge | 89 | #if 0 |
90 | // wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
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91 | // DEFINE_WAIT(wait); |
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5060 | serge | 92 | |
6084 | serge | 93 | vblank_start = adjusted_mode->crtc_vblank_start; |
94 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
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5060 | serge | 95 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
96 | |||
97 | /* FIXME needs to be calibrated sensibly */ |
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6084 | serge | 98 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
5060 | serge | 99 | max = vblank_start - 1; |
100 | |||
101 | if (min <= 0 || max <= 0) |
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6084 | serge | 102 | return; |
5060 | serge | 103 | |
104 | // if (WARN_ON(drm_vblank_get(dev, pipe))) |
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105 | // return false; |
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106 | |||
6084 | serge | 107 | crtc->debug.min_vbl = min; |
108 | crtc->debug.max_vbl = max; |
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109 | trace_i915_pipe_update_start(crtc); |
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5060 | serge | 110 | |
111 | for (;;) { |
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112 | /* |
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113 | * prepare_to_wait() has a memory barrier, which guarantees |
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114 | * other CPUs can see the task state update by the time we |
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115 | * read the scanline. |
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116 | */ |
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5354 | serge | 117 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
5060 | serge | 118 | |
119 | scanline = intel_get_crtc_scanline(crtc); |
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120 | if (scanline < min || scanline > max) |
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121 | break; |
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122 | |||
123 | if (timeout <= 0) { |
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124 | DRM_ERROR("Potential atomic update failure on pipe %c\n", |
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125 | pipe_name(crtc->pipe)); |
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126 | break; |
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127 | } |
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128 | |||
129 | // local_irq_enable(); |
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130 | |||
131 | schedule_timeout(timeout); |
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132 | timeout = 0; |
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133 | // local_irq_disable(); |
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134 | } |
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135 | |||
5354 | serge | 136 | finish_wait(wq, &wait); |
6084 | serge | 137 | #endif |
5060 | serge | 138 | |
6084 | serge | 139 | crtc->debug.scanline_start = scanline; |
140 | crtc->debug.start_vbl_time = ktime_get(); |
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141 | crtc->debug.start_vbl_count = |
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142 | dev->driver->get_vblank_counter(dev, pipe); |
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5060 | serge | 143 | |
6084 | serge | 144 | trace_i915_pipe_update_vblank_evaded(crtc); |
5060 | serge | 145 | } |
146 | |||
5354 | serge | 147 | /** |
148 | * intel_pipe_update_end() - end update of a set of display registers |
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149 | * @crtc: the crtc of which the registers were updated |
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150 | * @start_vbl_count: start vblank counter (used for error checking) |
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151 | * |
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152 | * Mark the end of an update started with intel_pipe_update_start(). This |
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153 | * re-enables interrupts and verifies the update was actually completed |
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154 | * before a vblank using the value of @start_vbl_count. |
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155 | */ |
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6084 | serge | 156 | void intel_pipe_update_end(struct intel_crtc *crtc) |
5060 | serge | 157 | { |
158 | struct drm_device *dev = crtc->base.dev; |
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159 | enum pipe pipe = crtc->pipe; |
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6084 | serge | 160 | int scanline_end = intel_get_crtc_scanline(crtc); |
5060 | serge | 161 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
6084 | serge | 162 | ktime_t end_vbl_time = ktime_get(); |
5060 | serge | 163 | |
6084 | serge | 164 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
5060 | serge | 165 | |
166 | // local_irq_enable(); |
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167 | |||
6084 | serge | 168 | if (crtc->debug.start_vbl_count && |
169 | crtc->debug.start_vbl_count != end_vbl_count) { |
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170 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", |
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171 | pipe_name(pipe), crtc->debug.start_vbl_count, |
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172 | end_vbl_count, |
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173 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), |
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174 | crtc->debug.min_vbl, crtc->debug.max_vbl, |
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175 | crtc->debug.scanline_start, scanline_end); |
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176 | } |
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5060 | serge | 177 | } |
178 | |||
2342 | Serge | 179 | static void |
5354 | serge | 180 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, |
181 | struct drm_framebuffer *fb, |
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6084 | serge | 182 | int crtc_x, int crtc_y, |
5354 | serge | 183 | unsigned int crtc_w, unsigned int crtc_h, |
184 | uint32_t x, uint32_t y, |
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185 | uint32_t src_w, uint32_t src_h) |
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186 | { |
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187 | struct drm_device *dev = drm_plane->dev; |
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188 | struct drm_i915_private *dev_priv = dev->dev_private; |
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189 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
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6084 | serge | 190 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
5354 | serge | 191 | const int pipe = intel_plane->pipe; |
192 | const int plane = intel_plane->plane + 1; |
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6084 | serge | 193 | u32 plane_ctl, stride_div, stride; |
5354 | serge | 194 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 195 | const struct drm_intel_sprite_colorkey *key = |
196 | &to_intel_plane_state(drm_plane->state)->ckey; |
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197 | unsigned long surf_addr; |
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198 | u32 tile_height, plane_offset, plane_size; |
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199 | unsigned int rotation; |
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200 | int x_offset, y_offset; |
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201 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
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202 | int scaler_id; |
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5354 | serge | 203 | |
6084 | serge | 204 | plane_ctl = PLANE_CTL_ENABLE | |
205 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
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206 | PLANE_CTL_PIPE_CSC_ENABLE; |
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5354 | serge | 207 | |
6084 | serge | 208 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
209 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
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5354 | serge | 210 | |
6084 | serge | 211 | rotation = drm_plane->state->rotation; |
212 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
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5354 | serge | 213 | |
214 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, |
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215 | pixel_size, true, |
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216 | src_w != crtc_w || src_h != crtc_h); |
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217 | |||
6084 | serge | 218 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
219 | fb->pixel_format); |
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220 | |||
221 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
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222 | |||
5354 | serge | 223 | /* Sizes are 0 based */ |
224 | src_w--; |
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225 | src_h--; |
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226 | crtc_w--; |
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227 | crtc_h--; |
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228 | |||
6084 | serge | 229 | if (key->flags) { |
230 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); |
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231 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); |
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232 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); |
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233 | } |
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5354 | serge | 234 | |
6084 | serge | 235 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
236 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; |
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237 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
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238 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; |
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5354 | serge | 239 | |
6084 | serge | 240 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
5354 | serge | 241 | |
6084 | serge | 242 | if (intel_rotation_90_or_270(rotation)) { |
243 | /* stride: Surface height in tiles */ |
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244 | tile_height = intel_tile_height(dev, fb->pixel_format, |
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245 | fb->modifier[0], 0); |
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246 | stride = DIV_ROUND_UP(fb->height, tile_height); |
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247 | plane_size = (src_w << 16) | src_h; |
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248 | x_offset = stride * tile_height - y - (src_h + 1); |
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249 | y_offset = x; |
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250 | } else { |
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251 | stride = fb->pitches[0] / stride_div; |
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252 | plane_size = (src_h << 16) | src_w; |
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253 | x_offset = x; |
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254 | y_offset = y; |
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255 | } |
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256 | plane_offset = y_offset << 16 | x_offset; |
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5354 | serge | 257 | |
6084 | serge | 258 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); |
259 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); |
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260 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
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5354 | serge | 261 | |
6084 | serge | 262 | /* program plane scaler */ |
263 | if (scaler_id >= 0) { |
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264 | uint32_t ps_ctrl = 0; |
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5354 | serge | 265 | |
6084 | serge | 266 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, |
267 | PS_PLANE_SEL(plane)); |
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268 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | |
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269 | crtc_state->scaler_state.scalers[scaler_id].mode; |
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270 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
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271 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
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272 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); |
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273 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), |
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274 | ((crtc_w + 1) << 16)|(crtc_h + 1)); |
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5354 | serge | 275 | |
6084 | serge | 276 | I915_WRITE(PLANE_POS(pipe, plane), 0); |
277 | } else { |
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278 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
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279 | } |
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280 | |||
5354 | serge | 281 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
6084 | serge | 282 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
283 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 284 | } |
285 | |||
286 | static void |
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6084 | serge | 287 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
5354 | serge | 288 | { |
6084 | serge | 289 | struct drm_device *dev = dplane->dev; |
5354 | serge | 290 | struct drm_i915_private *dev_priv = dev->dev_private; |
6084 | serge | 291 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
5354 | serge | 292 | const int pipe = intel_plane->pipe; |
6084 | serge | 293 | const int plane = intel_plane->plane + 1; |
5354 | serge | 294 | |
6084 | serge | 295 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
5354 | serge | 296 | |
6084 | serge | 297 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
298 | POSTING_READ(PLANE_SURF(pipe, plane)); |
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5354 | serge | 299 | |
6084 | serge | 300 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
5354 | serge | 301 | } |
302 | |||
303 | static void |
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304 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) |
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305 | { |
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306 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; |
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307 | int plane = intel_plane->plane; |
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308 | |||
309 | /* Seems RGB data bypasses the CSC always */ |
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310 | if (!format_is_yuv(format)) |
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311 | return; |
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312 | |||
313 | /* |
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314 | * BT.601 limited range YCbCr -> full range RGB |
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315 | * |
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316 | * |r| | 6537 4769 0| |cr | |
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317 | * |g| = |-3330 4769 -1605| x |y-64| |
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318 | * |b| | 0 4769 8263| |cb | |
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319 | * |
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320 | * Cb and Cr apparently come in as signed already, so no |
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321 | * need for any offset. For Y we need to remove the offset. |
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322 | */ |
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323 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); |
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324 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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325 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
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326 | |||
327 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); |
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328 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); |
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329 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); |
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330 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); |
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331 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); |
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332 | |||
333 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); |
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334 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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335 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
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336 | |||
337 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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338 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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339 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
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340 | } |
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341 | |||
342 | static void |
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4104 | Serge | 343 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
344 | struct drm_framebuffer *fb, |
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6084 | serge | 345 | int crtc_x, int crtc_y, |
3746 | Serge | 346 | unsigned int crtc_w, unsigned int crtc_h, |
347 | uint32_t x, uint32_t y, |
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348 | uint32_t src_w, uint32_t src_h) |
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349 | { |
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350 | struct drm_device *dev = dplane->dev; |
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351 | struct drm_i915_private *dev_priv = dev->dev_private; |
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352 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
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6084 | serge | 353 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3746 | Serge | 354 | int pipe = intel_plane->pipe; |
355 | int plane = intel_plane->plane; |
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356 | u32 sprctl; |
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357 | unsigned long sprsurf_offset, linear_offset; |
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358 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
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6084 | serge | 359 | const struct drm_intel_sprite_colorkey *key = |
360 | &to_intel_plane_state(dplane->state)->ckey; |
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3746 | Serge | 361 | |
6084 | serge | 362 | sprctl = SP_ENABLE; |
3746 | Serge | 363 | |
364 | switch (fb->pixel_format) { |
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365 | case DRM_FORMAT_YUYV: |
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366 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
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367 | break; |
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368 | case DRM_FORMAT_YVYU: |
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369 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
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370 | break; |
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371 | case DRM_FORMAT_UYVY: |
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372 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
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373 | break; |
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374 | case DRM_FORMAT_VYUY: |
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375 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
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376 | break; |
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377 | case DRM_FORMAT_RGB565: |
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378 | sprctl |= SP_FORMAT_BGR565; |
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379 | break; |
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380 | case DRM_FORMAT_XRGB8888: |
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381 | sprctl |= SP_FORMAT_BGRX8888; |
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382 | break; |
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383 | case DRM_FORMAT_ARGB8888: |
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384 | sprctl |= SP_FORMAT_BGRA8888; |
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385 | break; |
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386 | case DRM_FORMAT_XBGR2101010: |
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387 | sprctl |= SP_FORMAT_RGBX1010102; |
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388 | break; |
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389 | case DRM_FORMAT_ABGR2101010: |
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390 | sprctl |= SP_FORMAT_RGBA1010102; |
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391 | break; |
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392 | case DRM_FORMAT_XBGR8888: |
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393 | sprctl |= SP_FORMAT_RGBX8888; |
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394 | break; |
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395 | case DRM_FORMAT_ABGR8888: |
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396 | sprctl |= SP_FORMAT_RGBA8888; |
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397 | break; |
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398 | default: |
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399 | /* |
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400 | * If we get here one of the upper layers failed to filter |
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401 | * out the unsupported plane formats |
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402 | */ |
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403 | BUG(); |
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404 | break; |
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405 | } |
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406 | |||
4560 | Serge | 407 | /* |
408 | * Enable gamma to match primary/cursor plane behaviour. |
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409 | * FIXME should be user controllable via propertiesa. |
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410 | */ |
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411 | sprctl |= SP_GAMMA_ENABLE; |
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412 | |||
3746 | Serge | 413 | if (obj->tiling_mode != I915_TILING_NONE) |
414 | sprctl |= SP_TILED; |
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415 | |||
416 | /* Sizes are 0 based */ |
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417 | src_w--; |
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418 | src_h--; |
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419 | crtc_w--; |
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420 | crtc_h--; |
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421 | |||
422 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
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6084 | serge | 423 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, |
424 | &x, &y, |
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3746 | Serge | 425 | obj->tiling_mode, |
426 | pixel_size, |
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427 | fb->pitches[0]); |
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428 | linear_offset -= sprsurf_offset; |
||
429 | |||
6084 | serge | 430 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 431 | sprctl |= SP_ROTATE_180; |
432 | |||
433 | x += src_w; |
||
434 | y += src_h; |
||
435 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
436 | } |
||
437 | |||
6084 | serge | 438 | if (key->flags) { |
439 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
||
440 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
||
441 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
||
442 | } |
||
5060 | serge | 443 | |
6084 | serge | 444 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
445 | sprctl |= SP_SOURCE_KEY; |
||
5060 | serge | 446 | |
5354 | serge | 447 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
448 | chv_update_csc(intel_plane, fb->pixel_format); |
||
449 | |||
5060 | serge | 450 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
451 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
||
452 | |||
3746 | Serge | 453 | if (obj->tiling_mode != I915_TILING_NONE) |
454 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
||
455 | else |
||
456 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
||
457 | |||
5354 | serge | 458 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
459 | |||
3746 | Serge | 460 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
461 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
||
4560 | Serge | 462 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
6084 | serge | 463 | sprsurf_offset); |
464 | POSTING_READ(SPSURF(pipe, plane)); |
||
3746 | Serge | 465 | } |
466 | |||
467 | static void |
||
4104 | Serge | 468 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
3746 | Serge | 469 | { |
470 | struct drm_device *dev = dplane->dev; |
||
471 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
472 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
||
473 | int pipe = intel_plane->pipe; |
||
474 | int plane = intel_plane->plane; |
||
475 | |||
6084 | serge | 476 | I915_WRITE(SPCNTR(pipe, plane), 0); |
5060 | serge | 477 | |
4560 | Serge | 478 | I915_WRITE(SPSURF(pipe, plane), 0); |
6084 | serge | 479 | POSTING_READ(SPSURF(pipe, plane)); |
3746 | Serge | 480 | } |
481 | |||
482 | static void |
||
4104 | Serge | 483 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
484 | struct drm_framebuffer *fb, |
||
6084 | serge | 485 | int crtc_x, int crtc_y, |
2342 | Serge | 486 | unsigned int crtc_w, unsigned int crtc_h, |
487 | uint32_t x, uint32_t y, |
||
488 | uint32_t src_w, uint32_t src_h) |
||
489 | { |
||
490 | struct drm_device *dev = plane->dev; |
||
491 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
492 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 493 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
494 | enum pipe pipe = intel_plane->pipe; |
||
2342 | Serge | 495 | u32 sprctl, sprscale = 0; |
3243 | Serge | 496 | unsigned long sprsurf_offset, linear_offset; |
497 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
||
6084 | serge | 498 | const struct drm_intel_sprite_colorkey *key = |
499 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 500 | |
6084 | serge | 501 | sprctl = SPRITE_ENABLE; |
2342 | Serge | 502 | |
503 | switch (fb->pixel_format) { |
||
504 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 505 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
2342 | Serge | 506 | break; |
507 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 508 | sprctl |= SPRITE_FORMAT_RGBX888; |
2342 | Serge | 509 | break; |
510 | case DRM_FORMAT_YUYV: |
||
511 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
||
512 | break; |
||
513 | case DRM_FORMAT_YVYU: |
||
514 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
||
515 | break; |
||
516 | case DRM_FORMAT_UYVY: |
||
517 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
||
518 | break; |
||
519 | case DRM_FORMAT_VYUY: |
||
520 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
||
521 | break; |
||
522 | default: |
||
3243 | Serge | 523 | BUG(); |
2342 | Serge | 524 | } |
525 | |||
4560 | Serge | 526 | /* |
527 | * Enable gamma to match primary/cursor plane behaviour. |
||
528 | * FIXME should be user controllable via propertiesa. |
||
529 | */ |
||
530 | sprctl |= SPRITE_GAMMA_ENABLE; |
||
531 | |||
2342 | Serge | 532 | if (obj->tiling_mode != I915_TILING_NONE) |
533 | sprctl |= SPRITE_TILED; |
||
534 | |||
4560 | Serge | 535 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
4104 | Serge | 536 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
537 | else |
||
6084 | serge | 538 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
4104 | Serge | 539 | |
4560 | Serge | 540 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3480 | Serge | 541 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
542 | |||
5060 | serge | 543 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
544 | true, |
||
4104 | Serge | 545 | src_w != crtc_w || src_h != crtc_h); |
546 | |||
2342 | Serge | 547 | /* Sizes are 0 based */ |
548 | src_w--; |
||
549 | src_h--; |
||
550 | crtc_w--; |
||
551 | crtc_h--; |
||
552 | |||
4560 | Serge | 553 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 554 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
555 | |||
3243 | Serge | 556 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
557 | sprsurf_offset = |
||
6084 | serge | 558 | intel_gen4_compute_page_offset(dev_priv, |
559 | &x, &y, obj->tiling_mode, |
||
560 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 561 | linear_offset -= sprsurf_offset; |
562 | |||
6084 | serge | 563 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 564 | sprctl |= SPRITE_ROTATE_180; |
565 | |||
566 | /* HSW and BDW does this automagically in hardware */ |
||
567 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
||
568 | x += src_w; |
||
569 | y += src_h; |
||
570 | linear_offset += src_h * fb->pitches[0] + |
||
571 | src_w * pixel_size; |
||
572 | } |
||
573 | } |
||
574 | |||
6084 | serge | 575 | if (key->flags) { |
576 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); |
||
577 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); |
||
578 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); |
||
579 | } |
||
5060 | serge | 580 | |
6084 | serge | 581 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
582 | sprctl |= SPRITE_DEST_KEY; |
||
583 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
584 | sprctl |= SPRITE_SOURCE_KEY; |
||
5060 | serge | 585 | |
586 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
||
587 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
||
588 | |||
3243 | Serge | 589 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
590 | * register */ |
||
4560 | Serge | 591 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
3243 | Serge | 592 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
593 | else if (obj->tiling_mode != I915_TILING_NONE) |
||
2342 | Serge | 594 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 595 | else |
596 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
||
2342 | Serge | 597 | |
598 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
3243 | Serge | 599 | if (intel_plane->can_scale) |
6084 | serge | 600 | I915_WRITE(SPRSCALE(pipe), sprscale); |
2342 | Serge | 601 | I915_WRITE(SPRCTL(pipe), sprctl); |
4560 | Serge | 602 | I915_WRITE(SPRSURF(pipe), |
6084 | serge | 603 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
604 | POSTING_READ(SPRSURF(pipe)); |
||
2342 | Serge | 605 | } |
606 | |||
607 | static void |
||
4104 | Serge | 608 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 609 | { |
610 | struct drm_device *dev = plane->dev; |
||
611 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
612 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
613 | int pipe = intel_plane->pipe; |
||
614 | |||
6084 | serge | 615 | I915_WRITE(SPRCTL(pipe), 0); |
2342 | Serge | 616 | /* Can't leave the scaler enabled... */ |
3243 | Serge | 617 | if (intel_plane->can_scale) |
6084 | serge | 618 | I915_WRITE(SPRSCALE(pipe), 0); |
619 | |||
4560 | Serge | 620 | I915_WRITE(SPRSURF(pipe), 0); |
6084 | serge | 621 | POSTING_READ(SPRSURF(pipe)); |
2342 | Serge | 622 | } |
623 | |||
624 | static void |
||
4104 | Serge | 625 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
626 | struct drm_framebuffer *fb, |
||
6084 | serge | 627 | int crtc_x, int crtc_y, |
2342 | Serge | 628 | unsigned int crtc_w, unsigned int crtc_h, |
629 | uint32_t x, uint32_t y, |
||
630 | uint32_t src_w, uint32_t src_h) |
||
631 | { |
||
632 | struct drm_device *dev = plane->dev; |
||
633 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
634 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
6084 | serge | 635 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3243 | Serge | 636 | int pipe = intel_plane->pipe; |
637 | unsigned long dvssurf_offset, linear_offset; |
||
3031 | serge | 638 | u32 dvscntr, dvsscale; |
3243 | Serge | 639 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
6084 | serge | 640 | const struct drm_intel_sprite_colorkey *key = |
641 | &to_intel_plane_state(plane->state)->ckey; |
||
2342 | Serge | 642 | |
6084 | serge | 643 | dvscntr = DVS_ENABLE; |
2342 | Serge | 644 | |
645 | switch (fb->pixel_format) { |
||
646 | case DRM_FORMAT_XBGR8888: |
||
3031 | serge | 647 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
2342 | Serge | 648 | break; |
649 | case DRM_FORMAT_XRGB8888: |
||
3031 | serge | 650 | dvscntr |= DVS_FORMAT_RGBX888; |
2342 | Serge | 651 | break; |
652 | case DRM_FORMAT_YUYV: |
||
653 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
||
654 | break; |
||
655 | case DRM_FORMAT_YVYU: |
||
656 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
||
657 | break; |
||
658 | case DRM_FORMAT_UYVY: |
||
659 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
||
660 | break; |
||
661 | case DRM_FORMAT_VYUY: |
||
662 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
||
663 | break; |
||
664 | default: |
||
3243 | Serge | 665 | BUG(); |
2342 | Serge | 666 | } |
667 | |||
4560 | Serge | 668 | /* |
669 | * Enable gamma to match primary/cursor plane behaviour. |
||
670 | * FIXME should be user controllable via propertiesa. |
||
671 | */ |
||
672 | dvscntr |= DVS_GAMMA_ENABLE; |
||
673 | |||
2342 | Serge | 674 | if (obj->tiling_mode != I915_TILING_NONE) |
675 | dvscntr |= DVS_TILED; |
||
676 | |||
3031 | serge | 677 | if (IS_GEN6(dev)) |
678 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
||
2342 | Serge | 679 | |
5060 | serge | 680 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
681 | pixel_size, true, |
||
4104 | Serge | 682 | src_w != crtc_w || src_h != crtc_h); |
683 | |||
2342 | Serge | 684 | /* Sizes are 0 based */ |
685 | src_w--; |
||
686 | src_h--; |
||
687 | crtc_w--; |
||
688 | crtc_h--; |
||
689 | |||
3031 | serge | 690 | dvsscale = 0; |
4560 | Serge | 691 | if (crtc_w != src_w || crtc_h != src_h) |
2342 | Serge | 692 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
693 | |||
3243 | Serge | 694 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
695 | dvssurf_offset = |
||
6084 | serge | 696 | intel_gen4_compute_page_offset(dev_priv, |
697 | &x, &y, obj->tiling_mode, |
||
698 | pixel_size, fb->pitches[0]); |
||
3243 | Serge | 699 | linear_offset -= dvssurf_offset; |
700 | |||
6084 | serge | 701 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
5354 | serge | 702 | dvscntr |= DVS_ROTATE_180; |
703 | |||
704 | x += src_w; |
||
705 | y += src_h; |
||
706 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
||
707 | } |
||
708 | |||
6084 | serge | 709 | if (key->flags) { |
710 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); |
||
711 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); |
||
712 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); |
||
713 | } |
||
5060 | serge | 714 | |
6084 | serge | 715 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
716 | dvscntr |= DVS_DEST_KEY; |
||
717 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
||
718 | dvscntr |= DVS_SOURCE_KEY; |
||
5060 | serge | 719 | |
720 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
||
721 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
||
722 | |||
3243 | Serge | 723 | if (obj->tiling_mode != I915_TILING_NONE) |
2342 | Serge | 724 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
3243 | Serge | 725 | else |
726 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
||
2342 | Serge | 727 | |
728 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
||
729 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
||
730 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
||
4560 | Serge | 731 | I915_WRITE(DVSSURF(pipe), |
6084 | serge | 732 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
733 | POSTING_READ(DVSSURF(pipe)); |
||
2342 | Serge | 734 | } |
735 | |||
736 | static void |
||
4104 | Serge | 737 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
2342 | Serge | 738 | { |
739 | struct drm_device *dev = plane->dev; |
||
740 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
741 | struct intel_plane *intel_plane = to_intel_plane(plane); |
||
742 | int pipe = intel_plane->pipe; |
||
743 | |||
6084 | serge | 744 | I915_WRITE(DVSCNTR(pipe), 0); |
2342 | Serge | 745 | /* Disable the scaler */ |
746 | I915_WRITE(DVSSCALE(pipe), 0); |
||
6084 | serge | 747 | |
4560 | Serge | 748 | I915_WRITE(DVSSURF(pipe), 0); |
6084 | serge | 749 | POSTING_READ(DVSSURF(pipe)); |
2342 | Serge | 750 | } |
751 | |||
752 | static int |
||
5354 | serge | 753 | intel_check_sprite_plane(struct drm_plane *plane, |
6084 | serge | 754 | struct intel_crtc_state *crtc_state, |
5354 | serge | 755 | struct intel_plane_state *state) |
2342 | Serge | 756 | { |
6084 | serge | 757 | struct drm_device *dev = plane->dev; |
758 | struct drm_crtc *crtc = state->base.crtc; |
||
759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
2342 | Serge | 760 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 761 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 762 | int crtc_x, crtc_y; |
763 | unsigned int crtc_w, crtc_h; |
||
764 | uint32_t src_x, src_y, src_w, src_h; |
||
765 | struct drm_rect *src = &state->src; |
||
766 | struct drm_rect *dst = &state->dst; |
||
767 | const struct drm_rect *clip = &state->clip; |
||
4104 | Serge | 768 | int hscale, vscale; |
769 | int max_scale, min_scale; |
||
6084 | serge | 770 | bool can_scale; |
771 | int pixel_size; |
||
2342 | Serge | 772 | |
6084 | serge | 773 | if (!fb) { |
774 | state->visible = false; |
||
775 | return 0; |
||
776 | } |
||
777 | |||
4104 | Serge | 778 | /* Don't modify another pipe's plane */ |
779 | if (intel_plane->pipe != intel_crtc->pipe) { |
||
780 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
||
2342 | Serge | 781 | return -EINVAL; |
4104 | Serge | 782 | } |
2342 | Serge | 783 | |
4104 | Serge | 784 | /* FIXME check all gen limits */ |
785 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
||
786 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
||
2342 | Serge | 787 | return -EINVAL; |
4104 | Serge | 788 | } |
2342 | Serge | 789 | |
6084 | serge | 790 | /* setup can_scale, min_scale, max_scale */ |
791 | if (INTEL_INFO(dev)->gen >= 9) { |
||
792 | /* use scaler when colorkey is not required */ |
||
793 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
||
794 | can_scale = 1; |
||
795 | min_scale = 1; |
||
796 | max_scale = skl_max_scale(intel_crtc, crtc_state); |
||
797 | } else { |
||
798 | can_scale = 0; |
||
799 | min_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
800 | max_scale = DRM_PLANE_HELPER_NO_SCALING; |
||
801 | } |
||
802 | } else { |
||
803 | can_scale = intel_plane->can_scale; |
||
804 | max_scale = intel_plane->max_downscale << 16; |
||
805 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
||
3243 | Serge | 806 | } |
807 | |||
2342 | Serge | 808 | /* |
4104 | Serge | 809 | * FIXME the following code does a bunch of fuzzy adjustments to the |
810 | * coordinates and sizes. We probably need some way to decide whether |
||
811 | * more strict checking should be done instead. |
||
2342 | Serge | 812 | */ |
5354 | serge | 813 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
6084 | serge | 814 | state->base.rotation); |
5354 | serge | 815 | |
816 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
||
4104 | Serge | 817 | BUG_ON(hscale < 0); |
818 | |||
5354 | serge | 819 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
4104 | Serge | 820 | BUG_ON(vscale < 0); |
821 | |||
6084 | serge | 822 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
4104 | Serge | 823 | |
5354 | serge | 824 | crtc_x = dst->x1; |
825 | crtc_y = dst->y1; |
||
826 | crtc_w = drm_rect_width(dst); |
||
827 | crtc_h = drm_rect_height(dst); |
||
4104 | Serge | 828 | |
5354 | serge | 829 | if (state->visible) { |
4104 | Serge | 830 | /* check again in case clipping clamped the results */ |
5354 | serge | 831 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
4104 | Serge | 832 | if (hscale < 0) { |
833 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
||
5354 | serge | 834 | drm_rect_debug_print(src, true); |
835 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 836 | |
837 | return hscale; |
||
6084 | serge | 838 | } |
2342 | Serge | 839 | |
5354 | serge | 840 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
4104 | Serge | 841 | if (vscale < 0) { |
842 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
||
5354 | serge | 843 | drm_rect_debug_print(src, true); |
844 | drm_rect_debug_print(dst, false); |
||
4104 | Serge | 845 | |
846 | return vscale; |
||
6084 | serge | 847 | } |
2342 | Serge | 848 | |
4104 | Serge | 849 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
5354 | serge | 850 | drm_rect_adjust_size(src, |
851 | drm_rect_width(dst) * hscale - drm_rect_width(src), |
||
852 | drm_rect_height(dst) * vscale - drm_rect_height(src)); |
||
2342 | Serge | 853 | |
5354 | serge | 854 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
6084 | serge | 855 | state->base.rotation); |
5354 | serge | 856 | |
4104 | Serge | 857 | /* sanity check to make sure the src viewport wasn't enlarged */ |
6084 | serge | 858 | WARN_ON(src->x1 < (int) state->base.src_x || |
859 | src->y1 < (int) state->base.src_y || |
||
860 | src->x2 > (int) state->base.src_x + state->base.src_w || |
||
861 | src->y2 > (int) state->base.src_y + state->base.src_h); |
||
4104 | Serge | 862 | |
6084 | serge | 863 | /* |
4104 | Serge | 864 | * Hardware doesn't handle subpixel coordinates. |
865 | * Adjust to (macro)pixel boundary, but be careful not to |
||
866 | * increase the source viewport size, because that could |
||
867 | * push the downscaling factor out of bounds. |
||
6084 | serge | 868 | */ |
5354 | serge | 869 | src_x = src->x1 >> 16; |
870 | src_w = drm_rect_width(src) >> 16; |
||
871 | src_y = src->y1 >> 16; |
||
872 | src_h = drm_rect_height(src) >> 16; |
||
3243 | Serge | 873 | |
4104 | Serge | 874 | if (format_is_yuv(fb->pixel_format)) { |
875 | src_x &= ~1; |
||
876 | src_w &= ~1; |
||
877 | |||
6084 | serge | 878 | /* |
4104 | Serge | 879 | * Must keep src and dst the |
880 | * same if we can't scale. |
||
6084 | serge | 881 | */ |
882 | if (!can_scale) |
||
4104 | Serge | 883 | crtc_w &= ~1; |
884 | |||
885 | if (crtc_w == 0) |
||
5354 | serge | 886 | state->visible = false; |
4104 | Serge | 887 | } |
888 | } |
||
889 | |||
890 | /* Check size restrictions when scaling */ |
||
5354 | serge | 891 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
4104 | Serge | 892 | unsigned int width_bytes; |
893 | |||
6084 | serge | 894 | WARN_ON(!can_scale); |
4104 | Serge | 895 | |
896 | /* FIXME interlacing min height is 6 */ |
||
897 | |||
898 | if (crtc_w < 3 || crtc_h < 3) |
||
5354 | serge | 899 | state->visible = false; |
4104 | Serge | 900 | |
901 | if (src_w < 3 || src_h < 3) |
||
5354 | serge | 902 | state->visible = false; |
4104 | Serge | 903 | |
6084 | serge | 904 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
5354 | serge | 905 | width_bytes = ((src_x * pixel_size) & 63) + |
906 | src_w * pixel_size; |
||
4104 | Serge | 907 | |
6084 | serge | 908 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
909 | width_bytes > 4096 || fb->pitches[0] > 4096)) { |
||
4104 | Serge | 910 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
6084 | serge | 911 | return -EINVAL; |
4104 | Serge | 912 | } |
913 | } |
||
2342 | Serge | 914 | |
5354 | serge | 915 | if (state->visible) { |
6084 | serge | 916 | src->x1 = src_x << 16; |
917 | src->x2 = (src_x + src_w) << 16; |
||
918 | src->y1 = src_y << 16; |
||
919 | src->y2 = (src_y + src_h) << 16; |
||
5354 | serge | 920 | } |
4104 | Serge | 921 | |
5354 | serge | 922 | dst->x1 = crtc_x; |
923 | dst->x2 = crtc_x + crtc_w; |
||
924 | dst->y1 = crtc_y; |
||
925 | dst->y2 = crtc_y + crtc_h; |
||
2342 | Serge | 926 | |
5354 | serge | 927 | return 0; |
928 | } |
||
929 | |||
930 | static void |
||
931 | intel_commit_sprite_plane(struct drm_plane *plane, |
||
932 | struct intel_plane_state *state) |
||
933 | { |
||
6084 | serge | 934 | struct drm_crtc *crtc = state->base.crtc; |
5354 | serge | 935 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6084 | serge | 936 | struct drm_framebuffer *fb = state->base.fb; |
5354 | serge | 937 | |
6084 | serge | 938 | crtc = crtc ? crtc : plane->crtc; |
5354 | serge | 939 | |
6084 | serge | 940 | if (!crtc->state->active) |
941 | return; |
||
2342 | Serge | 942 | |
6084 | serge | 943 | if (state->visible) { |
944 | intel_plane->update_plane(plane, crtc, fb, |
||
945 | state->dst.x1, state->dst.y1, |
||
946 | drm_rect_width(&state->dst), |
||
947 | drm_rect_height(&state->dst), |
||
948 | state->src.x1 >> 16, |
||
949 | state->src.y1 >> 16, |
||
950 | drm_rect_width(&state->src) >> 16, |
||
951 | drm_rect_height(&state->src) >> 16); |
||
952 | } else { |
||
4104 | Serge | 953 | intel_plane->disable_plane(plane, crtc); |
4560 | Serge | 954 | } |
5354 | serge | 955 | } |
2342 | Serge | 956 | |
957 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
||
958 | struct drm_file *file_priv) |
||
959 | { |
||
960 | struct drm_intel_sprite_colorkey *set = data; |
||
961 | struct drm_plane *plane; |
||
6084 | serge | 962 | struct drm_plane_state *plane_state; |
963 | struct drm_atomic_state *state; |
||
964 | struct drm_modeset_acquire_ctx ctx; |
||
2342 | Serge | 965 | int ret = 0; |
966 | |||
967 | /* Make sure we don't try to enable both src & dest simultaneously */ |
||
968 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
||
969 | return -EINVAL; |
||
970 | |||
6084 | serge | 971 | if (IS_VALLEYVIEW(dev) && |
972 | set->flags & I915_SET_COLORKEY_DESTINATION) |
||
973 | return -EINVAL; |
||
2342 | Serge | 974 | |
5060 | serge | 975 | plane = drm_plane_find(dev, set->plane_id); |
6084 | serge | 976 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
977 | return -ENOENT; |
||
2342 | Serge | 978 | |
6084 | serge | 979 | drm_modeset_acquire_init(&ctx, 0); |
2342 | Serge | 980 | |
6084 | serge | 981 | state = drm_atomic_state_alloc(plane->dev); |
982 | if (!state) { |
||
983 | ret = -ENOMEM; |
||
984 | goto out; |
||
985 | } |
||
986 | state->acquire_ctx = &ctx; |
||
2342 | Serge | 987 | |
6084 | serge | 988 | while (1) { |
989 | plane_state = drm_atomic_get_plane_state(state, plane); |
||
990 | ret = PTR_ERR_OR_ZERO(plane_state); |
||
991 | if (!ret) { |
||
992 | to_intel_plane_state(plane_state)->ckey = *set; |
||
993 | ret = drm_atomic_commit(state); |
||
994 | } |
||
2342 | Serge | 995 | |
6084 | serge | 996 | if (ret != -EDEADLK) |
997 | break; |
||
2342 | Serge | 998 | |
6084 | serge | 999 | drm_atomic_state_clear(state); |
1000 | drm_modeset_backoff(&ctx); |
||
2342 | Serge | 1001 | } |
1002 | |||
6084 | serge | 1003 | if (ret) |
1004 | drm_atomic_state_free(state); |
||
2342 | Serge | 1005 | |
6084 | serge | 1006 | out: |
1007 | drm_modeset_drop_locks(&ctx); |
||
1008 | drm_modeset_acquire_fini(&ctx); |
||
2342 | Serge | 1009 | return ret; |
1010 | } |
||
1011 | |||
6084 | serge | 1012 | static const uint32_t ilk_plane_formats[] = { |
3031 | serge | 1013 | DRM_FORMAT_XRGB8888, |
1014 | DRM_FORMAT_YUYV, |
||
1015 | DRM_FORMAT_YVYU, |
||
1016 | DRM_FORMAT_UYVY, |
||
1017 | DRM_FORMAT_VYUY, |
||
1018 | }; |
||
1019 | |||
6084 | serge | 1020 | static const uint32_t snb_plane_formats[] = { |
2342 | Serge | 1021 | DRM_FORMAT_XBGR8888, |
1022 | DRM_FORMAT_XRGB8888, |
||
1023 | DRM_FORMAT_YUYV, |
||
1024 | DRM_FORMAT_YVYU, |
||
1025 | DRM_FORMAT_UYVY, |
||
1026 | DRM_FORMAT_VYUY, |
||
1027 | }; |
||
1028 | |||
6084 | serge | 1029 | static const uint32_t vlv_plane_formats[] = { |
3746 | Serge | 1030 | DRM_FORMAT_RGB565, |
1031 | DRM_FORMAT_ABGR8888, |
||
1032 | DRM_FORMAT_ARGB8888, |
||
1033 | DRM_FORMAT_XBGR8888, |
||
1034 | DRM_FORMAT_XRGB8888, |
||
1035 | DRM_FORMAT_XBGR2101010, |
||
1036 | DRM_FORMAT_ABGR2101010, |
||
1037 | DRM_FORMAT_YUYV, |
||
1038 | DRM_FORMAT_YVYU, |
||
1039 | DRM_FORMAT_UYVY, |
||
1040 | DRM_FORMAT_VYUY, |
||
1041 | }; |
||
1042 | |||
5354 | serge | 1043 | static uint32_t skl_plane_formats[] = { |
1044 | DRM_FORMAT_RGB565, |
||
1045 | DRM_FORMAT_ABGR8888, |
||
1046 | DRM_FORMAT_ARGB8888, |
||
1047 | DRM_FORMAT_XBGR8888, |
||
1048 | DRM_FORMAT_XRGB8888, |
||
1049 | DRM_FORMAT_YUYV, |
||
1050 | DRM_FORMAT_YVYU, |
||
1051 | DRM_FORMAT_UYVY, |
||
1052 | DRM_FORMAT_VYUY, |
||
1053 | }; |
||
1054 | |||
2342 | Serge | 1055 | int |
3746 | Serge | 1056 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
2342 | Serge | 1057 | { |
1058 | struct intel_plane *intel_plane; |
||
6084 | serge | 1059 | struct intel_plane_state *state; |
2342 | Serge | 1060 | unsigned long possible_crtcs; |
3031 | serge | 1061 | const uint32_t *plane_formats; |
1062 | int num_plane_formats; |
||
2342 | Serge | 1063 | int ret; |
1064 | |||
3031 | serge | 1065 | if (INTEL_INFO(dev)->gen < 5) |
2342 | Serge | 1066 | return -ENODEV; |
1067 | |||
4560 | Serge | 1068 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
2342 | Serge | 1069 | if (!intel_plane) |
1070 | return -ENOMEM; |
||
1071 | |||
6084 | serge | 1072 | state = intel_create_plane_state(&intel_plane->base); |
1073 | if (!state) { |
||
1074 | kfree(intel_plane); |
||
1075 | return -ENOMEM; |
||
1076 | } |
||
1077 | intel_plane->base.state = &state->base; |
||
1078 | |||
3031 | serge | 1079 | switch (INTEL_INFO(dev)->gen) { |
1080 | case 5: |
||
1081 | case 6: |
||
3243 | Serge | 1082 | intel_plane->can_scale = true; |
3031 | serge | 1083 | intel_plane->max_downscale = 16; |
1084 | intel_plane->update_plane = ilk_update_plane; |
||
1085 | intel_plane->disable_plane = ilk_disable_plane; |
||
1086 | |||
6084 | serge | 1087 | if (IS_GEN6(dev)) { |
3031 | serge | 1088 | plane_formats = snb_plane_formats; |
1089 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
1090 | } else { |
||
1091 | plane_formats = ilk_plane_formats; |
||
1092 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
||
1093 | } |
||
1094 | break; |
||
1095 | |||
1096 | case 7: |
||
4560 | Serge | 1097 | case 8: |
4104 | Serge | 1098 | if (IS_IVYBRIDGE(dev)) { |
1099 | intel_plane->can_scale = true; |
||
1100 | intel_plane->max_downscale = 2; |
||
1101 | } else { |
||
3243 | Serge | 1102 | intel_plane->can_scale = false; |
4104 | Serge | 1103 | intel_plane->max_downscale = 1; |
1104 | } |
||
3746 | Serge | 1105 | |
1106 | if (IS_VALLEYVIEW(dev)) { |
||
1107 | intel_plane->update_plane = vlv_update_plane; |
||
1108 | intel_plane->disable_plane = vlv_disable_plane; |
||
1109 | |||
1110 | plane_formats = vlv_plane_formats; |
||
1111 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
||
1112 | } else { |
||
6084 | serge | 1113 | intel_plane->update_plane = ivb_update_plane; |
1114 | intel_plane->disable_plane = ivb_disable_plane; |
||
3031 | serge | 1115 | |
6084 | serge | 1116 | plane_formats = snb_plane_formats; |
1117 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
||
3746 | Serge | 1118 | } |
3031 | serge | 1119 | break; |
5354 | serge | 1120 | case 9: |
6084 | serge | 1121 | intel_plane->can_scale = true; |
5354 | serge | 1122 | intel_plane->update_plane = skl_update_plane; |
1123 | intel_plane->disable_plane = skl_disable_plane; |
||
6084 | serge | 1124 | state->scaler_id = -1; |
3031 | serge | 1125 | |
5354 | serge | 1126 | plane_formats = skl_plane_formats; |
1127 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); |
||
1128 | break; |
||
3031 | serge | 1129 | default: |
1130 | kfree(intel_plane); |
||
1131 | return -ENODEV; |
||
2342 | Serge | 1132 | } |
1133 | |||
1134 | intel_plane->pipe = pipe; |
||
3746 | Serge | 1135 | intel_plane->plane = plane; |
6084 | serge | 1136 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
1137 | intel_plane->check_plane = intel_check_sprite_plane; |
||
1138 | intel_plane->commit_plane = intel_commit_sprite_plane; |
||
2342 | Serge | 1139 | possible_crtcs = (1 << pipe); |
5354 | serge | 1140 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
6084 | serge | 1141 | &intel_plane_funcs, |
1142 | plane_formats, num_plane_formats, |
||
5354 | serge | 1143 | DRM_PLANE_TYPE_OVERLAY); |
1144 | if (ret) { |
||
2342 | Serge | 1145 | kfree(intel_plane); |
5354 | serge | 1146 | goto out; |
1147 | } |
||
2342 | Serge | 1148 | |
6084 | serge | 1149 | intel_create_rotation_property(dev, intel_plane); |
5354 | serge | 1150 | |
6084 | serge | 1151 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
5354 | serge | 1152 | |
6084 | serge | 1153 | out: |
2342 | Serge | 1154 | return ret; |
1155 | }><>>><>><>><>><>>>>>>>>><>><>>>>>><>><>><>><>>>->><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>>=>=> |