WebSVN – Kolibri OS – Blame – /drivers/video/drm/i915/intel_sdvo.c

Rev	Author	Line No.	Line
2330	Serge	1	/*
		2	* Copyright 2006 Dave Airlie
		3	* Copyright © 2006-2007 Intel Corporation
		4	* Jesse Barnes
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice (including the next
		14	* paragraph) shall be included in all copies or substantial portions of the
		15	* Software.
		16	*
		17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
		22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		23	* DEALINGS IN THE SOFTWARE.
		24	*
		25	* Authors:
6084	serge	26	* Eric Anholt
2330	Serge	27	*/
		28	#include
		29	#include
3243	Serge	30	#include
3031	serge	31	#include
		32	#include
6084	serge	33	#include
3031	serge	34	#include
		35	#include
2330	Serge	36	#include "intel_drv.h"
3031	serge	37	#include
2330	Serge	38	#include "i915_drv.h"
		39	#include "intel_sdvo_regs.h"
		40
		41	#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 \| SDVO_OUTPUT_TMDS1)
		42	#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 \| SDVO_OUTPUT_RGB1)
		43	#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 \| SDVO_OUTPUT_LVDS1)
3031	serge	44	#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 \| SDVO_OUTPUT_SVID0 \| SDVO_OUTPUT_YPRPB0)
2330	Serge	45
		46	#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK \| SDVO_RGB_MASK \| SDVO_LVDS_MASK \|\
6084	serge	47	SDVO_TV_MASK)
2330	Serge	48
6084	serge	49	#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
		50	#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
		51	#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
2330	Serge	52	#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK \| SDVO_LVDS_MASK))
2342	Serge	53	#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK \| SDVO_LVDS_MASK))
2330	Serge	54
		55
6084	serge	56	static const char * const tv_format_names[] = {
		57	"NTSC_M" , "NTSC_J" , "NTSC_443",
		58	"PAL_B" , "PAL_D" , "PAL_G" ,
		59	"PAL_H" , "PAL_I" , "PAL_M" ,
		60	"PAL_N" , "PAL_NC" , "PAL_60" ,
		61	"SECAM_B" , "SECAM_D" , "SECAM_G" ,
		62	"SECAM_K" , "SECAM_K1", "SECAM_L" ,
		63	"SECAM_60"
2330	Serge	64	};
		65
6084	serge	66	#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
2330	Serge	67
		68	struct intel_sdvo {
6084	serge	69	struct intel_encoder base;
2330	Serge	70
6084	serge	71	struct i2c_adapter *i2c;
		72	u8 slave_addr;
2330	Serge	73
6084	serge	74	struct i2c_adapter ddc;
2330	Serge	75
6084	serge	76	/* Register for the SDVO device: SDVOB or SDVOC */
6937	serge	77	i915_reg_t sdvo_reg;
2330	Serge	78
6084	serge	79	/* Active outputs controlled by this SDVO output */
		80	uint16_t controlled_output;
2330	Serge	81
6084	serge	82	/*
		83	* Capabilities of the SDVO device returned by
4104	Serge	84	* intel_sdvo_get_capabilities()
6084	serge	85	*/
		86	struct intel_sdvo_caps caps;
2330	Serge	87
6084	serge	88	/* Pixel clock limitations reported by the SDVO device, in kHz */
		89	int pixel_clock_min, pixel_clock_max;
2330	Serge	90
6084	serge	91	/*
		92	* For multiple function SDVO device,
		93	* this is for current attached outputs.
		94	*/
		95	uint16_t attached_output;
2330	Serge	96
2342	Serge	97	/*
		98	* Hotplug activation bits for this device
		99	*/
3031	serge	100	uint16_t hotplug_active;
2342	Serge	101
6084	serge	102	/**
		103	* This is used to select the color range of RBG outputs in HDMI mode.
		104	* It is only valid when using TMDS encoding and 8 bit per color mode.
		105	*/
		106	uint32_t color_range;
3480	Serge	107	bool color_range_auto;
2330	Serge	108
6084	serge	109	/**
		110	* HDMI user specified aspect ratio
		111	*/
		112	enum hdmi_picture_aspect aspect_ratio;
2330	Serge	113
6084	serge	114	/**
		115	* This is set if we're going to treat the device as TV-out.
		116	*
		117	* While we have these nice friendly flags for output types that ought
		118	* to decide this for us, the S-Video output on our HDMI+S-Video card
		119	* shows up as RGB1 (VGA).
		120	*/
		121	bool is_tv;
		122
6937	serge	123	enum port port;
3031	serge	124
6084	serge	125	/* This is for current tv format name */
		126	int tv_format_index;
2330	Serge	127
6084	serge	128	/**
		129	* This is set if we treat the device as HDMI, instead of DVI.
		130	*/
		131	bool is_hdmi;
		132	bool has_hdmi_monitor;
		133	bool has_hdmi_audio;
3480	Serge	134	bool rgb_quant_range_selectable;
2330	Serge	135
6084	serge	136	/**
		137	* This is set if we detect output of sdvo device as LVDS and
		138	* have a valid fixed mode to use with the panel.
		139	*/
		140	bool is_lvds;
2330	Serge	141
6084	serge	142	/**
		143	* This is sdvo fixed pannel mode pointer
		144	*/
		145	struct drm_display_mode *sdvo_lvds_fixed_mode;
2330	Serge	146
6084	serge	147	/* DDC bus used by this SDVO encoder */
		148	uint8_t ddc_bus;
2330	Serge	149
3031	serge	150	/*
		151	* the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
		152	*/
		153	uint8_t dtd_sdvo_flags;
2330	Serge	154	};
		155
		156	struct intel_sdvo_connector {
6084	serge	157	struct intel_connector base;
2330	Serge	158
6084	serge	159	/* Mark the type of connector */
		160	uint16_t output_flag;
2330	Serge	161
3031	serge	162	enum hdmi_force_audio force_audio;
2330	Serge	163
6084	serge	164	/* This contains all current supported TV format */
		165	u8 tv_format_supported[TV_FORMAT_NUM];
		166	int format_supported_num;
		167	struct drm_property *tv_format;
2330	Serge	168
6084	serge	169	/* add the property for the SDVO-TV */
		170	struct drm_property *left;
		171	struct drm_property *right;
		172	struct drm_property *top;
		173	struct drm_property *bottom;
		174	struct drm_property *hpos;
		175	struct drm_property *vpos;
		176	struct drm_property *contrast;
		177	struct drm_property *saturation;
		178	struct drm_property *hue;
		179	struct drm_property *sharpness;
		180	struct drm_property *flicker_filter;
		181	struct drm_property *flicker_filter_adaptive;
		182	struct drm_property *flicker_filter_2d;
		183	struct drm_property *tv_chroma_filter;
		184	struct drm_property *tv_luma_filter;
		185	struct drm_property *dot_crawl;
2330	Serge	186
6084	serge	187	/* add the property for the SDVO-TV/LVDS */
		188	struct drm_property *brightness;
2330	Serge	189
6084	serge	190	/* Add variable to record current setting for the above property */
		191	u32 left_margin, right_margin, top_margin, bottom_margin;
2330	Serge	192
6084	serge	193	/* this is to get the range of margin.*/
		194	u32 max_hscan, max_vscan;
		195	u32 max_hpos, cur_hpos;
		196	u32 max_vpos, cur_vpos;
		197	u32 cur_brightness, max_brightness;
		198	u32 cur_contrast, max_contrast;
		199	u32 cur_saturation, max_saturation;
		200	u32 cur_hue, max_hue;
		201	u32 cur_sharpness, max_sharpness;
		202	u32 cur_flicker_filter, max_flicker_filter;
		203	u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
		204	u32 cur_flicker_filter_2d, max_flicker_filter_2d;
		205	u32 cur_tv_chroma_filter, max_tv_chroma_filter;
		206	u32 cur_tv_luma_filter, max_tv_luma_filter;
		207	u32 cur_dot_crawl, max_dot_crawl;
2330	Serge	208	};
		209
4104	Serge	210	static struct intel_sdvo to_sdvo(struct intel_encoder encoder)
2330	Serge	211	{
4104	Serge	212	return container_of(encoder, struct intel_sdvo, base);
2330	Serge	213	}
		214
		215	static struct intel_sdvo intel_attached_sdvo(struct drm_connector connector)
		216	{
4104	Serge	217	return to_sdvo(intel_attached_encoder(connector));
2330	Serge	218	}
		219
		220	static struct intel_sdvo_connector to_intel_sdvo_connector(struct drm_connector connector)
		221	{
		222	return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
		223	}
		224
		225	static bool
		226	intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
		227	static bool
		228	intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
		229	struct intel_sdvo_connector *intel_sdvo_connector,
		230	int type);
		231	static bool
		232	intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
		233	struct intel_sdvo_connector *intel_sdvo_connector);
		234
		235	/**
		236	* Writes the SDVOB or SDVOC with the given value, but always writes both
		237	* SDVOB and SDVOC to work around apparent hardware issues (according to
		238	* comments in the BIOS).
		239	*/
		240	static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
		241	{
		242	struct drm_device *dev = intel_sdvo->base.base.dev;
		243	struct drm_i915_private *dev_priv = dev->dev_private;
		244	u32 bval = val, cval = val;
		245	int i;
		246
6937	serge	247	if (HAS_PCH_SPLIT(dev_priv)) {
2330	Serge	248	I915_WRITE(intel_sdvo->sdvo_reg, val);
6084	serge	249	POSTING_READ(intel_sdvo->sdvo_reg);
		250	/*
		251	* HW workaround, need to write this twice for issue
		252	* that may result in first write getting masked.
		253	*/
		254	if (HAS_PCH_IBX(dev)) {
		255	I915_WRITE(intel_sdvo->sdvo_reg, val);
		256	POSTING_READ(intel_sdvo->sdvo_reg);
		257	}
2330	Serge	258	return;
		259	}
		260
6937	serge	261	if (intel_sdvo->port == PORT_B)
3746	Serge	262	cval = I915_READ(GEN3_SDVOC);
		263	else
		264	bval = I915_READ(GEN3_SDVOB);
		265
2330	Serge	266	/*
		267	* Write the registers twice for luck. Sometimes,
		268	* writing them only once doesn't appear to 'stick'.
		269	* The BIOS does this too. Yay, magic
		270	*/
		271	for (i = 0; i < 2; i++)
		272	{
3746	Serge	273	I915_WRITE(GEN3_SDVOB, bval);
6084	serge	274	POSTING_READ(GEN3_SDVOB);
3746	Serge	275	I915_WRITE(GEN3_SDVOC, cval);
6084	serge	276	POSTING_READ(GEN3_SDVOC);
2330	Serge	277	}
		278	}
		279
		280	static bool intel_sdvo_read_byte(struct intel_sdvo intel_sdvo, u8 addr, u8 ch)
		281	{
		282	struct i2c_msg msgs[] = {
		283	{
		284	.addr = intel_sdvo->slave_addr,
		285	.flags = 0,
		286	.len = 1,
		287	.buf = &addr,
		288	},
		289	{
		290	.addr = intel_sdvo->slave_addr,
		291	.flags = I2C_M_RD,
		292	.len = 1,
		293	.buf = ch,
		294	}
		295	};
		296	int ret;
		297
		298	if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
		299	return true;
		300
		301	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
		302	return false;
		303	}
		304
		305	#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
		306	/** Mapping of command numbers to names, for debug output */
		307	static const struct _sdvo_cmd_name {
		308	u8 cmd;
		309	const char *name;
		310	} sdvo_cmd_names[] = {
6084	serge	311	SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
		312	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
		313	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
		314	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
		315	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
		316	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
		317	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
		318	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
		319	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
		320	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
		321	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
		322	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
		323	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
		324	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
		325	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
		326	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
		327	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
		328	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
		329	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
		330	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
		331	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
		332	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
		333	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
		334	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
		335	SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
		336	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
		337	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
		338	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
		339	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
		340	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
		341	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
		342	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
		343	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
		344	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
		345	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
		346	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
		347	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
		348	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
		349	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
		350	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
		351	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
		352	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
		353	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
2330	Serge	354
6084	serge	355	/* Add the op code for SDVO enhancements */
		356	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
		357	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
		358	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
		359	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
		360	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
		361	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
		362	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
		363	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
		364	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
		365	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
		366	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
		367	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
		368	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
		369	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
		370	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
		371	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
		372	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
		373	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
		374	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
		375	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
		376	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
		377	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
		378	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
		379	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
		380	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
		381	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
		382	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
		383	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
		384	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
		385	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
		386	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
		387	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
		388	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
		389	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
		390	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
		391	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
		392	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
		393	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
		394	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
		395	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
		396	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
		397	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
		398	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
		399	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
2330	Serge	400
6084	serge	401	/* HDMI op code */
		402	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
		403	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
		404	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
		405	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
		406	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
		407	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
		408	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
		409	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
		410	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
		411	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
		412	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
		413	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
		414	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
		415	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
		416	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
		417	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
		418	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
		419	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
		420	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
		421	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
2330	Serge	422	};
		423
6937	serge	424	#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
2330	Serge	425
		426	static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
		427	const void *args, int args_len)
		428	{
4560	Serge	429	int i, pos = 0;
		430	#define BUF_LEN 256
		431	char buffer[BUF_LEN];
2330	Serge	432
4560	Serge	433	#define BUF_PRINT(args...) \
		434	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
		435
		436
		437	for (i = 0; i < args_len; i++) {
		438	BUF_PRINT("%02X ", ((u8 *)args)[i]);
		439	}
		440	for (; i < 8; i++) {
		441	BUF_PRINT(" ");
		442	}
2330	Serge	443	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
		444	if (cmd == sdvo_cmd_names[i].cmd) {
4560	Serge	445	BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
2330	Serge	446	break;
		447	}
		448	}
4560	Serge	449	if (i == ARRAY_SIZE(sdvo_cmd_names)) {
		450	BUF_PRINT("(%02X)", cmd);
		451	}
		452	BUG_ON(pos >= BUF_LEN - 1);
		453	#undef BUF_PRINT
		454	#undef BUF_LEN
		455
		456	DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
2330	Serge	457	}
		458
6084	serge	459	static const char * const cmd_status_names[] = {
2330	Serge	460	"Power on",
		461	"Success",
		462	"Not supported",
		463	"Invalid arg",
		464	"Pending",
		465	"Target not specified",
		466	"Scaling not supported"
		467	};
		468
		469	static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
		470	const void *args, int args_len)
		471	{
3031	serge	472	u8 *buf, status;
		473	struct i2c_msg *msgs;
		474	int i, ret = true;
2330	Serge	475
3031	serge	476	/* Would be simpler to allocate both in one go ? */
3746	Serge	477	buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3031	serge	478	if (!buf)
		479	return false;
		480
		481	msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
		482	if (!msgs) {
		483	kfree(buf);
		484	return false;
		485	}
		486
2330	Serge	487	intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
		488
		489	for (i = 0; i < args_len; i++) {
		490	msgs[i].addr = intel_sdvo->slave_addr;
		491	msgs[i].flags = 0;
		492	msgs[i].len = 2;
		493	msgs[i].buf = buf + 2 *i;
		494	buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
		495	buf[2i + 1] = ((u8)args)[i];
		496	}
		497	msgs[i].addr = intel_sdvo->slave_addr;
		498	msgs[i].flags = 0;
		499	msgs[i].len = 2;
		500	msgs[i].buf = buf + 2*i;
		501	buf[2*i + 0] = SDVO_I2C_OPCODE;
		502	buf[2*i + 1] = cmd;
		503
		504	/* the following two are to read the response */
		505	status = SDVO_I2C_CMD_STATUS;
		506	msgs[i+1].addr = intel_sdvo->slave_addr;
		507	msgs[i+1].flags = 0;
		508	msgs[i+1].len = 1;
		509	msgs[i+1].buf = &status;
		510
		511	msgs[i+2].addr = intel_sdvo->slave_addr;
		512	msgs[i+2].flags = I2C_M_RD;
		513	msgs[i+2].len = 1;
		514	msgs[i+2].buf = &status;
		515
		516	ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
		517	if (ret < 0) {
		518	DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3031	serge	519	ret = false;
		520	goto out;
2330	Serge	521	}
		522	if (ret != i+3) {
		523	/* failure in I2C transfer */
		524	DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3031	serge	525	ret = false;
2330	Serge	526	}
		527
3031	serge	528	out:
		529	kfree(msgs);
		530	kfree(buf);
		531	return ret;
2330	Serge	532	}
		533
		534	static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
		535	void *response, int response_len)
		536	{
3243	Serge	537	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
2330	Serge	538	u8 status;
4560	Serge	539	int i, pos = 0;
		540	#define BUF_LEN 256
		541	char buffer[BUF_LEN];
2330	Serge	542
		543
		544	/*
		545	* The documentation states that all commands will be
		546	* processed within 15µs, and that we need only poll
		547	* the status byte a maximum of 3 times in order for the
		548	* command to be complete.
		549	*
		550	* Check 5 times in case the hardware failed to read the docs.
3243	Serge	551	*
		552	* Also beware that the first response by many devices is to
		553	* reply PENDING and stall for time. TVs are notorious for
		554	* requiring longer than specified to complete their replies.
		555	* Originally (in the DDX long ago), the delay was only ever 15ms
		556	* with an additional delay of 30ms applied for TVs added later after
		557	* many experiments. To accommodate both sets of delays, we do a
		558	* sequence of slow checks if the device is falling behind and fails
		559	* to reply within 5*15µs.
2330	Serge	560	*/
		561	if (!intel_sdvo_read_byte(intel_sdvo,
		562	SDVO_I2C_CMD_STATUS,
		563	&status))
		564	goto log_fail;
		565
4104	Serge	566	while ((status == SDVO_CMD_STATUS_PENDING \|\|
6084	serge	567	status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
3243	Serge	568	if (retry < 10)
		569	msleep(15);
		570	else
		571	udelay(15);
		572
2330	Serge	573	if (!intel_sdvo_read_byte(intel_sdvo,
		574	SDVO_I2C_CMD_STATUS,
		575	&status))
		576	goto log_fail;
		577	}
		578
4560	Serge	579	#define BUF_PRINT(args...) \
		580	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
		581
2330	Serge	582	if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
4560	Serge	583	BUF_PRINT("(%s)", cmd_status_names[status]);
2330	Serge	584	else
4560	Serge	585	BUF_PRINT("(??? %d)", status);
2330	Serge	586
		587	if (status != SDVO_CMD_STATUS_SUCCESS)
		588	goto log_fail;
		589
		590	/* Read the command response */
		591	for (i = 0; i < response_len; i++) {
		592	if (!intel_sdvo_read_byte(intel_sdvo,
		593	SDVO_I2C_RETURN_0 + i,
		594	&((u8 *)response)[i]))
		595	goto log_fail;
4560	Serge	596	BUF_PRINT(" %02X", ((u8 *)response)[i]);
2330	Serge	597	}
4560	Serge	598	BUG_ON(pos >= BUF_LEN - 1);
		599	#undef BUF_PRINT
		600	#undef BUF_LEN
		601
		602	DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
2330	Serge	603	return true;
		604
		605	log_fail:
4560	Serge	606	DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
2330	Serge	607	return false;
		608	}
		609
6084	serge	610	static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
2330	Serge	611	{
6084	serge	612	if (adjusted_mode->crtc_clock >= 100000)
2330	Serge	613	return 1;
6084	serge	614	else if (adjusted_mode->crtc_clock >= 50000)
2330	Serge	615	return 2;
		616	else
		617	return 4;
		618	}
		619
		620	static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
		621	u8 ddc_bus)
		622	{
		623	/* This must be the immediately preceding write before the i2c xfer */
		624	return intel_sdvo_write_cmd(intel_sdvo,
		625	SDVO_CMD_SET_CONTROL_BUS_SWITCH,
		626	&ddc_bus, 1);
		627	}
		628
		629	static bool intel_sdvo_set_value(struct intel_sdvo intel_sdvo, u8 cmd, const void data, int len)
		630	{
		631	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
		632	return false;
		633
		634	return intel_sdvo_read_response(intel_sdvo, NULL, 0);
		635	}
		636
		637	static bool
		638	intel_sdvo_get_value(struct intel_sdvo intel_sdvo, u8 cmd, void value, int len)
		639	{
		640	if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
		641	return false;
		642
		643	return intel_sdvo_read_response(intel_sdvo, value, len);
		644	}
		645
		646	static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
		647	{
		648	struct intel_sdvo_set_target_input_args targets = {0};
		649	return intel_sdvo_set_value(intel_sdvo,
		650	SDVO_CMD_SET_TARGET_INPUT,
		651	&targets, sizeof(targets));
		652	}
		653
		654	/**
		655	* Return whether each input is trained.
		656	*
		657	* This function is making an assumption about the layout of the response,
		658	* which should be checked against the docs.
		659	*/
		660	static bool intel_sdvo_get_trained_inputs(struct intel_sdvo intel_sdvo, bool input_1, bool *input_2)
		661	{
		662	struct intel_sdvo_get_trained_inputs_response response;
		663
		664	BUILD_BUG_ON(sizeof(response) != 1);
		665	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
		666	&response, sizeof(response)))
		667	return false;
		668
		669	*input_1 = response.input0_trained;
		670	*input_2 = response.input1_trained;
		671	return true;
		672	}
		673
		674	static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
		675	u16 outputs)
		676	{
		677	return intel_sdvo_set_value(intel_sdvo,
		678	SDVO_CMD_SET_ACTIVE_OUTPUTS,
		679	&outputs, sizeof(outputs));
		680	}
		681
3031	serge	682	static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
		683	u16 *outputs)
		684	{
		685	return intel_sdvo_get_value(intel_sdvo,
		686	SDVO_CMD_GET_ACTIVE_OUTPUTS,
		687	outputs, sizeof(*outputs));
		688	}
		689
2340	Serge	690	static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
		691	int mode)
		692	{
		693	u8 state = SDVO_ENCODER_STATE_ON;
2330	Serge	694
2340	Serge	695	switch (mode) {
		696	case DRM_MODE_DPMS_ON:
		697	state = SDVO_ENCODER_STATE_ON;
		698	break;
		699	case DRM_MODE_DPMS_STANDBY:
		700	state = SDVO_ENCODER_STATE_STANDBY;
		701	break;
		702	case DRM_MODE_DPMS_SUSPEND:
		703	state = SDVO_ENCODER_STATE_SUSPEND;
		704	break;
		705	case DRM_MODE_DPMS_OFF:
		706	state = SDVO_ENCODER_STATE_OFF;
		707	break;
		708	}
2330	Serge	709
2340	Serge	710	return intel_sdvo_set_value(intel_sdvo,
		711	SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
		712	}
2330	Serge	713
		714	static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
		715	int *clock_min,
		716	int *clock_max)
		717	{
		718	struct intel_sdvo_pixel_clock_range clocks;
		719
		720	BUILD_BUG_ON(sizeof(clocks) != 4);
		721	if (!intel_sdvo_get_value(intel_sdvo,
		722	SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
		723	&clocks, sizeof(clocks)))
		724	return false;
		725
		726	/* Convert the values from units of 10 kHz to kHz. */
		727	clock_min = clocks.min 10;
		728	clock_max = clocks.max 10;
		729	return true;
		730	}
		731
		732	static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
		733	u16 outputs)
		734	{
		735	return intel_sdvo_set_value(intel_sdvo,
		736	SDVO_CMD_SET_TARGET_OUTPUT,
		737	&outputs, sizeof(outputs));
		738	}
		739
		740	static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
		741	struct intel_sdvo_dtd *dtd)
		742	{
		743	return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
		744	intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
		745	}
		746
4104	Serge	747	static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
		748	struct intel_sdvo_dtd *dtd)
		749	{
		750	return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
		751	intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
		752	}
		753
2330	Serge	754	static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
		755	struct intel_sdvo_dtd *dtd)
		756	{
		757	return intel_sdvo_set_timing(intel_sdvo,
		758	SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
		759	}
		760
		761	static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
		762	struct intel_sdvo_dtd *dtd)
		763	{
		764	return intel_sdvo_set_timing(intel_sdvo,
		765	SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
		766	}
		767
4104	Serge	768	static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
		769	struct intel_sdvo_dtd *dtd)
		770	{
		771	return intel_sdvo_get_timing(intel_sdvo,
		772	SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
		773	}
		774
2330	Serge	775	static bool
		776	intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
		777	uint16_t clock,
		778	uint16_t width,
		779	uint16_t height)
		780	{
		781	struct intel_sdvo_preferred_input_timing_args args;
		782
		783	memset(&args, 0, sizeof(args));
		784	args.clock = clock;
		785	args.width = width;
		786	args.height = height;
		787	args.interlace = 0;
		788
		789	if (intel_sdvo->is_lvds &&
		790	(intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width \|\|
		791	intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
		792	args.scaled = 1;
		793
		794	return intel_sdvo_set_value(intel_sdvo,
		795	SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
		796	&args, sizeof(args));
		797	}
		798
		799	static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
		800	struct intel_sdvo_dtd *dtd)
		801	{
		802	BUILD_BUG_ON(sizeof(dtd->part1) != 8);
		803	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
		804	return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
		805	&dtd->part1, sizeof(dtd->part1)) &&
		806	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
		807	&dtd->part2, sizeof(dtd->part2));
		808	}
		809
		810	static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
		811	{
		812	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
		813	}
		814
		815	static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
		816	const struct drm_display_mode *mode)
		817	{
		818	uint16_t width, height;
		819	uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
		820	uint16_t h_sync_offset, v_sync_offset;
3031	serge	821	int mode_clock;
2330	Serge	822
4104	Serge	823	memset(dtd, 0, sizeof(*dtd));
		824
3031	serge	825	width = mode->hdisplay;
		826	height = mode->vdisplay;
2330	Serge	827
		828	/* do some mode translations */
3031	serge	829	h_blank_len = mode->htotal - mode->hdisplay;
		830	h_sync_len = mode->hsync_end - mode->hsync_start;
2330	Serge	831
3031	serge	832	v_blank_len = mode->vtotal - mode->vdisplay;
		833	v_sync_len = mode->vsync_end - mode->vsync_start;
2330	Serge	834
3031	serge	835	h_sync_offset = mode->hsync_start - mode->hdisplay;
		836	v_sync_offset = mode->vsync_start - mode->vdisplay;
2330	Serge	837
3031	serge	838	mode_clock = mode->clock;
		839	mode_clock /= 10;
		840	dtd->part1.clock = mode_clock;
		841
2330	Serge	842	dtd->part1.h_active = width & 0xff;
		843	dtd->part1.h_blank = h_blank_len & 0xff;
		844	dtd->part1.h_high = (((width >> 8) & 0xf) << 4) \|
		845	((h_blank_len >> 8) & 0xf);
		846	dtd->part1.v_active = height & 0xff;
		847	dtd->part1.v_blank = v_blank_len & 0xff;
		848	dtd->part1.v_high = (((height >> 8) & 0xf) << 4) \|
		849	((v_blank_len >> 8) & 0xf);
		850
		851	dtd->part2.h_sync_off = h_sync_offset & 0xff;
		852	dtd->part2.h_sync_width = h_sync_len & 0xff;
		853	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 \|
		854	(v_sync_len & 0xf);
		855	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) \|
		856	((h_sync_len & 0x300) >> 4) \| ((v_sync_offset & 0x30) >> 2) \|
		857	((v_sync_len & 0x30) >> 4);
		858
		859	dtd->part2.dtd_flags = 0x18;
3031	serge	860	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		861	dtd->part2.dtd_flags \|= DTD_FLAG_INTERLACE;
2330	Serge	862	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
3031	serge	863	dtd->part2.dtd_flags \|= DTD_FLAG_HSYNC_POSITIVE;
2330	Serge	864	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
3031	serge	865	dtd->part2.dtd_flags \|= DTD_FLAG_VSYNC_POSITIVE;
2330	Serge	866
		867	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
		868	}
		869
4104	Serge	870	static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
2330	Serge	871	const struct intel_sdvo_dtd *dtd)
		872	{
4104	Serge	873	struct drm_display_mode mode = {};
2330	Serge	874
4104	Serge	875	mode.hdisplay = dtd->part1.h_active;
		876	mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
		877	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
		878	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
		879	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
		880	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
		881	mode.htotal = mode.hdisplay + dtd->part1.h_blank;
		882	mode.htotal += (dtd->part1.h_high & 0xf) << 8;
		883
		884	mode.vdisplay = dtd->part1.v_active;
		885	mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
		886	mode.vsync_start = mode.vdisplay;
		887	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
		888	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
		889	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
		890	mode.vsync_end = mode.vsync_start +
2330	Serge	891	(dtd->part2.v_sync_off_width & 0xf);
4104	Serge	892	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
		893	mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
		894	mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
2330	Serge	895
4104	Serge	896	mode.clock = dtd->part1.clock * 10;
2330	Serge	897
3031	serge	898	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
4104	Serge	899	mode.flags \|= DRM_MODE_FLAG_INTERLACE;
3031	serge	900	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
4104	Serge	901	mode.flags \|= DRM_MODE_FLAG_PHSYNC;
		902	else
		903	mode.flags \|= DRM_MODE_FLAG_NHSYNC;
3031	serge	904	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
4104	Serge	905	mode.flags \|= DRM_MODE_FLAG_PVSYNC;
		906	else
		907	mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		908
		909	drm_mode_set_crtcinfo(&mode, 0);
		910
		911	drm_mode_copy(pmode, &mode);
2330	Serge	912	}
		913
		914	static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
		915	{
		916	struct intel_sdvo_encode encode;
		917
		918	BUILD_BUG_ON(sizeof(encode) != 2);
		919	return intel_sdvo_get_value(intel_sdvo,
		920	SDVO_CMD_GET_SUPP_ENCODE,
		921	&encode, sizeof(encode));
		922	}
		923
		924	static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
		925	uint8_t mode)
		926	{
		927	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
		928	}
		929
		930	static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
		931	uint8_t mode)
		932	{
		933	return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
		934	}
		935
		936	#if 0
		937	static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
		938	{
		939	int i, j;
		940	uint8_t set_buf_index[2];
		941	uint8_t av_split;
		942	uint8_t buf_size;
		943	uint8_t buf[48];
		944	uint8_t *pos;
		945
		946	intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
		947
		948	for (i = 0; i <= av_split; i++) {
		949	set_buf_index[0] = i; set_buf_index[1] = 0;
		950	intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
		951	set_buf_index, 2);
		952	intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
		953	intel_sdvo_read_response(encoder, &buf_size, 1);
		954
		955	pos = buf;
		956	for (j = 0; j <= buf_size; j += 8) {
		957	intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
		958	NULL, 0);
		959	intel_sdvo_read_response(encoder, pos, 8);
		960	pos += 8;
		961	}
		962	}
		963	}
		964	#endif
		965
3031	serge	966	static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
		967	unsigned if_index, uint8_t tx_rate,
4560	Serge	968	const uint8_t *data, unsigned length)
2330	Serge	969	{
3031	serge	970	uint8_t set_buf_index[2] = { if_index, 0 };
		971	uint8_t hbuf_size, tmp[8];
		972	int i;
2330	Serge	973
		974	if (!intel_sdvo_set_value(intel_sdvo,
		975	SDVO_CMD_SET_HBUF_INDEX,
		976	set_buf_index, 2))
		977	return false;
		978
3031	serge	979	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
		980	&hbuf_size, 1))
		981	return false;
		982
		983	/* Buffer size is 0 based, hooray! */
		984	hbuf_size++;
		985
		986	DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
		987	if_index, length, hbuf_size);
		988
		989	for (i = 0; i < hbuf_size; i += 8) {
		990	memset(tmp, 0, 8);
		991	if (i < length)
		992	memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
		993
2330	Serge	994	if (!intel_sdvo_set_value(intel_sdvo,
		995	SDVO_CMD_SET_HBUF_DATA,
3031	serge	996	tmp, 8))
2330	Serge	997	return false;
		998	}
		999
		1000	return intel_sdvo_set_value(intel_sdvo,
		1001	SDVO_CMD_SET_HBUF_TXRATE,
		1002	&tx_rate, 1);
		1003	}
		1004
3480	Serge	1005	static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
		1006	const struct drm_display_mode *adjusted_mode)
3031	serge	1007	{
4104	Serge	1008	uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
		1009	struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
		1010	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		1011	union hdmi_infoframe frame;
		1012	int ret;
		1013	ssize_t len;
3031	serge	1014
4104	Serge	1015	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
		1016	adjusted_mode);
		1017	if (ret < 0) {
		1018	DRM_ERROR("couldn't fill AVI infoframe\n");
		1019	return false;
		1020	}
		1021
3480	Serge	1022	if (intel_sdvo->rgb_quant_range_selectable) {
6084	serge	1023	if (intel_crtc->config->limited_color_range)
4104	Serge	1024	frame.avi.quantization_range =
		1025	HDMI_QUANTIZATION_RANGE_LIMITED;
3480	Serge	1026	else
4104	Serge	1027	frame.avi.quantization_range =
		1028	HDMI_QUANTIZATION_RANGE_FULL;
3480	Serge	1029	}
		1030
4104	Serge	1031	len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
		1032	if (len < 0)
		1033	return false;
3746	Serge	1034
3031	serge	1035	return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
		1036	SDVO_HBUF_TX_VSYNC,
		1037	sdvo_data, sizeof(sdvo_data));
		1038	}
		1039
2330	Serge	1040	static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
		1041	{
		1042	struct intel_sdvo_tv_format format;
		1043	uint32_t format_map;
		1044
		1045	format_map = 1 << intel_sdvo->tv_format_index;
		1046	memset(&format, 0, sizeof(format));
		1047	memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
		1048
		1049	BUILD_BUG_ON(sizeof(format) != 6);
		1050	return intel_sdvo_set_value(intel_sdvo,
		1051	SDVO_CMD_SET_TV_FORMAT,
		1052	&format, sizeof(format));
		1053	}
		1054
		1055	static bool
		1056	intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
3031	serge	1057	const struct drm_display_mode *mode)
2330	Serge	1058	{
		1059	struct intel_sdvo_dtd output_dtd;
		1060
		1061	if (!intel_sdvo_set_target_output(intel_sdvo,
		1062	intel_sdvo->attached_output))
		1063	return false;
		1064
		1065	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
		1066	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
		1067	return false;
		1068
		1069	return true;
		1070	}
		1071
3031	serge	1072	/* Asks the sdvo controller for the preferred input mode given the output mode.
		1073	* Unfortunately we have to set up the full output mode to do that. */
2330	Serge	1074	static bool
3031	serge	1075	intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
		1076	const struct drm_display_mode *mode,
6084	serge	1077	struct drm_display_mode *adjusted_mode)
2330	Serge	1078	{
3031	serge	1079	struct intel_sdvo_dtd input_dtd;
		1080
2330	Serge	1081	/* Reset the input timing to the screen. Assume always input 0. */
		1082	if (!intel_sdvo_set_target_input(intel_sdvo))
		1083	return false;
		1084
		1085	if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
		1086	mode->clock / 10,
		1087	mode->hdisplay,
		1088	mode->vdisplay))
		1089	return false;
		1090
		1091	if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
3031	serge	1092	&input_dtd))
2330	Serge	1093	return false;
		1094
3031	serge	1095	intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
		1096	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
2330	Serge	1097
		1098	return true;
		1099	}
		1100
6084	serge	1101	static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
4104	Serge	1102	{
4560	Serge	1103	unsigned dotclock = pipe_config->port_clock;
4104	Serge	1104	struct dpll *clock = &pipe_config->dpll;
		1105
		1106	/* SDVO TV has fixed PLL values depend on its clock range,
		1107	this mirrors vbios setting. */
		1108	if (dotclock >= 100000 && dotclock < 140500) {
		1109	clock->p1 = 2;
		1110	clock->p2 = 10;
		1111	clock->n = 3;
		1112	clock->m1 = 16;
		1113	clock->m2 = 8;
		1114	} else if (dotclock >= 140500 && dotclock <= 200000) {
		1115	clock->p1 = 1;
		1116	clock->p2 = 10;
		1117	clock->n = 6;
		1118	clock->m1 = 12;
		1119	clock->m2 = 8;
		1120	} else {
		1121	WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
		1122	}
		1123
		1124	pipe_config->clock_set = true;
		1125	}
		1126
3746	Serge	1127	static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
6084	serge	1128	struct intel_crtc_state *pipe_config)
2330	Serge	1129	{
4104	Serge	1130	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6084	serge	1131	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
		1132	struct drm_display_mode *mode = &pipe_config->base.mode;
2330	Serge	1133
3746	Serge	1134	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
		1135	pipe_config->pipe_bpp = 8*3;
		1136
		1137	if (HAS_PCH_SPLIT(encoder->base.dev))
		1138	pipe_config->has_pch_encoder = true;
		1139
2330	Serge	1140	/* We need to construct preferred input timings based on our
		1141	* output timings. To do that, we have to set the output
		1142	* timings, even though this isn't really the right place in
		1143	* the sequence to do it. Oh well.
		1144	*/
		1145	if (intel_sdvo->is_tv) {
		1146	if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
		1147	return false;
		1148
3031	serge	1149	(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
6084	serge	1150	mode,
		1151	adjusted_mode);
4104	Serge	1152	pipe_config->sdvo_tv_clock = true;
2330	Serge	1153	} else if (intel_sdvo->is_lvds) {
		1154	if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
		1155	intel_sdvo->sdvo_lvds_fixed_mode))
		1156	return false;
		1157
3031	serge	1158	(void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
6084	serge	1159	mode,
		1160	adjusted_mode);
2330	Serge	1161	}
		1162
		1163	/* Make the CRTC code factor in the SDVO pixel multiplier. The
		1164	* SDVO device will factor out the multiplier during mode_set.
		1165	*/
3746	Serge	1166	pipe_config->pixel_multiplier =
		1167	intel_sdvo_get_pixel_multiplier(adjusted_mode);
2330	Serge	1168
5060	serge	1169	pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
		1170
3480	Serge	1171	if (intel_sdvo->color_range_auto) {
		1172	/* See CEA-861-E - 5.1 Default Encoding Parameters */
3746	Serge	1173	/* FIXME: This bit is only valid when using TMDS encoding and 8
		1174	* bit per color mode. */
5060	serge	1175	if (pipe_config->has_hdmi_sink &&
3480	Serge	1176	drm_match_cea_mode(adjusted_mode) > 1)
5060	serge	1177	pipe_config->limited_color_range = true;
		1178	} else {
		1179	if (pipe_config->has_hdmi_sink &&
		1180	intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
		1181	pipe_config->limited_color_range = true;
3480	Serge	1182	}
		1183
4104	Serge	1184	/* Clock computation needs to happen after pixel multiplier. */
		1185	if (intel_sdvo->is_tv)
		1186	i9xx_adjust_sdvo_tv_clock(pipe_config);
		1187
6084	serge	1188	/* Set user selected PAR to incoming mode's member */
		1189	if (intel_sdvo->is_hdmi)
		1190	adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio;
		1191
2330	Serge	1192	return true;
		1193	}
		1194
5060	serge	1195	static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
2330	Serge	1196	{
3746	Serge	1197	struct drm_device *dev = intel_encoder->base.dev;
2330	Serge	1198	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1199	struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6084	serge	1200	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
		1201	struct drm_display_mode *mode = &crtc->config->base.mode;
4104	Serge	1202	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
2330	Serge	1203	u32 sdvox;
		1204	struct intel_sdvo_in_out_map in_out;
3031	serge	1205	struct intel_sdvo_dtd input_dtd, output_dtd;
2330	Serge	1206	int rate;
		1207
		1208	if (!mode)
		1209	return;
		1210
		1211	/* First, set the input mapping for the first input to our controlled
		1212	* output. This is only correct if we're a single-input device, in
		1213	* which case the first input is the output from the appropriate SDVO
		1214	* channel on the motherboard. In a two-input device, the first input
		1215	* will be SDVOB and the second SDVOC.
		1216	*/
		1217	in_out.in0 = intel_sdvo->attached_output;
		1218	in_out.in1 = 0;
		1219
		1220	intel_sdvo_set_value(intel_sdvo,
		1221	SDVO_CMD_SET_IN_OUT_MAP,
		1222	&in_out, sizeof(in_out));
		1223
		1224	/* Set the output timings to the screen */
		1225	if (!intel_sdvo_set_target_output(intel_sdvo,
		1226	intel_sdvo->attached_output))
		1227	return;
		1228
3031	serge	1229	/* lvds has a special fixed output timing. */
		1230	if (intel_sdvo->is_lvds)
		1231	intel_sdvo_get_dtd_from_mode(&output_dtd,
		1232	intel_sdvo->sdvo_lvds_fixed_mode);
		1233	else
		1234	intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
		1235	if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
		1236	DRM_INFO("Setting output timings on %s failed\n",
		1237	SDVO_NAME(intel_sdvo));
2330	Serge	1238
		1239	/* Set the input timing to the screen. Assume always input 0. */
		1240	if (!intel_sdvo_set_target_input(intel_sdvo))
		1241	return;
		1242
6084	serge	1243	if (crtc->config->has_hdmi_sink) {
2330	Serge	1244	intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
		1245	intel_sdvo_set_colorimetry(intel_sdvo,
		1246	SDVO_COLORIMETRY_RGB256);
3480	Serge	1247	intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
2330	Serge	1248	} else
		1249	intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
		1250
		1251	if (intel_sdvo->is_tv &&
		1252	!intel_sdvo_set_tv_format(intel_sdvo))
		1253	return;
		1254
3031	serge	1255	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
4104	Serge	1256
3031	serge	1257	if (intel_sdvo->is_tv \|\| intel_sdvo->is_lvds)
		1258	input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
		1259	if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
		1260	DRM_INFO("Setting input timings on %s failed\n",
		1261	SDVO_NAME(intel_sdvo));
2330	Serge	1262
6084	serge	1263	switch (crtc->config->pixel_multiplier) {
2330	Serge	1264	default:
6084	serge	1265	WARN(1, "unknown pixel multiplier specified\n");
2330	Serge	1266	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
		1267	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
		1268	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
		1269	}
		1270	if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
		1271	return;
		1272
		1273	/* Set the SDVO control regs. */
		1274	if (INTEL_INFO(dev)->gen >= 4) {
2342	Serge	1275	/* The real mode polarity is set by the SDVO commands, using
		1276	* struct intel_sdvo_dtd. */
		1277	sdvox = SDVO_VSYNC_ACTIVE_HIGH \| SDVO_HSYNC_ACTIVE_HIGH;
6084	serge	1278	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
5060	serge	1279	sdvox \|= HDMI_COLOR_RANGE_16_235;
2330	Serge	1280	if (INTEL_INFO(dev)->gen < 5)
		1281	sdvox \|= SDVO_BORDER_ENABLE;
		1282	} else {
		1283	sdvox = I915_READ(intel_sdvo->sdvo_reg);
6937	serge	1284	if (intel_sdvo->port == PORT_B)
2330	Serge	1285	sdvox &= SDVOB_PRESERVE_MASK;
6937	serge	1286	else
2330	Serge	1287	sdvox &= SDVOC_PRESERVE_MASK;
		1288	sdvox \|= (9 << 19) \| SDVO_BORDER_ENABLE;
		1289	}
2342	Serge	1290
		1291	if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
4104	Serge	1292	sdvox \|= SDVO_PIPE_SEL_CPT(crtc->pipe);
2342	Serge	1293	else
4104	Serge	1294	sdvox \|= SDVO_PIPE_SEL(crtc->pipe);
2342	Serge	1295
2330	Serge	1296	if (intel_sdvo->has_hdmi_audio)
		1297	sdvox \|= SDVO_AUDIO_ENABLE;
		1298
		1299	if (INTEL_INFO(dev)->gen >= 4) {
		1300	/* done in crtc_mode_set as the dpll_md reg must be written early */
		1301	} else if (IS_I945G(dev) \|\| IS_I945GM(dev) \|\| IS_G33(dev)) {
		1302	/* done in crtc_mode_set as it lives inside the dpll register */
		1303	} else {
6084	serge	1304	sdvox \|= (crtc->config->pixel_multiplier - 1)
3746	Serge	1305	<< SDVO_PORT_MULTIPLY_SHIFT;
2330	Serge	1306	}
		1307
		1308	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
		1309	INTEL_INFO(dev)->gen < 5)
		1310	sdvox \|= SDVO_STALL_SELECT;
		1311	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
		1312	}
		1313
3031	serge	1314	static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
2330	Serge	1315	{
3031	serge	1316	struct intel_sdvo_connector *intel_sdvo_connector =
		1317	to_intel_sdvo_connector(&connector->base);
		1318	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
4104	Serge	1319	u16 active_outputs = 0;
3031	serge	1320
		1321	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
		1322
		1323	if (active_outputs & intel_sdvo_connector->output_flag)
		1324	return true;
		1325	else
		1326	return false;
		1327	}
		1328
		1329	static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
		1330	enum pipe *pipe)
		1331	{
		1332	struct drm_device *dev = encoder->base.dev;
2330	Serge	1333	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1334	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
		1335	u16 active_outputs = 0;
3031	serge	1336	u32 tmp;
		1337
		1338	tmp = I915_READ(intel_sdvo->sdvo_reg);
3746	Serge	1339	intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
3031	serge	1340
3746	Serge	1341	if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
3031	serge	1342	return false;
		1343
		1344	if (HAS_PCH_CPT(dev))
		1345	*pipe = PORT_TO_PIPE_CPT(tmp);
		1346	else
		1347	*pipe = PORT_TO_PIPE(tmp);
		1348
		1349	return true;
		1350	}
		1351
4104	Serge	1352	static void intel_sdvo_get_config(struct intel_encoder *encoder,
6084	serge	1353	struct intel_crtc_state *pipe_config)
4104	Serge	1354	{
		1355	struct drm_device *dev = encoder->base.dev;
		1356	struct drm_i915_private *dev_priv = dev->dev_private;
		1357	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
		1358	struct intel_sdvo_dtd dtd;
		1359	int encoder_pixel_multiplier = 0;
4560	Serge	1360	int dotclock;
4104	Serge	1361	u32 flags = 0, sdvox;
		1362	u8 val;
		1363	bool ret;
		1364
5060	serge	1365	sdvox = I915_READ(intel_sdvo->sdvo_reg);
		1366
4104	Serge	1367	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
		1368	if (!ret) {
		1369	/* Some sdvo encoders are not spec compliant and don't
		1370	* implement the mandatory get_timings function. */
		1371	DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
		1372	pipe_config->quirks \|= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
		1373	} else {
		1374	if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
		1375	flags \|= DRM_MODE_FLAG_PHSYNC;
		1376	else
		1377	flags \|= DRM_MODE_FLAG_NHSYNC;
		1378
		1379	if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
		1380	flags \|= DRM_MODE_FLAG_PVSYNC;
		1381	else
		1382	flags \|= DRM_MODE_FLAG_NVSYNC;
		1383	}
		1384
6084	serge	1385	pipe_config->base.adjusted_mode.flags \|= flags;
4104	Serge	1386
		1387	/*
		1388	* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
		1389	* the sdvo port register, on all other platforms it is part of the dpll
		1390	* state. Since the general pipe state readout happens before the
		1391	* encoder->get_config we so already have a valid pixel multplier on all
		1392	* other platfroms.
		1393	*/
		1394	if (IS_I915G(dev) \|\| IS_I915GM(dev)) {
		1395	pipe_config->pixel_multiplier =
		1396	((sdvox & SDVO_PORT_MULTIPLY_MASK)
		1397	>> SDVO_PORT_MULTIPLY_SHIFT) + 1;
		1398	}
		1399
5060	serge	1400	dotclock = pipe_config->port_clock;
		1401	if (pipe_config->pixel_multiplier)
		1402	dotclock /= pipe_config->pixel_multiplier;
4560	Serge	1403
		1404	if (HAS_PCH_SPLIT(dev))
		1405	ironlake_check_encoder_dotclock(pipe_config, dotclock);
		1406
6084	serge	1407	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
4560	Serge	1408
4104	Serge	1409	/* Cross check the port pixel multiplier with the sdvo encoder state. */
		1410	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
		1411	&val, 1)) {
6084	serge	1412	switch (val) {
		1413	case SDVO_CLOCK_RATE_MULT_1X:
		1414	encoder_pixel_multiplier = 1;
		1415	break;
		1416	case SDVO_CLOCK_RATE_MULT_2X:
		1417	encoder_pixel_multiplier = 2;
		1418	break;
		1419	case SDVO_CLOCK_RATE_MULT_4X:
		1420	encoder_pixel_multiplier = 4;
		1421	break;
		1422	}
4104	Serge	1423	}
		1424
5060	serge	1425	if (sdvox & HDMI_COLOR_RANGE_16_235)
		1426	pipe_config->limited_color_range = true;
		1427
		1428	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
		1429	&val, 1)) {
		1430	if (val == SDVO_ENCODE_HDMI)
		1431	pipe_config->has_hdmi_sink = true;
		1432	}
		1433
4104	Serge	1434	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
		1435	"SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
		1436	pipe_config->pixel_multiplier, encoder_pixel_multiplier);
		1437	}
		1438
3031	serge	1439	static void intel_disable_sdvo(struct intel_encoder *encoder)
		1440	{
		1441	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
4104	Serge	1442	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6084	serge	1443	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2330	Serge	1444	u32 temp;
		1445
6084	serge	1446	intel_sdvo_set_active_outputs(intel_sdvo, 0);
		1447	if (0)
3031	serge	1448	intel_sdvo_set_encoder_power_state(intel_sdvo,
		1449	DRM_MODE_DPMS_OFF);
2330	Serge	1450
6084	serge	1451	temp = I915_READ(intel_sdvo->sdvo_reg);
3243	Serge	1452
6084	serge	1453	temp &= ~SDVO_ENABLE;
		1454	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1455
6084	serge	1456	/*
		1457	* HW workaround for IBX, we need to move the port
		1458	* to transcoder A after disabling it to allow the
		1459	* matching DP port to be enabled on transcoder A.
		1460	*/
		1461	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
6937	serge	1462	/*
		1463	* We get CPU/PCH FIFO underruns on the other pipe when
		1464	* doing the workaround. Sweep them under the rug.
		1465	*/
		1466	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1467	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		1468
6084	serge	1469	temp &= ~SDVO_PIPE_B_SELECT;
		1470	temp \|= SDVO_ENABLE;
		1471	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1472
6084	serge	1473	temp &= ~SDVO_ENABLE;
		1474	intel_sdvo_write_sdvox(intel_sdvo, temp);
6937	serge	1475
		1476	intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		1477	intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		1478	intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
6084	serge	1479	}
		1480	}
3243	Serge	1481
6084	serge	1482	static void pch_disable_sdvo(struct intel_encoder *encoder)
		1483	{
3031	serge	1484	}
		1485
6084	serge	1486	static void pch_post_disable_sdvo(struct intel_encoder *encoder)
		1487	{
		1488	intel_disable_sdvo(encoder);
		1489	}
		1490
3031	serge	1491	static void intel_enable_sdvo(struct intel_encoder *encoder)
		1492	{
		1493	struct drm_device *dev = encoder->base.dev;
		1494	struct drm_i915_private *dev_priv = dev->dev_private;
4104	Serge	1495	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
3031	serge	1496	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
		1497	u32 temp;
6084	serge	1498	bool input1, input2;
		1499	int i;
5060	serge	1500	bool success;
2330	Serge	1501
6084	serge	1502	temp = I915_READ(intel_sdvo->sdvo_reg);
		1503	temp \|= SDVO_ENABLE;
		1504	intel_sdvo_write_sdvox(intel_sdvo, temp);
3243	Serge	1505
6084	serge	1506	for (i = 0; i < 2; i++)
		1507	intel_wait_for_vblank(dev, intel_crtc->pipe);
2330	Serge	1508
5060	serge	1509	success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
6084	serge	1510	/* Warn if the device reported failure to sync.
		1511	* A lot of SDVO devices fail to notify of sync, but it's
		1512	* a given it the status is a success, we succeeded.
		1513	*/
5060	serge	1514	if (success && !input1) {
6084	serge	1515	DRM_DEBUG_KMS("First %s output reported failure to "
		1516	"sync\n", SDVO_NAME(intel_sdvo));
		1517	}
2330	Serge	1518
6084	serge	1519	if (0)
3031	serge	1520	intel_sdvo_set_encoder_power_state(intel_sdvo,
		1521	DRM_MODE_DPMS_ON);
		1522	intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
		1523	}
		1524
4560	Serge	1525	static enum drm_mode_status
		1526	intel_sdvo_mode_valid(struct drm_connector *connector,
6084	serge	1527	struct drm_display_mode *mode)
2330	Serge	1528	{
		1529	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1530
		1531	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		1532	return MODE_NO_DBLESCAN;
		1533
		1534	if (intel_sdvo->pixel_clock_min > mode->clock)
		1535	return MODE_CLOCK_LOW;
		1536
		1537	if (intel_sdvo->pixel_clock_max < mode->clock)
		1538	return MODE_CLOCK_HIGH;
		1539
		1540	if (intel_sdvo->is_lvds) {
		1541	if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
		1542	return MODE_PANEL;
		1543
		1544	if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
		1545	return MODE_PANEL;
		1546	}
		1547
		1548	return MODE_OK;
		1549	}
		1550
		1551	static bool intel_sdvo_get_capabilities(struct intel_sdvo intel_sdvo, struct intel_sdvo_caps caps)
		1552	{
		1553	BUILD_BUG_ON(sizeof(*caps) != 8);
		1554	if (!intel_sdvo_get_value(intel_sdvo,
		1555	SDVO_CMD_GET_DEVICE_CAPS,
		1556	caps, sizeof(*caps)))
		1557	return false;
		1558
		1559	DRM_DEBUG_KMS("SDVO capabilities:\n"
		1560	" vendor_id: %d\n"
		1561	" device_id: %d\n"
		1562	" device_rev_id: %d\n"
		1563	" sdvo_version_major: %d\n"
		1564	" sdvo_version_minor: %d\n"
		1565	" sdvo_inputs_mask: %d\n"
		1566	" smooth_scaling: %d\n"
		1567	" sharp_scaling: %d\n"
		1568	" up_scaling: %d\n"
		1569	" down_scaling: %d\n"
		1570	" stall_support: %d\n"
		1571	" output_flags: %d\n",
		1572	caps->vendor_id,
		1573	caps->device_id,
		1574	caps->device_rev_id,
		1575	caps->sdvo_version_major,
		1576	caps->sdvo_version_minor,
		1577	caps->sdvo_inputs_mask,
		1578	caps->smooth_scaling,
		1579	caps->sharp_scaling,
		1580	caps->up_scaling,
		1581	caps->down_scaling,
		1582	caps->stall_support,
		1583	caps->output_flags);
		1584
		1585	return true;
		1586	}
		1587
3031	serge	1588	static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
2330	Serge	1589	{
3031	serge	1590	struct drm_device *dev = intel_sdvo->base.base.dev;
		1591	uint16_t hotplug;
2330	Serge	1592
6084	serge	1593	if (!I915_HAS_HOTPLUG(dev))
		1594	return 0;
		1595
3031	serge	1596	/* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
		1597	* on the line. */
		1598	if (IS_I945G(dev) \|\| IS_I945GM(dev))
		1599	return 0;
		1600
		1601	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
		1602	&hotplug, sizeof(hotplug)))
		1603	return 0;
		1604
		1605	return hotplug;
2330	Serge	1606	}
		1607
2342	Serge	1608	static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
2330	Serge	1609	{
4104	Serge	1610	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2330	Serge	1611
3031	serge	1612	intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
		1613	&intel_sdvo->hotplug_active, 2);
2330	Serge	1614	}
		1615
		1616	static bool
		1617	intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
		1618	{
		1619	/* Is there more than one type of output? */
2342	Serge	1620	return hweight16(intel_sdvo->caps.output_flags) > 1;
2330	Serge	1621	}
		1622
		1623	static struct edid *
		1624	intel_sdvo_get_edid(struct drm_connector *connector)
		1625	{
		1626	struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
		1627	return drm_get_edid(connector, &sdvo->ddc);
		1628	}
		1629
		1630	/* Mac mini hack -- use the same DDC as the analog connector */
		1631	static struct edid *
		1632	intel_sdvo_get_analog_edid(struct drm_connector *connector)
		1633	{
		1634	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1635
		1636	return drm_get_edid(connector,
3031	serge	1637	intel_gmbus_get_adapter(dev_priv,
4104	Serge	1638	dev_priv->vbt.crt_ddc_pin));
2330	Serge	1639	}
		1640
3031	serge	1641	static enum drm_connector_status
2342	Serge	1642	intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2330	Serge	1643	{
		1644	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1645	enum drm_connector_status status;
		1646	struct edid *edid;
		1647
		1648	edid = intel_sdvo_get_edid(connector);
		1649
		1650	if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
		1651	u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
		1652
		1653	/*
		1654	* Don't use the 1 as the argument of DDC bus switch to get
		1655	* the EDID. It is used for SDVO SPD ROM.
		1656	*/
		1657	for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
		1658	intel_sdvo->ddc_bus = ddc;
		1659	edid = intel_sdvo_get_edid(connector);
		1660	if (edid)
		1661	break;
		1662	}
		1663	/*
		1664	* If we found the EDID on the other bus,
		1665	* assume that is the correct DDC bus.
		1666	*/
		1667	if (edid == NULL)
		1668	intel_sdvo->ddc_bus = saved_ddc;
		1669	}
		1670
		1671	/*
		1672	* When there is no edid and no monitor is connected with VGA
		1673	* port, try to use the CRT ddc to read the EDID for DVI-connector.
		1674	*/
		1675	if (edid == NULL)
		1676	edid = intel_sdvo_get_analog_edid(connector);
		1677
		1678	status = connector_status_unknown;
		1679	if (edid != NULL) {
		1680	/* DDC bus is shared, match EDID to connector type */
		1681	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
		1682	status = connector_status_connected;
		1683	if (intel_sdvo->is_hdmi) {
		1684	intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
		1685	intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
3480	Serge	1686	intel_sdvo->rgb_quant_range_selectable =
		1687	drm_rgb_quant_range_selectable(edid);
2330	Serge	1688	}
		1689	} else
		1690	status = connector_status_disconnected;
		1691	kfree(edid);
		1692	}
		1693
		1694	if (status == connector_status_connected) {
		1695	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
3031	serge	1696	if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
		1697	intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
2330	Serge	1698	}
		1699
		1700	return status;
		1701	}
		1702
2342	Serge	1703	static bool
		1704	intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
		1705	struct edid *edid)
		1706	{
		1707	bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
		1708	bool connector_is_digital = !!IS_DIGITAL(sdvo);
		1709
		1710	DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
		1711	connector_is_digital, monitor_is_digital);
		1712	return connector_is_digital == monitor_is_digital;
		1713	}
		1714
2330	Serge	1715	static enum drm_connector_status
		1716	intel_sdvo_detect(struct drm_connector *connector, bool force)
		1717	{
		1718	uint16_t response;
		1719	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1720	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1721	enum drm_connector_status ret;
		1722
4104	Serge	1723	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1724	connector->base.id, connector->name);
4104	Serge	1725
3243	Serge	1726	if (!intel_sdvo_get_value(intel_sdvo,
		1727	SDVO_CMD_GET_ATTACHED_DISPLAYS,
		1728	&response, 2))
2330	Serge	1729	return connector_status_unknown;
		1730
		1731	DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
		1732	response & 0xff, response >> 8,
		1733	intel_sdvo_connector->output_flag);
		1734
		1735	if (response == 0)
		1736	return connector_status_disconnected;
		1737
		1738	intel_sdvo->attached_output = response;
		1739
		1740	intel_sdvo->has_hdmi_monitor = false;
		1741	intel_sdvo->has_hdmi_audio = false;
3480	Serge	1742	intel_sdvo->rgb_quant_range_selectable = false;
2330	Serge	1743
		1744	if ((intel_sdvo_connector->output_flag & response) == 0)
		1745	ret = connector_status_disconnected;
		1746	else if (IS_TMDS(intel_sdvo_connector))
2342	Serge	1747	ret = intel_sdvo_tmds_sink_detect(connector);
2330	Serge	1748	else {
		1749	struct edid *edid;
		1750
		1751	/* if we have an edid check it matches the connection */
		1752	edid = intel_sdvo_get_edid(connector);
		1753	if (edid == NULL)
		1754	edid = intel_sdvo_get_analog_edid(connector);
		1755	if (edid != NULL) {
2342	Serge	1756	if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
		1757	edid))
		1758	ret = connector_status_connected;
		1759	else
2330	Serge	1760	ret = connector_status_disconnected;
2342	Serge	1761
2330	Serge	1762	kfree(edid);
		1763	} else
		1764	ret = connector_status_connected;
		1765	}
		1766
		1767	/* May update encoder flag for like clock for SDVO TV, etc.*/
		1768	if (ret == connector_status_connected) {
		1769	intel_sdvo->is_tv = false;
		1770	intel_sdvo->is_lvds = false;
		1771
4104	Serge	1772	if (response & SDVO_TV_MASK)
2330	Serge	1773	intel_sdvo->is_tv = true;
		1774	if (response & SDVO_LVDS_MASK)
		1775	intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
		1776	}
		1777
		1778	return ret;
		1779	}
		1780
		1781	static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
		1782	{
		1783	struct edid *edid;
		1784
4560	Serge	1785	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1786	connector->base.id, connector->name);
4560	Serge	1787
2330	Serge	1788	/* set the bus switch and get the modes */
		1789	edid = intel_sdvo_get_edid(connector);
		1790
		1791	/*
		1792	* Mac mini hack. On this device, the DVI-I connector shares one DDC
		1793	* link between analog and digital outputs. So, if the regular SDVO
		1794	* DDC fails, check to see if the analog output is disconnected, in
		1795	* which case we'll look there for the digital DDC data.
		1796	*/
		1797	if (edid == NULL)
		1798	edid = intel_sdvo_get_analog_edid(connector);
		1799
		1800	if (edid != NULL) {
2342	Serge	1801	if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
		1802	edid)) {
2330	Serge	1803	drm_mode_connector_update_edid_property(connector, edid);
		1804	drm_add_edid_modes(connector, edid);
		1805	}
		1806
		1807	kfree(edid);
		1808	}
		1809	}
		1810
		1811	/*
		1812	* Set of SDVO TV modes.
		1813	* Note! This is in reply order (see loop in get_tv_modes).
		1814	* XXX: all 60Hz refresh?
		1815	*/
		1816	static const struct drm_display_mode sdvo_tv_modes[] = {
		1817	{ DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
		1818	416, 0, 200, 201, 232, 233, 0,
		1819	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1820	{ DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
		1821	416, 0, 240, 241, 272, 273, 0,
		1822	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1823	{ DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
		1824	496, 0, 300, 301, 332, 333, 0,
		1825	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1826	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
		1827	736, 0, 350, 351, 382, 383, 0,
		1828	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1829	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
		1830	736, 0, 400, 401, 432, 433, 0,
		1831	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1832	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
		1833	736, 0, 480, 481, 512, 513, 0,
		1834	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1835	{ DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
		1836	800, 0, 480, 481, 512, 513, 0,
		1837	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1838	{ DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
		1839	800, 0, 576, 577, 608, 609, 0,
		1840	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1841	{ DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
		1842	816, 0, 350, 351, 382, 383, 0,
		1843	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1844	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
		1845	816, 0, 400, 401, 432, 433, 0,
		1846	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1847	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
		1848	816, 0, 480, 481, 512, 513, 0,
		1849	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1850	{ DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
		1851	816, 0, 540, 541, 572, 573, 0,
		1852	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1853	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
		1854	816, 0, 576, 577, 608, 609, 0,
		1855	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1856	{ DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
		1857	864, 0, 576, 577, 608, 609, 0,
		1858	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1859	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
		1860	896, 0, 600, 601, 632, 633, 0,
		1861	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1862	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
		1863	928, 0, 624, 625, 656, 657, 0,
		1864	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1865	{ DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
		1866	1016, 0, 766, 767, 798, 799, 0,
		1867	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1868	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
		1869	1120, 0, 768, 769, 800, 801, 0,
		1870	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1871	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
		1872	1376, 0, 1024, 1025, 1056, 1057, 0,
		1873	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC) },
		1874	};
		1875
		1876	static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
		1877	{
		1878	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1879	struct intel_sdvo_sdtv_resolution_request tv_res;
		1880	uint32_t reply = 0, format_map = 0;
		1881	int i;
		1882
4560	Serge	1883	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1884	connector->base.id, connector->name);
4560	Serge	1885
2330	Serge	1886	/* Read the list of supported input resolutions for the selected TV
		1887	* format.
		1888	*/
		1889	format_map = 1 << intel_sdvo->tv_format_index;
		1890	memcpy(&tv_res, &format_map,
		1891	min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
		1892
		1893	if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
		1894	return;
		1895
		1896	BUILD_BUG_ON(sizeof(tv_res) != 3);
		1897	if (!intel_sdvo_write_cmd(intel_sdvo,
		1898	SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
		1899	&tv_res, sizeof(tv_res)))
		1900	return;
		1901	if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
		1902	return;
		1903
		1904	for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
		1905	if (reply & (1 << i)) {
		1906	struct drm_display_mode *nmode;
		1907	nmode = drm_mode_duplicate(connector->dev,
		1908	&sdvo_tv_modes[i]);
		1909	if (nmode)
		1910	drm_mode_probed_add(connector, nmode);
		1911	}
		1912	}
		1913
		1914	static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
		1915	{
		1916	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1917	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		1918	struct drm_display_mode *newmode;
		1919
4560	Serge	1920	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5060	serge	1921	connector->base.id, connector->name);
4560	Serge	1922
2330	Serge	1923	/*
3746	Serge	1924	* Fetch modes from VBT. For SDVO prefer the VBT mode since some
4104	Serge	1925	* SDVO->LVDS transcoders can't cope with the EDID mode.
3746	Serge	1926	*/
4104	Serge	1927	if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2330	Serge	1928	newmode = drm_mode_duplicate(connector->dev,
4104	Serge	1929	dev_priv->vbt.sdvo_lvds_vbt_mode);
2330	Serge	1930	if (newmode != NULL) {
		1931	/* Guarantee the mode is preferred */
		1932	newmode->type = (DRM_MODE_TYPE_PREFERRED \|
		1933	DRM_MODE_TYPE_DRIVER);
		1934	drm_mode_probed_add(connector, newmode);
		1935	}
		1936	}
		1937
4104	Serge	1938	/*
		1939	* Attempt to get the mode list from DDC.
		1940	* Assume that the preferred modes are
		1941	* arranged in priority order.
		1942	*/
		1943	intel_ddc_get_modes(connector, &intel_sdvo->ddc);
		1944
2330	Serge	1945	list_for_each_entry(newmode, &connector->probed_modes, head) {
		1946	if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
		1947	intel_sdvo->sdvo_lvds_fixed_mode =
		1948	drm_mode_duplicate(connector->dev, newmode);
		1949
		1950	intel_sdvo->is_lvds = true;
		1951	break;
		1952	}
		1953	}
		1954	}
		1955
		1956	static int intel_sdvo_get_modes(struct drm_connector *connector)
		1957	{
		1958	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1959
		1960	if (IS_TV(intel_sdvo_connector))
		1961	intel_sdvo_get_tv_modes(connector);
		1962	else if (IS_LVDS(intel_sdvo_connector))
		1963	intel_sdvo_get_lvds_modes(connector);
		1964	else
		1965	intel_sdvo_get_ddc_modes(connector);
		1966
		1967	return !list_empty(&connector->probed_modes);
		1968	}
		1969
		1970	static void intel_sdvo_destroy(struct drm_connector *connector)
		1971	{
		1972	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		1973
		1974	drm_connector_cleanup(connector);
3243	Serge	1975	kfree(intel_sdvo_connector);
2330	Serge	1976	}
		1977
3031	serge	1978	static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
		1979	{
		1980	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		1981	struct edid *edid;
		1982	bool has_audio = false;
2330	Serge	1983
3031	serge	1984	if (!intel_sdvo->is_hdmi)
		1985	return false;
2330	Serge	1986
3031	serge	1987	edid = intel_sdvo_get_edid(connector);
		1988	if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
		1989	has_audio = drm_detect_monitor_audio(edid);
		1990	kfree(edid);
2330	Serge	1991
3031	serge	1992	return has_audio;
		1993	}
2330	Serge	1994
		1995	static int
		1996	intel_sdvo_set_property(struct drm_connector *connector,
		1997	struct drm_property *property,
		1998	uint64_t val)
		1999	{
		2000	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
		2001	struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
		2002	struct drm_i915_private *dev_priv = connector->dev->dev_private;
		2003	uint16_t temp_value;
		2004	uint8_t cmd;
		2005	int ret;
		2006
3243	Serge	2007	ret = drm_object_property_set_value(&connector->base, property, val);
2330	Serge	2008	if (ret)
		2009	return ret;
		2010
		2011	if (property == dev_priv->force_audio_property) {
		2012	int i = val;
		2013	bool has_audio;
		2014
		2015	if (i == intel_sdvo_connector->force_audio)
		2016	return 0;
		2017
		2018	intel_sdvo_connector->force_audio = i;
		2019
3031	serge	2020	if (i == HDMI_AUDIO_AUTO)
2330	Serge	2021	has_audio = intel_sdvo_detect_hdmi_audio(connector);
		2022	else
3031	serge	2023	has_audio = (i == HDMI_AUDIO_ON);
2330	Serge	2024
		2025	if (has_audio == intel_sdvo->has_hdmi_audio)
		2026	return 0;
		2027
		2028	intel_sdvo->has_hdmi_audio = has_audio;
		2029	goto done;
		2030	}
		2031
		2032	if (property == dev_priv->broadcast_rgb_property) {
3746	Serge	2033	bool old_auto = intel_sdvo->color_range_auto;
		2034	uint32_t old_range = intel_sdvo->color_range;
		2035
3480	Serge	2036	switch (val) {
		2037	case INTEL_BROADCAST_RGB_AUTO:
		2038	intel_sdvo->color_range_auto = true;
		2039	break;
		2040	case INTEL_BROADCAST_RGB_FULL:
		2041	intel_sdvo->color_range_auto = false;
		2042	intel_sdvo->color_range = 0;
		2043	break;
		2044	case INTEL_BROADCAST_RGB_LIMITED:
		2045	intel_sdvo->color_range_auto = false;
3746	Serge	2046	/* FIXME: this bit is only valid when using TMDS
		2047	* encoding and 8 bit per color mode. */
		2048	intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
3480	Serge	2049	break;
		2050	default:
		2051	return -EINVAL;
		2052	}
3746	Serge	2053
		2054	if (old_auto == intel_sdvo->color_range_auto &&
		2055	old_range == intel_sdvo->color_range)
		2056	return 0;
		2057
2330	Serge	2058	goto done;
		2059	}
		2060
6084	serge	2061	if (property == connector->dev->mode_config.aspect_ratio_property) {
		2062	switch (val) {
		2063	case DRM_MODE_PICTURE_ASPECT_NONE:
		2064	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
		2065	break;
		2066	case DRM_MODE_PICTURE_ASPECT_4_3:
		2067	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
		2068	break;
		2069	case DRM_MODE_PICTURE_ASPECT_16_9:
		2070	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
		2071	break;
		2072	default:
		2073	return -EINVAL;
		2074	}
		2075	goto done;
		2076	}
		2077
2330	Serge	2078	#define CHECK_PROPERTY(name, NAME) \
		2079	if (intel_sdvo_connector->name == property) { \
		2080	if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
		2081	if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
		2082	cmd = SDVO_CMD_SET_##NAME; \
		2083	intel_sdvo_connector->cur_##name = temp_value; \
		2084	goto set_value; \
		2085	}
		2086
		2087	if (property == intel_sdvo_connector->tv_format) {
		2088	if (val >= TV_FORMAT_NUM)
		2089	return -EINVAL;
		2090
		2091	if (intel_sdvo->tv_format_index ==
		2092	intel_sdvo_connector->tv_format_supported[val])
		2093	return 0;
		2094
		2095	intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
		2096	goto done;
		2097	} else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
		2098	temp_value = val;
		2099	if (intel_sdvo_connector->left == property) {
3243	Serge	2100	drm_object_property_set_value(&connector->base,
2330	Serge	2101	intel_sdvo_connector->right, val);
		2102	if (intel_sdvo_connector->left_margin == temp_value)
		2103	return 0;
		2104
		2105	intel_sdvo_connector->left_margin = temp_value;
		2106	intel_sdvo_connector->right_margin = temp_value;
		2107	temp_value = intel_sdvo_connector->max_hscan -
		2108	intel_sdvo_connector->left_margin;
		2109	cmd = SDVO_CMD_SET_OVERSCAN_H;
		2110	goto set_value;
		2111	} else if (intel_sdvo_connector->right == property) {
3243	Serge	2112	drm_object_property_set_value(&connector->base,
2330	Serge	2113	intel_sdvo_connector->left, val);
		2114	if (intel_sdvo_connector->right_margin == temp_value)
		2115	return 0;
		2116
		2117	intel_sdvo_connector->left_margin = temp_value;
		2118	intel_sdvo_connector->right_margin = temp_value;
		2119	temp_value = intel_sdvo_connector->max_hscan -
		2120	intel_sdvo_connector->left_margin;
		2121	cmd = SDVO_CMD_SET_OVERSCAN_H;
		2122	goto set_value;
		2123	} else if (intel_sdvo_connector->top == property) {
3243	Serge	2124	drm_object_property_set_value(&connector->base,
2330	Serge	2125	intel_sdvo_connector->bottom, val);
		2126	if (intel_sdvo_connector->top_margin == temp_value)
		2127	return 0;
		2128
		2129	intel_sdvo_connector->top_margin = temp_value;
		2130	intel_sdvo_connector->bottom_margin = temp_value;
		2131	temp_value = intel_sdvo_connector->max_vscan -
		2132	intel_sdvo_connector->top_margin;
		2133	cmd = SDVO_CMD_SET_OVERSCAN_V;
		2134	goto set_value;
		2135	} else if (intel_sdvo_connector->bottom == property) {
3243	Serge	2136	drm_object_property_set_value(&connector->base,
2330	Serge	2137	intel_sdvo_connector->top, val);
		2138	if (intel_sdvo_connector->bottom_margin == temp_value)
		2139	return 0;
		2140
		2141	intel_sdvo_connector->top_margin = temp_value;
		2142	intel_sdvo_connector->bottom_margin = temp_value;
		2143	temp_value = intel_sdvo_connector->max_vscan -
		2144	intel_sdvo_connector->top_margin;
		2145	cmd = SDVO_CMD_SET_OVERSCAN_V;
		2146	goto set_value;
		2147	}
		2148	CHECK_PROPERTY(hpos, HPOS)
		2149	CHECK_PROPERTY(vpos, VPOS)
		2150	CHECK_PROPERTY(saturation, SATURATION)
		2151	CHECK_PROPERTY(contrast, CONTRAST)
		2152	CHECK_PROPERTY(hue, HUE)
		2153	CHECK_PROPERTY(brightness, BRIGHTNESS)
		2154	CHECK_PROPERTY(sharpness, SHARPNESS)
		2155	CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
		2156	CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
		2157	CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
		2158	CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
		2159	CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
		2160	CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
		2161	}
		2162
		2163	return -EINVAL; /* unknown property */
		2164
		2165	set_value:
		2166	if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
		2167	return -EIO;
		2168
		2169
		2170	done:
3480	Serge	2171	if (intel_sdvo->base.base.crtc)
		2172	intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2330	Serge	2173
		2174	return 0;
		2175	#undef CHECK_PROPERTY
		2176	}
		2177
		2178	static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
6084	serge	2179	.dpms = drm_atomic_helper_connector_dpms,
2330	Serge	2180	.detect = intel_sdvo_detect,
		2181	.fill_modes = drm_helper_probe_single_connector_modes,
		2182	.set_property = intel_sdvo_set_property,
6084	serge	2183	.atomic_get_property = intel_connector_atomic_get_property,
2330	Serge	2184	.destroy = intel_sdvo_destroy,
6084	serge	2185	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
		2186	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2330	Serge	2187	};
		2188
		2189	static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
		2190	.get_modes = intel_sdvo_get_modes,
		2191	.mode_valid = intel_sdvo_mode_valid,
		2192	.best_encoder = intel_best_encoder,
		2193	};
		2194
		2195	static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
		2196	{
4104	Serge	2197	struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2330	Serge	2198
		2199	if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
		2200	drm_mode_destroy(encoder->dev,
		2201	intel_sdvo->sdvo_lvds_fixed_mode);
		2202
3243	Serge	2203	i2c_del_adapter(&intel_sdvo->ddc);
2330	Serge	2204	intel_encoder_destroy(encoder);
		2205	}
		2206
		2207	static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
		2208	.destroy = intel_sdvo_enc_destroy,
		2209	};
		2210
		2211	static void
		2212	intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
		2213	{
		2214	uint16_t mask = 0;
		2215	unsigned int num_bits;
		2216
		2217	/* Make a mask of outputs less than or equal to our own priority in the
		2218	* list.
		2219	*/
		2220	switch (sdvo->controlled_output) {
		2221	case SDVO_OUTPUT_LVDS1:
		2222	mask \|= SDVO_OUTPUT_LVDS1;
		2223	case SDVO_OUTPUT_LVDS0:
		2224	mask \|= SDVO_OUTPUT_LVDS0;
		2225	case SDVO_OUTPUT_TMDS1:
		2226	mask \|= SDVO_OUTPUT_TMDS1;
		2227	case SDVO_OUTPUT_TMDS0:
		2228	mask \|= SDVO_OUTPUT_TMDS0;
		2229	case SDVO_OUTPUT_RGB1:
		2230	mask \|= SDVO_OUTPUT_RGB1;
		2231	case SDVO_OUTPUT_RGB0:
		2232	mask \|= SDVO_OUTPUT_RGB0;
		2233	break;
		2234	}
		2235
		2236	/* Count bits to find what number we are in the priority list. */
		2237	mask &= sdvo->caps.output_flags;
		2238	num_bits = hweight16(mask);
		2239	/* If more than 3 outputs, default to DDC bus 3 for now. */
		2240	if (num_bits > 3)
		2241	num_bits = 3;
		2242
		2243	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
		2244	sdvo->ddc_bus = 1 << num_bits;
		2245	}
		2246
		2247	/**
		2248	* Choose the appropriate DDC bus for control bus switch command for this
		2249	* SDVO output based on the controlled output.
		2250	*
		2251	* DDC bus number assignment is in a priority order of RGB outputs, then TMDS
		2252	* outputs, then LVDS outputs.
		2253	*/
		2254	static void
		2255	intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
6084	serge	2256	struct intel_sdvo *sdvo)
2330	Serge	2257	{
		2258	struct sdvo_device_mapping *mapping;
		2259
6937	serge	2260	if (sdvo->port == PORT_B)
2330	Serge	2261	mapping = &(dev_priv->sdvo_mappings[0]);
		2262	else
		2263	mapping = &(dev_priv->sdvo_mappings[1]);
		2264
		2265	if (mapping->initialized)
		2266	sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
		2267	else
		2268	intel_sdvo_guess_ddc_bus(sdvo);
		2269	}
		2270
		2271	static void
		2272	intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
6084	serge	2273	struct intel_sdvo *sdvo)
2330	Serge	2274	{
		2275	struct sdvo_device_mapping *mapping;
2342	Serge	2276	u8 pin;
2330	Serge	2277
6937	serge	2278	if (sdvo->port == PORT_B)
2330	Serge	2279	mapping = &dev_priv->sdvo_mappings[0];
		2280	else
		2281	mapping = &dev_priv->sdvo_mappings[1];
		2282
6084	serge	2283	if (mapping->initialized &&
		2284	intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
3243	Serge	2285	pin = mapping->i2c_pin;
		2286	else
6084	serge	2287	pin = GMBUS_PIN_DPB;
2330	Serge	2288
6084	serge	2289	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
3243	Serge	2290
		2291	/* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
		2292	* our code totally fails once we start using gmbus. Hence fall back to
		2293	* bit banging for now. */
6084	serge	2294	intel_gmbus_force_bit(sdvo->i2c, true);
2330	Serge	2295	}
		2296
3243	Serge	2297	/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
		2298	static void
		2299	intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
		2300	{
		2301	intel_gmbus_force_bit(sdvo->i2c, false);
		2302	}
		2303
2330	Serge	2304	static bool
		2305	intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
		2306	{
		2307	return intel_sdvo_check_supp_encode(intel_sdvo);
		2308	}
		2309
		2310	static u8
3031	serge	2311	intel_sdvo_get_slave_addr(struct drm_device dev, struct intel_sdvo sdvo)
2330	Serge	2312	{
		2313	struct drm_i915_private *dev_priv = dev->dev_private;
		2314	struct sdvo_device_mapping my_mapping, other_mapping;
		2315
6937	serge	2316	if (sdvo->port == PORT_B) {
2330	Serge	2317	my_mapping = &dev_priv->sdvo_mappings[0];
		2318	other_mapping = &dev_priv->sdvo_mappings[1];
		2319	} else {
		2320	my_mapping = &dev_priv->sdvo_mappings[1];
		2321	other_mapping = &dev_priv->sdvo_mappings[0];
		2322	}
		2323
		2324	/* If the BIOS described our SDVO device, take advantage of it. */
		2325	if (my_mapping->slave_addr)
		2326	return my_mapping->slave_addr;
		2327
		2328	/* If the BIOS only described a different SDVO device, use the
		2329	* address that it isn't using.
		2330	*/
		2331	if (other_mapping->slave_addr) {
		2332	if (other_mapping->slave_addr == 0x70)
		2333	return 0x72;
		2334	else
		2335	return 0x70;
		2336	}
		2337
		2338	/* No SDVO device info is found for another DVO port,
		2339	* so use mapping assumption we had before BIOS parsing.
		2340	*/
6937	serge	2341	if (sdvo->port == PORT_B)
2330	Serge	2342	return 0x70;
		2343	else
		2344	return 0x72;
		2345	}
		2346
		2347	static void
5060	serge	2348	intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
		2349	{
		2350	struct drm_connector *drm_connector;
		2351	struct intel_sdvo *sdvo_encoder;
		2352
		2353	drm_connector = &intel_connector->base;
		2354	sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
		2355
6103	serge	2356	sysfs_remove_link(&drm_connector->kdev->kobj,
		2357	sdvo_encoder->ddc.dev.kobj.name);
5060	serge	2358	intel_connector_unregister(intel_connector);
		2359	}
		2360
		2361	static int
2330	Serge	2362	intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
		2363	struct intel_sdvo *encoder)
		2364	{
5060	serge	2365	struct drm_connector *drm_connector;
		2366	int ret;
		2367
		2368	drm_connector = &connector->base.base;
		2369	ret = drm_connector_init(encoder->base.base.dev,
		2370	drm_connector,
2330	Serge	2371	&intel_sdvo_connector_funcs,
		2372	connector->base.base.connector_type);
5060	serge	2373	if (ret < 0)
		2374	return ret;
2330	Serge	2375
5060	serge	2376	drm_connector_helper_add(drm_connector,
2330	Serge	2377	&intel_sdvo_connector_helper_funcs);
		2378
3031	serge	2379	connector->base.base.interlace_allowed = 1;
2330	Serge	2380	connector->base.base.doublescan_allowed = 0;
		2381	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
3031	serge	2382	connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
5060	serge	2383	connector->base.unregister = intel_sdvo_connector_unregister;
2330	Serge	2384
		2385	intel_connector_attach_encoder(&connector->base, &encoder->base);
5367	serge	2386	ret = drm_connector_register(drm_connector);
		2387	if (ret < 0)
		2388	goto err1;
5060	serge	2389
6103	serge	2390	ret = sysfs_create_link(&drm_connector->kdev->kobj,
		2391	&encoder->ddc.dev.kobj,
		2392	encoder->ddc.dev.kobj.name);
		2393	if (ret < 0)
		2394	goto err2;
		2395
5367	serge	2396	return 0;
		2397
		2398	err2:
		2399	drm_connector_unregister(drm_connector);
		2400	err1:
		2401	drm_connector_cleanup(drm_connector);
		2402
5060	serge	2403	return ret;
2330	Serge	2404	}
		2405
		2406	static void
3480	Serge	2407	intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
		2408	struct intel_sdvo_connector *connector)
2330	Serge	2409	{
		2410	struct drm_device *dev = connector->base.base.dev;
		2411
		2412	intel_attach_force_audio_property(&connector->base.base);
3480	Serge	2413	if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2330	Serge	2414	intel_attach_broadcast_rgb_property(&connector->base.base);
3480	Serge	2415	intel_sdvo->color_range_auto = true;
		2416	}
6084	serge	2417	intel_attach_aspect_ratio_property(&connector->base.base);
		2418	intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2330	Serge	2419	}
		2420
6084	serge	2421	static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
		2422	{
		2423	struct intel_sdvo_connector *sdvo_connector;
		2424
		2425	sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
		2426	if (!sdvo_connector)
		2427	return NULL;
		2428
		2429	if (intel_connector_init(&sdvo_connector->base) < 0) {
		2430	kfree(sdvo_connector);
		2431	return NULL;
		2432	}
		2433
		2434	return sdvo_connector;
		2435	}
		2436
2330	Serge	2437	static bool
		2438	intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
		2439	{
		2440	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2441	struct drm_connector *connector;
2342	Serge	2442	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2330	Serge	2443	struct intel_connector *intel_connector;
		2444	struct intel_sdvo_connector *intel_sdvo_connector;
		2445
4560	Serge	2446	DRM_DEBUG_KMS("initialising DVI device %d\n", device);
		2447
6084	serge	2448	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2449	if (!intel_sdvo_connector)
		2450	return false;
		2451
		2452	if (device == 0) {
		2453	intel_sdvo->controlled_output \|= SDVO_OUTPUT_TMDS0;
		2454	intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
		2455	} else if (device == 1) {
		2456	intel_sdvo->controlled_output \|= SDVO_OUTPUT_TMDS1;
		2457	intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
		2458	}
		2459
		2460	intel_connector = &intel_sdvo_connector->base;
		2461	connector = &intel_connector->base;
3031	serge	2462	if (intel_sdvo_get_hotplug_support(intel_sdvo) &
		2463	intel_sdvo_connector->output_flag) {
		2464	intel_sdvo->hotplug_active \|= intel_sdvo_connector->output_flag;
2342	Serge	2465	/* Some SDVO devices have one-shot hotplug interrupts.
		2466	* Ensure that they get re-enabled when an interrupt happens.
		2467	*/
		2468	intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
		2469	intel_sdvo_enable_hotplug(intel_encoder);
3031	serge	2470	} else {
3746	Serge	2471	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT \| DRM_CONNECTOR_POLL_DISCONNECT;
2342	Serge	2472	}
2330	Serge	2473	encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
		2474	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
		2475
		2476	if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
		2477	connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
		2478	intel_sdvo->is_hdmi = true;
		2479	}
		2480
5060	serge	2481	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2482	kfree(intel_sdvo_connector);
		2483	return false;
		2484	}
		2485
2330	Serge	2486	if (intel_sdvo->is_hdmi)
3480	Serge	2487	intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2330	Serge	2488
		2489	return true;
		2490	}
		2491
		2492	static bool
		2493	intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
		2494	{
		2495	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2496	struct drm_connector *connector;
		2497	struct intel_connector *intel_connector;
		2498	struct intel_sdvo_connector *intel_sdvo_connector;
		2499
4560	Serge	2500	DRM_DEBUG_KMS("initialising TV type %d\n", type);
		2501
6084	serge	2502	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2503	if (!intel_sdvo_connector)
		2504	return false;
		2505
		2506	intel_connector = &intel_sdvo_connector->base;
		2507	connector = &intel_connector->base;
		2508	encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
		2509	connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
		2510
		2511	intel_sdvo->controlled_output \|= type;
		2512	intel_sdvo_connector->output_flag = type;
		2513
		2514	intel_sdvo->is_tv = true;
		2515
5060	serge	2516	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2517	kfree(intel_sdvo_connector);
		2518	return false;
		2519	}
2330	Serge	2520
		2521	if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
		2522	goto err;
		2523
		2524	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
		2525	goto err;
		2526
		2527	return true;
		2528
		2529	err:
5060	serge	2530	drm_connector_unregister(connector);
2330	Serge	2531	intel_sdvo_destroy(connector);
		2532	return false;
		2533	}
		2534
		2535	static bool
		2536	intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
		2537	{
		2538	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2539	struct drm_connector *connector;
		2540	struct intel_connector *intel_connector;
		2541	struct intel_sdvo_connector *intel_sdvo_connector;
		2542
4560	Serge	2543	DRM_DEBUG_KMS("initialising analog device %d\n", device);
		2544
6084	serge	2545	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2546	if (!intel_sdvo_connector)
		2547	return false;
		2548
		2549	intel_connector = &intel_sdvo_connector->base;
		2550	connector = &intel_connector->base;
3746	Serge	2551	intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2330	Serge	2552	encoder->encoder_type = DRM_MODE_ENCODER_DAC;
		2553	connector->connector_type = DRM_MODE_CONNECTOR_VGA;
		2554
		2555	if (device == 0) {
		2556	intel_sdvo->controlled_output \|= SDVO_OUTPUT_RGB0;
		2557	intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
		2558	} else if (device == 1) {
		2559	intel_sdvo->controlled_output \|= SDVO_OUTPUT_RGB1;
		2560	intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
		2561	}
		2562
5060	serge	2563	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2564	kfree(intel_sdvo_connector);
		2565	return false;
		2566	}
		2567
2330	Serge	2568	return true;
		2569	}
		2570
		2571	static bool
		2572	intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
		2573	{
		2574	struct drm_encoder *encoder = &intel_sdvo->base.base;
		2575	struct drm_connector *connector;
		2576	struct intel_connector *intel_connector;
		2577	struct intel_sdvo_connector *intel_sdvo_connector;
		2578
4560	Serge	2579	DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
		2580
6084	serge	2581	intel_sdvo_connector = intel_sdvo_connector_alloc();
2330	Serge	2582	if (!intel_sdvo_connector)
		2583	return false;
		2584
		2585	intel_connector = &intel_sdvo_connector->base;
		2586	connector = &intel_connector->base;
		2587	encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
		2588	connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
		2589
		2590	if (device == 0) {
		2591	intel_sdvo->controlled_output \|= SDVO_OUTPUT_LVDS0;
		2592	intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
		2593	} else if (device == 1) {
		2594	intel_sdvo->controlled_output \|= SDVO_OUTPUT_LVDS1;
		2595	intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
		2596	}
		2597
5060	serge	2598	if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
		2599	kfree(intel_sdvo_connector);
		2600	return false;
		2601	}
		2602
2330	Serge	2603	if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
		2604	goto err;
		2605
		2606	return true;
		2607
		2608	err:
5060	serge	2609	drm_connector_unregister(connector);
2330	Serge	2610	intel_sdvo_destroy(connector);
		2611	return false;
		2612	}
		2613
		2614	static bool
		2615	intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
		2616	{
		2617	intel_sdvo->is_tv = false;
		2618	intel_sdvo->is_lvds = false;
		2619
		2620	/* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
		2621
		2622	if (flags & SDVO_OUTPUT_TMDS0)
		2623	if (!intel_sdvo_dvi_init(intel_sdvo, 0))
		2624	return false;
		2625
		2626	if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
		2627	if (!intel_sdvo_dvi_init(intel_sdvo, 1))
		2628	return false;
		2629
		2630	/* TV has no XXX1 function block */
		2631	if (flags & SDVO_OUTPUT_SVID0)
		2632	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
		2633	return false;
		2634
		2635	if (flags & SDVO_OUTPUT_CVBS0)
		2636	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
		2637	return false;
		2638
3031	serge	2639	if (flags & SDVO_OUTPUT_YPRPB0)
		2640	if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
		2641	return false;
		2642
2330	Serge	2643	if (flags & SDVO_OUTPUT_RGB0)
		2644	if (!intel_sdvo_analog_init(intel_sdvo, 0))
		2645	return false;
		2646
		2647	if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
		2648	if (!intel_sdvo_analog_init(intel_sdvo, 1))
		2649	return false;
		2650
		2651	if (flags & SDVO_OUTPUT_LVDS0)
		2652	if (!intel_sdvo_lvds_init(intel_sdvo, 0))
		2653	return false;
		2654
		2655	if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
		2656	if (!intel_sdvo_lvds_init(intel_sdvo, 1))
		2657	return false;
		2658
		2659	if ((flags & SDVO_OUTPUT_MASK) == 0) {
		2660	unsigned char bytes[2];
		2661
		2662	intel_sdvo->controlled_output = 0;
		2663	memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
		2664	DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
		2665	SDVO_NAME(intel_sdvo),
		2666	bytes[0], bytes[1]);
		2667	return false;
		2668	}
2342	Serge	2669	intel_sdvo->base.crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
2330	Serge	2670
		2671	return true;
		2672	}
		2673
3120	serge	2674	static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
		2675	{
		2676	struct drm_device *dev = intel_sdvo->base.base.dev;
		2677	struct drm_connector connector, tmp;
		2678
		2679	list_for_each_entry_safe(connector, tmp,
		2680	&dev->mode_config.connector_list, head) {
4560	Serge	2681	if (intel_attached_encoder(connector) == &intel_sdvo->base) {
5060	serge	2682	drm_connector_unregister(connector);
3120	serge	2683	intel_sdvo_destroy(connector);
6084	serge	2684	}
3120	serge	2685	}
		2686	}
		2687
2330	Serge	2688	static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
		2689	struct intel_sdvo_connector *intel_sdvo_connector,
		2690	int type)
		2691	{
		2692	struct drm_device *dev = intel_sdvo->base.base.dev;
		2693	struct intel_sdvo_tv_format format;
		2694	uint32_t format_map, i;
		2695
		2696	if (!intel_sdvo_set_target_output(intel_sdvo, type))
		2697	return false;
		2698
		2699	BUILD_BUG_ON(sizeof(format) != 6);
		2700	if (!intel_sdvo_get_value(intel_sdvo,
		2701	SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
		2702	&format, sizeof(format)))
		2703	return false;
		2704
		2705	memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
		2706
		2707	if (format_map == 0)
		2708	return false;
		2709
		2710	intel_sdvo_connector->format_supported_num = 0;
		2711	for (i = 0 ; i < TV_FORMAT_NUM; i++)
		2712	if (format_map & (1 << i))
		2713	intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
		2714
		2715
		2716	intel_sdvo_connector->tv_format =
		2717	drm_property_create(dev, DRM_MODE_PROP_ENUM,
		2718	"mode", intel_sdvo_connector->format_supported_num);
		2719	if (!intel_sdvo_connector->tv_format)
		2720	return false;
		2721
		2722	for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
		2723	drm_property_add_enum(
		2724	intel_sdvo_connector->tv_format, i,
		2725	i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
		2726
		2727	intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
3243	Serge	2728	drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2330	Serge	2729	intel_sdvo_connector->tv_format, 0);
		2730	return true;
		2731
		2732	}
		2733
		2734	#define ENHANCEMENT(name, NAME) do { \
		2735	if (enhancements.name) { \
		2736	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) \|\| \
		2737	!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
		2738	return false; \
		2739	intel_sdvo_connector->max_##name = data_value[0]; \
		2740	intel_sdvo_connector->cur_##name = response; \
		2741	intel_sdvo_connector->name = \
3031	serge	2742	drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2330	Serge	2743	if (!intel_sdvo_connector->name) return false; \
3243	Serge	2744	drm_object_attach_property(&connector->base, \
2330	Serge	2745	intel_sdvo_connector->name, \
		2746	intel_sdvo_connector->cur_##name); \
		2747	DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
		2748	data_value[0], data_value[1], response); \
		2749	} \
2342	Serge	2750	} while (0)
2330	Serge	2751
		2752	static bool
		2753	intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
		2754	struct intel_sdvo_connector *intel_sdvo_connector,
		2755	struct intel_sdvo_enhancements_reply enhancements)
		2756	{
		2757	struct drm_device *dev = intel_sdvo->base.base.dev;
		2758	struct drm_connector *connector = &intel_sdvo_connector->base.base;
		2759	uint16_t response, data_value[2];
		2760
		2761	/* when horizontal overscan is supported, Add the left/right property */
		2762	if (enhancements.overscan_h) {
		2763	if (!intel_sdvo_get_value(intel_sdvo,
		2764	SDVO_CMD_GET_MAX_OVERSCAN_H,
		2765	&data_value, 4))
		2766	return false;
		2767
		2768	if (!intel_sdvo_get_value(intel_sdvo,
		2769	SDVO_CMD_GET_OVERSCAN_H,
		2770	&response, 2))
		2771	return false;
		2772
		2773	intel_sdvo_connector->max_hscan = data_value[0];
		2774	intel_sdvo_connector->left_margin = data_value[0] - response;
		2775	intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
		2776	intel_sdvo_connector->left =
3031	serge	2777	drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2330	Serge	2778	if (!intel_sdvo_connector->left)
		2779	return false;
		2780
3243	Serge	2781	drm_object_attach_property(&connector->base,
2330	Serge	2782	intel_sdvo_connector->left,
		2783	intel_sdvo_connector->left_margin);
		2784
		2785	intel_sdvo_connector->right =
3031	serge	2786	drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2330	Serge	2787	if (!intel_sdvo_connector->right)
		2788	return false;
		2789
3243	Serge	2790	drm_object_attach_property(&connector->base,
2330	Serge	2791	intel_sdvo_connector->right,
		2792	intel_sdvo_connector->right_margin);
		2793	DRM_DEBUG_KMS("h_overscan: max %d, "
		2794	"default %d, current %d\n",
		2795	data_value[0], data_value[1], response);
		2796	}
		2797
		2798	if (enhancements.overscan_v) {
		2799	if (!intel_sdvo_get_value(intel_sdvo,
		2800	SDVO_CMD_GET_MAX_OVERSCAN_V,
		2801	&data_value, 4))
		2802	return false;
		2803
		2804	if (!intel_sdvo_get_value(intel_sdvo,
		2805	SDVO_CMD_GET_OVERSCAN_V,
		2806	&response, 2))
		2807	return false;
		2808
		2809	intel_sdvo_connector->max_vscan = data_value[0];
		2810	intel_sdvo_connector->top_margin = data_value[0] - response;
		2811	intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
		2812	intel_sdvo_connector->top =
3031	serge	2813	drm_property_create_range(dev, 0,
		2814	"top_margin", 0, data_value[0]);
2330	Serge	2815	if (!intel_sdvo_connector->top)
		2816	return false;
		2817
3243	Serge	2818	drm_object_attach_property(&connector->base,
2330	Serge	2819	intel_sdvo_connector->top,
		2820	intel_sdvo_connector->top_margin);
		2821
		2822	intel_sdvo_connector->bottom =
3031	serge	2823	drm_property_create_range(dev, 0,
		2824	"bottom_margin", 0, data_value[0]);
2330	Serge	2825	if (!intel_sdvo_connector->bottom)
		2826	return false;
		2827
3243	Serge	2828	drm_object_attach_property(&connector->base,
2330	Serge	2829	intel_sdvo_connector->bottom,
		2830	intel_sdvo_connector->bottom_margin);
		2831	DRM_DEBUG_KMS("v_overscan: max %d, "
		2832	"default %d, current %d\n",
		2833	data_value[0], data_value[1], response);
		2834	}
		2835
		2836	ENHANCEMENT(hpos, HPOS);
		2837	ENHANCEMENT(vpos, VPOS);
		2838	ENHANCEMENT(saturation, SATURATION);
		2839	ENHANCEMENT(contrast, CONTRAST);
		2840	ENHANCEMENT(hue, HUE);
		2841	ENHANCEMENT(sharpness, SHARPNESS);
		2842	ENHANCEMENT(brightness, BRIGHTNESS);
		2843	ENHANCEMENT(flicker_filter, FLICKER_FILTER);
		2844	ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
		2845	ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
		2846	ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
		2847	ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
		2848
		2849	if (enhancements.dot_crawl) {
		2850	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
		2851	return false;
		2852
		2853	intel_sdvo_connector->max_dot_crawl = 1;
		2854	intel_sdvo_connector->cur_dot_crawl = response & 0x1;
		2855	intel_sdvo_connector->dot_crawl =
3031	serge	2856	drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2330	Serge	2857	if (!intel_sdvo_connector->dot_crawl)
		2858	return false;
		2859
3243	Serge	2860	drm_object_attach_property(&connector->base,
2330	Serge	2861	intel_sdvo_connector->dot_crawl,
		2862	intel_sdvo_connector->cur_dot_crawl);
		2863	DRM_DEBUG_KMS("dot crawl: current %d\n", response);
		2864	}
		2865
		2866	return true;
		2867	}
		2868
		2869	static bool
		2870	intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
		2871	struct intel_sdvo_connector *intel_sdvo_connector,
		2872	struct intel_sdvo_enhancements_reply enhancements)
		2873	{
		2874	struct drm_device *dev = intel_sdvo->base.base.dev;
		2875	struct drm_connector *connector = &intel_sdvo_connector->base.base;
		2876	uint16_t response, data_value[2];
		2877
		2878	ENHANCEMENT(brightness, BRIGHTNESS);
		2879
		2880	return true;
		2881	}
		2882	#undef ENHANCEMENT
		2883
		2884	static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
		2885	struct intel_sdvo_connector *intel_sdvo_connector)
		2886	{
		2887	union {
		2888	struct intel_sdvo_enhancements_reply reply;
		2889	uint16_t response;
		2890	} enhancements;
		2891
		2892	BUILD_BUG_ON(sizeof(enhancements) != 2);
		2893
		2894	enhancements.response = 0;
		2895	intel_sdvo_get_value(intel_sdvo,
		2896	SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
		2897	&enhancements, sizeof(enhancements));
		2898	if (enhancements.response == 0) {
		2899	DRM_DEBUG_KMS("No enhancement is supported\n");
		2900	return true;
		2901	}
		2902
		2903	if (IS_TV(intel_sdvo_connector))
		2904	return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2342	Serge	2905	else if (IS_LVDS(intel_sdvo_connector))
2330	Serge	2906	return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
		2907	else
		2908	return true;
		2909	}
		2910
		2911	static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
		2912	struct i2c_msg *msgs,
		2913	int num)
		2914	{
		2915	struct intel_sdvo *sdvo = adapter->algo_data;
		2916
		2917	if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
		2918	return -EIO;
		2919
		2920	return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
		2921	}
		2922
		2923	static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
		2924	{
		2925	struct intel_sdvo *sdvo = adapter->algo_data;
		2926	return sdvo->i2c->algo->functionality(sdvo->i2c);
		2927	}
		2928
		2929	static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
		2930	.master_xfer = intel_sdvo_ddc_proxy_xfer,
		2931	.functionality = intel_sdvo_ddc_proxy_func
		2932	};
		2933
		2934	static bool
		2935	intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
		2936	struct drm_device *dev)
		2937	{
3031	serge	2938	sdvo->ddc.owner = THIS_MODULE;
2330	Serge	2939	sdvo->ddc.class = I2C_CLASS_DDC;
		2940	snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
		2941	sdvo->ddc.dev.parent = &dev->pdev->dev;
		2942	sdvo->ddc.algo_data = sdvo;
		2943	sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
		2944
3243	Serge	2945	return i2c_add_adapter(&sdvo->ddc) == 0;
2330	Serge	2946	}
		2947
6937	serge	2948	static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
		2949	enum port port)
2330	Serge	2950	{
6937	serge	2951	if (HAS_PCH_SPLIT(dev_priv))
		2952	WARN_ON(port != PORT_B);
		2953	else
		2954	WARN_ON(port != PORT_B && port != PORT_C);
		2955	}
		2956
		2957	bool intel_sdvo_init(struct drm_device *dev,
		2958	i915_reg_t sdvo_reg, enum port port)
		2959	{
6084	serge	2960	struct drm_i915_private *dev_priv = dev->dev_private;
		2961	struct intel_encoder *intel_encoder;
		2962	struct intel_sdvo *intel_sdvo;
		2963	int i;
6937	serge	2964
		2965	assert_sdvo_port_valid(dev_priv, port);
		2966
4560	Serge	2967	intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
6084	serge	2968	if (!intel_sdvo)
		2969	return false;
2330	Serge	2970
6084	serge	2971	intel_sdvo->sdvo_reg = sdvo_reg;
6937	serge	2972	intel_sdvo->port = port;
3031	serge	2973	intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
6084	serge	2974	intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3243	Serge	2975	if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
		2976	goto err_i2c_bus;
2330	Serge	2977
6084	serge	2978	/* encoder type will be decided later */
		2979	intel_encoder = &intel_sdvo->base;
		2980	intel_encoder->type = INTEL_OUTPUT_SDVO;
6937	serge	2981	drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0,
		2982	NULL);
2330	Serge	2983
6084	serge	2984	/* Read the regs to test if we can talk to the device */
		2985	for (i = 0; i < 0x40; i++) {
		2986	u8 byte;
2330	Serge	2987
6084	serge	2988	if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3031	serge	2989	DRM_DEBUG_KMS("No SDVO device found on %s\n",
		2990	SDVO_NAME(intel_sdvo));
6084	serge	2991	goto err;
		2992	}
		2993	}
2330	Serge	2994
3746	Serge	2995	intel_encoder->compute_config = intel_sdvo_compute_config;
6084	serge	2996	if (HAS_PCH_SPLIT(dev)) {
		2997	intel_encoder->disable = pch_disable_sdvo;
		2998	intel_encoder->post_disable = pch_post_disable_sdvo;
		2999	} else {
		3000	intel_encoder->disable = intel_disable_sdvo;
		3001	}
5060	serge	3002	intel_encoder->pre_enable = intel_sdvo_pre_enable;
3031	serge	3003	intel_encoder->enable = intel_enable_sdvo;
		3004	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
4104	Serge	3005	intel_encoder->get_config = intel_sdvo_get_config;
3031	serge	3006
6084	serge	3007	/* In default case sdvo lvds is false */
		3008	if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
		3009	goto err;
2330	Serge	3010
6084	serge	3011	if (intel_sdvo_output_setup(intel_sdvo,
		3012	intel_sdvo->caps.output_flags) != true) {
3031	serge	3013	DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
		3014	SDVO_NAME(intel_sdvo));
3120	serge	3015	/* Output_setup can leave behind connectors! */
		3016	goto err_output;
6084	serge	3017	}
2330	Serge	3018
3746	Serge	3019	/* Only enable the hotplug irq if we need it, to work around noisy
		3020	* hotplug lines.
		3021	*/
		3022	if (intel_sdvo->hotplug_active) {
6937	serge	3023	if (intel_sdvo->port == PORT_B)
		3024	intel_encoder->hpd_pin = HPD_SDVO_B;
		3025	else
		3026	intel_encoder->hpd_pin = HPD_SDVO_C;
3746	Serge	3027	}
		3028
3120	serge	3029	/*
		3030	* Cloning SDVO with anything is often impossible, since the SDVO
		3031	* encoder can request a special input timing mode. And even if that's
		3032	* not the case we have evidence that cloning a plain unscaled mode with
		3033	* VGA doesn't really work. Furthermore the cloning flags are way too
		3034	* simplistic anyway to express such constraints, so just give up on
		3035	* cloning for SDVO encoders.
		3036	*/
5060	serge	3037	intel_sdvo->base.cloneable = 0;
3120	serge	3038
6084	serge	3039	intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
2330	Serge	3040
6084	serge	3041	/* Set the input timing to the screen. Assume always input 0. */
		3042	if (!intel_sdvo_set_target_input(intel_sdvo))
3120	serge	3043	goto err_output;
2330	Serge	3044
6084	serge	3045	if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
		3046	&intel_sdvo->pixel_clock_min,
		3047	&intel_sdvo->pixel_clock_max))
3120	serge	3048	goto err_output;
2330	Serge	3049
6084	serge	3050	DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
		3051	"clock range %dMHz - %dMHz, "
		3052	"input 1: %c, input 2: %c, "
		3053	"output 1: %c, output 2: %c\n",
		3054	SDVO_NAME(intel_sdvo),
		3055	intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
		3056	intel_sdvo->caps.device_rev_id,
		3057	intel_sdvo->pixel_clock_min / 1000,
		3058	intel_sdvo->pixel_clock_max / 1000,
		3059	(intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
		3060	(intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
		3061	/* check currently supported outputs */
		3062	intel_sdvo->caps.output_flags &
		3063	(SDVO_OUTPUT_TMDS0 \| SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
		3064	intel_sdvo->caps.output_flags &
		3065	(SDVO_OUTPUT_TMDS1 \| SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
		3066	return true;
2330	Serge	3067
3120	serge	3068	err_output:
		3069	intel_sdvo_output_cleanup(intel_sdvo);
		3070
2330	Serge	3071	err:
6084	serge	3072	drm_encoder_cleanup(&intel_encoder->base);
3243	Serge	3073	i2c_del_adapter(&intel_sdvo->ddc);
		3074	err_i2c_bus:
		3075	intel_sdvo_unselect_i2c_bus(intel_sdvo);
6084	serge	3076	kfree(intel_sdvo);
2330	Serge	3077
6084	serge	3078	return false;
2330	Serge	3079	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_sdvo.c – Rev 6937