Rev 3480 | Rev 3746 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
2330 | Serge | 1 | /* |
2 | * Copyright 2006 Dave Airlie |
||
3 | * Copyright © 2006-2007 Intel Corporation |
||
4 | * Jesse Barnes |
||
5 | * |
||
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
7 | * copy of this software and associated documentation files (the "Software"), |
||
8 | * to deal in the Software without restriction, including without limitation |
||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
11 | * Software is furnished to do so, subject to the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice (including the next |
||
14 | * paragraph) shall be included in all copies or substantial portions of the |
||
15 | * Software. |
||
16 | * |
||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
||
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
||
23 | * DEALINGS IN THE SOFTWARE. |
||
24 | * |
||
25 | * Authors: |
||
26 | * Eric Anholt |
||
27 | */ |
||
28 | #include |
||
29 | #include |
||
3243 | Serge | 30 | #include |
3031 | serge | 31 | #include |
32 | #include |
||
33 | #include |
||
34 | #include |
||
2330 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2330 | Serge | 37 | #include "i915_drv.h" |
38 | #include "intel_sdvo_regs.h" |
||
39 | |||
40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
||
41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
||
42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
||
3031 | serge | 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
2330 | Serge | 44 | |
45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
||
46 | SDVO_TV_MASK) |
||
47 | |||
48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
||
49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
||
50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
||
51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
||
2342 | Serge | 52 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
2330 | Serge | 53 | |
54 | |||
55 | static const char *tv_format_names[] = { |
||
56 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
||
57 | "PAL_B" , "PAL_D" , "PAL_G" , |
||
58 | "PAL_H" , "PAL_I" , "PAL_M" , |
||
59 | "PAL_N" , "PAL_NC" , "PAL_60" , |
||
60 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
||
61 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
||
62 | "SECAM_60" |
||
63 | }; |
||
64 | |||
65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
||
66 | |||
67 | struct intel_sdvo { |
||
68 | struct intel_encoder base; |
||
69 | |||
70 | struct i2c_adapter *i2c; |
||
71 | u8 slave_addr; |
||
72 | |||
73 | struct i2c_adapter ddc; |
||
74 | |||
75 | /* Register for the SDVO device: SDVOB or SDVOC */ |
||
3031 | serge | 76 | uint32_t sdvo_reg; |
2330 | Serge | 77 | |
78 | /* Active outputs controlled by this SDVO output */ |
||
79 | uint16_t controlled_output; |
||
80 | |||
81 | /* |
||
82 | * Capabilities of the SDVO device returned by |
||
83 | * i830_sdvo_get_capabilities() |
||
84 | */ |
||
85 | struct intel_sdvo_caps caps; |
||
86 | |||
87 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
||
88 | int pixel_clock_min, pixel_clock_max; |
||
89 | |||
90 | /* |
||
91 | * For multiple function SDVO device, |
||
92 | * this is for current attached outputs. |
||
93 | */ |
||
94 | uint16_t attached_output; |
||
95 | |||
2342 | Serge | 96 | /* |
97 | * Hotplug activation bits for this device |
||
98 | */ |
||
3031 | serge | 99 | uint16_t hotplug_active; |
2342 | Serge | 100 | |
2330 | Serge | 101 | /** |
102 | * This is used to select the color range of RBG outputs in HDMI mode. |
||
103 | * It is only valid when using TMDS encoding and 8 bit per color mode. |
||
104 | */ |
||
105 | uint32_t color_range; |
||
3480 | Serge | 106 | bool color_range_auto; |
2330 | Serge | 107 | |
108 | /** |
||
109 | * This is set if we're going to treat the device as TV-out. |
||
110 | * |
||
111 | * While we have these nice friendly flags for output types that ought |
||
112 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
||
113 | * shows up as RGB1 (VGA). |
||
114 | */ |
||
115 | bool is_tv; |
||
116 | |||
3031 | serge | 117 | /* On different gens SDVOB is at different places. */ |
118 | bool is_sdvob; |
||
119 | |||
2330 | Serge | 120 | /* This is for current tv format name */ |
121 | int tv_format_index; |
||
122 | |||
123 | /** |
||
124 | * This is set if we treat the device as HDMI, instead of DVI. |
||
125 | */ |
||
126 | bool is_hdmi; |
||
127 | bool has_hdmi_monitor; |
||
128 | bool has_hdmi_audio; |
||
3480 | Serge | 129 | bool rgb_quant_range_selectable; |
2330 | Serge | 130 | |
131 | /** |
||
132 | * This is set if we detect output of sdvo device as LVDS and |
||
133 | * have a valid fixed mode to use with the panel. |
||
134 | */ |
||
135 | bool is_lvds; |
||
136 | |||
137 | /** |
||
138 | * This is sdvo fixed pannel mode pointer |
||
139 | */ |
||
140 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
||
141 | |||
142 | /* DDC bus used by this SDVO encoder */ |
||
143 | uint8_t ddc_bus; |
||
144 | |||
3031 | serge | 145 | /* |
146 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd |
||
147 | */ |
||
148 | uint8_t dtd_sdvo_flags; |
||
2330 | Serge | 149 | }; |
150 | |||
151 | struct intel_sdvo_connector { |
||
152 | struct intel_connector base; |
||
153 | |||
154 | /* Mark the type of connector */ |
||
155 | uint16_t output_flag; |
||
156 | |||
3031 | serge | 157 | enum hdmi_force_audio force_audio; |
2330 | Serge | 158 | |
159 | /* This contains all current supported TV format */ |
||
160 | u8 tv_format_supported[TV_FORMAT_NUM]; |
||
161 | int format_supported_num; |
||
162 | struct drm_property *tv_format; |
||
163 | |||
164 | /* add the property for the SDVO-TV */ |
||
165 | struct drm_property *left; |
||
166 | struct drm_property *right; |
||
167 | struct drm_property *top; |
||
168 | struct drm_property *bottom; |
||
169 | struct drm_property *hpos; |
||
170 | struct drm_property *vpos; |
||
171 | struct drm_property *contrast; |
||
172 | struct drm_property *saturation; |
||
173 | struct drm_property *hue; |
||
174 | struct drm_property *sharpness; |
||
175 | struct drm_property *flicker_filter; |
||
176 | struct drm_property *flicker_filter_adaptive; |
||
177 | struct drm_property *flicker_filter_2d; |
||
178 | struct drm_property *tv_chroma_filter; |
||
179 | struct drm_property *tv_luma_filter; |
||
180 | struct drm_property *dot_crawl; |
||
181 | |||
182 | /* add the property for the SDVO-TV/LVDS */ |
||
183 | struct drm_property *brightness; |
||
184 | |||
185 | /* Add variable to record current setting for the above property */ |
||
186 | u32 left_margin, right_margin, top_margin, bottom_margin; |
||
187 | |||
188 | /* this is to get the range of margin.*/ |
||
189 | u32 max_hscan, max_vscan; |
||
190 | u32 max_hpos, cur_hpos; |
||
191 | u32 max_vpos, cur_vpos; |
||
192 | u32 cur_brightness, max_brightness; |
||
193 | u32 cur_contrast, max_contrast; |
||
194 | u32 cur_saturation, max_saturation; |
||
195 | u32 cur_hue, max_hue; |
||
196 | u32 cur_sharpness, max_sharpness; |
||
197 | u32 cur_flicker_filter, max_flicker_filter; |
||
198 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
||
199 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
||
200 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
||
201 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
||
202 | u32 cur_dot_crawl, max_dot_crawl; |
||
203 | }; |
||
204 | |||
205 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
||
206 | { |
||
207 | return container_of(encoder, struct intel_sdvo, base.base); |
||
208 | } |
||
209 | |||
210 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
||
211 | { |
||
212 | return container_of(intel_attached_encoder(connector), |
||
213 | struct intel_sdvo, base); |
||
214 | } |
||
215 | |||
216 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
||
217 | { |
||
218 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
||
219 | } |
||
220 | |||
221 | static bool |
||
222 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
||
223 | static bool |
||
224 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
||
225 | struct intel_sdvo_connector *intel_sdvo_connector, |
||
226 | int type); |
||
227 | static bool |
||
228 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
||
229 | struct intel_sdvo_connector *intel_sdvo_connector); |
||
230 | |||
231 | /** |
||
232 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
||
233 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
||
234 | * comments in the BIOS). |
||
235 | */ |
||
236 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
||
237 | { |
||
238 | struct drm_device *dev = intel_sdvo->base.base.dev; |
||
239 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
240 | u32 bval = val, cval = val; |
||
241 | int i; |
||
242 | |||
243 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
||
244 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
||
245 | I915_READ(intel_sdvo->sdvo_reg); |
||
246 | return; |
||
247 | } |
||
248 | |||
249 | if (intel_sdvo->sdvo_reg == SDVOB) { |
||
250 | cval = I915_READ(SDVOC); |
||
251 | } else { |
||
252 | bval = I915_READ(SDVOB); |
||
253 | } |
||
254 | /* |
||
255 | * Write the registers twice for luck. Sometimes, |
||
256 | * writing them only once doesn't appear to 'stick'. |
||
257 | * The BIOS does this too. Yay, magic |
||
258 | */ |
||
259 | for (i = 0; i < 2; i++) |
||
260 | { |
||
261 | I915_WRITE(SDVOB, bval); |
||
262 | I915_READ(SDVOB); |
||
263 | I915_WRITE(SDVOC, cval); |
||
264 | I915_READ(SDVOC); |
||
265 | } |
||
266 | } |
||
267 | |||
268 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
||
269 | { |
||
270 | struct i2c_msg msgs[] = { |
||
271 | { |
||
272 | .addr = intel_sdvo->slave_addr, |
||
273 | .flags = 0, |
||
274 | .len = 1, |
||
275 | .buf = &addr, |
||
276 | }, |
||
277 | { |
||
278 | .addr = intel_sdvo->slave_addr, |
||
279 | .flags = I2C_M_RD, |
||
280 | .len = 1, |
||
281 | .buf = ch, |
||
282 | } |
||
283 | }; |
||
284 | int ret; |
||
285 | |||
286 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
||
287 | return true; |
||
288 | |||
289 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
||
290 | return false; |
||
291 | } |
||
292 | |||
293 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
||
294 | /** Mapping of command numbers to names, for debug output */ |
||
295 | static const struct _sdvo_cmd_name { |
||
296 | u8 cmd; |
||
297 | const char *name; |
||
298 | } sdvo_cmd_names[] = { |
||
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
||
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
||
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
||
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
||
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
||
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
||
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
||
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
||
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
||
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
||
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
||
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
||
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
||
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
||
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
||
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
||
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
||
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
||
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
||
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
||
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
||
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
||
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
||
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
||
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
||
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
||
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
||
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
||
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
||
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
||
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
||
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
||
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
||
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
||
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
||
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
||
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
||
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
||
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
||
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
||
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
||
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
||
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
||
342 | |||
343 | /* Add the op code for SDVO enhancements */ |
||
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
||
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
||
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
||
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
||
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
||
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
||
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
||
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
||
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
||
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
||
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
||
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
||
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
||
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
||
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
||
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
||
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
||
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
||
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
||
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
||
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
||
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
||
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
||
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
||
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
||
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
||
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
||
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
||
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
||
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
||
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
||
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
||
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
||
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
||
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
||
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
||
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
||
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
||
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
||
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
||
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
||
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
||
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
||
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
||
388 | |||
389 | /* HDMI op code */ |
||
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
||
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
||
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
||
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
||
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
||
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
||
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
||
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
||
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
||
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
||
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
||
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
||
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
||
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
||
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
||
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
||
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
||
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
||
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
||
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
||
410 | }; |
||
411 | |||
3031 | serge | 412 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
2330 | Serge | 413 | |
414 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
||
415 | const void *args, int args_len) |
||
416 | { |
||
417 | int i; |
||
418 | |||
419 | DRM_DEBUG_KMS("%s: W: %02X ", |
||
420 | SDVO_NAME(intel_sdvo), cmd); |
||
421 | for (i = 0; i < args_len; i++) |
||
422 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
||
423 | for (; i < 8; i++) |
||
424 | DRM_LOG_KMS(" "); |
||
425 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
||
426 | if (cmd == sdvo_cmd_names[i].cmd) { |
||
427 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
||
428 | break; |
||
429 | } |
||
430 | } |
||
431 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
||
432 | DRM_LOG_KMS("(%02X)", cmd); |
||
433 | DRM_LOG_KMS("\n"); |
||
434 | } |
||
435 | |||
436 | static const char *cmd_status_names[] = { |
||
437 | "Power on", |
||
438 | "Success", |
||
439 | "Not supported", |
||
440 | "Invalid arg", |
||
441 | "Pending", |
||
442 | "Target not specified", |
||
443 | "Scaling not supported" |
||
444 | }; |
||
445 | |||
446 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
||
447 | const void *args, int args_len) |
||
448 | { |
||
3031 | serge | 449 | u8 *buf, status; |
450 | struct i2c_msg *msgs; |
||
451 | int i, ret = true; |
||
2330 | Serge | 452 | |
3031 | serge | 453 | /* Would be simpler to allocate both in one go ? */ |
454 | buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL); |
||
455 | if (!buf) |
||
456 | return false; |
||
457 | |||
458 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); |
||
459 | if (!msgs) { |
||
460 | kfree(buf); |
||
461 | return false; |
||
462 | } |
||
463 | |||
2330 | Serge | 464 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
465 | |||
466 | for (i = 0; i < args_len; i++) { |
||
467 | msgs[i].addr = intel_sdvo->slave_addr; |
||
468 | msgs[i].flags = 0; |
||
469 | msgs[i].len = 2; |
||
470 | msgs[i].buf = buf + 2 *i; |
||
471 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
||
472 | buf[2*i + 1] = ((u8*)args)[i]; |
||
473 | } |
||
474 | msgs[i].addr = intel_sdvo->slave_addr; |
||
475 | msgs[i].flags = 0; |
||
476 | msgs[i].len = 2; |
||
477 | msgs[i].buf = buf + 2*i; |
||
478 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
||
479 | buf[2*i + 1] = cmd; |
||
480 | |||
481 | /* the following two are to read the response */ |
||
482 | status = SDVO_I2C_CMD_STATUS; |
||
483 | msgs[i+1].addr = intel_sdvo->slave_addr; |
||
484 | msgs[i+1].flags = 0; |
||
485 | msgs[i+1].len = 1; |
||
486 | msgs[i+1].buf = &status; |
||
487 | |||
488 | msgs[i+2].addr = intel_sdvo->slave_addr; |
||
489 | msgs[i+2].flags = I2C_M_RD; |
||
490 | msgs[i+2].len = 1; |
||
491 | msgs[i+2].buf = &status; |
||
492 | |||
493 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
||
494 | if (ret < 0) { |
||
495 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
||
3031 | serge | 496 | ret = false; |
497 | goto out; |
||
2330 | Serge | 498 | } |
499 | if (ret != i+3) { |
||
500 | /* failure in I2C transfer */ |
||
501 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
||
3031 | serge | 502 | ret = false; |
2330 | Serge | 503 | } |
504 | |||
3031 | serge | 505 | out: |
506 | kfree(msgs); |
||
507 | kfree(buf); |
||
508 | return ret; |
||
2330 | Serge | 509 | } |
510 | |||
511 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
||
512 | void *response, int response_len) |
||
513 | { |
||
3243 | Serge | 514 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
2330 | Serge | 515 | u8 status; |
516 | int i; |
||
517 | |||
518 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
||
519 | |||
520 | /* |
||
521 | * The documentation states that all commands will be |
||
522 | * processed within 15µs, and that we need only poll |
||
523 | * the status byte a maximum of 3 times in order for the |
||
524 | * command to be complete. |
||
525 | * |
||
526 | * Check 5 times in case the hardware failed to read the docs. |
||
3243 | Serge | 527 | * |
528 | * Also beware that the first response by many devices is to |
||
529 | * reply PENDING and stall for time. TVs are notorious for |
||
530 | * requiring longer than specified to complete their replies. |
||
531 | * Originally (in the DDX long ago), the delay was only ever 15ms |
||
532 | * with an additional delay of 30ms applied for TVs added later after |
||
533 | * many experiments. To accommodate both sets of delays, we do a |
||
534 | * sequence of slow checks if the device is falling behind and fails |
||
535 | * to reply within 5*15µs. |
||
2330 | Serge | 536 | */ |
537 | if (!intel_sdvo_read_byte(intel_sdvo, |
||
538 | SDVO_I2C_CMD_STATUS, |
||
539 | &status)) |
||
540 | goto log_fail; |
||
541 | |||
3243 | Serge | 542 | while (status == SDVO_CMD_STATUS_PENDING && --retry) { |
543 | if (retry < 10) |
||
544 | msleep(15); |
||
545 | else |
||
546 | udelay(15); |
||
547 | |||
2330 | Serge | 548 | if (!intel_sdvo_read_byte(intel_sdvo, |
549 | SDVO_I2C_CMD_STATUS, |
||
550 | &status)) |
||
551 | goto log_fail; |
||
552 | } |
||
553 | |||
554 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
||
555 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
||
556 | else |
||
557 | DRM_LOG_KMS("(??? %d)", status); |
||
558 | |||
559 | if (status != SDVO_CMD_STATUS_SUCCESS) |
||
560 | goto log_fail; |
||
561 | |||
562 | /* Read the command response */ |
||
563 | for (i = 0; i < response_len; i++) { |
||
564 | if (!intel_sdvo_read_byte(intel_sdvo, |
||
565 | SDVO_I2C_RETURN_0 + i, |
||
566 | &((u8 *)response)[i])) |
||
567 | goto log_fail; |
||
568 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
||
569 | } |
||
570 | DRM_LOG_KMS("\n"); |
||
571 | return true; |
||
572 | |||
573 | log_fail: |
||
574 | DRM_LOG_KMS("... failed\n"); |
||
575 | return false; |
||
576 | } |
||
577 | |||
578 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
||
579 | { |
||
580 | if (mode->clock >= 100000) |
||
581 | return 1; |
||
582 | else if (mode->clock >= 50000) |
||
583 | return 2; |
||
584 | else |
||
585 | return 4; |
||
586 | } |
||
587 | |||
588 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
||
589 | u8 ddc_bus) |
||
590 | { |
||
591 | /* This must be the immediately preceding write before the i2c xfer */ |
||
592 | return intel_sdvo_write_cmd(intel_sdvo, |
||
593 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
||
594 | &ddc_bus, 1); |
||
595 | } |
||
596 | |||
597 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
||
598 | { |
||
599 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
||
600 | return false; |
||
601 | |||
602 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
||
603 | } |
||
604 | |||
605 | static bool |
||
606 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
||
607 | { |
||
608 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
||
609 | return false; |
||
610 | |||
611 | return intel_sdvo_read_response(intel_sdvo, value, len); |
||
612 | } |
||
613 | |||
614 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
||
615 | { |
||
616 | struct intel_sdvo_set_target_input_args targets = {0}; |
||
617 | return intel_sdvo_set_value(intel_sdvo, |
||
618 | SDVO_CMD_SET_TARGET_INPUT, |
||
619 | &targets, sizeof(targets)); |
||
620 | } |
||
621 | |||
622 | /** |
||
623 | * Return whether each input is trained. |
||
624 | * |
||
625 | * This function is making an assumption about the layout of the response, |
||
626 | * which should be checked against the docs. |
||
627 | */ |
||
628 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
||
629 | { |
||
630 | struct intel_sdvo_get_trained_inputs_response response; |
||
631 | |||
632 | BUILD_BUG_ON(sizeof(response) != 1); |
||
633 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
||
634 | &response, sizeof(response))) |
||
635 | return false; |
||
636 | |||
637 | *input_1 = response.input0_trained; |
||
638 | *input_2 = response.input1_trained; |
||
639 | return true; |
||
640 | } |
||
641 | |||
642 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
||
643 | u16 outputs) |
||
644 | { |
||
645 | return intel_sdvo_set_value(intel_sdvo, |
||
646 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
||
647 | &outputs, sizeof(outputs)); |
||
648 | } |
||
649 | |||
3031 | serge | 650 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
651 | u16 *outputs) |
||
652 | { |
||
653 | return intel_sdvo_get_value(intel_sdvo, |
||
654 | SDVO_CMD_GET_ACTIVE_OUTPUTS, |
||
655 | outputs, sizeof(*outputs)); |
||
656 | } |
||
657 | |||
2340 | Serge | 658 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
659 | int mode) |
||
660 | { |
||
661 | u8 state = SDVO_ENCODER_STATE_ON; |
||
2330 | Serge | 662 | |
2340 | Serge | 663 | switch (mode) { |
664 | case DRM_MODE_DPMS_ON: |
||
665 | state = SDVO_ENCODER_STATE_ON; |
||
666 | break; |
||
667 | case DRM_MODE_DPMS_STANDBY: |
||
668 | state = SDVO_ENCODER_STATE_STANDBY; |
||
669 | break; |
||
670 | case DRM_MODE_DPMS_SUSPEND: |
||
671 | state = SDVO_ENCODER_STATE_SUSPEND; |
||
672 | break; |
||
673 | case DRM_MODE_DPMS_OFF: |
||
674 | state = SDVO_ENCODER_STATE_OFF; |
||
675 | break; |
||
676 | } |
||
2330 | Serge | 677 | |
2340 | Serge | 678 | return intel_sdvo_set_value(intel_sdvo, |
679 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
||
680 | } |
||
2330 | Serge | 681 | |
682 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
||
683 | int *clock_min, |
||
684 | int *clock_max) |
||
685 | { |
||
686 | struct intel_sdvo_pixel_clock_range clocks; |
||
687 | |||
688 | BUILD_BUG_ON(sizeof(clocks) != 4); |
||
689 | if (!intel_sdvo_get_value(intel_sdvo, |
||
690 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
||
691 | &clocks, sizeof(clocks))) |
||
692 | return false; |
||
693 | |||
694 | /* Convert the values from units of 10 kHz to kHz. */ |
||
695 | *clock_min = clocks.min * 10; |
||
696 | *clock_max = clocks.max * 10; |
||
697 | return true; |
||
698 | } |
||
699 | |||
700 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
||
701 | u16 outputs) |
||
702 | { |
||
703 | return intel_sdvo_set_value(intel_sdvo, |
||
704 | SDVO_CMD_SET_TARGET_OUTPUT, |
||
705 | &outputs, sizeof(outputs)); |
||
706 | } |
||
707 | |||
708 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
||
709 | struct intel_sdvo_dtd *dtd) |
||
710 | { |
||
711 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
||
712 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
||
713 | } |
||
714 | |||
715 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
||
716 | struct intel_sdvo_dtd *dtd) |
||
717 | { |
||
718 | return intel_sdvo_set_timing(intel_sdvo, |
||
719 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
||
720 | } |
||
721 | |||
722 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
||
723 | struct intel_sdvo_dtd *dtd) |
||
724 | { |
||
725 | return intel_sdvo_set_timing(intel_sdvo, |
||
726 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
||
727 | } |
||
728 | |||
729 | static bool |
||
730 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
||
731 | uint16_t clock, |
||
732 | uint16_t width, |
||
733 | uint16_t height) |
||
734 | { |
||
735 | struct intel_sdvo_preferred_input_timing_args args; |
||
736 | |||
737 | memset(&args, 0, sizeof(args)); |
||
738 | args.clock = clock; |
||
739 | args.width = width; |
||
740 | args.height = height; |
||
741 | args.interlace = 0; |
||
742 | |||
743 | if (intel_sdvo->is_lvds && |
||
744 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
||
745 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
||
746 | args.scaled = 1; |
||
747 | |||
748 | return intel_sdvo_set_value(intel_sdvo, |
||
749 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
||
750 | &args, sizeof(args)); |
||
751 | } |
||
752 | |||
753 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
||
754 | struct intel_sdvo_dtd *dtd) |
||
755 | { |
||
756 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
||
757 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); |
||
758 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
||
759 | &dtd->part1, sizeof(dtd->part1)) && |
||
760 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
||
761 | &dtd->part2, sizeof(dtd->part2)); |
||
762 | } |
||
763 | |||
764 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
||
765 | { |
||
766 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
||
767 | } |
||
768 | |||
769 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
||
770 | const struct drm_display_mode *mode) |
||
771 | { |
||
772 | uint16_t width, height; |
||
773 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
||
774 | uint16_t h_sync_offset, v_sync_offset; |
||
3031 | serge | 775 | int mode_clock; |
2330 | Serge | 776 | |
3031 | serge | 777 | width = mode->hdisplay; |
778 | height = mode->vdisplay; |
||
2330 | Serge | 779 | |
780 | /* do some mode translations */ |
||
3031 | serge | 781 | h_blank_len = mode->htotal - mode->hdisplay; |
782 | h_sync_len = mode->hsync_end - mode->hsync_start; |
||
2330 | Serge | 783 | |
3031 | serge | 784 | v_blank_len = mode->vtotal - mode->vdisplay; |
785 | v_sync_len = mode->vsync_end - mode->vsync_start; |
||
2330 | Serge | 786 | |
3031 | serge | 787 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
788 | v_sync_offset = mode->vsync_start - mode->vdisplay; |
||
2330 | Serge | 789 | |
3031 | serge | 790 | mode_clock = mode->clock; |
791 | mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1; |
||
792 | mode_clock /= 10; |
||
793 | dtd->part1.clock = mode_clock; |
||
794 | |||
2330 | Serge | 795 | dtd->part1.h_active = width & 0xff; |
796 | dtd->part1.h_blank = h_blank_len & 0xff; |
||
797 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
||
798 | ((h_blank_len >> 8) & 0xf); |
||
799 | dtd->part1.v_active = height & 0xff; |
||
800 | dtd->part1.v_blank = v_blank_len & 0xff; |
||
801 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
||
802 | ((v_blank_len >> 8) & 0xf); |
||
803 | |||
804 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
||
805 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
||
806 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
||
807 | (v_sync_len & 0xf); |
||
808 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
||
809 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
||
810 | ((v_sync_len & 0x30) >> 4); |
||
811 | |||
812 | dtd->part2.dtd_flags = 0x18; |
||
3031 | serge | 813 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
814 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; |
||
2330 | Serge | 815 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
3031 | serge | 816 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
2330 | Serge | 817 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
3031 | serge | 818 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
2330 | Serge | 819 | |
820 | dtd->part2.sdvo_flags = 0; |
||
821 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
||
822 | dtd->part2.reserved = 0; |
||
823 | } |
||
824 | |||
825 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
||
826 | const struct intel_sdvo_dtd *dtd) |
||
827 | { |
||
828 | mode->hdisplay = dtd->part1.h_active; |
||
829 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
||
830 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
||
831 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
||
832 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
||
833 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
||
834 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
||
835 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
||
836 | |||
837 | mode->vdisplay = dtd->part1.v_active; |
||
838 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
||
839 | mode->vsync_start = mode->vdisplay; |
||
840 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
||
841 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
||
842 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
||
843 | mode->vsync_end = mode->vsync_start + |
||
844 | (dtd->part2.v_sync_off_width & 0xf); |
||
845 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
||
846 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
||
847 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
||
848 | |||
849 | mode->clock = dtd->part1.clock * 10; |
||
850 | |||
851 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
||
3031 | serge | 852 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
853 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
||
854 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
||
2330 | Serge | 855 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
3031 | serge | 856 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
2330 | Serge | 857 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
858 | } |
||
859 | |||
860 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
||
861 | { |
||
862 | struct intel_sdvo_encode encode; |
||
863 | |||
864 | BUILD_BUG_ON(sizeof(encode) != 2); |
||
865 | return intel_sdvo_get_value(intel_sdvo, |
||
866 | SDVO_CMD_GET_SUPP_ENCODE, |
||
867 | &encode, sizeof(encode)); |
||
868 | } |
||
869 | |||
870 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
||
871 | uint8_t mode) |
||
872 | { |
||
873 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
||
874 | } |
||
875 | |||
876 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
||
877 | uint8_t mode) |
||
878 | { |
||
879 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
||
880 | } |
||
881 | |||
882 | #if 0 |
||
883 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
||
884 | { |
||
885 | int i, j; |
||
886 | uint8_t set_buf_index[2]; |
||
887 | uint8_t av_split; |
||
888 | uint8_t buf_size; |
||
889 | uint8_t buf[48]; |
||
890 | uint8_t *pos; |
||
891 | |||
892 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
||
893 | |||
894 | for (i = 0; i <= av_split; i++) { |
||
895 | set_buf_index[0] = i; set_buf_index[1] = 0; |
||
896 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
||
897 | set_buf_index, 2); |
||
898 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
||
899 | intel_sdvo_read_response(encoder, &buf_size, 1); |
||
900 | |||
901 | pos = buf; |
||
902 | for (j = 0; j <= buf_size; j += 8) { |
||
903 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
||
904 | NULL, 0); |
||
905 | intel_sdvo_read_response(encoder, pos, 8); |
||
906 | pos += 8; |
||
907 | } |
||
908 | } |
||
909 | } |
||
910 | #endif |
||
911 | |||
3031 | serge | 912 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
913 | unsigned if_index, uint8_t tx_rate, |
||
914 | uint8_t *data, unsigned length) |
||
2330 | Serge | 915 | { |
3031 | serge | 916 | uint8_t set_buf_index[2] = { if_index, 0 }; |
917 | uint8_t hbuf_size, tmp[8]; |
||
918 | int i; |
||
2330 | Serge | 919 | |
920 | if (!intel_sdvo_set_value(intel_sdvo, |
||
921 | SDVO_CMD_SET_HBUF_INDEX, |
||
922 | set_buf_index, 2)) |
||
923 | return false; |
||
924 | |||
3031 | serge | 925 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, |
926 | &hbuf_size, 1)) |
||
927 | return false; |
||
928 | |||
929 | /* Buffer size is 0 based, hooray! */ |
||
930 | hbuf_size++; |
||
931 | |||
932 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", |
||
933 | if_index, length, hbuf_size); |
||
934 | |||
935 | for (i = 0; i < hbuf_size; i += 8) { |
||
936 | memset(tmp, 0, 8); |
||
937 | if (i < length) |
||
938 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); |
||
939 | |||
2330 | Serge | 940 | if (!intel_sdvo_set_value(intel_sdvo, |
941 | SDVO_CMD_SET_HBUF_DATA, |
||
3031 | serge | 942 | tmp, 8)) |
2330 | Serge | 943 | return false; |
944 | } |
||
945 | |||
946 | return intel_sdvo_set_value(intel_sdvo, |
||
947 | SDVO_CMD_SET_HBUF_TXRATE, |
||
948 | &tx_rate, 1); |
||
949 | } |
||
950 | |||
3480 | Serge | 951 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
952 | const struct drm_display_mode *adjusted_mode) |
||
3031 | serge | 953 | { |
954 | struct dip_infoframe avi_if = { |
||
955 | .type = DIP_TYPE_AVI, |
||
956 | .ver = DIP_VERSION_AVI, |
||
957 | .len = DIP_LEN_AVI, |
||
958 | }; |
||
959 | uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; |
||
960 | |||
3480 | Serge | 961 | if (intel_sdvo->rgb_quant_range_selectable) { |
962 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) |
||
963 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
||
964 | else |
||
965 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; |
||
966 | } |
||
967 | |||
3031 | serge | 968 | intel_dip_infoframe_csum(&avi_if); |
969 | |||
970 | /* sdvo spec says that the ecc is handled by the hw, and it looks like |
||
971 | * we must not send the ecc field, either. */ |
||
972 | memcpy(sdvo_data, &avi_if, 3); |
||
973 | sdvo_data[3] = avi_if.checksum; |
||
974 | memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); |
||
975 | |||
976 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
||
977 | SDVO_HBUF_TX_VSYNC, |
||
978 | sdvo_data, sizeof(sdvo_data)); |
||
979 | } |
||
980 | |||
2330 | Serge | 981 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
982 | { |
||
983 | struct intel_sdvo_tv_format format; |
||
984 | uint32_t format_map; |
||
985 | |||
986 | format_map = 1 << intel_sdvo->tv_format_index; |
||
987 | memset(&format, 0, sizeof(format)); |
||
988 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
||
989 | |||
990 | BUILD_BUG_ON(sizeof(format) != 6); |
||
991 | return intel_sdvo_set_value(intel_sdvo, |
||
992 | SDVO_CMD_SET_TV_FORMAT, |
||
993 | &format, sizeof(format)); |
||
994 | } |
||
995 | |||
996 | static bool |
||
997 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
||
3031 | serge | 998 | const struct drm_display_mode *mode) |
2330 | Serge | 999 | { |
1000 | struct intel_sdvo_dtd output_dtd; |
||
1001 | |||
1002 | if (!intel_sdvo_set_target_output(intel_sdvo, |
||
1003 | intel_sdvo->attached_output)) |
||
1004 | return false; |
||
1005 | |||
1006 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
||
1007 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
||
1008 | return false; |
||
1009 | |||
1010 | return true; |
||
1011 | } |
||
1012 | |||
3031 | serge | 1013 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1014 | * Unfortunately we have to set up the full output mode to do that. */ |
||
2330 | Serge | 1015 | static bool |
3031 | serge | 1016 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
1017 | const struct drm_display_mode *mode, |
||
2330 | Serge | 1018 | struct drm_display_mode *adjusted_mode) |
1019 | { |
||
3031 | serge | 1020 | struct intel_sdvo_dtd input_dtd; |
1021 | |||
2330 | Serge | 1022 | /* Reset the input timing to the screen. Assume always input 0. */ |
1023 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
||
1024 | return false; |
||
1025 | |||
1026 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
||
1027 | mode->clock / 10, |
||
1028 | mode->hdisplay, |
||
1029 | mode->vdisplay)) |
||
1030 | return false; |
||
1031 | |||
1032 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
||
3031 | serge | 1033 | &input_dtd)) |
2330 | Serge | 1034 | return false; |
1035 | |||
3031 | serge | 1036 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
1037 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
||
2330 | Serge | 1038 | |
1039 | return true; |
||
1040 | } |
||
1041 | |||
1042 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
||
3031 | serge | 1043 | const struct drm_display_mode *mode, |
2330 | Serge | 1044 | struct drm_display_mode *adjusted_mode) |
1045 | { |
||
1046 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
||
1047 | int multiplier; |
||
1048 | |||
1049 | /* We need to construct preferred input timings based on our |
||
1050 | * output timings. To do that, we have to set the output |
||
1051 | * timings, even though this isn't really the right place in |
||
1052 | * the sequence to do it. Oh well. |
||
1053 | */ |
||
1054 | if (intel_sdvo->is_tv) { |
||
1055 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
||
1056 | return false; |
||
1057 | |||
3031 | serge | 1058 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
2330 | Serge | 1059 | mode, |
1060 | adjusted_mode); |
||
1061 | } else if (intel_sdvo->is_lvds) { |
||
1062 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
||
1063 | intel_sdvo->sdvo_lvds_fixed_mode)) |
||
1064 | return false; |
||
1065 | |||
3031 | serge | 1066 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
2330 | Serge | 1067 | mode, |
1068 | adjusted_mode); |
||
1069 | } |
||
1070 | |||
1071 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
||
1072 | * SDVO device will factor out the multiplier during mode_set. |
||
1073 | */ |
||
1074 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
||
1075 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
||
1076 | |||
3480 | Serge | 1077 | if (intel_sdvo->color_range_auto) { |
1078 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
||
1079 | if (intel_sdvo->has_hdmi_monitor && |
||
1080 | drm_match_cea_mode(adjusted_mode) > 1) |
||
1081 | intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235; |
||
1082 | else |
||
1083 | intel_sdvo->color_range = 0; |
||
1084 | } |
||
1085 | |||
1086 | if (intel_sdvo->color_range) |
||
1087 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; |
||
1088 | |||
2330 | Serge | 1089 | return true; |
1090 | } |
||
1091 | |||
1092 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
||
1093 | struct drm_display_mode *mode, |
||
1094 | struct drm_display_mode *adjusted_mode) |
||
1095 | { |
||
1096 | struct drm_device *dev = encoder->dev; |
||
1097 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1098 | struct drm_crtc *crtc = encoder->crtc; |
||
1099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
1100 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
||
1101 | u32 sdvox; |
||
1102 | struct intel_sdvo_in_out_map in_out; |
||
3031 | serge | 1103 | struct intel_sdvo_dtd input_dtd, output_dtd; |
2330 | Serge | 1104 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
1105 | int rate; |
||
1106 | |||
1107 | if (!mode) |
||
1108 | return; |
||
1109 | |||
1110 | /* First, set the input mapping for the first input to our controlled |
||
1111 | * output. This is only correct if we're a single-input device, in |
||
1112 | * which case the first input is the output from the appropriate SDVO |
||
1113 | * channel on the motherboard. In a two-input device, the first input |
||
1114 | * will be SDVOB and the second SDVOC. |
||
1115 | */ |
||
1116 | in_out.in0 = intel_sdvo->attached_output; |
||
1117 | in_out.in1 = 0; |
||
1118 | |||
1119 | intel_sdvo_set_value(intel_sdvo, |
||
1120 | SDVO_CMD_SET_IN_OUT_MAP, |
||
1121 | &in_out, sizeof(in_out)); |
||
1122 | |||
1123 | /* Set the output timings to the screen */ |
||
1124 | if (!intel_sdvo_set_target_output(intel_sdvo, |
||
1125 | intel_sdvo->attached_output)) |
||
1126 | return; |
||
1127 | |||
3031 | serge | 1128 | /* lvds has a special fixed output timing. */ |
1129 | if (intel_sdvo->is_lvds) |
||
1130 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
||
1131 | intel_sdvo->sdvo_lvds_fixed_mode); |
||
1132 | else |
||
1133 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
||
1134 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
||
1135 | DRM_INFO("Setting output timings on %s failed\n", |
||
1136 | SDVO_NAME(intel_sdvo)); |
||
2330 | Serge | 1137 | |
1138 | /* Set the input timing to the screen. Assume always input 0. */ |
||
1139 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
||
1140 | return; |
||
1141 | |||
1142 | if (intel_sdvo->has_hdmi_monitor) { |
||
1143 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
||
1144 | intel_sdvo_set_colorimetry(intel_sdvo, |
||
1145 | SDVO_COLORIMETRY_RGB256); |
||
3480 | Serge | 1146 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
2330 | Serge | 1147 | } else |
1148 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
||
1149 | |||
1150 | if (intel_sdvo->is_tv && |
||
1151 | !intel_sdvo_set_tv_format(intel_sdvo)) |
||
1152 | return; |
||
1153 | |||
3031 | serge | 1154 | /* We have tried to get input timing in mode_fixup, and filled into |
1155 | * adjusted_mode. |
||
1156 | */ |
||
1157 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
||
1158 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
||
1159 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; |
||
1160 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
||
1161 | DRM_INFO("Setting input timings on %s failed\n", |
||
1162 | SDVO_NAME(intel_sdvo)); |
||
2330 | Serge | 1163 | |
1164 | switch (pixel_multiplier) { |
||
1165 | default: |
||
1166 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
||
1167 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
||
1168 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
||
1169 | } |
||
1170 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
||
1171 | return; |
||
1172 | |||
1173 | /* Set the SDVO control regs. */ |
||
1174 | if (INTEL_INFO(dev)->gen >= 4) { |
||
2342 | Serge | 1175 | /* The real mode polarity is set by the SDVO commands, using |
1176 | * struct intel_sdvo_dtd. */ |
||
1177 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; |
||
3480 | Serge | 1178 | if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) |
2330 | Serge | 1179 | sdvox |= intel_sdvo->color_range; |
1180 | if (INTEL_INFO(dev)->gen < 5) |
||
1181 | sdvox |= SDVO_BORDER_ENABLE; |
||
1182 | } else { |
||
1183 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
||
1184 | switch (intel_sdvo->sdvo_reg) { |
||
1185 | case SDVOB: |
||
1186 | sdvox &= SDVOB_PRESERVE_MASK; |
||
1187 | break; |
||
1188 | case SDVOC: |
||
1189 | sdvox &= SDVOC_PRESERVE_MASK; |
||
1190 | break; |
||
1191 | } |
||
1192 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
||
1193 | } |
||
2342 | Serge | 1194 | |
1195 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) |
||
1196 | sdvox |= TRANSCODER_CPT(intel_crtc->pipe); |
||
1197 | else |
||
1198 | sdvox |= TRANSCODER(intel_crtc->pipe); |
||
1199 | |||
2330 | Serge | 1200 | if (intel_sdvo->has_hdmi_audio) |
1201 | sdvox |= SDVO_AUDIO_ENABLE; |
||
1202 | |||
1203 | if (INTEL_INFO(dev)->gen >= 4) { |
||
1204 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
||
1205 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
||
1206 | /* done in crtc_mode_set as it lives inside the dpll register */ |
||
1207 | } else { |
||
1208 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
||
1209 | } |
||
1210 | |||
1211 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
||
1212 | INTEL_INFO(dev)->gen < 5) |
||
1213 | sdvox |= SDVO_STALL_SELECT; |
||
1214 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
||
1215 | } |
||
1216 | |||
3031 | serge | 1217 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
2330 | Serge | 1218 | { |
3031 | serge | 1219 | struct intel_sdvo_connector *intel_sdvo_connector = |
1220 | to_intel_sdvo_connector(&connector->base); |
||
1221 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); |
||
1222 | u16 active_outputs; |
||
1223 | |||
1224 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
||
1225 | |||
1226 | if (active_outputs & intel_sdvo_connector->output_flag) |
||
1227 | return true; |
||
1228 | else |
||
1229 | return false; |
||
1230 | } |
||
1231 | |||
1232 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, |
||
1233 | enum pipe *pipe) |
||
1234 | { |
||
1235 | struct drm_device *dev = encoder->base.dev; |
||
2330 | Serge | 1236 | struct drm_i915_private *dev_priv = dev->dev_private; |
3031 | serge | 1237 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
1238 | u32 tmp; |
||
1239 | |||
1240 | tmp = I915_READ(intel_sdvo->sdvo_reg); |
||
1241 | |||
1242 | if (!(tmp & SDVO_ENABLE)) |
||
1243 | return false; |
||
1244 | |||
1245 | if (HAS_PCH_CPT(dev)) |
||
1246 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
1247 | else |
||
1248 | *pipe = PORT_TO_PIPE(tmp); |
||
1249 | |||
1250 | return true; |
||
1251 | } |
||
1252 | |||
1253 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
||
1254 | { |
||
1255 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
1256 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
||
2330 | Serge | 1257 | u32 temp; |
1258 | |||
1259 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
||
1260 | if (0) |
||
3031 | serge | 1261 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
1262 | DRM_MODE_DPMS_OFF); |
||
2330 | Serge | 1263 | |
1264 | temp = I915_READ(intel_sdvo->sdvo_reg); |
||
1265 | if ((temp & SDVO_ENABLE) != 0) { |
||
3243 | Serge | 1266 | /* HW workaround for IBX, we need to move the port to |
1267 | * transcoder A before disabling it. */ |
||
1268 | if (HAS_PCH_IBX(encoder->base.dev)) { |
||
1269 | struct drm_crtc *crtc = encoder->base.crtc; |
||
1270 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
1271 | |||
1272 | if (temp & SDVO_PIPE_B_SELECT) { |
||
1273 | temp &= ~SDVO_PIPE_B_SELECT; |
||
1274 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
||
1275 | POSTING_READ(intel_sdvo->sdvo_reg); |
||
1276 | |||
1277 | /* Again we need to write this twice. */ |
||
1278 | I915_WRITE(intel_sdvo->sdvo_reg, temp); |
||
1279 | POSTING_READ(intel_sdvo->sdvo_reg); |
||
1280 | |||
1281 | /* Transcoder selection bits only update |
||
1282 | * effectively on vblank. */ |
||
1283 | if (crtc) |
||
1284 | intel_wait_for_vblank(encoder->base.dev, pipe); |
||
1285 | else |
||
1286 | msleep(50); |
||
1287 | } |
||
1288 | } |
||
1289 | |||
2330 | Serge | 1290 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
1291 | } |
||
3031 | serge | 1292 | } |
1293 | |||
1294 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
||
1295 | { |
||
1296 | struct drm_device *dev = encoder->base.dev; |
||
1297 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1298 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
||
1299 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
||
1300 | u32 temp; |
||
2330 | Serge | 1301 | bool input1, input2; |
1302 | int i; |
||
1303 | u8 status; |
||
1304 | |||
1305 | temp = I915_READ(intel_sdvo->sdvo_reg); |
||
3243 | Serge | 1306 | if ((temp & SDVO_ENABLE) == 0) { |
1307 | /* HW workaround for IBX, we need to move the port |
||
1308 | * to transcoder A before disabling it. */ |
||
1309 | if (HAS_PCH_IBX(dev)) { |
||
1310 | struct drm_crtc *crtc = encoder->base.crtc; |
||
1311 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
||
1312 | |||
1313 | /* Restore the transcoder select bit. */ |
||
1314 | if (pipe == PIPE_B) |
||
1315 | temp |= SDVO_PIPE_B_SELECT; |
||
1316 | } |
||
1317 | |||
2330 | Serge | 1318 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
3243 | Serge | 1319 | } |
2330 | Serge | 1320 | for (i = 0; i < 2; i++) |
1321 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
1322 | |||
1323 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
||
1324 | /* Warn if the device reported failure to sync. |
||
1325 | * A lot of SDVO devices fail to notify of sync, but it's |
||
1326 | * a given it the status is a success, we succeeded. |
||
1327 | */ |
||
1328 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
||
1329 | DRM_DEBUG_KMS("First %s output reported failure to " |
||
1330 | "sync\n", SDVO_NAME(intel_sdvo)); |
||
1331 | } |
||
1332 | |||
1333 | if (0) |
||
3031 | serge | 1334 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
1335 | DRM_MODE_DPMS_ON); |
||
1336 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
||
1337 | } |
||
1338 | |||
1339 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
||
1340 | { |
||
1341 | struct drm_crtc *crtc; |
||
1342 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1343 | |||
1344 | /* dvo supports only 2 dpms states. */ |
||
1345 | if (mode != DRM_MODE_DPMS_ON) |
||
1346 | mode = DRM_MODE_DPMS_OFF; |
||
1347 | |||
1348 | if (mode == connector->dpms) |
||
1349 | return; |
||
1350 | |||
1351 | connector->dpms = mode; |
||
1352 | |||
1353 | /* Only need to change hw state when actually enabled */ |
||
1354 | crtc = intel_sdvo->base.base.crtc; |
||
1355 | if (!crtc) { |
||
1356 | intel_sdvo->base.connectors_active = false; |
||
1357 | return; |
||
1358 | } |
||
1359 | |||
1360 | if (mode != DRM_MODE_DPMS_ON) { |
||
1361 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
||
1362 | if (0) |
||
2330 | Serge | 1363 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
3031 | serge | 1364 | |
1365 | intel_sdvo->base.connectors_active = false; |
||
1366 | |||
1367 | intel_crtc_update_dpms(crtc); |
||
1368 | } else { |
||
1369 | intel_sdvo->base.connectors_active = true; |
||
1370 | |||
1371 | intel_crtc_update_dpms(crtc); |
||
1372 | |||
1373 | if (0) |
||
1374 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
||
2330 | Serge | 1375 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
1376 | } |
||
3031 | serge | 1377 | |
1378 | intel_modeset_check_state(connector->dev); |
||
2330 | Serge | 1379 | } |
1380 | |||
1381 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
||
1382 | struct drm_display_mode *mode) |
||
1383 | { |
||
1384 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1385 | |||
1386 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
1387 | return MODE_NO_DBLESCAN; |
||
1388 | |||
1389 | if (intel_sdvo->pixel_clock_min > mode->clock) |
||
1390 | return MODE_CLOCK_LOW; |
||
1391 | |||
1392 | if (intel_sdvo->pixel_clock_max < mode->clock) |
||
1393 | return MODE_CLOCK_HIGH; |
||
1394 | |||
1395 | if (intel_sdvo->is_lvds) { |
||
1396 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
||
1397 | return MODE_PANEL; |
||
1398 | |||
1399 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
||
1400 | return MODE_PANEL; |
||
1401 | } |
||
1402 | |||
1403 | return MODE_OK; |
||
1404 | } |
||
1405 | |||
1406 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
||
1407 | { |
||
1408 | BUILD_BUG_ON(sizeof(*caps) != 8); |
||
1409 | if (!intel_sdvo_get_value(intel_sdvo, |
||
1410 | SDVO_CMD_GET_DEVICE_CAPS, |
||
1411 | caps, sizeof(*caps))) |
||
1412 | return false; |
||
1413 | |||
1414 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
||
1415 | " vendor_id: %d\n" |
||
1416 | " device_id: %d\n" |
||
1417 | " device_rev_id: %d\n" |
||
1418 | " sdvo_version_major: %d\n" |
||
1419 | " sdvo_version_minor: %d\n" |
||
1420 | " sdvo_inputs_mask: %d\n" |
||
1421 | " smooth_scaling: %d\n" |
||
1422 | " sharp_scaling: %d\n" |
||
1423 | " up_scaling: %d\n" |
||
1424 | " down_scaling: %d\n" |
||
1425 | " stall_support: %d\n" |
||
1426 | " output_flags: %d\n", |
||
1427 | caps->vendor_id, |
||
1428 | caps->device_id, |
||
1429 | caps->device_rev_id, |
||
1430 | caps->sdvo_version_major, |
||
1431 | caps->sdvo_version_minor, |
||
1432 | caps->sdvo_inputs_mask, |
||
1433 | caps->smooth_scaling, |
||
1434 | caps->sharp_scaling, |
||
1435 | caps->up_scaling, |
||
1436 | caps->down_scaling, |
||
1437 | caps->stall_support, |
||
1438 | caps->output_flags); |
||
1439 | |||
1440 | return true; |
||
1441 | } |
||
1442 | |||
3031 | serge | 1443 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
2330 | Serge | 1444 | { |
3031 | serge | 1445 | struct drm_device *dev = intel_sdvo->base.base.dev; |
1446 | uint16_t hotplug; |
||
2330 | Serge | 1447 | |
3031 | serge | 1448 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1449 | * on the line. */ |
||
1450 | if (IS_I945G(dev) || IS_I945GM(dev)) |
||
1451 | return 0; |
||
1452 | |||
1453 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
||
1454 | &hotplug, sizeof(hotplug))) |
||
1455 | return 0; |
||
1456 | |||
1457 | return hotplug; |
||
2330 | Serge | 1458 | } |
1459 | |||
2342 | Serge | 1460 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
2330 | Serge | 1461 | { |
2342 | Serge | 1462 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
2330 | Serge | 1463 | |
3031 | serge | 1464 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1465 | &intel_sdvo->hotplug_active, 2); |
||
2330 | Serge | 1466 | } |
1467 | |||
1468 | static bool |
||
1469 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
||
1470 | { |
||
1471 | /* Is there more than one type of output? */ |
||
2342 | Serge | 1472 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
2330 | Serge | 1473 | } |
1474 | |||
1475 | static struct edid * |
||
1476 | intel_sdvo_get_edid(struct drm_connector *connector) |
||
1477 | { |
||
1478 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
||
1479 | return drm_get_edid(connector, &sdvo->ddc); |
||
1480 | } |
||
1481 | |||
1482 | /* Mac mini hack -- use the same DDC as the analog connector */ |
||
1483 | static struct edid * |
||
1484 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
||
1485 | { |
||
1486 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
1487 | |||
1488 | return drm_get_edid(connector, |
||
3031 | serge | 1489 | intel_gmbus_get_adapter(dev_priv, |
1490 | dev_priv->crt_ddc_pin)); |
||
2330 | Serge | 1491 | } |
1492 | |||
3031 | serge | 1493 | static enum drm_connector_status |
2342 | Serge | 1494 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
2330 | Serge | 1495 | { |
1496 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1497 | enum drm_connector_status status; |
||
1498 | struct edid *edid; |
||
1499 | |||
1500 | edid = intel_sdvo_get_edid(connector); |
||
1501 | |||
1502 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
||
1503 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
||
1504 | |||
1505 | /* |
||
1506 | * Don't use the 1 as the argument of DDC bus switch to get |
||
1507 | * the EDID. It is used for SDVO SPD ROM. |
||
1508 | */ |
||
1509 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
||
1510 | intel_sdvo->ddc_bus = ddc; |
||
1511 | edid = intel_sdvo_get_edid(connector); |
||
1512 | if (edid) |
||
1513 | break; |
||
1514 | } |
||
1515 | /* |
||
1516 | * If we found the EDID on the other bus, |
||
1517 | * assume that is the correct DDC bus. |
||
1518 | */ |
||
1519 | if (edid == NULL) |
||
1520 | intel_sdvo->ddc_bus = saved_ddc; |
||
1521 | } |
||
1522 | |||
1523 | /* |
||
1524 | * When there is no edid and no monitor is connected with VGA |
||
1525 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
||
1526 | */ |
||
1527 | if (edid == NULL) |
||
1528 | edid = intel_sdvo_get_analog_edid(connector); |
||
1529 | |||
1530 | status = connector_status_unknown; |
||
1531 | if (edid != NULL) { |
||
1532 | /* DDC bus is shared, match EDID to connector type */ |
||
1533 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
||
1534 | status = connector_status_connected; |
||
1535 | if (intel_sdvo->is_hdmi) { |
||
1536 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
||
1537 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
||
3480 | Serge | 1538 | intel_sdvo->rgb_quant_range_selectable = |
1539 | drm_rgb_quant_range_selectable(edid); |
||
2330 | Serge | 1540 | } |
1541 | } else |
||
1542 | status = connector_status_disconnected; |
||
1543 | kfree(edid); |
||
1544 | } |
||
1545 | |||
1546 | if (status == connector_status_connected) { |
||
1547 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
3031 | serge | 1548 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1549 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); |
||
2330 | Serge | 1550 | } |
1551 | |||
1552 | return status; |
||
1553 | } |
||
1554 | |||
2342 | Serge | 1555 | static bool |
1556 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
||
1557 | struct edid *edid) |
||
1558 | { |
||
1559 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
||
1560 | bool connector_is_digital = !!IS_DIGITAL(sdvo); |
||
1561 | |||
1562 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", |
||
1563 | connector_is_digital, monitor_is_digital); |
||
1564 | return connector_is_digital == monitor_is_digital; |
||
1565 | } |
||
1566 | |||
2330 | Serge | 1567 | static enum drm_connector_status |
1568 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
||
1569 | { |
||
1570 | uint16_t response; |
||
1571 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1572 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
1573 | enum drm_connector_status ret; |
||
1574 | |||
3243 | Serge | 1575 | if (!intel_sdvo_get_value(intel_sdvo, |
1576 | SDVO_CMD_GET_ATTACHED_DISPLAYS, |
||
1577 | &response, 2)) |
||
2330 | Serge | 1578 | return connector_status_unknown; |
1579 | |||
1580 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
||
1581 | response & 0xff, response >> 8, |
||
1582 | intel_sdvo_connector->output_flag); |
||
1583 | |||
1584 | if (response == 0) |
||
1585 | return connector_status_disconnected; |
||
1586 | |||
1587 | intel_sdvo->attached_output = response; |
||
1588 | |||
1589 | intel_sdvo->has_hdmi_monitor = false; |
||
1590 | intel_sdvo->has_hdmi_audio = false; |
||
3480 | Serge | 1591 | intel_sdvo->rgb_quant_range_selectable = false; |
2330 | Serge | 1592 | |
1593 | if ((intel_sdvo_connector->output_flag & response) == 0) |
||
1594 | ret = connector_status_disconnected; |
||
1595 | else if (IS_TMDS(intel_sdvo_connector)) |
||
2342 | Serge | 1596 | ret = intel_sdvo_tmds_sink_detect(connector); |
2330 | Serge | 1597 | else { |
1598 | struct edid *edid; |
||
1599 | |||
1600 | /* if we have an edid check it matches the connection */ |
||
1601 | edid = intel_sdvo_get_edid(connector); |
||
1602 | if (edid == NULL) |
||
1603 | edid = intel_sdvo_get_analog_edid(connector); |
||
1604 | if (edid != NULL) { |
||
2342 | Serge | 1605 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1606 | edid)) |
||
1607 | ret = connector_status_connected; |
||
1608 | else |
||
2330 | Serge | 1609 | ret = connector_status_disconnected; |
2342 | Serge | 1610 | |
2330 | Serge | 1611 | kfree(edid); |
1612 | } else |
||
1613 | ret = connector_status_connected; |
||
1614 | } |
||
1615 | |||
1616 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
||
1617 | if (ret == connector_status_connected) { |
||
1618 | intel_sdvo->is_tv = false; |
||
1619 | intel_sdvo->is_lvds = false; |
||
1620 | intel_sdvo->base.needs_tv_clock = false; |
||
1621 | |||
1622 | if (response & SDVO_TV_MASK) { |
||
1623 | intel_sdvo->is_tv = true; |
||
1624 | intel_sdvo->base.needs_tv_clock = true; |
||
1625 | } |
||
1626 | if (response & SDVO_LVDS_MASK) |
||
1627 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
||
1628 | } |
||
1629 | |||
1630 | return ret; |
||
1631 | } |
||
1632 | |||
1633 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
||
1634 | { |
||
1635 | struct edid *edid; |
||
1636 | |||
1637 | /* set the bus switch and get the modes */ |
||
1638 | edid = intel_sdvo_get_edid(connector); |
||
1639 | |||
1640 | /* |
||
1641 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
||
1642 | * link between analog and digital outputs. So, if the regular SDVO |
||
1643 | * DDC fails, check to see if the analog output is disconnected, in |
||
1644 | * which case we'll look there for the digital DDC data. |
||
1645 | */ |
||
1646 | if (edid == NULL) |
||
1647 | edid = intel_sdvo_get_analog_edid(connector); |
||
1648 | |||
1649 | if (edid != NULL) { |
||
2342 | Serge | 1650 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1651 | edid)) { |
||
2330 | Serge | 1652 | drm_mode_connector_update_edid_property(connector, edid); |
1653 | drm_add_edid_modes(connector, edid); |
||
1654 | } |
||
1655 | |||
1656 | kfree(edid); |
||
1657 | } |
||
1658 | } |
||
1659 | |||
1660 | /* |
||
1661 | * Set of SDVO TV modes. |
||
1662 | * Note! This is in reply order (see loop in get_tv_modes). |
||
1663 | * XXX: all 60Hz refresh? |
||
1664 | */ |
||
1665 | static const struct drm_display_mode sdvo_tv_modes[] = { |
||
1666 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
||
1667 | 416, 0, 200, 201, 232, 233, 0, |
||
1668 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1669 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
||
1670 | 416, 0, 240, 241, 272, 273, 0, |
||
1671 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1672 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
||
1673 | 496, 0, 300, 301, 332, 333, 0, |
||
1674 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1675 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
||
1676 | 736, 0, 350, 351, 382, 383, 0, |
||
1677 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1678 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
||
1679 | 736, 0, 400, 401, 432, 433, 0, |
||
1680 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1681 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
||
1682 | 736, 0, 480, 481, 512, 513, 0, |
||
1683 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1684 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
||
1685 | 800, 0, 480, 481, 512, 513, 0, |
||
1686 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1687 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
||
1688 | 800, 0, 576, 577, 608, 609, 0, |
||
1689 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1690 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
||
1691 | 816, 0, 350, 351, 382, 383, 0, |
||
1692 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1693 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
||
1694 | 816, 0, 400, 401, 432, 433, 0, |
||
1695 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1696 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
||
1697 | 816, 0, 480, 481, 512, 513, 0, |
||
1698 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1699 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
||
1700 | 816, 0, 540, 541, 572, 573, 0, |
||
1701 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1702 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
||
1703 | 816, 0, 576, 577, 608, 609, 0, |
||
1704 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1705 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
||
1706 | 864, 0, 576, 577, 608, 609, 0, |
||
1707 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1708 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
||
1709 | 896, 0, 600, 601, 632, 633, 0, |
||
1710 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1711 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
||
1712 | 928, 0, 624, 625, 656, 657, 0, |
||
1713 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1714 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
||
1715 | 1016, 0, 766, 767, 798, 799, 0, |
||
1716 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1717 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
||
1718 | 1120, 0, 768, 769, 800, 801, 0, |
||
1719 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1720 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
||
1721 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
||
1722 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
||
1723 | }; |
||
1724 | |||
1725 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
||
1726 | { |
||
1727 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1728 | struct intel_sdvo_sdtv_resolution_request tv_res; |
||
1729 | uint32_t reply = 0, format_map = 0; |
||
1730 | int i; |
||
1731 | |||
1732 | /* Read the list of supported input resolutions for the selected TV |
||
1733 | * format. |
||
1734 | */ |
||
1735 | format_map = 1 << intel_sdvo->tv_format_index; |
||
1736 | memcpy(&tv_res, &format_map, |
||
1737 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
||
1738 | |||
1739 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
||
1740 | return; |
||
1741 | |||
1742 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
||
1743 | if (!intel_sdvo_write_cmd(intel_sdvo, |
||
1744 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
||
1745 | &tv_res, sizeof(tv_res))) |
||
1746 | return; |
||
1747 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
||
1748 | return; |
||
1749 | |||
1750 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
||
1751 | if (reply & (1 << i)) { |
||
1752 | struct drm_display_mode *nmode; |
||
1753 | nmode = drm_mode_duplicate(connector->dev, |
||
1754 | &sdvo_tv_modes[i]); |
||
1755 | if (nmode) |
||
1756 | drm_mode_probed_add(connector, nmode); |
||
1757 | } |
||
1758 | } |
||
1759 | |||
1760 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
||
1761 | { |
||
1762 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1763 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
1764 | struct drm_display_mode *newmode; |
||
1765 | |||
1766 | /* |
||
1767 | * Attempt to get the mode list from DDC. |
||
1768 | * Assume that the preferred modes are |
||
1769 | * arranged in priority order. |
||
1770 | */ |
||
1771 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
||
1772 | if (list_empty(&connector->probed_modes) == false) |
||
1773 | goto end; |
||
1774 | |||
1775 | /* Fetch modes from VBT */ |
||
1776 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
||
1777 | newmode = drm_mode_duplicate(connector->dev, |
||
1778 | dev_priv->sdvo_lvds_vbt_mode); |
||
1779 | if (newmode != NULL) { |
||
1780 | /* Guarantee the mode is preferred */ |
||
1781 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
||
1782 | DRM_MODE_TYPE_DRIVER); |
||
1783 | drm_mode_probed_add(connector, newmode); |
||
1784 | } |
||
1785 | } |
||
1786 | |||
1787 | end: |
||
1788 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
||
1789 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
||
1790 | intel_sdvo->sdvo_lvds_fixed_mode = |
||
1791 | drm_mode_duplicate(connector->dev, newmode); |
||
1792 | |||
1793 | intel_sdvo->is_lvds = true; |
||
1794 | break; |
||
1795 | } |
||
1796 | } |
||
1797 | |||
1798 | } |
||
1799 | |||
1800 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
||
1801 | { |
||
1802 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
1803 | |||
1804 | if (IS_TV(intel_sdvo_connector)) |
||
1805 | intel_sdvo_get_tv_modes(connector); |
||
1806 | else if (IS_LVDS(intel_sdvo_connector)) |
||
1807 | intel_sdvo_get_lvds_modes(connector); |
||
1808 | else |
||
1809 | intel_sdvo_get_ddc_modes(connector); |
||
1810 | |||
1811 | return !list_empty(&connector->probed_modes); |
||
1812 | } |
||
1813 | |||
1814 | static void |
||
1815 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
||
1816 | { |
||
1817 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
1818 | struct drm_device *dev = connector->dev; |
||
1819 | |||
1820 | if (intel_sdvo_connector->left) |
||
1821 | drm_property_destroy(dev, intel_sdvo_connector->left); |
||
1822 | if (intel_sdvo_connector->right) |
||
1823 | drm_property_destroy(dev, intel_sdvo_connector->right); |
||
1824 | if (intel_sdvo_connector->top) |
||
1825 | drm_property_destroy(dev, intel_sdvo_connector->top); |
||
1826 | if (intel_sdvo_connector->bottom) |
||
1827 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
||
1828 | if (intel_sdvo_connector->hpos) |
||
1829 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
||
1830 | if (intel_sdvo_connector->vpos) |
||
1831 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
||
1832 | if (intel_sdvo_connector->saturation) |
||
1833 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
||
1834 | if (intel_sdvo_connector->contrast) |
||
1835 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
||
1836 | if (intel_sdvo_connector->hue) |
||
1837 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
||
1838 | if (intel_sdvo_connector->sharpness) |
||
1839 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
||
1840 | if (intel_sdvo_connector->flicker_filter) |
||
1841 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
||
1842 | if (intel_sdvo_connector->flicker_filter_2d) |
||
1843 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
||
1844 | if (intel_sdvo_connector->flicker_filter_adaptive) |
||
1845 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
||
1846 | if (intel_sdvo_connector->tv_luma_filter) |
||
1847 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
||
1848 | if (intel_sdvo_connector->tv_chroma_filter) |
||
1849 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
||
1850 | if (intel_sdvo_connector->dot_crawl) |
||
1851 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
||
1852 | if (intel_sdvo_connector->brightness) |
||
1853 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
||
1854 | } |
||
1855 | |||
1856 | static void intel_sdvo_destroy(struct drm_connector *connector) |
||
1857 | { |
||
1858 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
1859 | |||
1860 | if (intel_sdvo_connector->tv_format) |
||
1861 | drm_property_destroy(connector->dev, |
||
1862 | intel_sdvo_connector->tv_format); |
||
1863 | |||
1864 | intel_sdvo_destroy_enhance_property(connector); |
||
1865 | drm_sysfs_connector_remove(connector); |
||
1866 | drm_connector_cleanup(connector); |
||
3243 | Serge | 1867 | kfree(intel_sdvo_connector); |
2330 | Serge | 1868 | } |
1869 | |||
3031 | serge | 1870 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1871 | { |
||
1872 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1873 | struct edid *edid; |
||
1874 | bool has_audio = false; |
||
2330 | Serge | 1875 | |
3031 | serge | 1876 | if (!intel_sdvo->is_hdmi) |
1877 | return false; |
||
2330 | Serge | 1878 | |
3031 | serge | 1879 | edid = intel_sdvo_get_edid(connector); |
1880 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) |
||
1881 | has_audio = drm_detect_monitor_audio(edid); |
||
1882 | kfree(edid); |
||
2330 | Serge | 1883 | |
3031 | serge | 1884 | return has_audio; |
1885 | } |
||
2330 | Serge | 1886 | |
1887 | static int |
||
1888 | intel_sdvo_set_property(struct drm_connector *connector, |
||
1889 | struct drm_property *property, |
||
1890 | uint64_t val) |
||
1891 | { |
||
1892 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
||
1893 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
||
1894 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
1895 | uint16_t temp_value; |
||
1896 | uint8_t cmd; |
||
1897 | int ret; |
||
1898 | |||
3243 | Serge | 1899 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 1900 | if (ret) |
1901 | return ret; |
||
1902 | |||
1903 | if (property == dev_priv->force_audio_property) { |
||
1904 | int i = val; |
||
1905 | bool has_audio; |
||
1906 | |||
1907 | if (i == intel_sdvo_connector->force_audio) |
||
1908 | return 0; |
||
1909 | |||
1910 | intel_sdvo_connector->force_audio = i; |
||
1911 | |||
3031 | serge | 1912 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 1913 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
1914 | else |
||
3031 | serge | 1915 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 1916 | |
1917 | if (has_audio == intel_sdvo->has_hdmi_audio) |
||
1918 | return 0; |
||
1919 | |||
1920 | intel_sdvo->has_hdmi_audio = has_audio; |
||
1921 | goto done; |
||
1922 | } |
||
1923 | |||
1924 | if (property == dev_priv->broadcast_rgb_property) { |
||
3480 | Serge | 1925 | switch (val) { |
1926 | case INTEL_BROADCAST_RGB_AUTO: |
||
1927 | intel_sdvo->color_range_auto = true; |
||
1928 | break; |
||
1929 | case INTEL_BROADCAST_RGB_FULL: |
||
1930 | intel_sdvo->color_range_auto = false; |
||
1931 | intel_sdvo->color_range = 0; |
||
1932 | break; |
||
1933 | case INTEL_BROADCAST_RGB_LIMITED: |
||
1934 | intel_sdvo->color_range_auto = false; |
||
1935 | intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235; |
||
1936 | break; |
||
1937 | default: |
||
1938 | return -EINVAL; |
||
1939 | } |
||
2330 | Serge | 1940 | goto done; |
1941 | } |
||
1942 | |||
1943 | #define CHECK_PROPERTY(name, NAME) \ |
||
1944 | if (intel_sdvo_connector->name == property) { \ |
||
1945 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
||
1946 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
||
1947 | cmd = SDVO_CMD_SET_##NAME; \ |
||
1948 | intel_sdvo_connector->cur_##name = temp_value; \ |
||
1949 | goto set_value; \ |
||
1950 | } |
||
1951 | |||
1952 | if (property == intel_sdvo_connector->tv_format) { |
||
1953 | if (val >= TV_FORMAT_NUM) |
||
1954 | return -EINVAL; |
||
1955 | |||
1956 | if (intel_sdvo->tv_format_index == |
||
1957 | intel_sdvo_connector->tv_format_supported[val]) |
||
1958 | return 0; |
||
1959 | |||
1960 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
||
1961 | goto done; |
||
1962 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
||
1963 | temp_value = val; |
||
1964 | if (intel_sdvo_connector->left == property) { |
||
3243 | Serge | 1965 | drm_object_property_set_value(&connector->base, |
2330 | Serge | 1966 | intel_sdvo_connector->right, val); |
1967 | if (intel_sdvo_connector->left_margin == temp_value) |
||
1968 | return 0; |
||
1969 | |||
1970 | intel_sdvo_connector->left_margin = temp_value; |
||
1971 | intel_sdvo_connector->right_margin = temp_value; |
||
1972 | temp_value = intel_sdvo_connector->max_hscan - |
||
1973 | intel_sdvo_connector->left_margin; |
||
1974 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
||
1975 | goto set_value; |
||
1976 | } else if (intel_sdvo_connector->right == property) { |
||
3243 | Serge | 1977 | drm_object_property_set_value(&connector->base, |
2330 | Serge | 1978 | intel_sdvo_connector->left, val); |
1979 | if (intel_sdvo_connector->right_margin == temp_value) |
||
1980 | return 0; |
||
1981 | |||
1982 | intel_sdvo_connector->left_margin = temp_value; |
||
1983 | intel_sdvo_connector->right_margin = temp_value; |
||
1984 | temp_value = intel_sdvo_connector->max_hscan - |
||
1985 | intel_sdvo_connector->left_margin; |
||
1986 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
||
1987 | goto set_value; |
||
1988 | } else if (intel_sdvo_connector->top == property) { |
||
3243 | Serge | 1989 | drm_object_property_set_value(&connector->base, |
2330 | Serge | 1990 | intel_sdvo_connector->bottom, val); |
1991 | if (intel_sdvo_connector->top_margin == temp_value) |
||
1992 | return 0; |
||
1993 | |||
1994 | intel_sdvo_connector->top_margin = temp_value; |
||
1995 | intel_sdvo_connector->bottom_margin = temp_value; |
||
1996 | temp_value = intel_sdvo_connector->max_vscan - |
||
1997 | intel_sdvo_connector->top_margin; |
||
1998 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
||
1999 | goto set_value; |
||
2000 | } else if (intel_sdvo_connector->bottom == property) { |
||
3243 | Serge | 2001 | drm_object_property_set_value(&connector->base, |
2330 | Serge | 2002 | intel_sdvo_connector->top, val); |
2003 | if (intel_sdvo_connector->bottom_margin == temp_value) |
||
2004 | return 0; |
||
2005 | |||
2006 | intel_sdvo_connector->top_margin = temp_value; |
||
2007 | intel_sdvo_connector->bottom_margin = temp_value; |
||
2008 | temp_value = intel_sdvo_connector->max_vscan - |
||
2009 | intel_sdvo_connector->top_margin; |
||
2010 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
||
2011 | goto set_value; |
||
2012 | } |
||
2013 | CHECK_PROPERTY(hpos, HPOS) |
||
2014 | CHECK_PROPERTY(vpos, VPOS) |
||
2015 | CHECK_PROPERTY(saturation, SATURATION) |
||
2016 | CHECK_PROPERTY(contrast, CONTRAST) |
||
2017 | CHECK_PROPERTY(hue, HUE) |
||
2018 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
||
2019 | CHECK_PROPERTY(sharpness, SHARPNESS) |
||
2020 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
||
2021 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
||
2022 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
||
2023 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
||
2024 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
||
2025 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
||
2026 | } |
||
2027 | |||
2028 | return -EINVAL; /* unknown property */ |
||
2029 | |||
2030 | set_value: |
||
2031 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
||
2032 | return -EIO; |
||
2033 | |||
2034 | |||
2035 | done: |
||
3480 | Serge | 2036 | if (intel_sdvo->base.base.crtc) |
2037 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); |
||
2330 | Serge | 2038 | |
2039 | return 0; |
||
2040 | #undef CHECK_PROPERTY |
||
2041 | } |
||
2042 | |||
2043 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
||
2044 | .mode_fixup = intel_sdvo_mode_fixup, |
||
2045 | .mode_set = intel_sdvo_mode_set, |
||
2046 | }; |
||
2047 | |||
2048 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
||
3031 | serge | 2049 | .dpms = intel_sdvo_dpms, |
2330 | Serge | 2050 | .detect = intel_sdvo_detect, |
2051 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
2052 | .set_property = intel_sdvo_set_property, |
||
2053 | .destroy = intel_sdvo_destroy, |
||
2054 | }; |
||
2055 | |||
2056 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
||
2057 | .get_modes = intel_sdvo_get_modes, |
||
2058 | .mode_valid = intel_sdvo_mode_valid, |
||
2059 | .best_encoder = intel_best_encoder, |
||
2060 | }; |
||
2061 | |||
2062 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
||
2063 | { |
||
2064 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
||
2065 | |||
2066 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
||
2067 | drm_mode_destroy(encoder->dev, |
||
2068 | intel_sdvo->sdvo_lvds_fixed_mode); |
||
2069 | |||
3243 | Serge | 2070 | i2c_del_adapter(&intel_sdvo->ddc); |
2330 | Serge | 2071 | intel_encoder_destroy(encoder); |
2072 | } |
||
2073 | |||
2074 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
||
2075 | .destroy = intel_sdvo_enc_destroy, |
||
2076 | }; |
||
2077 | |||
2078 | static void |
||
2079 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
||
2080 | { |
||
2081 | uint16_t mask = 0; |
||
2082 | unsigned int num_bits; |
||
2083 | |||
2084 | /* Make a mask of outputs less than or equal to our own priority in the |
||
2085 | * list. |
||
2086 | */ |
||
2087 | switch (sdvo->controlled_output) { |
||
2088 | case SDVO_OUTPUT_LVDS1: |
||
2089 | mask |= SDVO_OUTPUT_LVDS1; |
||
2090 | case SDVO_OUTPUT_LVDS0: |
||
2091 | mask |= SDVO_OUTPUT_LVDS0; |
||
2092 | case SDVO_OUTPUT_TMDS1: |
||
2093 | mask |= SDVO_OUTPUT_TMDS1; |
||
2094 | case SDVO_OUTPUT_TMDS0: |
||
2095 | mask |= SDVO_OUTPUT_TMDS0; |
||
2096 | case SDVO_OUTPUT_RGB1: |
||
2097 | mask |= SDVO_OUTPUT_RGB1; |
||
2098 | case SDVO_OUTPUT_RGB0: |
||
2099 | mask |= SDVO_OUTPUT_RGB0; |
||
2100 | break; |
||
2101 | } |
||
2102 | |||
2103 | /* Count bits to find what number we are in the priority list. */ |
||
2104 | mask &= sdvo->caps.output_flags; |
||
2105 | num_bits = hweight16(mask); |
||
2106 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
||
2107 | if (num_bits > 3) |
||
2108 | num_bits = 3; |
||
2109 | |||
2110 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
||
2111 | sdvo->ddc_bus = 1 << num_bits; |
||
2112 | } |
||
2113 | |||
2114 | /** |
||
2115 | * Choose the appropriate DDC bus for control bus switch command for this |
||
2116 | * SDVO output based on the controlled output. |
||
2117 | * |
||
2118 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
||
2119 | * outputs, then LVDS outputs. |
||
2120 | */ |
||
2121 | static void |
||
2122 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
||
2123 | struct intel_sdvo *sdvo, u32 reg) |
||
2124 | { |
||
2125 | struct sdvo_device_mapping *mapping; |
||
2126 | |||
3031 | serge | 2127 | if (sdvo->is_sdvob) |
2330 | Serge | 2128 | mapping = &(dev_priv->sdvo_mappings[0]); |
2129 | else |
||
2130 | mapping = &(dev_priv->sdvo_mappings[1]); |
||
2131 | |||
2132 | if (mapping->initialized) |
||
2133 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
||
2134 | else |
||
2135 | intel_sdvo_guess_ddc_bus(sdvo); |
||
2136 | } |
||
2137 | |||
2138 | static void |
||
2139 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
||
2140 | struct intel_sdvo *sdvo, u32 reg) |
||
2141 | { |
||
2142 | struct sdvo_device_mapping *mapping; |
||
2342 | Serge | 2143 | u8 pin; |
2330 | Serge | 2144 | |
3031 | serge | 2145 | if (sdvo->is_sdvob) |
2330 | Serge | 2146 | mapping = &dev_priv->sdvo_mappings[0]; |
2147 | else |
||
2148 | mapping = &dev_priv->sdvo_mappings[1]; |
||
2149 | |||
3243 | Serge | 2150 | if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) |
2151 | pin = mapping->i2c_pin; |
||
2152 | else |
||
2330 | Serge | 2153 | pin = GMBUS_PORT_DPB; |
2154 | |||
3031 | serge | 2155 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
3243 | Serge | 2156 | |
2157 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow |
||
2158 | * our code totally fails once we start using gmbus. Hence fall back to |
||
2159 | * bit banging for now. */ |
||
2330 | Serge | 2160 | intel_gmbus_force_bit(sdvo->i2c, true); |
2161 | } |
||
2162 | |||
3243 | Serge | 2163 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2164 | static void |
||
2165 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) |
||
2166 | { |
||
2167 | intel_gmbus_force_bit(sdvo->i2c, false); |
||
2168 | } |
||
2169 | |||
2330 | Serge | 2170 | static bool |
2171 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
||
2172 | { |
||
2173 | return intel_sdvo_check_supp_encode(intel_sdvo); |
||
2174 | } |
||
2175 | |||
2176 | static u8 |
||
3031 | serge | 2177 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
2330 | Serge | 2178 | { |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2180 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
||
2181 | |||
3031 | serge | 2182 | if (sdvo->is_sdvob) { |
2330 | Serge | 2183 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2184 | other_mapping = &dev_priv->sdvo_mappings[1]; |
||
2185 | } else { |
||
2186 | my_mapping = &dev_priv->sdvo_mappings[1]; |
||
2187 | other_mapping = &dev_priv->sdvo_mappings[0]; |
||
2188 | } |
||
2189 | |||
2190 | /* If the BIOS described our SDVO device, take advantage of it. */ |
||
2191 | if (my_mapping->slave_addr) |
||
2192 | return my_mapping->slave_addr; |
||
2193 | |||
2194 | /* If the BIOS only described a different SDVO device, use the |
||
2195 | * address that it isn't using. |
||
2196 | */ |
||
2197 | if (other_mapping->slave_addr) { |
||
2198 | if (other_mapping->slave_addr == 0x70) |
||
2199 | return 0x72; |
||
2200 | else |
||
2201 | return 0x70; |
||
2202 | } |
||
2203 | |||
2204 | /* No SDVO device info is found for another DVO port, |
||
2205 | * so use mapping assumption we had before BIOS parsing. |
||
2206 | */ |
||
3031 | serge | 2207 | if (sdvo->is_sdvob) |
2330 | Serge | 2208 | return 0x70; |
2209 | else |
||
2210 | return 0x72; |
||
2211 | } |
||
2212 | |||
2213 | static void |
||
2214 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
||
2215 | struct intel_sdvo *encoder) |
||
2216 | { |
||
2217 | drm_connector_init(encoder->base.base.dev, |
||
2218 | &connector->base.base, |
||
2219 | &intel_sdvo_connector_funcs, |
||
2220 | connector->base.base.connector_type); |
||
2221 | |||
2222 | drm_connector_helper_add(&connector->base.base, |
||
2223 | &intel_sdvo_connector_helper_funcs); |
||
2224 | |||
3031 | serge | 2225 | connector->base.base.interlace_allowed = 1; |
2330 | Serge | 2226 | connector->base.base.doublescan_allowed = 0; |
2227 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
||
3031 | serge | 2228 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
2330 | Serge | 2229 | |
2230 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
||
2231 | drm_sysfs_connector_add(&connector->base.base); |
||
2232 | } |
||
2233 | |||
2234 | static void |
||
3480 | Serge | 2235 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2236 | struct intel_sdvo_connector *connector) |
||
2330 | Serge | 2237 | { |
2238 | struct drm_device *dev = connector->base.base.dev; |
||
2239 | |||
2240 | intel_attach_force_audio_property(&connector->base.base); |
||
3480 | Serge | 2241 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
2330 | Serge | 2242 | intel_attach_broadcast_rgb_property(&connector->base.base); |
3480 | Serge | 2243 | intel_sdvo->color_range_auto = true; |
2244 | } |
||
2330 | Serge | 2245 | } |
2246 | |||
2247 | static bool |
||
2248 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
||
2249 | { |
||
2250 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
||
2251 | struct drm_connector *connector; |
||
2342 | Serge | 2252 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
2330 | Serge | 2253 | struct intel_connector *intel_connector; |
2254 | struct intel_sdvo_connector *intel_sdvo_connector; |
||
2255 | |||
2256 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
||
2257 | if (!intel_sdvo_connector) |
||
2258 | return false; |
||
2259 | |||
2260 | if (device == 0) { |
||
2261 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
||
2262 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
||
2263 | } else if (device == 1) { |
||
2264 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
||
2265 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
||
2266 | } |
||
2267 | |||
2268 | intel_connector = &intel_sdvo_connector->base; |
||
2269 | connector = &intel_connector->base; |
||
3031 | serge | 2270 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2271 | intel_sdvo_connector->output_flag) { |
||
2342 | Serge | 2272 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
3031 | serge | 2273 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
2342 | Serge | 2274 | /* Some SDVO devices have one-shot hotplug interrupts. |
2275 | * Ensure that they get re-enabled when an interrupt happens. |
||
2276 | */ |
||
2277 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; |
||
2278 | intel_sdvo_enable_hotplug(intel_encoder); |
||
3031 | serge | 2279 | } else { |
2280 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
||
2342 | Serge | 2281 | } |
2330 | Serge | 2282 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2283 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
||
2284 | |||
2285 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
||
2286 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
||
2287 | intel_sdvo->is_hdmi = true; |
||
2288 | } |
||
2289 | |||
2290 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
||
2291 | if (intel_sdvo->is_hdmi) |
||
3480 | Serge | 2292 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
2330 | Serge | 2293 | |
2294 | return true; |
||
2295 | } |
||
2296 | |||
2297 | static bool |
||
2298 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
||
2299 | { |
||
2300 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
||
2301 | struct drm_connector *connector; |
||
2302 | struct intel_connector *intel_connector; |
||
2303 | struct intel_sdvo_connector *intel_sdvo_connector; |
||
2304 | |||
2305 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
||
2306 | if (!intel_sdvo_connector) |
||
2307 | return false; |
||
2308 | |||
2309 | intel_connector = &intel_sdvo_connector->base; |
||
2310 | connector = &intel_connector->base; |
||
2311 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
||
2312 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
||
2313 | |||
2314 | intel_sdvo->controlled_output |= type; |
||
2315 | intel_sdvo_connector->output_flag = type; |
||
2316 | |||
2317 | intel_sdvo->is_tv = true; |
||
2318 | intel_sdvo->base.needs_tv_clock = true; |
||
2319 | |||
2320 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
||
2321 | |||
2322 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
||
2323 | goto err; |
||
2324 | |||
2325 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
||
2326 | goto err; |
||
2327 | |||
2328 | return true; |
||
2329 | |||
2330 | err: |
||
2331 | intel_sdvo_destroy(connector); |
||
2332 | return false; |
||
2333 | } |
||
2334 | |||
2335 | static bool |
||
2336 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
||
2337 | { |
||
2338 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
||
2339 | struct drm_connector *connector; |
||
2340 | struct intel_connector *intel_connector; |
||
2341 | struct intel_sdvo_connector *intel_sdvo_connector; |
||
2342 | |||
2343 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
||
2344 | if (!intel_sdvo_connector) |
||
2345 | return false; |
||
2346 | |||
2347 | intel_connector = &intel_sdvo_connector->base; |
||
2348 | connector = &intel_connector->base; |
||
2349 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
||
2350 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
||
2351 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
||
2352 | |||
2353 | if (device == 0) { |
||
2354 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
||
2355 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
||
2356 | } else if (device == 1) { |
||
2357 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
||
2358 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
||
2359 | } |
||
2360 | |||
2361 | intel_sdvo_connector_init(intel_sdvo_connector, |
||
2362 | intel_sdvo); |
||
2363 | return true; |
||
2364 | } |
||
2365 | |||
2366 | static bool |
||
2367 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
||
2368 | { |
||
2369 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
||
2370 | struct drm_connector *connector; |
||
2371 | struct intel_connector *intel_connector; |
||
2372 | struct intel_sdvo_connector *intel_sdvo_connector; |
||
2373 | |||
2374 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
||
2375 | if (!intel_sdvo_connector) |
||
2376 | return false; |
||
2377 | |||
2378 | intel_connector = &intel_sdvo_connector->base; |
||
2379 | connector = &intel_connector->base; |
||
2380 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
||
2381 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
||
2382 | |||
2383 | if (device == 0) { |
||
2384 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
||
2385 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
||
2386 | } else if (device == 1) { |
||
2387 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
||
2388 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
||
2389 | } |
||
2390 | |||
2391 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
||
2392 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
||
2393 | goto err; |
||
2394 | |||
2395 | return true; |
||
2396 | |||
2397 | err: |
||
2398 | intel_sdvo_destroy(connector); |
||
2399 | return false; |
||
2400 | } |
||
2401 | |||
2402 | static bool |
||
2403 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
||
2404 | { |
||
2405 | intel_sdvo->is_tv = false; |
||
2406 | intel_sdvo->base.needs_tv_clock = false; |
||
2407 | intel_sdvo->is_lvds = false; |
||
2408 | |||
2409 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
||
2410 | |||
2411 | if (flags & SDVO_OUTPUT_TMDS0) |
||
2412 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
||
2413 | return false; |
||
2414 | |||
2415 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
||
2416 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
||
2417 | return false; |
||
2418 | |||
2419 | /* TV has no XXX1 function block */ |
||
2420 | if (flags & SDVO_OUTPUT_SVID0) |
||
2421 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
||
2422 | return false; |
||
2423 | |||
2424 | if (flags & SDVO_OUTPUT_CVBS0) |
||
2425 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
||
2426 | return false; |
||
2427 | |||
3031 | serge | 2428 | if (flags & SDVO_OUTPUT_YPRPB0) |
2429 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) |
||
2430 | return false; |
||
2431 | |||
2330 | Serge | 2432 | if (flags & SDVO_OUTPUT_RGB0) |
2433 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
||
2434 | return false; |
||
2435 | |||
2436 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
||
2437 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
||
2438 | return false; |
||
2439 | |||
2440 | if (flags & SDVO_OUTPUT_LVDS0) |
||
2441 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
||
2442 | return false; |
||
2443 | |||
2444 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
||
2445 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
||
2446 | return false; |
||
2447 | |||
2448 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
||
2449 | unsigned char bytes[2]; |
||
2450 | |||
2451 | intel_sdvo->controlled_output = 0; |
||
2452 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
||
2453 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
||
2454 | SDVO_NAME(intel_sdvo), |
||
2455 | bytes[0], bytes[1]); |
||
2456 | return false; |
||
2457 | } |
||
2342 | Serge | 2458 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2330 | Serge | 2459 | |
2460 | return true; |
||
2461 | } |
||
2462 | |||
3120 | serge | 2463 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2464 | { |
||
2465 | struct drm_device *dev = intel_sdvo->base.base.dev; |
||
2466 | struct drm_connector *connector, *tmp; |
||
2467 | |||
2468 | list_for_each_entry_safe(connector, tmp, |
||
2469 | &dev->mode_config.connector_list, head) { |
||
2470 | if (intel_attached_encoder(connector) == &intel_sdvo->base) |
||
2471 | intel_sdvo_destroy(connector); |
||
2472 | } |
||
2473 | } |
||
2474 | |||
2330 | Serge | 2475 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2476 | struct intel_sdvo_connector *intel_sdvo_connector, |
||
2477 | int type) |
||
2478 | { |
||
2479 | struct drm_device *dev = intel_sdvo->base.base.dev; |
||
2480 | struct intel_sdvo_tv_format format; |
||
2481 | uint32_t format_map, i; |
||
2482 | |||
2483 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
||
2484 | return false; |
||
2485 | |||
2486 | BUILD_BUG_ON(sizeof(format) != 6); |
||
2487 | if (!intel_sdvo_get_value(intel_sdvo, |
||
2488 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
||
2489 | &format, sizeof(format))) |
||
2490 | return false; |
||
2491 | |||
2492 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
||
2493 | |||
2494 | if (format_map == 0) |
||
2495 | return false; |
||
2496 | |||
2497 | intel_sdvo_connector->format_supported_num = 0; |
||
2498 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
||
2499 | if (format_map & (1 << i)) |
||
2500 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
||
2501 | |||
2502 | |||
2503 | intel_sdvo_connector->tv_format = |
||
2504 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
||
2505 | "mode", intel_sdvo_connector->format_supported_num); |
||
2506 | if (!intel_sdvo_connector->tv_format) |
||
2507 | return false; |
||
2508 | |||
2509 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
||
2510 | drm_property_add_enum( |
||
2511 | intel_sdvo_connector->tv_format, i, |
||
2512 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
||
2513 | |||
2514 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
||
3243 | Serge | 2515 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
2330 | Serge | 2516 | intel_sdvo_connector->tv_format, 0); |
2517 | return true; |
||
2518 | |||
2519 | } |
||
2520 | |||
2521 | #define ENHANCEMENT(name, NAME) do { \ |
||
2522 | if (enhancements.name) { \ |
||
2523 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
||
2524 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
||
2525 | return false; \ |
||
2526 | intel_sdvo_connector->max_##name = data_value[0]; \ |
||
2527 | intel_sdvo_connector->cur_##name = response; \ |
||
2528 | intel_sdvo_connector->name = \ |
||
3031 | serge | 2529 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
2330 | Serge | 2530 | if (!intel_sdvo_connector->name) return false; \ |
3243 | Serge | 2531 | drm_object_attach_property(&connector->base, \ |
2330 | Serge | 2532 | intel_sdvo_connector->name, \ |
2533 | intel_sdvo_connector->cur_##name); \ |
||
2534 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
||
2535 | data_value[0], data_value[1], response); \ |
||
2536 | } \ |
||
2342 | Serge | 2537 | } while (0) |
2330 | Serge | 2538 | |
2539 | static bool |
||
2540 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
||
2541 | struct intel_sdvo_connector *intel_sdvo_connector, |
||
2542 | struct intel_sdvo_enhancements_reply enhancements) |
||
2543 | { |
||
2544 | struct drm_device *dev = intel_sdvo->base.base.dev; |
||
2545 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
||
2546 | uint16_t response, data_value[2]; |
||
2547 | |||
2548 | /* when horizontal overscan is supported, Add the left/right property */ |
||
2549 | if (enhancements.overscan_h) { |
||
2550 | if (!intel_sdvo_get_value(intel_sdvo, |
||
2551 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
||
2552 | &data_value, 4)) |
||
2553 | return false; |
||
2554 | |||
2555 | if (!intel_sdvo_get_value(intel_sdvo, |
||
2556 | SDVO_CMD_GET_OVERSCAN_H, |
||
2557 | &response, 2)) |
||
2558 | return false; |
||
2559 | |||
2560 | intel_sdvo_connector->max_hscan = data_value[0]; |
||
2561 | intel_sdvo_connector->left_margin = data_value[0] - response; |
||
2562 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
||
2563 | intel_sdvo_connector->left = |
||
3031 | serge | 2564 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
2330 | Serge | 2565 | if (!intel_sdvo_connector->left) |
2566 | return false; |
||
2567 | |||
3243 | Serge | 2568 | drm_object_attach_property(&connector->base, |
2330 | Serge | 2569 | intel_sdvo_connector->left, |
2570 | intel_sdvo_connector->left_margin); |
||
2571 | |||
2572 | intel_sdvo_connector->right = |
||
3031 | serge | 2573 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
2330 | Serge | 2574 | if (!intel_sdvo_connector->right) |
2575 | return false; |
||
2576 | |||
3243 | Serge | 2577 | drm_object_attach_property(&connector->base, |
2330 | Serge | 2578 | intel_sdvo_connector->right, |
2579 | intel_sdvo_connector->right_margin); |
||
2580 | DRM_DEBUG_KMS("h_overscan: max %d, " |
||
2581 | "default %d, current %d\n", |
||
2582 | data_value[0], data_value[1], response); |
||
2583 | } |
||
2584 | |||
2585 | if (enhancements.overscan_v) { |
||
2586 | if (!intel_sdvo_get_value(intel_sdvo, |
||
2587 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
||
2588 | &data_value, 4)) |
||
2589 | return false; |
||
2590 | |||
2591 | if (!intel_sdvo_get_value(intel_sdvo, |
||
2592 | SDVO_CMD_GET_OVERSCAN_V, |
||
2593 | &response, 2)) |
||
2594 | return false; |
||
2595 | |||
2596 | intel_sdvo_connector->max_vscan = data_value[0]; |
||
2597 | intel_sdvo_connector->top_margin = data_value[0] - response; |
||
2598 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
||
2599 | intel_sdvo_connector->top = |
||
3031 | serge | 2600 | drm_property_create_range(dev, 0, |
2601 | "top_margin", 0, data_value[0]); |
||
2330 | Serge | 2602 | if (!intel_sdvo_connector->top) |
2603 | return false; |
||
2604 | |||
3243 | Serge | 2605 | drm_object_attach_property(&connector->base, |
2330 | Serge | 2606 | intel_sdvo_connector->top, |
2607 | intel_sdvo_connector->top_margin); |
||
2608 | |||
2609 | intel_sdvo_connector->bottom = |
||
3031 | serge | 2610 | drm_property_create_range(dev, 0, |
2611 | "bottom_margin", 0, data_value[0]); |
||
2330 | Serge | 2612 | if (!intel_sdvo_connector->bottom) |
2613 | return false; |
||
2614 | |||
3243 | Serge | 2615 | drm_object_attach_property(&connector->base, |
2330 | Serge | 2616 | intel_sdvo_connector->bottom, |
2617 | intel_sdvo_connector->bottom_margin); |
||
2618 | DRM_DEBUG_KMS("v_overscan: max %d, " |
||
2619 | "default %d, current %d\n", |
||
2620 | data_value[0], data_value[1], response); |
||
2621 | } |
||
2622 | |||
2623 | ENHANCEMENT(hpos, HPOS); |
||
2624 | ENHANCEMENT(vpos, VPOS); |
||
2625 | ENHANCEMENT(saturation, SATURATION); |
||
2626 | ENHANCEMENT(contrast, CONTRAST); |
||
2627 | ENHANCEMENT(hue, HUE); |
||
2628 | ENHANCEMENT(sharpness, SHARPNESS); |
||
2629 | ENHANCEMENT(brightness, BRIGHTNESS); |
||
2630 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
||
2631 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
||
2632 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
||
2633 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
||
2634 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
||
2635 | |||
2636 | if (enhancements.dot_crawl) { |
||
2637 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
||
2638 | return false; |
||
2639 | |||
2640 | intel_sdvo_connector->max_dot_crawl = 1; |
||
2641 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
||
2642 | intel_sdvo_connector->dot_crawl = |
||
3031 | serge | 2643 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
2330 | Serge | 2644 | if (!intel_sdvo_connector->dot_crawl) |
2645 | return false; |
||
2646 | |||
3243 | Serge | 2647 | drm_object_attach_property(&connector->base, |
2330 | Serge | 2648 | intel_sdvo_connector->dot_crawl, |
2649 | intel_sdvo_connector->cur_dot_crawl); |
||
2650 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
||
2651 | } |
||
2652 | |||
2653 | return true; |
||
2654 | } |
||
2655 | |||
2656 | static bool |
||
2657 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
||
2658 | struct intel_sdvo_connector *intel_sdvo_connector, |
||
2659 | struct intel_sdvo_enhancements_reply enhancements) |
||
2660 | { |
||
2661 | struct drm_device *dev = intel_sdvo->base.base.dev; |
||
2662 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
||
2663 | uint16_t response, data_value[2]; |
||
2664 | |||
2665 | ENHANCEMENT(brightness, BRIGHTNESS); |
||
2666 | |||
2667 | return true; |
||
2668 | } |
||
2669 | #undef ENHANCEMENT |
||
2670 | |||
2671 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
||
2672 | struct intel_sdvo_connector *intel_sdvo_connector) |
||
2673 | { |
||
2674 | union { |
||
2675 | struct intel_sdvo_enhancements_reply reply; |
||
2676 | uint16_t response; |
||
2677 | } enhancements; |
||
2678 | |||
2679 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
||
2680 | |||
2681 | enhancements.response = 0; |
||
2682 | intel_sdvo_get_value(intel_sdvo, |
||
2683 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
||
2684 | &enhancements, sizeof(enhancements)); |
||
2685 | if (enhancements.response == 0) { |
||
2686 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
||
2687 | return true; |
||
2688 | } |
||
2689 | |||
2690 | if (IS_TV(intel_sdvo_connector)) |
||
2691 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
||
2342 | Serge | 2692 | else if (IS_LVDS(intel_sdvo_connector)) |
2330 | Serge | 2693 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2694 | else |
||
2695 | return true; |
||
2696 | } |
||
2697 | |||
2698 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
||
2699 | struct i2c_msg *msgs, |
||
2700 | int num) |
||
2701 | { |
||
2702 | struct intel_sdvo *sdvo = adapter->algo_data; |
||
2703 | |||
2704 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
||
2705 | return -EIO; |
||
2706 | |||
2707 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
||
2708 | } |
||
2709 | |||
2710 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
||
2711 | { |
||
2712 | struct intel_sdvo *sdvo = adapter->algo_data; |
||
2713 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
||
2714 | } |
||
2715 | |||
2716 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
||
2717 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
||
2718 | .functionality = intel_sdvo_ddc_proxy_func |
||
2719 | }; |
||
2720 | |||
2721 | static bool |
||
2722 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
||
2723 | struct drm_device *dev) |
||
2724 | { |
||
3031 | serge | 2725 | sdvo->ddc.owner = THIS_MODULE; |
2330 | Serge | 2726 | sdvo->ddc.class = I2C_CLASS_DDC; |
2727 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
||
2728 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
||
2729 | sdvo->ddc.algo_data = sdvo; |
||
2730 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
||
2731 | |||
3243 | Serge | 2732 | return i2c_add_adapter(&sdvo->ddc) == 0; |
2330 | Serge | 2733 | } |
2734 | |||
3031 | serge | 2735 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
2330 | Serge | 2736 | { |
2737 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2738 | struct intel_encoder *intel_encoder; |
||
2739 | struct intel_sdvo *intel_sdvo; |
||
3031 | serge | 2740 | u32 hotplug_mask; |
2330 | Serge | 2741 | int i; |
2742 | |||
2743 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
||
2744 | if (!intel_sdvo) |
||
2745 | return false; |
||
2746 | |||
2747 | intel_sdvo->sdvo_reg = sdvo_reg; |
||
3031 | serge | 2748 | intel_sdvo->is_sdvob = is_sdvob; |
2749 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; |
||
2330 | Serge | 2750 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
3243 | Serge | 2751 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2752 | goto err_i2c_bus; |
||
2330 | Serge | 2753 | |
2754 | /* encoder type will be decided later */ |
||
2755 | intel_encoder = &intel_sdvo->base; |
||
2756 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
||
2757 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
||
2758 | |||
2759 | /* Read the regs to test if we can talk to the device */ |
||
2760 | for (i = 0; i < 0x40; i++) { |
||
2761 | u8 byte; |
||
2762 | |||
2763 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
||
3031 | serge | 2764 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2765 | SDVO_NAME(intel_sdvo)); |
||
2330 | Serge | 2766 | goto err; |
2767 | } |
||
2768 | } |
||
2769 | |||
3031 | serge | 2770 | hotplug_mask = 0; |
2771 | if (IS_G4X(dev)) { |
||
2772 | hotplug_mask = intel_sdvo->is_sdvob ? |
||
2773 | SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X; |
||
2774 | } else if (IS_GEN4(dev)) { |
||
2775 | hotplug_mask = intel_sdvo->is_sdvob ? |
||
2776 | SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965; |
||
2777 | } else { |
||
2778 | hotplug_mask = intel_sdvo->is_sdvob ? |
||
2779 | SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; |
||
2780 | } |
||
2330 | Serge | 2781 | |
2782 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
||
2783 | |||
3031 | serge | 2784 | intel_encoder->disable = intel_disable_sdvo; |
2785 | intel_encoder->enable = intel_enable_sdvo; |
||
2786 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
||
2787 | |||
2330 | Serge | 2788 | /* In default case sdvo lvds is false */ |
2789 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
||
2790 | goto err; |
||
2791 | |||
2792 | if (intel_sdvo_output_setup(intel_sdvo, |
||
2793 | intel_sdvo->caps.output_flags) != true) { |
||
3031 | serge | 2794 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
2795 | SDVO_NAME(intel_sdvo)); |
||
3120 | serge | 2796 | /* Output_setup can leave behind connectors! */ |
2797 | goto err_output; |
||
2330 | Serge | 2798 | } |
2799 | |||
3120 | serge | 2800 | /* |
2801 | * Cloning SDVO with anything is often impossible, since the SDVO |
||
2802 | * encoder can request a special input timing mode. And even if that's |
||
2803 | * not the case we have evidence that cloning a plain unscaled mode with |
||
2804 | * VGA doesn't really work. Furthermore the cloning flags are way too |
||
2805 | * simplistic anyway to express such constraints, so just give up on |
||
2806 | * cloning for SDVO encoders. |
||
2807 | */ |
||
2808 | intel_sdvo->base.cloneable = false; |
||
2809 | |||
3031 | serge | 2810 | /* Only enable the hotplug irq if we need it, to work around noisy |
2811 | * hotplug lines. |
||
2812 | */ |
||
2813 | if (intel_sdvo->hotplug_active) |
||
2814 | dev_priv->hotplug_supported_mask |= hotplug_mask; |
||
2815 | |||
2330 | Serge | 2816 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
2817 | |||
2818 | /* Set the input timing to the screen. Assume always input 0. */ |
||
2819 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
||
3120 | serge | 2820 | goto err_output; |
2330 | Serge | 2821 | |
2822 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
||
2823 | &intel_sdvo->pixel_clock_min, |
||
2824 | &intel_sdvo->pixel_clock_max)) |
||
3120 | serge | 2825 | goto err_output; |
2330 | Serge | 2826 | |
2827 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
||
2828 | "clock range %dMHz - %dMHz, " |
||
2829 | "input 1: %c, input 2: %c, " |
||
2830 | "output 1: %c, output 2: %c\n", |
||
2831 | SDVO_NAME(intel_sdvo), |
||
2832 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
||
2833 | intel_sdvo->caps.device_rev_id, |
||
2834 | intel_sdvo->pixel_clock_min / 1000, |
||
2835 | intel_sdvo->pixel_clock_max / 1000, |
||
2836 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
||
2837 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
||
2838 | /* check currently supported outputs */ |
||
2839 | intel_sdvo->caps.output_flags & |
||
2840 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
||
2841 | intel_sdvo->caps.output_flags & |
||
2842 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
||
2843 | return true; |
||
2844 | |||
3120 | serge | 2845 | err_output: |
2846 | intel_sdvo_output_cleanup(intel_sdvo); |
||
2847 | |||
2330 | Serge | 2848 | err: |
2849 | drm_encoder_cleanup(&intel_encoder->base); |
||
3243 | Serge | 2850 | i2c_del_adapter(&intel_sdvo->ddc); |
2851 | err_i2c_bus: |
||
2852 | intel_sdvo_unselect_i2c_bus(intel_sdvo); |
||
2330 | Serge | 2853 | kfree(intel_sdvo); |
2854 | |||
2855 | return false; |
||
2856 | }>>><>>><>><>><>><>><>>><>>><>>>>><>><>>><>>>=>=>><>><>><>><>><>><>><>><>><>><>><>>=>>>>>>>> |