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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
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3 | |||
5060 | serge | 4 | #include |
6084 | serge | 5 | #include "i915_gem_batch_pool.h" |
5060 | serge | 6 | |
7 | #define I915_CMD_HASH_ORDER 9 |
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8 | |||
5354 | serge | 9 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
10 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
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11 | * to give some inclination as to some of the magic values used in the various |
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12 | * workarounds! |
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13 | */ |
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14 | #define CACHELINE_BYTES 64 |
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6084 | serge | 15 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
5354 | serge | 16 | |
3243 | Serge | 17 | /* |
18 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
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19 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
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20 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
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21 | * |
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22 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
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23 | * cacheline, the Head Pointer must not be greater than the Tail |
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24 | * Pointer." |
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25 | */ |
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26 | #define I915_RING_FREE_SPACE 64 |
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27 | |||
2326 | Serge | 28 | struct intel_hw_status_page { |
3031 | serge | 29 | u32 *page_addr; |
2326 | Serge | 30 | unsigned int gfx_addr; |
31 | struct drm_i915_gem_object *obj; |
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32 | }; |
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33 | |||
34 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
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35 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
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36 | |||
37 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
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38 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
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39 | |||
40 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
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41 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
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42 | |||
43 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
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44 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
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45 | |||
46 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
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47 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
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48 | |||
5060 | serge | 49 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
50 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
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51 | |||
52 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
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53 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
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54 | */ |
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55 | #define i915_semaphore_seqno_size sizeof(uint64_t) |
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56 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
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57 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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58 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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59 | (i915_semaphore_seqno_size * (to))) |
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60 | |||
61 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
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62 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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63 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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64 | (i915_semaphore_seqno_size * (__ring)->id)) |
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65 | |||
66 | #define GEN8_RING_SEMAPHORE_INIT do { \ |
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67 | if (!dev_priv->semaphore_obj) { \ |
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68 | break; \ |
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69 | } \ |
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70 | ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \ |
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71 | ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \ |
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72 | ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \ |
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73 | ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \ |
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74 | ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \ |
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75 | ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \ |
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76 | } while(0) |
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77 | |||
4104 | Serge | 78 | enum intel_ring_hangcheck_action { |
4560 | Serge | 79 | HANGCHECK_IDLE = 0, |
4104 | Serge | 80 | HANGCHECK_WAIT, |
81 | HANGCHECK_ACTIVE, |
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5060 | serge | 82 | HANGCHECK_ACTIVE_LOOP, |
4104 | Serge | 83 | HANGCHECK_KICK, |
84 | HANGCHECK_HUNG, |
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85 | }; |
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2326 | Serge | 86 | |
5060 | serge | 87 | #define HANGCHECK_SCORE_RING_HUNG 31 |
88 | |||
4104 | Serge | 89 | struct intel_ring_hangcheck { |
5060 | serge | 90 | u64 acthd; |
91 | u64 max_acthd; |
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4104 | Serge | 92 | u32 seqno; |
93 | int score; |
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94 | enum intel_ring_hangcheck_action action; |
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5060 | serge | 95 | int deadlock; |
7144 | serge | 96 | u32 instdone[I915_NUM_INSTDONE_REG]; |
4104 | Serge | 97 | }; |
98 | |||
5060 | serge | 99 | struct intel_ringbuffer { |
100 | struct drm_i915_gem_object *obj; |
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6084 | serge | 101 | void __iomem *virtual_start; |
7144 | serge | 102 | struct i915_vma *vma; |
2326 | Serge | 103 | |
5354 | serge | 104 | struct intel_engine_cs *ring; |
6937 | serge | 105 | struct list_head link; |
5354 | serge | 106 | |
6084 | serge | 107 | u32 head; |
108 | u32 tail; |
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109 | int space; |
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110 | int size; |
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111 | int effective_size; |
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112 | int reserved_size; |
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113 | int reserved_tail; |
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114 | bool reserved_in_use; |
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5354 | serge | 115 | |
3031 | serge | 116 | /** We track the position of the requests in the ring buffer, and |
117 | * when each is retired we increment last_retired_head as the GPU |
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118 | * must have finished processing the request and so we know we |
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119 | * can advance the ringbuffer up to that position. |
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120 | * |
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121 | * last_retired_head is set to -1 after the value is consumed so |
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122 | * we can detect new retirements. |
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123 | */ |
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6084 | serge | 124 | u32 last_retired_head; |
5060 | serge | 125 | }; |
3031 | serge | 126 | |
6084 | serge | 127 | struct intel_context; |
128 | struct drm_i915_reg_descriptor; |
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129 | |||
130 | /* |
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131 | * we use a single page to load ctx workarounds so all of these |
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132 | * values are referred in terms of dwords |
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133 | * |
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134 | * struct i915_wa_ctx_bb: |
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135 | * offset: specifies batch starting position, also helpful in case |
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136 | * if we want to have multiple batches at different offsets based on |
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137 | * some criteria. It is not a requirement at the moment but provides |
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138 | * an option for future use. |
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139 | * size: size of the batch in DWORDS |
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140 | */ |
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141 | struct i915_ctx_workarounds { |
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142 | struct i915_wa_ctx_bb { |
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143 | u32 offset; |
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144 | u32 size; |
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145 | } indirect_ctx, per_ctx; |
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146 | struct drm_i915_gem_object *obj; |
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147 | }; |
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148 | |||
5060 | serge | 149 | struct intel_engine_cs { |
150 | const char *name; |
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151 | enum intel_ring_id { |
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7144 | serge | 152 | RCS = 0, |
153 | BCS, |
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5060 | serge | 154 | VCS, |
7144 | serge | 155 | VCS2, /* Keep instances of the same type engine together. */ |
156 | VECS |
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5060 | serge | 157 | } id; |
158 | #define I915_NUM_RINGS 5 |
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7144 | serge | 159 | #define _VCS(n) (VCS + (n)) |
160 | unsigned int exec_id; |
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161 | unsigned int guc_id; |
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5060 | serge | 162 | u32 mmio_base; |
163 | struct drm_device *dev; |
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164 | struct intel_ringbuffer *buffer; |
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6937 | serge | 165 | struct list_head buffers; |
5060 | serge | 166 | |
6084 | serge | 167 | /* |
168 | * A pool of objects to use as shadow copies of client batch buffers |
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169 | * when the command parser is enabled. Prevents the client from |
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170 | * modifying the batch contents after software parsing. |
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171 | */ |
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172 | struct i915_gem_batch_pool batch_pool; |
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173 | |||
5060 | serge | 174 | struct intel_hw_status_page status_page; |
6084 | serge | 175 | struct i915_ctx_workarounds wa_ctx; |
5060 | serge | 176 | |
4104 | Serge | 177 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
3031 | serge | 178 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
6084 | serge | 179 | struct drm_i915_gem_request *trace_irq_req; |
5060 | serge | 180 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
181 | void (*irq_put)(struct intel_engine_cs *ring); |
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2326 | Serge | 182 | |
6084 | serge | 183 | int (*init_hw)(struct intel_engine_cs *ring); |
2326 | Serge | 184 | |
6084 | serge | 185 | int (*init_context)(struct drm_i915_gem_request *req); |
5354 | serge | 186 | |
5060 | serge | 187 | void (*write_tail)(struct intel_engine_cs *ring, |
2326 | Serge | 188 | u32 value); |
6084 | serge | 189 | int __must_check (*flush)(struct drm_i915_gem_request *req, |
2326 | Serge | 190 | u32 invalidate_domains, |
191 | u32 flush_domains); |
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6084 | serge | 192 | int (*add_request)(struct drm_i915_gem_request *req); |
3031 | serge | 193 | /* Some chipsets are not quite as coherent as advertised and need |
194 | * an expensive kick to force a true read of the up-to-date seqno. |
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195 | * However, the up-to-date seqno is not always required and the last |
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196 | * seen value is good enough. Note that the seqno will always be |
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197 | * monotonic, even if not coherent. |
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198 | */ |
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5060 | serge | 199 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
3031 | serge | 200 | bool lazy_coherency); |
5060 | serge | 201 | void (*set_seqno)(struct intel_engine_cs *ring, |
3480 | Serge | 202 | u32 seqno); |
6084 | serge | 203 | int (*dispatch_execbuffer)(struct drm_i915_gem_request *req, |
5060 | serge | 204 | u64 offset, u32 length, |
6084 | serge | 205 | unsigned dispatch_flags); |
3243 | Serge | 206 | #define I915_DISPATCH_SECURE 0x1 |
207 | #define I915_DISPATCH_PINNED 0x2 |
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6084 | serge | 208 | #define I915_DISPATCH_RS 0x4 |
5060 | serge | 209 | void (*cleanup)(struct intel_engine_cs *ring); |
2326 | Serge | 210 | |
5060 | serge | 211 | /* GEN8 signal/wait table - never trust comments! |
212 | * signal to signal to signal to signal to signal to |
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213 | * RCS VCS BCS VECS VCS2 |
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214 | * -------------------------------------------------------------------- |
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215 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
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216 | * |------------------------------------------------------------------- |
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217 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
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218 | * |------------------------------------------------------------------- |
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219 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
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220 | * |------------------------------------------------------------------- |
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221 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
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222 | * |------------------------------------------------------------------- |
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223 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
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224 | * |------------------------------------------------------------------- |
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225 | * |
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226 | * Generalization: |
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227 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
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228 | * ie. transpose of g(x, y) |
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229 | * |
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230 | * sync from sync from sync from sync from sync from |
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231 | * RCS VCS BCS VECS VCS2 |
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232 | * -------------------------------------------------------------------- |
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233 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
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234 | * |------------------------------------------------------------------- |
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235 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
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236 | * |------------------------------------------------------------------- |
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237 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
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238 | * |------------------------------------------------------------------- |
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239 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
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240 | * |------------------------------------------------------------------- |
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241 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
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242 | * |------------------------------------------------------------------- |
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243 | * |
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244 | * Generalization: |
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245 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
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246 | * ie. transpose of f(x, y) |
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247 | */ |
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248 | struct { |
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249 | u32 sync_seqno[I915_NUM_RINGS-1]; |
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250 | |||
251 | union { |
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6084 | serge | 252 | struct { |
253 | /* our mbox written by others */ |
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254 | u32 wait[I915_NUM_RINGS]; |
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255 | /* mboxes this ring signals to */ |
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6937 | serge | 256 | i915_reg_t signal[I915_NUM_RINGS]; |
6084 | serge | 257 | } mbox; |
5060 | serge | 258 | u64 signal_ggtt[I915_NUM_RINGS]; |
259 | }; |
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4104 | Serge | 260 | |
5060 | serge | 261 | /* AKA wait() */ |
6084 | serge | 262 | int (*sync_to)(struct drm_i915_gem_request *to_req, |
263 | struct intel_engine_cs *from, |
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5060 | serge | 264 | u32 seqno); |
6084 | serge | 265 | int (*signal)(struct drm_i915_gem_request *signaller_req, |
5060 | serge | 266 | /* num_dwords needed by caller */ |
267 | unsigned int num_dwords); |
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268 | } semaphore; |
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269 | |||
5354 | serge | 270 | /* Execlists */ |
271 | spinlock_t execlist_lock; |
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272 | struct list_head execlist_queue; |
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273 | struct list_head execlist_retired_req_list; |
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274 | u8 next_context_status_buffer; |
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7144 | serge | 275 | bool disable_lite_restore_wa; |
276 | u32 ctx_desc_template; |
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5354 | serge | 277 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
6084 | serge | 278 | int (*emit_request)(struct drm_i915_gem_request *request); |
279 | int (*emit_flush)(struct drm_i915_gem_request *request, |
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5354 | serge | 280 | u32 invalidate_domains, |
281 | u32 flush_domains); |
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6084 | serge | 282 | int (*emit_bb_start)(struct drm_i915_gem_request *req, |
283 | u64 offset, unsigned dispatch_flags); |
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5354 | serge | 284 | |
2326 | Serge | 285 | /** |
286 | * List of objects currently involved in rendering from the |
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287 | * ringbuffer. |
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288 | * |
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289 | * Includes buffers having the contents of their GPU caches |
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6084 | serge | 290 | * flushed, not necessarily primitives. last_read_req |
2326 | Serge | 291 | * represents when the rendering involved will be completed. |
292 | * |
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293 | * A reference is held on the buffer while on this list. |
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294 | */ |
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295 | struct list_head active_list; |
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296 | |||
297 | /** |
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298 | * List of breadcrumbs associated with GPU requests currently |
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299 | * outstanding. |
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300 | */ |
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301 | struct list_head request_list; |
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302 | |||
303 | /** |
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6084 | serge | 304 | * Seqno of request most recently submitted to request_list. |
305 | * Used exclusively by hang checker to avoid grabbing lock while |
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306 | * inspecting request list. |
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2326 | Serge | 307 | */ |
6084 | serge | 308 | u32 last_submitted_seqno; |
309 | |||
3031 | serge | 310 | bool gpu_caches_dirty; |
2326 | Serge | 311 | |
2352 | Serge | 312 | wait_queue_head_t irq_queue; |
2326 | Serge | 313 | |
5060 | serge | 314 | struct intel_context *last_context; |
3031 | serge | 315 | |
4104 | Serge | 316 | struct intel_ring_hangcheck hangcheck; |
317 | |||
318 | struct { |
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319 | struct drm_i915_gem_object *obj; |
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320 | u32 gtt_offset; |
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321 | volatile u32 *cpu_page; |
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322 | } scratch; |
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5060 | serge | 323 | |
324 | bool needs_cmd_parser; |
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325 | |||
326 | /* |
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327 | * Table of commands the command parser needs to know about |
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328 | * for this ring. |
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329 | */ |
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330 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
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331 | |||
332 | /* |
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333 | * Table of registers allowed in commands that read/write registers. |
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334 | */ |
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6084 | serge | 335 | const struct drm_i915_reg_descriptor *reg_table; |
5060 | serge | 336 | int reg_count; |
337 | |||
338 | /* |
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339 | * Table of registers allowed in commands that read/write registers, but |
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340 | * only from the DRM master. |
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341 | */ |
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6084 | serge | 342 | const struct drm_i915_reg_descriptor *master_reg_table; |
5060 | serge | 343 | int master_reg_count; |
344 | |||
345 | /* |
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346 | * Returns the bitmask for the length field of the specified command. |
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347 | * Return 0 for an unrecognized/invalid command. |
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348 | * |
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349 | * If the command parser finds an entry for a command in the ring's |
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350 | * cmd_tables, it gets the command's length based on the table entry. |
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351 | * If not, it calls this function to determine the per-ring length field |
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352 | * encoding for the command (i.e. certain opcode ranges use certain bits |
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353 | * to encode the command length in the header). |
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354 | */ |
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355 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
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2326 | Serge | 356 | }; |
357 | |||
6937 | serge | 358 | static inline bool |
359 | intel_ring_initialized(struct intel_engine_cs *ring) |
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360 | { |
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361 | return ring->dev != NULL; |
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362 | } |
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3031 | serge | 363 | |
364 | static inline unsigned |
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5060 | serge | 365 | intel_ring_flag(struct intel_engine_cs *ring) |
3031 | serge | 366 | { |
367 | return 1 << ring->id; |
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368 | } |
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369 | |||
2326 | Serge | 370 | static inline u32 |
5060 | serge | 371 | intel_ring_sync_index(struct intel_engine_cs *ring, |
372 | struct intel_engine_cs *other) |
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2326 | Serge | 373 | { |
374 | int idx; |
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375 | |||
376 | /* |
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5060 | serge | 377 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
378 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
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379 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
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380 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
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381 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
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2326 | Serge | 382 | */ |
383 | |||
384 | idx = (other - ring) - 1; |
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385 | if (idx < 0) |
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386 | idx += I915_NUM_RINGS; |
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387 | |||
388 | return idx; |
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389 | } |
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390 | |||
6084 | serge | 391 | static inline void |
392 | intel_flush_status_page(struct intel_engine_cs *ring, int reg) |
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393 | { |
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394 | drm_clflush_virt_range(&ring->status_page.page_addr[reg], |
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395 | sizeof(uint32_t)); |
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396 | } |
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397 | |||
2326 | Serge | 398 | static inline u32 |
5060 | serge | 399 | intel_read_status_page(struct intel_engine_cs *ring, |
2326 | Serge | 400 | int reg) |
401 | { |
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3031 | serge | 402 | /* Ensure that the compiler doesn't optimize away the load. */ |
403 | barrier(); |
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404 | return ring->status_page.page_addr[reg]; |
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2326 | Serge | 405 | } |
406 | |||
3480 | Serge | 407 | static inline void |
5060 | serge | 408 | intel_write_status_page(struct intel_engine_cs *ring, |
3480 | Serge | 409 | int reg, u32 value) |
410 | { |
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411 | ring->status_page.page_addr[reg] = value; |
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412 | } |
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413 | |||
7144 | serge | 414 | /* |
2326 | Serge | 415 | * Reads a dword out of the status page, which is written to from the command |
416 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
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417 | * MI_STORE_DATA_IMM. |
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418 | * |
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419 | * The following dwords have a reserved meaning: |
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420 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
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421 | * 0x04: ring 0 head pointer |
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422 | * 0x05: ring 1 head pointer (915-class) |
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423 | * 0x06: ring 2 head pointer (915-class) |
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424 | * 0x10-0x1b: Context status DWords (GM45) |
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425 | * 0x1f: Last written status offset. (GM45) |
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6084 | serge | 426 | * 0x20-0x2f: Reserved (Gen6+) |
2326 | Serge | 427 | * |
6084 | serge | 428 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
2326 | Serge | 429 | */ |
6084 | serge | 430 | #define I915_GEM_HWS_INDEX 0x30 |
7144 | serge | 431 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
6084 | serge | 432 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
3243 | Serge | 433 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
2326 | Serge | 434 | |
6084 | serge | 435 | struct intel_ringbuffer * |
436 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size); |
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5354 | serge | 437 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
438 | struct intel_ringbuffer *ringbuf); |
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6084 | serge | 439 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
440 | void intel_ringbuffer_free(struct intel_ringbuffer *ring); |
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5354 | serge | 441 | |
5060 | serge | 442 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
443 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); |
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2326 | Serge | 444 | |
6084 | serge | 445 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
446 | |||
447 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
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448 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
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5060 | serge | 449 | static inline void intel_ring_emit(struct intel_engine_cs *ring, |
2326 | Serge | 450 | u32 data) |
451 | { |
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5060 | serge | 452 | struct intel_ringbuffer *ringbuf = ring->buffer; |
453 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
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454 | ringbuf->tail += 4; |
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2326 | Serge | 455 | } |
6937 | serge | 456 | static inline void intel_ring_emit_reg(struct intel_engine_cs *ring, |
457 | i915_reg_t reg) |
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458 | { |
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459 | intel_ring_emit(ring, i915_mmio_reg_offset(reg)); |
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460 | } |
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5060 | serge | 461 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
4560 | Serge | 462 | { |
5060 | serge | 463 | struct intel_ringbuffer *ringbuf = ring->buffer; |
464 | ringbuf->tail &= ringbuf->size - 1; |
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4560 | Serge | 465 | } |
5354 | serge | 466 | int __intel_ring_space(int head, int tail, int size); |
6084 | serge | 467 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf); |
5354 | serge | 468 | int intel_ring_space(struct intel_ringbuffer *ringbuf); |
469 | bool intel_ring_stopped(struct intel_engine_cs *ring); |
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4560 | Serge | 470 | |
5060 | serge | 471 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
472 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); |
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6084 | serge | 473 | int intel_ring_flush_all_caches(struct drm_i915_gem_request *req); |
474 | int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req); |
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2326 | Serge | 475 | |
5354 | serge | 476 | void intel_fini_pipe_control(struct intel_engine_cs *ring); |
477 | int intel_init_pipe_control(struct intel_engine_cs *ring); |
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478 | |||
2326 | Serge | 479 | int intel_init_render_ring_buffer(struct drm_device *dev); |
480 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
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5060 | serge | 481 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
2326 | Serge | 482 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
4104 | Serge | 483 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
2326 | Serge | 484 | |
5060 | serge | 485 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
2326 | Serge | 486 | |
5354 | serge | 487 | int init_workarounds_ring(struct intel_engine_cs *ring); |
488 | |||
5060 | serge | 489 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
3031 | serge | 490 | { |
5060 | serge | 491 | return ringbuf->tail; |
3031 | serge | 492 | } |
493 | |||
6084 | serge | 494 | /* |
495 | * Arbitrary size for largest possible 'add request' sequence. The code paths |
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496 | * are complex and variable. Empirical measurement shows that the worst case |
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497 | * is ILK at 136 words. Reserving too much is better than reserving too little |
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498 | * as that allows for corner cases that might have been missed. So the figure |
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499 | * has been rounded up to 160 words. |
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500 | */ |
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501 | #define MIN_SPACE_FOR_ADD_REQUEST 160 |
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3243 | Serge | 502 | |
6084 | serge | 503 | /* |
504 | * Reserve space in the ring to guarantee that the i915_add_request() call |
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505 | * will always have sufficient room to do its stuff. The request creation |
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506 | * code calls this automatically. |
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507 | */ |
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508 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size); |
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509 | /* Cancel the reservation, e.g. because the request is being discarded. */ |
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510 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf); |
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511 | /* Use the reserved space - for use by i915_add_request() only. */ |
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512 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf); |
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513 | /* Finish with the reserved space - for use by i915_add_request() only. */ |
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514 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf); |
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2326 | Serge | 515 | |
6084 | serge | 516 | /* Legacy ringbuffer specific portion of reservation code: */ |
517 | int intel_ring_reserve_space(struct drm_i915_gem_request *request); |
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518 | |||
2326 | Serge | 519 | #endif /* _INTEL_RINGBUFFER_H_ */><>><>>><> |