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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
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3 | |||
5060 | serge | 4 | #include |
6084 | serge | 5 | #include "i915_gem_batch_pool.h" |
5060 | serge | 6 | |
7 | #define I915_CMD_HASH_ORDER 9 |
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8 | |||
5354 | serge | 9 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
10 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
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11 | * to give some inclination as to some of the magic values used in the various |
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12 | * workarounds! |
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13 | */ |
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14 | #define CACHELINE_BYTES 64 |
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6084 | serge | 15 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
5354 | serge | 16 | |
3243 | Serge | 17 | /* |
18 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
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19 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
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20 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
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21 | * |
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22 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
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23 | * cacheline, the Head Pointer must not be greater than the Tail |
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24 | * Pointer." |
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25 | */ |
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26 | #define I915_RING_FREE_SPACE 64 |
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27 | |||
2326 | Serge | 28 | struct intel_hw_status_page { |
3031 | serge | 29 | u32 *page_addr; |
2326 | Serge | 30 | unsigned int gfx_addr; |
31 | struct drm_i915_gem_object *obj; |
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32 | }; |
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33 | |||
34 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
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35 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
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36 | |||
37 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
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38 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
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39 | |||
40 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
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41 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
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42 | |||
43 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
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44 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
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45 | |||
46 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
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47 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
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48 | |||
5060 | serge | 49 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
50 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
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51 | |||
52 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
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53 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
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54 | */ |
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55 | #define i915_semaphore_seqno_size sizeof(uint64_t) |
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56 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
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57 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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58 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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59 | (i915_semaphore_seqno_size * (to))) |
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60 | |||
61 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
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62 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
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63 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ |
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64 | (i915_semaphore_seqno_size * (__ring)->id)) |
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65 | |||
66 | #define GEN8_RING_SEMAPHORE_INIT do { \ |
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67 | if (!dev_priv->semaphore_obj) { \ |
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68 | break; \ |
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69 | } \ |
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70 | ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \ |
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71 | ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \ |
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72 | ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \ |
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73 | ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \ |
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74 | ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \ |
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75 | ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \ |
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76 | } while(0) |
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77 | |||
4104 | Serge | 78 | enum intel_ring_hangcheck_action { |
4560 | Serge | 79 | HANGCHECK_IDLE = 0, |
4104 | Serge | 80 | HANGCHECK_WAIT, |
81 | HANGCHECK_ACTIVE, |
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5060 | serge | 82 | HANGCHECK_ACTIVE_LOOP, |
4104 | Serge | 83 | HANGCHECK_KICK, |
84 | HANGCHECK_HUNG, |
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85 | }; |
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2326 | Serge | 86 | |
5060 | serge | 87 | #define HANGCHECK_SCORE_RING_HUNG 31 |
88 | |||
4104 | Serge | 89 | struct intel_ring_hangcheck { |
5060 | serge | 90 | u64 acthd; |
91 | u64 max_acthd; |
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4104 | Serge | 92 | u32 seqno; |
93 | int score; |
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94 | enum intel_ring_hangcheck_action action; |
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5060 | serge | 95 | int deadlock; |
4104 | Serge | 96 | }; |
97 | |||
5060 | serge | 98 | struct intel_ringbuffer { |
99 | struct drm_i915_gem_object *obj; |
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6084 | serge | 100 | void __iomem *virtual_start; |
2326 | Serge | 101 | |
5354 | serge | 102 | struct intel_engine_cs *ring; |
103 | |||
6084 | serge | 104 | u32 head; |
105 | u32 tail; |
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106 | int space; |
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107 | int size; |
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108 | int effective_size; |
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109 | int reserved_size; |
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110 | int reserved_tail; |
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111 | bool reserved_in_use; |
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5354 | serge | 112 | |
3031 | serge | 113 | /** We track the position of the requests in the ring buffer, and |
114 | * when each is retired we increment last_retired_head as the GPU |
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115 | * must have finished processing the request and so we know we |
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116 | * can advance the ringbuffer up to that position. |
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117 | * |
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118 | * last_retired_head is set to -1 after the value is consumed so |
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119 | * we can detect new retirements. |
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120 | */ |
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6084 | serge | 121 | u32 last_retired_head; |
5060 | serge | 122 | }; |
3031 | serge | 123 | |
6084 | serge | 124 | struct intel_context; |
125 | struct drm_i915_reg_descriptor; |
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126 | |||
127 | /* |
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128 | * we use a single page to load ctx workarounds so all of these |
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129 | * values are referred in terms of dwords |
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130 | * |
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131 | * struct i915_wa_ctx_bb: |
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132 | * offset: specifies batch starting position, also helpful in case |
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133 | * if we want to have multiple batches at different offsets based on |
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134 | * some criteria. It is not a requirement at the moment but provides |
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135 | * an option for future use. |
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136 | * size: size of the batch in DWORDS |
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137 | */ |
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138 | struct i915_ctx_workarounds { |
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139 | struct i915_wa_ctx_bb { |
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140 | u32 offset; |
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141 | u32 size; |
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142 | } indirect_ctx, per_ctx; |
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143 | struct drm_i915_gem_object *obj; |
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144 | }; |
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145 | |||
5060 | serge | 146 | struct intel_engine_cs { |
147 | const char *name; |
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148 | enum intel_ring_id { |
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149 | RCS = 0x0, |
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150 | VCS, |
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151 | BCS, |
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152 | VECS, |
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153 | VCS2 |
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154 | } id; |
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155 | #define I915_NUM_RINGS 5 |
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156 | #define LAST_USER_RING (VECS + 1) |
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157 | u32 mmio_base; |
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158 | struct drm_device *dev; |
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159 | struct intel_ringbuffer *buffer; |
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160 | |||
6084 | serge | 161 | /* |
162 | * A pool of objects to use as shadow copies of client batch buffers |
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163 | * when the command parser is enabled. Prevents the client from |
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164 | * modifying the batch contents after software parsing. |
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165 | */ |
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166 | struct i915_gem_batch_pool batch_pool; |
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167 | |||
5060 | serge | 168 | struct intel_hw_status_page status_page; |
6084 | serge | 169 | struct i915_ctx_workarounds wa_ctx; |
5060 | serge | 170 | |
4104 | Serge | 171 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
3031 | serge | 172 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
6084 | serge | 173 | struct drm_i915_gem_request *trace_irq_req; |
5060 | serge | 174 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
175 | void (*irq_put)(struct intel_engine_cs *ring); |
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2326 | Serge | 176 | |
6084 | serge | 177 | int (*init_hw)(struct intel_engine_cs *ring); |
2326 | Serge | 178 | |
6084 | serge | 179 | int (*init_context)(struct drm_i915_gem_request *req); |
5354 | serge | 180 | |
5060 | serge | 181 | void (*write_tail)(struct intel_engine_cs *ring, |
2326 | Serge | 182 | u32 value); |
6084 | serge | 183 | int __must_check (*flush)(struct drm_i915_gem_request *req, |
2326 | Serge | 184 | u32 invalidate_domains, |
185 | u32 flush_domains); |
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6084 | serge | 186 | int (*add_request)(struct drm_i915_gem_request *req); |
3031 | serge | 187 | /* Some chipsets are not quite as coherent as advertised and need |
188 | * an expensive kick to force a true read of the up-to-date seqno. |
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189 | * However, the up-to-date seqno is not always required and the last |
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190 | * seen value is good enough. Note that the seqno will always be |
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191 | * monotonic, even if not coherent. |
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192 | */ |
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5060 | serge | 193 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
3031 | serge | 194 | bool lazy_coherency); |
5060 | serge | 195 | void (*set_seqno)(struct intel_engine_cs *ring, |
3480 | Serge | 196 | u32 seqno); |
6084 | serge | 197 | int (*dispatch_execbuffer)(struct drm_i915_gem_request *req, |
5060 | serge | 198 | u64 offset, u32 length, |
6084 | serge | 199 | unsigned dispatch_flags); |
3243 | Serge | 200 | #define I915_DISPATCH_SECURE 0x1 |
201 | #define I915_DISPATCH_PINNED 0x2 |
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6084 | serge | 202 | #define I915_DISPATCH_RS 0x4 |
5060 | serge | 203 | void (*cleanup)(struct intel_engine_cs *ring); |
2326 | Serge | 204 | |
5060 | serge | 205 | /* GEN8 signal/wait table - never trust comments! |
206 | * signal to signal to signal to signal to signal to |
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207 | * RCS VCS BCS VECS VCS2 |
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208 | * -------------------------------------------------------------------- |
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209 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
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210 | * |------------------------------------------------------------------- |
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211 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
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212 | * |------------------------------------------------------------------- |
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213 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
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214 | * |------------------------------------------------------------------- |
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215 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
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216 | * |------------------------------------------------------------------- |
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217 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
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218 | * |------------------------------------------------------------------- |
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219 | * |
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220 | * Generalization: |
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221 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
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222 | * ie. transpose of g(x, y) |
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223 | * |
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224 | * sync from sync from sync from sync from sync from |
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225 | * RCS VCS BCS VECS VCS2 |
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226 | * -------------------------------------------------------------------- |
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227 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
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228 | * |------------------------------------------------------------------- |
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229 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
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230 | * |------------------------------------------------------------------- |
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231 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
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232 | * |------------------------------------------------------------------- |
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233 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
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234 | * |------------------------------------------------------------------- |
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235 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
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236 | * |------------------------------------------------------------------- |
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237 | * |
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238 | * Generalization: |
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239 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
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240 | * ie. transpose of f(x, y) |
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241 | */ |
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242 | struct { |
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243 | u32 sync_seqno[I915_NUM_RINGS-1]; |
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244 | |||
245 | union { |
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6084 | serge | 246 | struct { |
247 | /* our mbox written by others */ |
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248 | u32 wait[I915_NUM_RINGS]; |
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249 | /* mboxes this ring signals to */ |
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250 | u32 signal[I915_NUM_RINGS]; |
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251 | } mbox; |
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5060 | serge | 252 | u64 signal_ggtt[I915_NUM_RINGS]; |
253 | }; |
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4104 | Serge | 254 | |
5060 | serge | 255 | /* AKA wait() */ |
6084 | serge | 256 | int (*sync_to)(struct drm_i915_gem_request *to_req, |
257 | struct intel_engine_cs *from, |
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5060 | serge | 258 | u32 seqno); |
6084 | serge | 259 | int (*signal)(struct drm_i915_gem_request *signaller_req, |
5060 | serge | 260 | /* num_dwords needed by caller */ |
261 | unsigned int num_dwords); |
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262 | } semaphore; |
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263 | |||
5354 | serge | 264 | /* Execlists */ |
265 | spinlock_t execlist_lock; |
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266 | struct list_head execlist_queue; |
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267 | struct list_head execlist_retired_req_list; |
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268 | u8 next_context_status_buffer; |
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269 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
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6084 | serge | 270 | int (*emit_request)(struct drm_i915_gem_request *request); |
271 | int (*emit_flush)(struct drm_i915_gem_request *request, |
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5354 | serge | 272 | u32 invalidate_domains, |
273 | u32 flush_domains); |
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6084 | serge | 274 | int (*emit_bb_start)(struct drm_i915_gem_request *req, |
275 | u64 offset, unsigned dispatch_flags); |
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5354 | serge | 276 | |
2326 | Serge | 277 | /** |
278 | * List of objects currently involved in rendering from the |
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279 | * ringbuffer. |
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280 | * |
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281 | * Includes buffers having the contents of their GPU caches |
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6084 | serge | 282 | * flushed, not necessarily primitives. last_read_req |
2326 | Serge | 283 | * represents when the rendering involved will be completed. |
284 | * |
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285 | * A reference is held on the buffer while on this list. |
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286 | */ |
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287 | struct list_head active_list; |
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288 | |||
289 | /** |
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290 | * List of breadcrumbs associated with GPU requests currently |
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291 | * outstanding. |
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292 | */ |
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293 | struct list_head request_list; |
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294 | |||
295 | /** |
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6084 | serge | 296 | * Seqno of request most recently submitted to request_list. |
297 | * Used exclusively by hang checker to avoid grabbing lock while |
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298 | * inspecting request list. |
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2326 | Serge | 299 | */ |
6084 | serge | 300 | u32 last_submitted_seqno; |
301 | |||
3031 | serge | 302 | bool gpu_caches_dirty; |
2326 | Serge | 303 | |
2352 | Serge | 304 | wait_queue_head_t irq_queue; |
2326 | Serge | 305 | |
5060 | serge | 306 | struct intel_context *default_context; |
307 | struct intel_context *last_context; |
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3031 | serge | 308 | |
4104 | Serge | 309 | struct intel_ring_hangcheck hangcheck; |
310 | |||
311 | struct { |
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312 | struct drm_i915_gem_object *obj; |
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313 | u32 gtt_offset; |
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314 | volatile u32 *cpu_page; |
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315 | } scratch; |
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5060 | serge | 316 | |
317 | bool needs_cmd_parser; |
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318 | |||
319 | /* |
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320 | * Table of commands the command parser needs to know about |
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321 | * for this ring. |
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322 | */ |
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323 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
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324 | |||
325 | /* |
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326 | * Table of registers allowed in commands that read/write registers. |
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327 | */ |
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6084 | serge | 328 | const struct drm_i915_reg_descriptor *reg_table; |
5060 | serge | 329 | int reg_count; |
330 | |||
331 | /* |
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332 | * Table of registers allowed in commands that read/write registers, but |
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333 | * only from the DRM master. |
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334 | */ |
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6084 | serge | 335 | const struct drm_i915_reg_descriptor *master_reg_table; |
5060 | serge | 336 | int master_reg_count; |
337 | |||
338 | /* |
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339 | * Returns the bitmask for the length field of the specified command. |
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340 | * Return 0 for an unrecognized/invalid command. |
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341 | * |
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342 | * If the command parser finds an entry for a command in the ring's |
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343 | * cmd_tables, it gets the command's length based on the table entry. |
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344 | * If not, it calls this function to determine the per-ring length field |
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345 | * encoding for the command (i.e. certain opcode ranges use certain bits |
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346 | * to encode the command length in the header). |
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347 | */ |
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348 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
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2326 | Serge | 349 | }; |
350 | |||
5354 | serge | 351 | bool intel_ring_initialized(struct intel_engine_cs *ring); |
3031 | serge | 352 | |
353 | static inline unsigned |
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5060 | serge | 354 | intel_ring_flag(struct intel_engine_cs *ring) |
3031 | serge | 355 | { |
356 | return 1 << ring->id; |
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357 | } |
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358 | |||
2326 | Serge | 359 | static inline u32 |
5060 | serge | 360 | intel_ring_sync_index(struct intel_engine_cs *ring, |
361 | struct intel_engine_cs *other) |
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2326 | Serge | 362 | { |
363 | int idx; |
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364 | |||
365 | /* |
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5060 | serge | 366 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
367 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
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368 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
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369 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
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370 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
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2326 | Serge | 371 | */ |
372 | |||
373 | idx = (other - ring) - 1; |
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374 | if (idx < 0) |
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375 | idx += I915_NUM_RINGS; |
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376 | |||
377 | return idx; |
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378 | } |
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379 | |||
6084 | serge | 380 | static inline void |
381 | intel_flush_status_page(struct intel_engine_cs *ring, int reg) |
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382 | { |
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383 | drm_clflush_virt_range(&ring->status_page.page_addr[reg], |
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384 | sizeof(uint32_t)); |
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385 | } |
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386 | |||
2326 | Serge | 387 | static inline u32 |
5060 | serge | 388 | intel_read_status_page(struct intel_engine_cs *ring, |
2326 | Serge | 389 | int reg) |
390 | { |
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3031 | serge | 391 | /* Ensure that the compiler doesn't optimize away the load. */ |
392 | barrier(); |
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393 | return ring->status_page.page_addr[reg]; |
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2326 | Serge | 394 | } |
395 | |||
3480 | Serge | 396 | static inline void |
5060 | serge | 397 | intel_write_status_page(struct intel_engine_cs *ring, |
3480 | Serge | 398 | int reg, u32 value) |
399 | { |
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400 | ring->status_page.page_addr[reg] = value; |
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401 | } |
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402 | |||
2326 | Serge | 403 | /** |
404 | * Reads a dword out of the status page, which is written to from the command |
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405 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
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406 | * MI_STORE_DATA_IMM. |
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407 | * |
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408 | * The following dwords have a reserved meaning: |
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409 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
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410 | * 0x04: ring 0 head pointer |
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411 | * 0x05: ring 1 head pointer (915-class) |
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412 | * 0x06: ring 2 head pointer (915-class) |
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413 | * 0x10-0x1b: Context status DWords (GM45) |
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414 | * 0x1f: Last written status offset. (GM45) |
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6084 | serge | 415 | * 0x20-0x2f: Reserved (Gen6+) |
2326 | Serge | 416 | * |
6084 | serge | 417 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
2326 | Serge | 418 | */ |
6084 | serge | 419 | #define I915_GEM_HWS_INDEX 0x30 |
420 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
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3243 | Serge | 421 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
2326 | Serge | 422 | |
6084 | serge | 423 | struct intel_ringbuffer * |
424 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size); |
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5354 | serge | 425 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
426 | struct intel_ringbuffer *ringbuf); |
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6084 | serge | 427 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
428 | void intel_ringbuffer_free(struct intel_ringbuffer *ring); |
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5354 | serge | 429 | |
5060 | serge | 430 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
431 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); |
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2326 | Serge | 432 | |
6084 | serge | 433 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
434 | |||
435 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
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436 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
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5060 | serge | 437 | static inline void intel_ring_emit(struct intel_engine_cs *ring, |
2326 | Serge | 438 | u32 data) |
439 | { |
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5060 | serge | 440 | struct intel_ringbuffer *ringbuf = ring->buffer; |
441 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
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442 | ringbuf->tail += 4; |
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2326 | Serge | 443 | } |
5060 | serge | 444 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
4560 | Serge | 445 | { |
5060 | serge | 446 | struct intel_ringbuffer *ringbuf = ring->buffer; |
447 | ringbuf->tail &= ringbuf->size - 1; |
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4560 | Serge | 448 | } |
5354 | serge | 449 | int __intel_ring_space(int head, int tail, int size); |
6084 | serge | 450 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf); |
5354 | serge | 451 | int intel_ring_space(struct intel_ringbuffer *ringbuf); |
452 | bool intel_ring_stopped(struct intel_engine_cs *ring); |
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4560 | Serge | 453 | |
5060 | serge | 454 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
455 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); |
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6084 | serge | 456 | int intel_ring_flush_all_caches(struct drm_i915_gem_request *req); |
457 | int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req); |
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2326 | Serge | 458 | |
5354 | serge | 459 | void intel_fini_pipe_control(struct intel_engine_cs *ring); |
460 | int intel_init_pipe_control(struct intel_engine_cs *ring); |
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461 | |||
2326 | Serge | 462 | int intel_init_render_ring_buffer(struct drm_device *dev); |
463 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
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5060 | serge | 464 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
2326 | Serge | 465 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
4104 | Serge | 466 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
2326 | Serge | 467 | |
5060 | serge | 468 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
2326 | Serge | 469 | |
5354 | serge | 470 | int init_workarounds_ring(struct intel_engine_cs *ring); |
471 | |||
5060 | serge | 472 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
3031 | serge | 473 | { |
5060 | serge | 474 | return ringbuf->tail; |
3031 | serge | 475 | } |
476 | |||
6084 | serge | 477 | /* |
478 | * Arbitrary size for largest possible 'add request' sequence. The code paths |
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479 | * are complex and variable. Empirical measurement shows that the worst case |
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480 | * is ILK at 136 words. Reserving too much is better than reserving too little |
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481 | * as that allows for corner cases that might have been missed. So the figure |
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482 | * has been rounded up to 160 words. |
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483 | */ |
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484 | #define MIN_SPACE_FOR_ADD_REQUEST 160 |
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3243 | Serge | 485 | |
6084 | serge | 486 | /* |
487 | * Reserve space in the ring to guarantee that the i915_add_request() call |
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488 | * will always have sufficient room to do its stuff. The request creation |
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489 | * code calls this automatically. |
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490 | */ |
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491 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size); |
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492 | /* Cancel the reservation, e.g. because the request is being discarded. */ |
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493 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf); |
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494 | /* Use the reserved space - for use by i915_add_request() only. */ |
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495 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf); |
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496 | /* Finish with the reserved space - for use by i915_add_request() only. */ |
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497 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf); |
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2326 | Serge | 498 | |
6084 | serge | 499 | /* Legacy ringbuffer specific portion of reservation code: */ |
500 | int intel_ring_reserve_space(struct drm_i915_gem_request *request); |
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501 | |||
2326 | Serge | 502 | #endif /* _INTEL_RINGBUFFER_H_ */><>>><> |