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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
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3 | |||
3243 | Serge | 4 | /* |
5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
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6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
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7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
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8 | * |
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9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
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10 | * cacheline, the Head Pointer must not be greater than the Tail |
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11 | * Pointer." |
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12 | */ |
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13 | #define I915_RING_FREE_SPACE 64 |
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14 | |||
2326 | Serge | 15 | struct intel_hw_status_page { |
3031 | serge | 16 | u32 *page_addr; |
2326 | Serge | 17 | unsigned int gfx_addr; |
18 | struct drm_i915_gem_object *obj; |
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19 | }; |
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20 | |||
21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
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22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
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23 | |||
24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
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25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
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26 | |||
27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
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28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
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29 | |||
30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
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31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
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32 | |||
33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
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34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
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35 | |||
36 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
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37 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) |
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38 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) |
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39 | |||
40 | struct intel_ring_buffer { |
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41 | const char *name; |
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42 | enum intel_ring_id { |
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3031 | serge | 43 | RCS = 0x0, |
44 | VCS, |
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45 | BCS, |
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2326 | Serge | 46 | } id; |
3031 | serge | 47 | #define I915_NUM_RINGS 3 |
2326 | Serge | 48 | u32 mmio_base; |
49 | void __iomem *virtual_start; |
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50 | struct drm_device *dev; |
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51 | struct drm_i915_gem_object *obj; |
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52 | |||
53 | u32 head; |
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54 | u32 tail; |
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55 | int space; |
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56 | int size; |
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57 | int effective_size; |
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58 | struct intel_hw_status_page status_page; |
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59 | |||
3031 | serge | 60 | /** We track the position of the requests in the ring buffer, and |
61 | * when each is retired we increment last_retired_head as the GPU |
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62 | * must have finished processing the request and so we know we |
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63 | * can advance the ringbuffer up to that position. |
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64 | * |
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65 | * last_retired_head is set to -1 after the value is consumed so |
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66 | * we can detect new retirements. |
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67 | */ |
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68 | u32 last_retired_head; |
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69 | |||
70 | u32 irq_refcount; /* protected by dev_priv->irq_lock */ |
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71 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
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2326 | Serge | 72 | u32 trace_irq_seqno; |
73 | u32 sync_seqno[I915_NUM_RINGS-1]; |
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74 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
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75 | void (*irq_put)(struct intel_ring_buffer *ring); |
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76 | |||
77 | int (*init)(struct intel_ring_buffer *ring); |
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78 | |||
79 | void (*write_tail)(struct intel_ring_buffer *ring, |
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80 | u32 value); |
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81 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
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82 | u32 invalidate_domains, |
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83 | u32 flush_domains); |
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3243 | Serge | 84 | int (*add_request)(struct intel_ring_buffer *ring); |
3031 | serge | 85 | /* Some chipsets are not quite as coherent as advertised and need |
86 | * an expensive kick to force a true read of the up-to-date seqno. |
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87 | * However, the up-to-date seqno is not always required and the last |
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88 | * seen value is good enough. Note that the seqno will always be |
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89 | * monotonic, even if not coherent. |
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90 | */ |
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91 | u32 (*get_seqno)(struct intel_ring_buffer *ring, |
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92 | bool lazy_coherency); |
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2326 | Serge | 93 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
3243 | Serge | 94 | u32 offset, u32 length, |
95 | unsigned flags); |
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96 | #define I915_DISPATCH_SECURE 0x1 |
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97 | #define I915_DISPATCH_PINNED 0x2 |
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2326 | Serge | 98 | void (*cleanup)(struct intel_ring_buffer *ring); |
2342 | Serge | 99 | int (*sync_to)(struct intel_ring_buffer *ring, |
100 | struct intel_ring_buffer *to, |
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101 | u32 seqno); |
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2326 | Serge | 102 | |
2342 | Serge | 103 | u32 semaphore_register[3]; /*our mbox written by others */ |
104 | u32 signal_mbox[2]; /* mboxes this ring signals to */ |
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2326 | Serge | 105 | /** |
106 | * List of objects currently involved in rendering from the |
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107 | * ringbuffer. |
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108 | * |
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109 | * Includes buffers having the contents of their GPU caches |
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110 | * flushed, not necessarily primitives. last_rendering_seqno |
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111 | * represents when the rendering involved will be completed. |
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112 | * |
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113 | * A reference is held on the buffer while on this list. |
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114 | */ |
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115 | struct list_head active_list; |
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116 | |||
117 | /** |
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118 | * List of breadcrumbs associated with GPU requests currently |
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119 | * outstanding. |
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120 | */ |
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121 | struct list_head request_list; |
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122 | |||
123 | /** |
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124 | * Do we have some not yet emitted requests outstanding? |
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125 | */ |
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126 | u32 outstanding_lazy_request; |
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3031 | serge | 127 | bool gpu_caches_dirty; |
2326 | Serge | 128 | |
2352 | Serge | 129 | wait_queue_head_t irq_queue; |
2326 | Serge | 130 | |
3031 | serge | 131 | /** |
132 | * Do an explicit TLB flush before MI_SET_CONTEXT |
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133 | */ |
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134 | bool itlb_before_ctx_switch; |
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135 | struct i915_hw_context *default_context; |
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136 | struct drm_i915_gem_object *last_context_obj; |
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137 | |||
2326 | Serge | 138 | void *private; |
139 | }; |
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140 | |||
3031 | serge | 141 | static inline bool |
142 | intel_ring_initialized(struct intel_ring_buffer *ring) |
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143 | { |
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144 | return ring->obj != NULL; |
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145 | } |
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146 | |||
147 | static inline unsigned |
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148 | intel_ring_flag(struct intel_ring_buffer *ring) |
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149 | { |
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150 | return 1 << ring->id; |
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151 | } |
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152 | |||
2326 | Serge | 153 | static inline u32 |
154 | intel_ring_sync_index(struct intel_ring_buffer *ring, |
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155 | struct intel_ring_buffer *other) |
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156 | { |
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157 | int idx; |
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158 | |||
159 | /* |
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160 | * cs -> 0 = vcs, 1 = bcs |
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161 | * vcs -> 0 = bcs, 1 = cs, |
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162 | * bcs -> 0 = cs, 1 = vcs. |
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163 | */ |
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164 | |||
165 | idx = (other - ring) - 1; |
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166 | if (idx < 0) |
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167 | idx += I915_NUM_RINGS; |
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168 | |||
169 | return idx; |
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170 | } |
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171 | |||
172 | static inline u32 |
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173 | intel_read_status_page(struct intel_ring_buffer *ring, |
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174 | int reg) |
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175 | { |
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3031 | serge | 176 | /* Ensure that the compiler doesn't optimize away the load. */ |
177 | barrier(); |
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178 | return ring->status_page.page_addr[reg]; |
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2326 | Serge | 179 | } |
180 | |||
181 | /** |
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182 | * Reads a dword out of the status page, which is written to from the command |
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183 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
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184 | * MI_STORE_DATA_IMM. |
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185 | * |
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186 | * The following dwords have a reserved meaning: |
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187 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
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188 | * 0x04: ring 0 head pointer |
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189 | * 0x05: ring 1 head pointer (915-class) |
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190 | * 0x06: ring 2 head pointer (915-class) |
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191 | * 0x10-0x1b: Context status DWords (GM45) |
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192 | * 0x1f: Last written status offset. (GM45) |
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193 | * |
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194 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
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195 | */ |
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196 | #define I915_GEM_HWS_INDEX 0x20 |
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3243 | Serge | 197 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
198 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
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2326 | Serge | 199 | |
200 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
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201 | |||
202 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
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203 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
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204 | u32 data) |
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205 | { |
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206 | iowrite32(data, ring->virtual_start + ring->tail); |
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207 | ring->tail += 4; |
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208 | } |
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209 | void intel_ring_advance(struct intel_ring_buffer *ring); |
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3243 | Serge | 210 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
2326 | Serge | 211 | |
3031 | serge | 212 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
213 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); |
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2326 | Serge | 214 | |
215 | int intel_init_render_ring_buffer(struct drm_device *dev); |
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216 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
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217 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
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218 | |||
219 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
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220 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
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221 | |||
3031 | serge | 222 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
223 | { |
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224 | return ring->tail; |
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225 | } |
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226 | |||
3243 | Serge | 227 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
228 | { |
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229 | BUG_ON(ring->outstanding_lazy_request == 0); |
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230 | return ring->outstanding_lazy_request; |
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231 | } |
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232 | |||
2326 | Serge | 233 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
234 | { |
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235 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
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236 | ring->trace_irq_seqno = seqno; |
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237 | } |
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238 | |||
239 | /* DRI warts */ |
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240 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); |
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241 | |||
242 | #endif /* _INTEL_RINGBUFFER_H_ */><>>><> |