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Rev | Author | Line No. | Line |
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2326 | Serge | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ |
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3 | |||
4 | struct intel_hw_status_page { |
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3031 | serge | 5 | u32 *page_addr; |
2326 | Serge | 6 | unsigned int gfx_addr; |
7 | struct drm_i915_gem_object *obj; |
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8 | }; |
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9 | |||
10 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
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11 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
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12 | |||
13 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
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14 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
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15 | |||
16 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
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17 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
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18 | |||
19 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
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20 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
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21 | |||
22 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
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23 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
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24 | |||
25 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
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26 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) |
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27 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) |
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28 | |||
29 | struct intel_ring_buffer { |
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30 | const char *name; |
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31 | enum intel_ring_id { |
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3031 | serge | 32 | RCS = 0x0, |
33 | VCS, |
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34 | BCS, |
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2326 | Serge | 35 | } id; |
3031 | serge | 36 | #define I915_NUM_RINGS 3 |
2326 | Serge | 37 | u32 mmio_base; |
38 | void __iomem *virtual_start; |
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39 | struct drm_device *dev; |
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40 | struct drm_i915_gem_object *obj; |
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41 | |||
42 | u32 head; |
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43 | u32 tail; |
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44 | int space; |
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45 | int size; |
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46 | int effective_size; |
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47 | struct intel_hw_status_page status_page; |
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48 | |||
3031 | serge | 49 | /** We track the position of the requests in the ring buffer, and |
50 | * when each is retired we increment last_retired_head as the GPU |
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51 | * must have finished processing the request and so we know we |
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52 | * can advance the ringbuffer up to that position. |
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53 | * |
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54 | * last_retired_head is set to -1 after the value is consumed so |
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55 | * we can detect new retirements. |
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56 | */ |
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57 | u32 last_retired_head; |
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58 | |||
59 | u32 irq_refcount; /* protected by dev_priv->irq_lock */ |
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60 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
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2326 | Serge | 61 | u32 trace_irq_seqno; |
62 | u32 sync_seqno[I915_NUM_RINGS-1]; |
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63 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
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64 | void (*irq_put)(struct intel_ring_buffer *ring); |
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65 | |||
66 | int (*init)(struct intel_ring_buffer *ring); |
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67 | |||
68 | void (*write_tail)(struct intel_ring_buffer *ring, |
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69 | u32 value); |
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70 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
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71 | u32 invalidate_domains, |
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72 | u32 flush_domains); |
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73 | int (*add_request)(struct intel_ring_buffer *ring, |
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74 | u32 *seqno); |
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3031 | serge | 75 | /* Some chipsets are not quite as coherent as advertised and need |
76 | * an expensive kick to force a true read of the up-to-date seqno. |
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77 | * However, the up-to-date seqno is not always required and the last |
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78 | * seen value is good enough. Note that the seqno will always be |
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79 | * monotonic, even if not coherent. |
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80 | */ |
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81 | u32 (*get_seqno)(struct intel_ring_buffer *ring, |
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82 | bool lazy_coherency); |
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2326 | Serge | 83 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
84 | u32 offset, u32 length); |
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85 | void (*cleanup)(struct intel_ring_buffer *ring); |
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2342 | Serge | 86 | int (*sync_to)(struct intel_ring_buffer *ring, |
87 | struct intel_ring_buffer *to, |
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88 | u32 seqno); |
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2326 | Serge | 89 | |
2342 | Serge | 90 | u32 semaphore_register[3]; /*our mbox written by others */ |
91 | u32 signal_mbox[2]; /* mboxes this ring signals to */ |
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2326 | Serge | 92 | /** |
93 | * List of objects currently involved in rendering from the |
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94 | * ringbuffer. |
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95 | * |
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96 | * Includes buffers having the contents of their GPU caches |
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97 | * flushed, not necessarily primitives. last_rendering_seqno |
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98 | * represents when the rendering involved will be completed. |
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99 | * |
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100 | * A reference is held on the buffer while on this list. |
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101 | */ |
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102 | struct list_head active_list; |
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103 | |||
104 | /** |
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105 | * List of breadcrumbs associated with GPU requests currently |
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106 | * outstanding. |
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107 | */ |
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108 | struct list_head request_list; |
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109 | |||
110 | /** |
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111 | * Do we have some not yet emitted requests outstanding? |
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112 | */ |
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113 | u32 outstanding_lazy_request; |
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3031 | serge | 114 | bool gpu_caches_dirty; |
2326 | Serge | 115 | |
2352 | Serge | 116 | wait_queue_head_t irq_queue; |
2326 | Serge | 117 | |
3031 | serge | 118 | /** |
119 | * Do an explicit TLB flush before MI_SET_CONTEXT |
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120 | */ |
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121 | bool itlb_before_ctx_switch; |
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122 | struct i915_hw_context *default_context; |
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123 | struct drm_i915_gem_object *last_context_obj; |
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124 | |||
2326 | Serge | 125 | void *private; |
126 | }; |
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127 | |||
3031 | serge | 128 | static inline bool |
129 | intel_ring_initialized(struct intel_ring_buffer *ring) |
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130 | { |
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131 | return ring->obj != NULL; |
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132 | } |
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133 | |||
134 | static inline unsigned |
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135 | intel_ring_flag(struct intel_ring_buffer *ring) |
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136 | { |
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137 | return 1 << ring->id; |
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138 | } |
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139 | |||
2326 | Serge | 140 | static inline u32 |
141 | intel_ring_sync_index(struct intel_ring_buffer *ring, |
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142 | struct intel_ring_buffer *other) |
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143 | { |
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144 | int idx; |
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145 | |||
146 | /* |
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147 | * cs -> 0 = vcs, 1 = bcs |
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148 | * vcs -> 0 = bcs, 1 = cs, |
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149 | * bcs -> 0 = cs, 1 = vcs. |
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150 | */ |
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151 | |||
152 | idx = (other - ring) - 1; |
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153 | if (idx < 0) |
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154 | idx += I915_NUM_RINGS; |
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155 | |||
156 | return idx; |
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157 | } |
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158 | |||
159 | static inline u32 |
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160 | intel_read_status_page(struct intel_ring_buffer *ring, |
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161 | int reg) |
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162 | { |
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3031 | serge | 163 | /* Ensure that the compiler doesn't optimize away the load. */ |
164 | barrier(); |
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165 | return ring->status_page.page_addr[reg]; |
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2326 | Serge | 166 | } |
167 | |||
168 | /** |
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169 | * Reads a dword out of the status page, which is written to from the command |
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170 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
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171 | * MI_STORE_DATA_IMM. |
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172 | * |
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173 | * The following dwords have a reserved meaning: |
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174 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
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175 | * 0x04: ring 0 head pointer |
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176 | * 0x05: ring 1 head pointer (915-class) |
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177 | * 0x06: ring 2 head pointer (915-class) |
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178 | * 0x10-0x1b: Context status DWords (GM45) |
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179 | * 0x1f: Last written status offset. (GM45) |
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180 | * |
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181 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
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182 | */ |
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183 | #define I915_GEM_HWS_INDEX 0x20 |
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184 | |||
185 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
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186 | |||
187 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
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188 | static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) |
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189 | { |
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190 | return intel_wait_ring_buffer(ring, ring->size - 8); |
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191 | } |
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192 | |||
193 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
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194 | |||
195 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
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196 | u32 data) |
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197 | { |
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198 | iowrite32(data, ring->virtual_start + ring->tail); |
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199 | ring->tail += 4; |
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200 | } |
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201 | |||
202 | void intel_ring_advance(struct intel_ring_buffer *ring); |
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203 | |||
204 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
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3031 | serge | 205 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
206 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); |
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2326 | Serge | 207 | |
208 | int intel_init_render_ring_buffer(struct drm_device *dev); |
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209 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
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210 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
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211 | |||
212 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
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213 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
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214 | |||
3031 | serge | 215 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
216 | { |
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217 | return ring->tail; |
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218 | } |
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219 | |||
2326 | Serge | 220 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
221 | { |
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222 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
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223 | ring->trace_irq_seqno = seqno; |
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224 | } |
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225 | |||
226 | /* DRI warts */ |
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227 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); |
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228 | |||
229 | #endif /* _INTEL_RINGBUFFER_H_ */>><> |