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Rev | Author | Line No. | Line |
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2330 | Serge | 1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
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3 | * Copyright (c) 2006 Dave Airlie |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice (including the next |
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13 | * paragraph) shall be included in all copies or substantial portions of the |
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14 | * Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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22 | * DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: |
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25 | * Eric Anholt |
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26 | * Dave Airlie |
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27 | * Jesse Barnes |
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28 | */ |
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29 | |||
30 | //#include |
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5097 | serge | 31 | #include |
2330 | Serge | 32 | #include |
33 | #include |
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3031 | serge | 34 | #include |
35 | #include |
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36 | #include |
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2330 | Serge | 37 | #include "intel_drv.h" |
3031 | serge | 38 | #include |
2330 | Serge | 39 | #include "i915_drv.h" |
40 | //#include |
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41 | |||
42 | /* Private structure for the integrated LVDS support */ |
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3243 | Serge | 43 | struct intel_lvds_connector { |
44 | struct intel_connector base; |
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45 | |||
46 | // struct notifier_block lid_notifier; |
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47 | }; |
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48 | |||
49 | struct intel_lvds_encoder { |
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2330 | Serge | 50 | struct intel_encoder base; |
51 | |||
3480 | Serge | 52 | bool is_dual_link; |
53 | u32 reg; |
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5060 | serge | 54 | u32 a3_power; |
2330 | Serge | 55 | |
3243 | Serge | 56 | struct intel_lvds_connector *attached_connector; |
2330 | Serge | 57 | }; |
58 | |||
3243 | Serge | 59 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
2330 | Serge | 60 | { |
3243 | Serge | 61 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
2330 | Serge | 62 | } |
63 | |||
3243 | Serge | 64 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
2330 | Serge | 65 | { |
3243 | Serge | 66 | return container_of(connector, struct intel_lvds_connector, base.base); |
2330 | Serge | 67 | } |
68 | |||
3031 | serge | 69 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
70 | enum pipe *pipe) |
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71 | { |
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72 | struct drm_device *dev = encoder->base.dev; |
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73 | struct drm_i915_private *dev_priv = dev->dev_private; |
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3480 | Serge | 74 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
5060 | serge | 75 | enum intel_display_power_domain power_domain; |
3480 | Serge | 76 | u32 tmp; |
3031 | serge | 77 | |
5060 | serge | 78 | power_domain = intel_display_port_power_domain(encoder); |
5354 | serge | 79 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
5060 | serge | 80 | return false; |
81 | |||
3480 | Serge | 82 | tmp = I915_READ(lvds_encoder->reg); |
3031 | serge | 83 | |
84 | if (!(tmp & LVDS_PORT_EN)) |
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85 | return false; |
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86 | |||
87 | if (HAS_PCH_CPT(dev)) |
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88 | *pipe = PORT_TO_PIPE_CPT(tmp); |
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89 | else |
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90 | *pipe = PORT_TO_PIPE(tmp); |
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91 | |||
92 | return true; |
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93 | } |
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94 | |||
4104 | Serge | 95 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
96 | struct intel_crtc_config *pipe_config) |
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97 | { |
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98 | struct drm_device *dev = encoder->base.dev; |
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99 | struct drm_i915_private *dev_priv = dev->dev_private; |
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100 | u32 lvds_reg, tmp, flags = 0; |
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4560 | Serge | 101 | int dotclock; |
4104 | Serge | 102 | |
103 | if (HAS_PCH_SPLIT(dev)) |
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104 | lvds_reg = PCH_LVDS; |
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105 | else |
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106 | lvds_reg = LVDS; |
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107 | |||
108 | tmp = I915_READ(lvds_reg); |
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109 | if (tmp & LVDS_HSYNC_POLARITY) |
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110 | flags |= DRM_MODE_FLAG_NHSYNC; |
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111 | else |
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112 | flags |= DRM_MODE_FLAG_PHSYNC; |
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113 | if (tmp & LVDS_VSYNC_POLARITY) |
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114 | flags |= DRM_MODE_FLAG_NVSYNC; |
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115 | else |
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116 | flags |= DRM_MODE_FLAG_PVSYNC; |
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117 | |||
118 | pipe_config->adjusted_mode.flags |= flags; |
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119 | |||
120 | /* gen2/3 store dither state in pfit control, needs to match */ |
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121 | if (INTEL_INFO(dev)->gen < 4) { |
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122 | tmp = I915_READ(PFIT_CONTROL); |
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123 | |||
124 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; |
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125 | } |
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4560 | Serge | 126 | |
127 | dotclock = pipe_config->port_clock; |
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128 | |||
129 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
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130 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
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131 | |||
132 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
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4104 | Serge | 133 | } |
134 | |||
135 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
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3480 | Serge | 136 | { |
137 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
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138 | struct drm_device *dev = encoder->base.dev; |
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139 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4104 | Serge | 140 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
141 | const struct drm_display_mode *adjusted_mode = |
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142 | &crtc->config.adjusted_mode; |
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143 | int pipe = crtc->pipe; |
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3480 | Serge | 144 | u32 temp; |
145 | |||
4104 | Serge | 146 | if (HAS_PCH_SPLIT(dev)) { |
147 | assert_fdi_rx_pll_disabled(dev_priv, pipe); |
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148 | assert_shared_dpll_disabled(dev_priv, |
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149 | intel_crtc_to_shared_dpll(crtc)); |
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150 | } else { |
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151 | assert_pll_disabled(dev_priv, pipe); |
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152 | } |
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153 | |||
3480 | Serge | 154 | temp = I915_READ(lvds_encoder->reg); |
155 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
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156 | |||
157 | if (HAS_PCH_CPT(dev)) { |
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158 | temp &= ~PORT_TRANS_SEL_MASK; |
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159 | temp |= PORT_TRANS_SEL_CPT(pipe); |
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160 | } else { |
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161 | if (pipe == 1) { |
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162 | temp |= LVDS_PIPEB_SELECT; |
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163 | } else { |
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164 | temp &= ~LVDS_PIPEB_SELECT; |
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165 | } |
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166 | } |
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167 | |||
168 | /* set the corresponsding LVDS_BORDER bit */ |
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4104 | Serge | 169 | temp &= ~LVDS_BORDER_ENABLE; |
170 | temp |= crtc->config.gmch_pfit.lvds_border_bits; |
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3480 | Serge | 171 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
172 | * set the DPLLs for dual-channel mode or not. |
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173 | */ |
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174 | if (lvds_encoder->is_dual_link) |
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175 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
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176 | else |
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177 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
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178 | |||
179 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
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180 | * appropriately here, but we need to look more thoroughly into how |
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5060 | serge | 181 | * panels behave in the two modes. For now, let's just maintain the |
182 | * value we got from the BIOS. |
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3480 | Serge | 183 | */ |
5060 | serge | 184 | temp &= ~LVDS_A3_POWER_MASK; |
185 | temp |= lvds_encoder->a3_power; |
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3480 | Serge | 186 | |
187 | /* Set the dithering flag on LVDS as needed, note that there is no |
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188 | * special lvds dither control bit on pch-split platforms, dithering is |
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189 | * only controlled through the PIPECONF reg. */ |
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190 | if (INTEL_INFO(dev)->gen == 4) { |
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4104 | Serge | 191 | /* Bspec wording suggests that LVDS port dithering only exists |
192 | * for 18bpp panels. */ |
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193 | if (crtc->config.dither && crtc->config.pipe_bpp == 18) |
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3480 | Serge | 194 | temp |= LVDS_ENABLE_DITHER; |
195 | else |
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196 | temp &= ~LVDS_ENABLE_DITHER; |
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197 | } |
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198 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
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4104 | Serge | 199 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
3480 | Serge | 200 | temp |= LVDS_HSYNC_POLARITY; |
4104 | Serge | 201 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
3480 | Serge | 202 | temp |= LVDS_VSYNC_POLARITY; |
203 | |||
204 | I915_WRITE(lvds_encoder->reg, temp); |
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205 | } |
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206 | |||
2330 | Serge | 207 | /** |
208 | * Sets the power state for the panel. |
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209 | */ |
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3031 | serge | 210 | static void intel_enable_lvds(struct intel_encoder *encoder) |
2330 | Serge | 211 | { |
3031 | serge | 212 | struct drm_device *dev = encoder->base.dev; |
3243 | Serge | 213 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
4560 | Serge | 214 | struct intel_connector *intel_connector = |
215 | &lvds_encoder->attached_connector->base; |
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2330 | Serge | 216 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 217 | u32 ctl_reg, stat_reg; |
2330 | Serge | 218 | |
219 | if (HAS_PCH_SPLIT(dev)) { |
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220 | ctl_reg = PCH_PP_CONTROL; |
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221 | stat_reg = PCH_PP_STATUS; |
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222 | } else { |
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223 | ctl_reg = PP_CONTROL; |
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224 | stat_reg = PP_STATUS; |
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225 | } |
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226 | |||
3480 | Serge | 227 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
2330 | Serge | 228 | |
229 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
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3480 | Serge | 230 | POSTING_READ(lvds_encoder->reg); |
2330 | Serge | 231 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
232 | DRM_ERROR("timed out waiting for panel to power on\n"); |
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233 | |||
4560 | Serge | 234 | intel_panel_enable_backlight(intel_connector); |
2330 | Serge | 235 | } |
236 | |||
3031 | serge | 237 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2330 | Serge | 238 | { |
3031 | serge | 239 | struct drm_device *dev = encoder->base.dev; |
3243 | Serge | 240 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
4560 | Serge | 241 | struct intel_connector *intel_connector = |
242 | &lvds_encoder->attached_connector->base; |
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2330 | Serge | 243 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 244 | u32 ctl_reg, stat_reg; |
2330 | Serge | 245 | |
246 | if (HAS_PCH_SPLIT(dev)) { |
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247 | ctl_reg = PCH_PP_CONTROL; |
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248 | stat_reg = PCH_PP_STATUS; |
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249 | } else { |
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250 | ctl_reg = PP_CONTROL; |
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251 | stat_reg = PP_STATUS; |
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252 | } |
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253 | |||
4560 | Serge | 254 | intel_panel_disable_backlight(intel_connector); |
2330 | Serge | 255 | |
256 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
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257 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
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258 | DRM_ERROR("timed out waiting for panel to power off\n"); |
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259 | |||
3480 | Serge | 260 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
261 | POSTING_READ(lvds_encoder->reg); |
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2330 | Serge | 262 | } |
263 | |||
4560 | Serge | 264 | static enum drm_mode_status |
265 | intel_lvds_mode_valid(struct drm_connector *connector, |
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2330 | Serge | 266 | struct drm_display_mode *mode) |
267 | { |
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3243 | Serge | 268 | struct intel_connector *intel_connector = to_intel_connector(connector); |
269 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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2330 | Serge | 270 | |
271 | if (mode->hdisplay > fixed_mode->hdisplay) |
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272 | return MODE_PANEL; |
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273 | if (mode->vdisplay > fixed_mode->vdisplay) |
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274 | return MODE_PANEL; |
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275 | |||
276 | return MODE_OK; |
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277 | } |
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278 | |||
3746 | Serge | 279 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
280 | struct intel_crtc_config *pipe_config) |
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2330 | Serge | 281 | { |
3746 | Serge | 282 | struct drm_device *dev = intel_encoder->base.dev; |
283 | struct intel_lvds_encoder *lvds_encoder = |
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284 | to_lvds_encoder(&intel_encoder->base); |
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3243 | Serge | 285 | struct intel_connector *intel_connector = |
286 | &lvds_encoder->attached_connector->base; |
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3746 | Serge | 287 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
3243 | Serge | 288 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
3746 | Serge | 289 | unsigned int lvds_bpp; |
2330 | Serge | 290 | |
291 | /* Should never happen!! */ |
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292 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
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293 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
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294 | return false; |
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295 | } |
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296 | |||
5060 | serge | 297 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
3746 | Serge | 298 | lvds_bpp = 8*3; |
299 | else |
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300 | lvds_bpp = 6*3; |
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301 | |||
4104 | Serge | 302 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
3746 | Serge | 303 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
304 | pipe_config->pipe_bpp, lvds_bpp); |
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305 | pipe_config->pipe_bpp = lvds_bpp; |
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306 | } |
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4104 | Serge | 307 | |
2330 | Serge | 308 | /* |
309 | * We have timings from the BIOS for the panel, put them in |
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310 | * to the adjusted mode. The CRTC will be set up for this mode, |
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311 | * with the panel scaling set up to source from the H/VDisplay |
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312 | * of the original mode. |
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313 | */ |
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3243 | Serge | 314 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
315 | adjusted_mode); |
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2330 | Serge | 316 | |
317 | if (HAS_PCH_SPLIT(dev)) { |
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3746 | Serge | 318 | pipe_config->has_pch_encoder = true; |
319 | |||
4104 | Serge | 320 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
321 | intel_connector->panel.fitting_mode); |
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322 | } else { |
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323 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
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324 | intel_connector->panel.fitting_mode); |
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2330 | Serge | 325 | |
326 | } |
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327 | |||
328 | /* |
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329 | * XXX: It would be nice to support lower refresh rates on the |
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330 | * panels to reduce power consumption, and perhaps match the |
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331 | * user's requested refresh rate. |
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332 | */ |
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333 | |||
334 | return true; |
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335 | } |
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336 | |||
337 | /** |
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338 | * Detect the LVDS connection. |
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339 | * |
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340 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
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341 | * connected and closed means disconnected. We also send hotplug events as |
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342 | * needed, using lid status notification from the input layer. |
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343 | */ |
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344 | static enum drm_connector_status |
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345 | intel_lvds_detect(struct drm_connector *connector, bool force) |
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346 | { |
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347 | struct drm_device *dev = connector->dev; |
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348 | enum drm_connector_status status; |
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349 | |||
4104 | Serge | 350 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5060 | serge | 351 | connector->base.id, connector->name); |
4104 | Serge | 352 | |
2330 | Serge | 353 | status = intel_panel_detect(dev); |
354 | if (status != connector_status_unknown) |
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355 | return status; |
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356 | |||
357 | return connector_status_connected; |
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358 | } |
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359 | |||
360 | /** |
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361 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. |
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362 | */ |
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363 | static int intel_lvds_get_modes(struct drm_connector *connector) |
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364 | { |
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3243 | Serge | 365 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
2330 | Serge | 366 | struct drm_device *dev = connector->dev; |
367 | struct drm_display_mode *mode; |
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368 | |||
3243 | Serge | 369 | /* use cached edid if we have one */ |
370 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
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371 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
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2330 | Serge | 372 | |
3243 | Serge | 373 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
2330 | Serge | 374 | if (mode == NULL) |
375 | return 0; |
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376 | |||
377 | drm_mode_probed_add(connector, mode); |
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378 | return 1; |
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379 | } |
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380 | |||
381 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
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382 | { |
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3031 | serge | 383 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
2330 | Serge | 384 | return 1; |
385 | } |
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386 | |||
387 | /* The GPU hangs up on these systems if modeset is performed on LID open */ |
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388 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { |
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389 | { |
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390 | .callback = intel_no_modeset_on_lid_dmi_callback, |
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391 | .ident = "Toshiba Tecra A11", |
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392 | .matches = { |
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393 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
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394 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), |
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395 | }, |
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396 | }, |
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397 | |||
398 | { } /* terminating entry */ |
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399 | }; |
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400 | |||
401 | #if 0 |
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402 | /* |
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3480 | Serge | 403 | * Lid events. Note the use of 'modeset': |
404 | * - we set it to MODESET_ON_LID_OPEN on lid close, |
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405 | * and set it to MODESET_DONE on open |
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2330 | Serge | 406 | * - we use it as a "only once" bit (ie we ignore |
3480 | Serge | 407 | * duplicate events where it was already properly set) |
408 | * - the suspend/resume paths will set it to |
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409 | * MODESET_SUSPENDED and ignore the lid open event, |
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410 | * because they restore the mode ("lid open"). |
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2330 | Serge | 411 | */ |
412 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
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413 | void *unused) |
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414 | { |
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3243 | Serge | 415 | struct intel_lvds_connector *lvds_connector = |
416 | container_of(nb, struct intel_lvds_connector, lid_notifier); |
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417 | struct drm_connector *connector = &lvds_connector->base.base; |
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418 | struct drm_device *dev = connector->dev; |
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419 | struct drm_i915_private *dev_priv = dev->dev_private; |
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2330 | Serge | 420 | |
421 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
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422 | return NOTIFY_OK; |
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423 | |||
3480 | Serge | 424 | mutex_lock(&dev_priv->modeset_restore_lock); |
425 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) |
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426 | goto exit; |
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2330 | Serge | 427 | /* |
428 | * check and update the status of LVDS connector after receiving |
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429 | * the LID nofication event. |
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430 | */ |
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3243 | Serge | 431 | connector->status = connector->funcs->detect(connector, false); |
2330 | Serge | 432 | |
433 | /* Don't force modeset on machines where it causes a GPU lockup */ |
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434 | if (dmi_check_system(intel_no_modeset_on_lid)) |
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3480 | Serge | 435 | goto exit; |
2330 | Serge | 436 | if (!acpi_lid_open()) { |
3480 | Serge | 437 | /* do modeset on next lid open event */ |
438 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; |
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439 | goto exit; |
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2330 | Serge | 440 | } |
441 | |||
3480 | Serge | 442 | if (dev_priv->modeset_restore == MODESET_DONE) |
443 | goto exit; |
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2330 | Serge | 444 | |
4560 | Serge | 445 | /* |
446 | * Some old platform's BIOS love to wreak havoc while the lid is closed. |
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447 | * We try to detect this here and undo any damage. The split for PCH |
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448 | * platforms is rather conservative and a bit arbitrary expect that on |
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449 | * those platforms VGA disabling requires actual legacy VGA I/O access, |
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450 | * and as part of the cleanup in the hw state restore we also redisable |
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451 | * the vga plane. |
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452 | */ |
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453 | if (!HAS_PCH_SPLIT(dev)) { |
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3480 | Serge | 454 | drm_modeset_lock_all(dev); |
3243 | Serge | 455 | intel_modeset_setup_hw_state(dev, true); |
3480 | Serge | 456 | drm_modeset_unlock_all(dev); |
4560 | Serge | 457 | } |
2330 | Serge | 458 | |
3480 | Serge | 459 | dev_priv->modeset_restore = MODESET_DONE; |
460 | |||
461 | exit: |
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462 | mutex_unlock(&dev_priv->modeset_restore_lock); |
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2330 | Serge | 463 | return NOTIFY_OK; |
464 | } |
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465 | #endif |
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466 | |||
467 | /** |
||
468 | * intel_lvds_destroy - unregister and free LVDS structures |
||
469 | * @connector: connector to free |
||
470 | * |
||
471 | * Unregister the DDC bus for this connector then free the driver private |
||
472 | * structure. |
||
473 | */ |
||
474 | static void intel_lvds_destroy(struct drm_connector *connector) |
||
475 | { |
||
3243 | Serge | 476 | struct intel_lvds_connector *lvds_connector = |
477 | to_lvds_connector(connector); |
||
2330 | Serge | 478 | |
479 | |||
3243 | Serge | 480 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
481 | kfree(lvds_connector->base.edid); |
||
482 | |||
483 | intel_panel_fini(&lvds_connector->base.panel); |
||
484 | |||
2330 | Serge | 485 | drm_connector_cleanup(connector); |
486 | kfree(connector); |
||
487 | } |
||
488 | |||
489 | static int intel_lvds_set_property(struct drm_connector *connector, |
||
490 | struct drm_property *property, |
||
491 | uint64_t value) |
||
492 | { |
||
3243 | Serge | 493 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2330 | Serge | 494 | struct drm_device *dev = connector->dev; |
495 | |||
496 | if (property == dev->mode_config.scaling_mode_property) { |
||
3243 | Serge | 497 | struct drm_crtc *crtc; |
2330 | Serge | 498 | |
499 | if (value == DRM_MODE_SCALE_NONE) { |
||
500 | DRM_DEBUG_KMS("no scaling not supported\n"); |
||
501 | return -EINVAL; |
||
502 | } |
||
503 | |||
3243 | Serge | 504 | if (intel_connector->panel.fitting_mode == value) { |
2330 | Serge | 505 | /* the LVDS scaling property is not changed */ |
506 | return 0; |
||
507 | } |
||
3243 | Serge | 508 | intel_connector->panel.fitting_mode = value; |
509 | |||
510 | crtc = intel_attached_encoder(connector)->base.crtc; |
||
2330 | Serge | 511 | if (crtc && crtc->enabled) { |
512 | /* |
||
513 | * If the CRTC is enabled, the display will be changed |
||
514 | * according to the new panel fitting mode. |
||
515 | */ |
||
3480 | Serge | 516 | intel_crtc_restore_mode(crtc); |
2330 | Serge | 517 | } |
518 | } |
||
519 | |||
520 | return 0; |
||
521 | } |
||
522 | |||
523 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
||
524 | .get_modes = intel_lvds_get_modes, |
||
525 | .mode_valid = intel_lvds_mode_valid, |
||
526 | .best_encoder = intel_best_encoder, |
||
527 | }; |
||
528 | |||
529 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { |
||
3031 | serge | 530 | .dpms = intel_connector_dpms, |
2330 | Serge | 531 | .detect = intel_lvds_detect, |
532 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
533 | .set_property = intel_lvds_set_property, |
||
534 | .destroy = intel_lvds_destroy, |
||
535 | }; |
||
536 | |||
537 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
||
538 | .destroy = intel_encoder_destroy, |
||
539 | }; |
||
540 | |||
5097 | serge | 541 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
2330 | Serge | 542 | { |
3031 | serge | 543 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
2330 | Serge | 544 | return 1; |
545 | } |
||
546 | |||
547 | /* These systems claim to have LVDS, but really don't */ |
||
548 | static const struct dmi_system_id intel_no_lvds[] = { |
||
549 | { |
||
550 | .callback = intel_no_lvds_dmi_callback, |
||
551 | .ident = "Apple Mac Mini (Core series)", |
||
552 | .matches = { |
||
553 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
||
554 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
||
555 | }, |
||
556 | }, |
||
557 | { |
||
558 | .callback = intel_no_lvds_dmi_callback, |
||
559 | .ident = "Apple Mac Mini (Core 2 series)", |
||
560 | .matches = { |
||
561 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
||
562 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
||
563 | }, |
||
564 | }, |
||
565 | { |
||
566 | .callback = intel_no_lvds_dmi_callback, |
||
567 | .ident = "MSI IM-945GSE-A", |
||
568 | .matches = { |
||
569 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), |
||
570 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), |
||
571 | }, |
||
572 | }, |
||
573 | { |
||
574 | .callback = intel_no_lvds_dmi_callback, |
||
575 | .ident = "Dell Studio Hybrid", |
||
576 | .matches = { |
||
577 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
578 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), |
||
579 | }, |
||
580 | }, |
||
581 | { |
||
582 | .callback = intel_no_lvds_dmi_callback, |
||
583 | .ident = "Dell OptiPlex FX170", |
||
584 | .matches = { |
||
585 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
||
586 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), |
||
587 | }, |
||
588 | }, |
||
589 | { |
||
590 | .callback = intel_no_lvds_dmi_callback, |
||
591 | .ident = "AOpen Mini PC", |
||
592 | .matches = { |
||
593 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), |
||
594 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), |
||
595 | }, |
||
596 | }, |
||
597 | { |
||
598 | .callback = intel_no_lvds_dmi_callback, |
||
599 | .ident = "AOpen Mini PC MP915", |
||
600 | .matches = { |
||
601 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
602 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), |
||
603 | }, |
||
604 | }, |
||
605 | { |
||
606 | .callback = intel_no_lvds_dmi_callback, |
||
607 | .ident = "AOpen i915GMm-HFS", |
||
608 | .matches = { |
||
609 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
610 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), |
||
611 | }, |
||
612 | }, |
||
613 | { |
||
614 | .callback = intel_no_lvds_dmi_callback, |
||
2351 | Serge | 615 | .ident = "AOpen i45GMx-I", |
616 | .matches = { |
||
617 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
||
618 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), |
||
619 | }, |
||
620 | }, |
||
621 | { |
||
622 | .callback = intel_no_lvds_dmi_callback, |
||
2330 | Serge | 623 | .ident = "Aopen i945GTt-VFA", |
624 | .matches = { |
||
625 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), |
||
626 | }, |
||
627 | }, |
||
628 | { |
||
629 | .callback = intel_no_lvds_dmi_callback, |
||
630 | .ident = "Clientron U800", |
||
631 | .matches = { |
||
632 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), |
||
633 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), |
||
634 | }, |
||
635 | }, |
||
636 | { |
||
637 | .callback = intel_no_lvds_dmi_callback, |
||
2342 | Serge | 638 | .ident = "Clientron E830", |
639 | .matches = { |
||
640 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), |
||
641 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), |
||
642 | }, |
||
643 | }, |
||
644 | { |
||
645 | .callback = intel_no_lvds_dmi_callback, |
||
2330 | Serge | 646 | .ident = "Asus EeeBox PC EB1007", |
647 | .matches = { |
||
648 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), |
||
649 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), |
||
650 | }, |
||
651 | }, |
||
2342 | Serge | 652 | { |
653 | .callback = intel_no_lvds_dmi_callback, |
||
654 | .ident = "Asus AT5NM10T-I", |
||
655 | .matches = { |
||
656 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), |
||
657 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), |
||
658 | }, |
||
659 | }, |
||
3031 | serge | 660 | { |
661 | .callback = intel_no_lvds_dmi_callback, |
||
3746 | Serge | 662 | .ident = "Hewlett-Packard HP t5740", |
3031 | serge | 663 | .matches = { |
664 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
3746 | Serge | 665 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
3031 | serge | 666 | }, |
667 | }, |
||
668 | { |
||
669 | .callback = intel_no_lvds_dmi_callback, |
||
670 | .ident = "Hewlett-Packard t5745", |
||
671 | .matches = { |
||
672 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
673 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
||
674 | }, |
||
675 | }, |
||
676 | { |
||
677 | .callback = intel_no_lvds_dmi_callback, |
||
678 | .ident = "Hewlett-Packard st5747", |
||
679 | .matches = { |
||
680 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), |
||
681 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
||
682 | }, |
||
683 | }, |
||
684 | { |
||
685 | .callback = intel_no_lvds_dmi_callback, |
||
686 | .ident = "MSI Wind Box DC500", |
||
687 | .matches = { |
||
688 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), |
||
689 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), |
||
690 | }, |
||
691 | }, |
||
692 | { |
||
693 | .callback = intel_no_lvds_dmi_callback, |
||
694 | .ident = "Gigabyte GA-D525TUD", |
||
695 | .matches = { |
||
696 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), |
||
697 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), |
||
698 | }, |
||
699 | }, |
||
700 | { |
||
701 | .callback = intel_no_lvds_dmi_callback, |
||
702 | .ident = "Supermicro X7SPA-H", |
||
703 | .matches = { |
||
704 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), |
||
705 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), |
||
706 | }, |
||
707 | }, |
||
3746 | Serge | 708 | { |
709 | .callback = intel_no_lvds_dmi_callback, |
||
710 | .ident = "Fujitsu Esprimo Q900", |
||
711 | .matches = { |
||
712 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), |
||
713 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), |
||
714 | }, |
||
715 | }, |
||
4104 | Serge | 716 | { |
717 | .callback = intel_no_lvds_dmi_callback, |
||
4280 | Serge | 718 | .ident = "Intel D410PT", |
719 | .matches = { |
||
720 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
721 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), |
||
722 | }, |
||
723 | }, |
||
724 | { |
||
725 | .callback = intel_no_lvds_dmi_callback, |
||
726 | .ident = "Intel D425KT", |
||
727 | .matches = { |
||
728 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
729 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), |
||
730 | }, |
||
731 | }, |
||
732 | { |
||
733 | .callback = intel_no_lvds_dmi_callback, |
||
4104 | Serge | 734 | .ident = "Intel D510MO", |
735 | .matches = { |
||
736 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
737 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), |
||
738 | }, |
||
739 | }, |
||
740 | { |
||
741 | .callback = intel_no_lvds_dmi_callback, |
||
742 | .ident = "Intel D525MW", |
||
743 | .matches = { |
||
744 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), |
||
745 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), |
||
746 | }, |
||
747 | }, |
||
2330 | Serge | 748 | |
749 | { } /* terminating entry */ |
||
750 | }; |
||
751 | |||
752 | /* |
||
753 | * Enumerate the child dev array parsed from VBT to check whether |
||
754 | * the LVDS is present. |
||
755 | * If it is present, return 1. |
||
756 | * If it is not present, return false. |
||
757 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. |
||
758 | */ |
||
759 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
||
760 | u8 *i2c_pin) |
||
761 | { |
||
762 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
763 | int i; |
||
764 | |||
4104 | Serge | 765 | if (!dev_priv->vbt.child_dev_num) |
2330 | Serge | 766 | return true; |
767 | |||
4104 | Serge | 768 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
4560 | Serge | 769 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
770 | struct old_child_dev_config *child = &uchild->old; |
||
2330 | Serge | 771 | |
772 | /* If the device type is not LFP, continue. |
||
773 | * We have to check both the new identifiers as well as the |
||
774 | * old for compatibility with some BIOSes. |
||
775 | */ |
||
776 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
||
777 | child->device_type != DEVICE_TYPE_LFP) |
||
778 | continue; |
||
779 | |||
3031 | serge | 780 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
2330 | Serge | 781 | *i2c_pin = child->i2c_pin; |
782 | |||
783 | /* However, we cannot trust the BIOS writers to populate |
||
784 | * the VBT correctly. Since LVDS requires additional |
||
785 | * information from AIM blocks, a non-zero addin offset is |
||
786 | * a good indicator that the LVDS is actually present. |
||
787 | */ |
||
788 | if (child->addin_offset) |
||
789 | return true; |
||
790 | |||
791 | /* But even then some BIOS writers perform some black magic |
||
792 | * and instantiate the device without reference to any |
||
793 | * additional data. Trust that if the VBT was written into |
||
794 | * the OpRegion then they have validated the LVDS's existence. |
||
795 | */ |
||
796 | if (dev_priv->opregion.vbt) |
||
797 | return true; |
||
798 | } |
||
799 | |||
800 | return false; |
||
801 | } |
||
802 | |||
3480 | Serge | 803 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
804 | { |
||
805 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); |
||
806 | return 1; |
||
807 | } |
||
4104 | Serge | 808 | |
809 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
||
810 | { |
||
811 | .callback = intel_dual_link_lvds_callback, |
||
812 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", |
||
813 | .matches = { |
||
814 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
||
815 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), |
||
816 | }, |
||
817 | }, |
||
818 | { } /* terminating entry */ |
||
819 | }; |
||
820 | |||
3480 | Serge | 821 | bool intel_is_dual_link_lvds(struct drm_device *dev) |
822 | { |
||
823 | struct intel_encoder *encoder; |
||
824 | struct intel_lvds_encoder *lvds_encoder; |
||
825 | |||
5354 | serge | 826 | for_each_intel_encoder(dev, encoder) { |
3480 | Serge | 827 | if (encoder->type == INTEL_OUTPUT_LVDS) { |
828 | lvds_encoder = to_lvds_encoder(&encoder->base); |
||
829 | |||
830 | return lvds_encoder->is_dual_link; |
||
831 | } |
||
832 | } |
||
833 | |||
834 | return false; |
||
835 | } |
||
836 | |||
837 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
||
838 | { |
||
839 | struct drm_device *dev = lvds_encoder->base.base.dev; |
||
840 | unsigned int val; |
||
841 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
842 | |||
843 | /* use the module option value if specified */ |
||
5060 | serge | 844 | if (i915.lvds_channel_mode > 0) |
845 | return i915.lvds_channel_mode == 2; |
||
3480 | Serge | 846 | |
5097 | serge | 847 | if (dmi_check_system(intel_dual_link_lvds)) |
848 | return true; |
||
3480 | Serge | 849 | |
850 | /* BIOS should set the proper LVDS register value at boot, but |
||
851 | * in reality, it doesn't set the value when the lid is closed; |
||
852 | * we need to check "the value to be set" in VBT when LVDS |
||
853 | * register is uninitialized. |
||
854 | */ |
||
855 | val = I915_READ(lvds_encoder->reg); |
||
856 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
||
4104 | Serge | 857 | val = dev_priv->vbt.bios_lvds_val; |
3480 | Serge | 858 | |
859 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
||
860 | } |
||
861 | |||
3031 | serge | 862 | static bool intel_lvds_supported(struct drm_device *dev) |
863 | { |
||
864 | /* With the introduction of the PCH we gained a dedicated |
||
865 | * LVDS presence pin, use it. */ |
||
3746 | Serge | 866 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
3031 | serge | 867 | return true; |
868 | |||
869 | /* Otherwise LVDS was only attached to mobile products, |
||
870 | * except for the inglorious 830gm */ |
||
3746 | Serge | 871 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
872 | return true; |
||
873 | |||
874 | return false; |
||
3031 | serge | 875 | } |
876 | |||
2330 | Serge | 877 | /** |
878 | * intel_lvds_init - setup LVDS connectors on this device |
||
879 | * @dev: drm device |
||
880 | * |
||
881 | * Create the connector, register the LVDS DDC bus, and try to figure out what |
||
882 | * modes we can display on the LVDS panel (if present). |
||
883 | */ |
||
4104 | Serge | 884 | void intel_lvds_init(struct drm_device *dev) |
2330 | Serge | 885 | { |
886 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
3243 | Serge | 887 | struct intel_lvds_encoder *lvds_encoder; |
2330 | Serge | 888 | struct intel_encoder *intel_encoder; |
3243 | Serge | 889 | struct intel_lvds_connector *lvds_connector; |
2330 | Serge | 890 | struct intel_connector *intel_connector; |
891 | struct drm_connector *connector; |
||
892 | struct drm_encoder *encoder; |
||
893 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ |
||
3243 | Serge | 894 | struct drm_display_mode *fixed_mode = NULL; |
5060 | serge | 895 | struct drm_display_mode *downclock_mode = NULL; |
3243 | Serge | 896 | struct edid *edid; |
2330 | Serge | 897 | struct drm_crtc *crtc; |
898 | u32 lvds; |
||
899 | int pipe; |
||
900 | u8 pin; |
||
901 | |||
5354 | serge | 902 | /* |
903 | * Unlock registers and just leave them unlocked. Do this before |
||
904 | * checking quirk lists to avoid bogus WARNINGs. |
||
905 | */ |
||
906 | if (HAS_PCH_SPLIT(dev)) { |
||
907 | I915_WRITE(PCH_PP_CONTROL, |
||
908 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); |
||
909 | } else { |
||
910 | I915_WRITE(PP_CONTROL, |
||
911 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); |
||
912 | } |
||
3031 | serge | 913 | if (!intel_lvds_supported(dev)) |
4104 | Serge | 914 | return; |
3031 | serge | 915 | |
2330 | Serge | 916 | /* Skip init on machines we know falsely report LVDS */ |
5097 | serge | 917 | if (dmi_check_system(intel_no_lvds)) |
918 | return; |
||
2330 | Serge | 919 | |
920 | pin = GMBUS_PORT_PANEL; |
||
921 | if (!lvds_is_present_in_vbt(dev, &pin)) { |
||
922 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
||
4104 | Serge | 923 | return; |
2330 | Serge | 924 | } |
925 | |||
926 | if (HAS_PCH_SPLIT(dev)) { |
||
927 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
||
4104 | Serge | 928 | return; |
929 | if (dev_priv->vbt.edp_support) { |
||
2330 | Serge | 930 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
4104 | Serge | 931 | return; |
2330 | Serge | 932 | } |
933 | } |
||
934 | |||
4560 | Serge | 935 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
3243 | Serge | 936 | if (!lvds_encoder) |
4104 | Serge | 937 | return; |
2330 | Serge | 938 | |
4560 | Serge | 939 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
3243 | Serge | 940 | if (!lvds_connector) { |
941 | kfree(lvds_encoder); |
||
4104 | Serge | 942 | return; |
2330 | Serge | 943 | } |
944 | |||
3243 | Serge | 945 | lvds_encoder->attached_connector = lvds_connector; |
946 | |||
947 | intel_encoder = &lvds_encoder->base; |
||
2330 | Serge | 948 | encoder = &intel_encoder->base; |
3243 | Serge | 949 | intel_connector = &lvds_connector->base; |
2330 | Serge | 950 | connector = &intel_connector->base; |
951 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
||
952 | DRM_MODE_CONNECTOR_LVDS); |
||
953 | |||
954 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
||
955 | DRM_MODE_ENCODER_LVDS); |
||
956 | |||
3031 | serge | 957 | intel_encoder->enable = intel_enable_lvds; |
3480 | Serge | 958 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
3746 | Serge | 959 | intel_encoder->compute_config = intel_lvds_compute_config; |
3031 | serge | 960 | intel_encoder->disable = intel_disable_lvds; |
961 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
||
4104 | Serge | 962 | intel_encoder->get_config = intel_lvds_get_config; |
3031 | serge | 963 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
5060 | serge | 964 | intel_connector->unregister = intel_connector_unregister; |
3031 | serge | 965 | |
2330 | Serge | 966 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
967 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
||
968 | |||
5060 | serge | 969 | intel_encoder->cloneable = 0; |
2342 | Serge | 970 | if (HAS_PCH_SPLIT(dev)) |
971 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
3031 | serge | 972 | else if (IS_GEN4(dev)) |
973 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
||
2342 | Serge | 974 | else |
2330 | Serge | 975 | intel_encoder->crtc_mask = (1 << 1); |
2342 | Serge | 976 | |
2330 | Serge | 977 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
978 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
||
979 | connector->interlace_allowed = false; |
||
980 | connector->doublescan_allowed = false; |
||
981 | |||
3480 | Serge | 982 | if (HAS_PCH_SPLIT(dev)) { |
983 | lvds_encoder->reg = PCH_LVDS; |
||
984 | } else { |
||
985 | lvds_encoder->reg = LVDS; |
||
986 | } |
||
987 | |||
2330 | Serge | 988 | /* create the scaling mode property */ |
989 | drm_mode_create_scaling_mode_property(dev); |
||
3243 | Serge | 990 | drm_object_attach_property(&connector->base, |
2330 | Serge | 991 | dev->mode_config.scaling_mode_property, |
992 | DRM_MODE_SCALE_ASPECT); |
||
3243 | Serge | 993 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
2330 | Serge | 994 | /* |
995 | * LVDS discovery: |
||
996 | * 1) check for EDID on DDC |
||
997 | * 2) check for VBT data |
||
998 | * 3) check to see if LVDS is already on |
||
999 | * if none of the above, no panel |
||
1000 | * 4) make sure lid is open |
||
1001 | * if closed, act like it's not there for now |
||
1002 | */ |
||
1003 | |||
1004 | /* |
||
1005 | * Attempt to get the fixed panel mode from DDC. Assume that the |
||
1006 | * preferred mode is the right one. |
||
1007 | */ |
||
5060 | serge | 1008 | mutex_lock(&dev->mode_config.mutex); |
3243 | Serge | 1009 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1010 | if (edid) { |
||
1011 | if (drm_add_edid_modes(connector, edid)) { |
||
2330 | Serge | 1012 | drm_mode_connector_update_edid_property(connector, |
3243 | Serge | 1013 | edid); |
2330 | Serge | 1014 | } else { |
3243 | Serge | 1015 | kfree(edid); |
1016 | edid = ERR_PTR(-EINVAL); |
||
2330 | Serge | 1017 | } |
3243 | Serge | 1018 | } else { |
1019 | edid = ERR_PTR(-ENOENT); |
||
2330 | Serge | 1020 | } |
3243 | Serge | 1021 | lvds_connector->base.edid = edid; |
1022 | |||
1023 | if (IS_ERR_OR_NULL(edid)) { |
||
2330 | Serge | 1024 | /* Didn't get an EDID, so |
1025 | * Set wide sync ranges so we get all modes |
||
1026 | * handed to valid_mode for checking |
||
1027 | */ |
||
1028 | connector->display_info.min_vfreq = 0; |
||
1029 | connector->display_info.max_vfreq = 200; |
||
1030 | connector->display_info.min_hfreq = 0; |
||
1031 | connector->display_info.max_hfreq = 200; |
||
1032 | } |
||
1033 | |||
1034 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
1035 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
||
3243 | Serge | 1036 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1037 | drm_mode_debug_printmodeline(scan); |
||
1038 | |||
1039 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
1040 | if (fixed_mode) { |
||
5060 | serge | 1041 | downclock_mode = |
4560 | Serge | 1042 | intel_find_panel_downclock(dev, |
1043 | fixed_mode, connector); |
||
5060 | serge | 1044 | if (downclock_mode != NULL && |
1045 | i915.lvds_downclock) { |
||
4560 | Serge | 1046 | /* We found the downclock for LVDS. */ |
1047 | dev_priv->lvds_downclock_avail = true; |
||
1048 | dev_priv->lvds_downclock = |
||
1049 | downclock_mode->clock; |
||
1050 | DRM_DEBUG_KMS("LVDS downclock is found" |
||
1051 | " in EDID. Normal clock %dKhz, " |
||
1052 | "downclock %dKhz\n", |
||
1053 | fixed_mode->clock, |
||
1054 | dev_priv->lvds_downclock); |
||
1055 | } |
||
2330 | Serge | 1056 | goto out; |
1057 | } |
||
1058 | } |
||
3243 | Serge | 1059 | } |
2330 | Serge | 1060 | |
1061 | /* Failed to get EDID, what about VBT? */ |
||
4104 | Serge | 1062 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
3243 | Serge | 1063 | DRM_DEBUG_KMS("using mode from VBT: "); |
4104 | Serge | 1064 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
3243 | Serge | 1065 | |
4104 | Serge | 1066 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
3243 | Serge | 1067 | if (fixed_mode) { |
1068 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2330 | Serge | 1069 | goto out; |
1070 | } |
||
1071 | } |
||
1072 | |||
1073 | /* |
||
1074 | * If we didn't get EDID, try checking if the panel is already turned |
||
1075 | * on. If so, assume that whatever is currently programmed is the |
||
1076 | * correct mode. |
||
1077 | */ |
||
1078 | |||
1079 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
||
1080 | if (HAS_PCH_SPLIT(dev)) |
||
1081 | goto failed; |
||
1082 | |||
1083 | lvds = I915_READ(LVDS); |
||
1084 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
||
1085 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
||
1086 | |||
1087 | if (crtc && (lvds & LVDS_PORT_EN)) { |
||
3243 | Serge | 1088 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1089 | if (fixed_mode) { |
||
1090 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
||
1091 | drm_mode_debug_printmodeline(fixed_mode); |
||
1092 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2330 | Serge | 1093 | goto out; |
1094 | } |
||
1095 | } |
||
1096 | |||
1097 | /* If we still don't have a mode after all that, give up. */ |
||
3243 | Serge | 1098 | if (!fixed_mode) |
2330 | Serge | 1099 | goto failed; |
1100 | |||
1101 | out: |
||
5060 | serge | 1102 | mutex_unlock(&dev->mode_config.mutex); |
1103 | |||
3480 | Serge | 1104 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
1105 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
||
1106 | lvds_encoder->is_dual_link ? "dual" : "single"); |
||
1107 | |||
5060 | serge | 1108 | lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) & |
1109 | LVDS_A3_POWER_MASK; |
||
1110 | |||
1111 | drm_connector_register(connector); |
||
2330 | Serge | 1112 | |
5060 | serge | 1113 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5354 | serge | 1114 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
2330 | Serge | 1115 | |
4104 | Serge | 1116 | return; |
2330 | Serge | 1117 | |
1118 | failed: |
||
5060 | serge | 1119 | mutex_unlock(&dev->mode_config.mutex); |
1120 | |||
2330 | Serge | 1121 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
1122 | drm_connector_cleanup(connector); |
||
1123 | drm_encoder_cleanup(encoder); |
||
3243 | Serge | 1124 | kfree(lvds_encoder); |
1125 | kfree(lvds_connector); |
||
4104 | Serge | 1126 | return; |
2330 | Serge | 1127 | }><>><>><>><>><>><>=>>>> |