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/*

 * Copyright © 2014 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 *

 * Authors:

 *    Ben Widawsky 

 *    Michel Thierry 

 *    Thomas Daniel 

 *    Oscar Mateo 

 *

 */

/**

 * DOC: Logical Rings, Logical Ring Contexts and Execlists

 *

 * Motivation:

 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".

 * These expanded contexts enable a number of new abilities, especially

 * "Execlists" (also implemented in this file).

 *

 * One of the main differences with the legacy HW contexts is that logical

 * ring contexts incorporate many more things to the context's state, like

 * PDPs or ringbuffer control registers:

 *

 * The reason why PDPs are included in the context is straightforward: as

 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs

 * contained there mean you don't need to do a ppgtt->switch_mm yourself,

 * instead, the GPU will do it for you on the context switch.

 *

 * But, what about the ringbuffer control registers (head, tail, etc..)?

 * shouldn't we just need a set of those per engine command streamer? This is

 * where the name "Logical Rings" starts to make sense: by virtualizing the

 * rings, the engine cs shifts to a new "ring buffer" with every context

 * switch. When you want to submit a workload to the GPU you: A) choose your

 * context, B) find its appropriate virtualized ring, C) write commands to it

 * and then, finally, D) tell the GPU to switch to that context.

 *

 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch

 * to a contexts is via a context execution list, ergo "Execlists".

 *

 * LRC implementation:

 * Regarding the creation of contexts, we have:

 *

 * - One global default context.

 * - One local default context for each opened fd.

 * - One local extra context for each context create ioctl call.

 *

 * Now that ringbuffers belong per-context (and not per-engine, like before)

 * and that contexts are uniquely tied to a given engine (and not reusable,

 * like before) we need:

 *

 * - One ringbuffer per-engine inside each context.

 * - One backing object per-engine inside each context.

 *

 * The global default context starts its life with these new objects fully

 * allocated and populated. The local default context for each opened fd is

 * more complex, because we don't know at creation time which engine is going

 * to use them. To handle this, we have implemented a deferred creation of LR

 * contexts:

 *

 * The local context starts its life as a hollow or blank holder, that only

 * gets populated for a given engine once we receive an execbuffer. If later

 * on we receive another execbuffer ioctl for the same context but a different

 * engine, we allocate/populate a new ringbuffer and context backing object and

 * so on.

 *

 * Finally, regarding local contexts created using the ioctl call: as they are

 * only allowed with the render ring, we can allocate & populate them right

 * away (no need to defer anything, at least for now).

 *

 * Execlists implementation:

 * Execlists are the new method by which, on gen8+ hardware, workloads are

 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).

 * This method works as follows:

 *

 * When a request is committed, its commands (the BB start and any leading or

 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer

 * for the appropriate context. The tail pointer in the hardware context is not

 * updated at this time, but instead, kept by the driver in the ringbuffer

 * structure. A structure representing this request is added to a request queue

 * for the appropriate engine: this structure contains a copy of the context's

 * tail after the request was written to the ring buffer and a pointer to the

 * context itself.

 *

 * If the engine's request queue was empty before the request was added, the

 * queue is processed immediately. Otherwise the queue will be processed during

 * a context switch interrupt. In any case, elements on the queue will get sent

 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a

 * globally unique 20-bits submission ID.

 *

 * When execution of a request completes, the GPU updates the context status

 * buffer with a context complete event and generates a context switch interrupt.

 * During the interrupt handling, the driver examines the events in the buffer:

 * for each context complete event, if the announced ID matches that on the head

 * of the request queue, then that request is retired and removed from the queue.

 *

 * After processing, if any requests were retired and the queue is not empty

 * then a new execution list can be submitted. The two requests at the front of

 * the queue are next to be submitted but since a context may not occur twice in

 * an execution list, if subsequent requests have the same ID as the first then

 * the two requests must be combined. This is done simply by discarding requests

 * at the head of the queue until either only one requests is left (in which case

 * we use a NULL second context) or the first two requests have unique IDs.

 *

 * By always executing the first two requests in the queue the driver ensures

 * that the GPU is kept as busy as possible. In the case where a single context

 * completes but a second context is still executing, the request for this second

 * context will be at the head of the queue when we remove the first one. This

 * request will then be resubmitted along with a new request for a different context,

 * which will cause the hardware to continue executing the second request and queue

 * the new request (the GPU detects the condition of a context getting preempted

 * with the same context and optimizes the context switch flow by not doing

 * preemption, but just sampling the new tail pointer).

 *

 */

#include 

#include 

#include "i915_drv.h"

#include "intel_mocs.h"

#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)

#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)

#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

#define RING_EXECLIST_QFULL		(1 << 0x2)

#define RING_EXECLIST1_VALID		(1 << 0x3)

#define RING_EXECLIST0_VALID		(1 << 0x4)

#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)

#define RING_EXECLIST1_ACTIVE		(1 << 0x11)

#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)

#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)

#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)

#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)

#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)

#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)

#define CTX_LRI_HEADER_0		0x01

#define CTX_CONTEXT_CONTROL		0x02

#define CTX_RING_HEAD			0x04

#define CTX_RING_TAIL			0x06

#define CTX_RING_BUFFER_START		0x08

#define CTX_RING_BUFFER_CONTROL		0x0a

#define CTX_BB_HEAD_U			0x0c

#define CTX_BB_HEAD_L			0x0e

#define CTX_BB_STATE			0x10

#define CTX_SECOND_BB_HEAD_U		0x12

#define CTX_SECOND_BB_HEAD_L		0x14

#define CTX_SECOND_BB_STATE		0x16

#define CTX_BB_PER_CTX_PTR		0x18

#define CTX_RCS_INDIRECT_CTX		0x1a

#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c

#define CTX_LRI_HEADER_1		0x21

#define CTX_CTX_TIMESTAMP		0x22

#define CTX_PDP3_UDW			0x24

#define CTX_PDP3_LDW			0x26

#define CTX_PDP2_UDW			0x28

#define CTX_PDP2_LDW			0x2a

#define CTX_PDP1_UDW			0x2c

#define CTX_PDP1_LDW			0x2e

#define CTX_PDP0_UDW			0x30

#define CTX_PDP0_LDW			0x32

#define CTX_LRI_HEADER_2		0x41

#define CTX_R_PWR_CLK_STATE		0x42

#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

#define GEN8_CTX_VALID (1<<0)

#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)

#define GEN8_CTX_FORCE_RESTORE (1<<2)

#define GEN8_CTX_L3LLC_COHERENT (1<<5)

#define GEN8_CTX_PRIVILEGE (1<<8)

#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \

	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \

	(reg_state)[(pos)+1] = (val); \

} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\

	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\

	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \

	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \

} while (0)

#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \

	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \

	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \

} while (0)

enum {

	ADVANCED_CONTEXT = 0,

	LEGACY_32B_CONTEXT,

	ADVANCED_AD_CONTEXT,

	LEGACY_64B_CONTEXT

};

#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3

#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\

		LEGACY_64B_CONTEXT :\

		LEGACY_32B_CONTEXT)

enum {

	FAULT_AND_HANG = 0,

	FAULT_AND_HALT, /* Debug only */

	FAULT_AND_STREAM,

	FAULT_AND_CONTINUE /* Unsupported */

};

#define GEN8_CTX_ID_SHIFT 32

#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17

#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26

static int intel_lr_context_pin(struct intel_context *ctx,

				struct intel_engine_cs *engine);

static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,

		struct drm_i915_gem_object *default_ctx_obj);

/**

 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists

 * @dev: DRM device.

 * @enable_execlists: value of i915.enable_execlists module parameter.

 *

 * Only certain platforms support Execlists (the prerequisites being

 * support for Logical Ring Contexts and Aliasing PPGTT or better).

 *

 * Return: 1 if Execlists is supported and has to be enabled.

 */

int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)

{

	WARN_ON(i915.enable_ppgtt == -1);

	/* On platforms with execlist available, vGPU will only

	 * support execlist mode, no ring buffer mode.

	 */

	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))

		return 1;

	if (INTEL_INFO(dev)->gen >= 9)

		return 1;

	if (enable_execlists == 0)

		return 0;

	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&

	    i915.use_mmio_flip >= 0)

		return 1;

	return 0;

}

static void

logical_ring_init_platform_invariants(struct intel_engine_cs *ring)

{

	struct drm_device *dev = ring->dev;

	ring->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||

					IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&

					(ring->id == VCS || ring->id == VCS2);

	ring->ctx_desc_template = GEN8_CTX_VALID;

	ring->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<

				   GEN8_CTX_ADDRESSING_MODE_SHIFT;

	if (IS_GEN8(dev))

		ring->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;

	ring->ctx_desc_template |= GEN8_CTX_PRIVILEGE;

	/* TODO: WaDisableLiteRestore when we start using semaphore

	 * signalling between Command Streamers */

	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */

	/* WaEnableForceRestoreInCtxtDescForVCS:skl */

	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */

	if (ring->disable_lite_restore_wa)

		ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;

}

/**

 * intel_lr_context_descriptor_update() - calculate & cache the descriptor

 * 					  descriptor for a pinned context

 *

 * @ctx: Context to work on

 * @ring: Engine the descriptor will be used with

 *

 * The context descriptor encodes various attributes of a context,

 * including its GTT address and some flags. Because it's fairly

 * expensive to calculate, we'll just do it once and cache the result,

 * which remains valid until the context is unpinned.

 *

 * This is what a descriptor looks like, from LSB to MSB:

 *    bits 0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)

 *    bits 12-31:    LRCA, GTT address of (the HWSP of) this context

 *    bits 32-51:    ctx ID, a globally unique tag (the LRCA again!)

 *    bits 52-63:    reserved, may encode the engine ID (for GuC)

 */

static void

intel_lr_context_descriptor_update(struct intel_context *ctx,

				   struct intel_engine_cs *ring)

{

	uint64_t lrca, desc;

	lrca = ctx->engine[ring->id].lrc_vma->node.start +

	       LRC_PPHWSP_PN * PAGE_SIZE;

	desc = ring->ctx_desc_template;			   /* bits  0-11 */

	desc |= lrca;					   /* bits 12-31 */

	desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */

	ctx->engine[ring->id].lrc_desc = desc;

}

uint64_t intel_lr_context_descriptor(struct intel_context *ctx,

				     struct intel_engine_cs *ring)

{

	return ctx->engine[ring->id].lrc_desc;

}

/**

 * intel_execlists_ctx_id() - get the Execlists Context ID

 * @ctx: Context to get the ID for

 * @ring: Engine to get the ID for

 *

 * Do not confuse with ctx->id! Unfortunately we have a name overload

 * here: the old context ID we pass to userspace as a handler so that

 * they can refer to a context, and the new context ID we pass to the

 * ELSP so that the GPU can inform us of the context status via

 * interrupts.

 *

 * The context ID is a portion of the context descriptor, so we can

 * just extract the required part from the cached descriptor.

 *

 * Return: 20-bits globally unique context ID.

 */

u32 intel_execlists_ctx_id(struct intel_context *ctx,

			   struct intel_engine_cs *ring)

{

	return intel_lr_context_descriptor(ctx, ring) >> GEN8_CTX_ID_SHIFT;

}

static void execlists_elsp_write(struct drm_i915_gem_request *rq0,

				 struct drm_i915_gem_request *rq1)

{

	struct intel_engine_cs *ring = rq0->ring;

	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint64_t desc[2];

	if (rq1) {

		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring);

		rq1->elsp_submitted++;

	} else {

		desc[1] = 0;

	}

	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring);

	rq0->elsp_submitted++;

	/* You must always write both descriptors in the order below. */

	spin_lock(&dev_priv->uncore.lock);

	intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);

	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));

	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));

	I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));

	/* The context is automatically loaded after the following */

	I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));

	/* ELSP is a wo register, use another nearby reg for posting */

	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));

	intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);

	spin_unlock(&dev_priv->uncore.lock);

}

static int execlists_update_context(struct drm_i915_gem_request *rq)

{

	struct intel_engine_cs *ring = rq->ring;

	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;

	uint32_t *reg_state = rq->ctx->engine[ring->id].lrc_reg_state;

	reg_state[CTX_RING_TAIL+1] = rq->tail;

	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {

		/* True 32b PPGTT with dynamic page allocation: update PDP

		 * registers and point the unallocated PDPs to scratch page.

		 * PML4 is allocated during ppgtt init, so this is not needed

		 * in 48-bit mode.

		 */

		ASSIGN_CTX_PDP(ppgtt, reg_state, 3);

		ASSIGN_CTX_PDP(ppgtt, reg_state, 2);

		ASSIGN_CTX_PDP(ppgtt, reg_state, 1);

		ASSIGN_CTX_PDP(ppgtt, reg_state, 0);

	}

	return 0;

}

static void execlists_submit_requests(struct drm_i915_gem_request *rq0,

				      struct drm_i915_gem_request *rq1)

{

	execlists_update_context(rq0);

	if (rq1)

		execlists_update_context(rq1);

	execlists_elsp_write(rq0, rq1);

}

static void execlists_context_unqueue(struct intel_engine_cs *ring)

{

	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;

	struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;

	assert_spin_locked(&ring->execlist_lock);

	/*

	 * If irqs are not active generate a warning as batches that finish

	 * without the irqs may get lost and a GPU Hang may occur.

	 */

	WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));

	if (list_empty(&ring->execlist_queue))

		return;

	/* Try to read in pairs */

	list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,

				 execlist_link) {

		if (!req0) {

			req0 = cursor;

		} else if (req0->ctx == cursor->ctx) {

			/* Same ctx: ignore first request, as second request

			 * will update tail past first request's workload */

			cursor->elsp_submitted = req0->elsp_submitted;

			list_move_tail(&req0->execlist_link,

				       &ring->execlist_retired_req_list);

			req0 = cursor;

		} else {

			req1 = cursor;

			break;

		}

	}

	if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {

		/*

		 * WaIdleLiteRestore: make sure we never cause a lite

		 * restore with HEAD==TAIL

		 */

		if (req0->elsp_submitted) {

			/*

			 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL

			 * as we resubmit the request. See gen8_emit_request()

			 * for where we prepare the padding after the end of the

			 * request.

			 */

			struct intel_ringbuffer *ringbuf;

			ringbuf = req0->ctx->engine[ring->id].ringbuf;

			req0->tail += 8;

			req0->tail &= ringbuf->size - 1;

		}

	}

	WARN_ON(req1 && req1->elsp_submitted);

	execlists_submit_requests(req0, req1);

}

static bool execlists_check_remove_request(struct intel_engine_cs *ring,

					   u32 request_id)

{

	struct drm_i915_gem_request *head_req;

	assert_spin_locked(&ring->execlist_lock);

	head_req = list_first_entry_or_null(&ring->execlist_queue,

					    struct drm_i915_gem_request,

					    execlist_link);

	if (head_req != NULL) {

		if (intel_execlists_ctx_id(head_req->ctx, ring) == request_id) {

			WARN(head_req->elsp_submitted == 0,

			     "Never submitted head request\n");

			if (--head_req->elsp_submitted <= 0) {

				list_move_tail(&head_req->execlist_link,

					       &ring->execlist_retired_req_list);

				return true;

			}

		}

	}

	return false;

}

static void get_context_status(struct intel_engine_cs *ring,

			       u8 read_pointer,

			       u32 *status, u32 *context_id)

{

	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	if (WARN_ON(read_pointer >= GEN8_CSB_ENTRIES))

		return;

	*status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer));

	*context_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer));

}

/**

 * intel_lrc_irq_handler() - handle Context Switch interrupts

 * @ring: Engine Command Streamer to handle.

 *

 * Check the unread Context Status Buffers and manage the submission of new

 * contexts to the ELSP accordingly.

 */

void intel_lrc_irq_handler(struct intel_engine_cs *ring)

{

	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	u32 status_pointer;

	u8 read_pointer;

	u8 write_pointer;

	u32 status = 0;

	u32 status_id;

	u32 submit_contexts = 0;

	status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));

	read_pointer = ring->next_context_status_buffer;

	write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);

	if (read_pointer > write_pointer)

		write_pointer += GEN8_CSB_ENTRIES;

	spin_lock(&ring->execlist_lock);

	while (read_pointer < write_pointer) {

		get_context_status(ring, ++read_pointer % GEN8_CSB_ENTRIES,

				   &status, &status_id);

		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)

			continue;

		if (status & GEN8_CTX_STATUS_PREEMPTED) {

			if (status & GEN8_CTX_STATUS_LITE_RESTORE) {

				if (execlists_check_remove_request(ring, status_id))

					WARN(1, "Lite Restored request removed from queue\n");

			} else

				WARN(1, "Preemption without Lite Restore\n");

		}

		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||

		    (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {

			if (execlists_check_remove_request(ring, status_id))

				submit_contexts++;

		}

	}

	if (ring->disable_lite_restore_wa) {

		/* Prevent a ctx to preempt itself */

		if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&

		    (submit_contexts != 0))

			execlists_context_unqueue(ring);

	} else if (submit_contexts != 0) {

		execlists_context_unqueue(ring);

	}

	spin_unlock(&ring->execlist_lock);

	if (unlikely(submit_contexts > 2))

		DRM_ERROR("More than two context complete events?\n");

	ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;

	/* Update the read pointer to the old write pointer. Manual ringbuffer

	 * management ftw  */

	I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),

		   _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,

				 ring->next_context_status_buffer << 8));

}

static int execlists_context_queue(struct drm_i915_gem_request *request)

{

	struct intel_engine_cs *ring = request->ring;

	struct drm_i915_gem_request *cursor;

	int num_elements = 0;

	if (request->ctx != request->i915->kernel_context)

		intel_lr_context_pin(request->ctx, ring);

	i915_gem_request_reference(request);

	spin_lock_irq(&ring->execlist_lock);

	list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)

		if (++num_elements > 2)

			break;

	if (num_elements > 2) {

		struct drm_i915_gem_request *tail_req;

		tail_req = list_last_entry(&ring->execlist_queue,

					   struct drm_i915_gem_request,

					   execlist_link);

		if (request->ctx == tail_req->ctx) {

			WARN(tail_req->elsp_submitted != 0,

				"More than 2 already-submitted reqs queued\n");

			list_move_tail(&tail_req->execlist_link,

				       &ring->execlist_retired_req_list);

		}

	}

	list_add_tail(&request->execlist_link, &ring->execlist_queue);

	if (num_elements == 0)

		execlists_context_unqueue(ring);

	spin_unlock_irq(&ring->execlist_lock);

	return 0;

}

static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)

{

	struct intel_engine_cs *ring = req->ring;

	uint32_t flush_domains;

	int ret;

	flush_domains = 0;

	if (ring->gpu_caches_dirty)

		flush_domains = I915_GEM_GPU_DOMAINS;

	ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);

	if (ret)

		return ret;

	ring->gpu_caches_dirty = false;

	return 0;

}

static int execlists_move_to_gpu(struct drm_i915_gem_request *req,

				 struct list_head *vmas)

{

	const unsigned other_rings = ~intel_ring_flag(req->ring);

	struct i915_vma *vma;

	uint32_t flush_domains = 0;

	bool flush_chipset = false;

	int ret;

	list_for_each_entry(vma, vmas, exec_list) {

		struct drm_i915_gem_object *obj = vma->obj;

		if (obj->active & other_rings) {

			ret = i915_gem_object_sync(obj, req->ring, &req);

			if (ret)

				return ret;

		}

		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)

			flush_chipset |= i915_gem_clflush_object(obj, false);

		flush_domains |= obj->base.write_domain;

	}

	if (flush_domains & I915_GEM_DOMAIN_GTT)

		wmb();

	/* Unconditionally invalidate gpu caches and ensure that we do flush

	 * any residual writes from the previous batch.

	 */

	return logical_ring_invalidate_all_caches(req);

}

int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)

{

	int ret = 0;

	request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;

	if (i915.enable_guc_submission) {

		/*

		 * Check that the GuC has space for the request before

		 * going any further, as the i915_add_request() call

		 * later on mustn't fail ...

		 */

		struct intel_guc *guc = &request->i915->guc;

		ret = i915_guc_wq_check_space(guc->execbuf_client);

		if (ret)

			return ret;

	}

	if (request->ctx != request->i915->kernel_context)

		ret = intel_lr_context_pin(request->ctx, request->ring);

	return ret;

}

static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,

				       int bytes)

{

	struct intel_ringbuffer *ringbuf = req->ringbuf;

	struct intel_engine_cs *ring = req->ring;

	struct drm_i915_gem_request *target;

	unsigned space;

	int ret;

	if (intel_ring_space(ringbuf) >= bytes)

		return 0;

	/* The whole point of reserving space is to not wait! */

	WARN_ON(ringbuf->reserved_in_use);

	list_for_each_entry(target, &ring->request_list, list) {

		/*

		 * The request queue is per-engine, so can contain requests

		 * from multiple ringbuffers. Here, we must ignore any that

		 * aren't from the ringbuffer we're considering.

		 */

		if (target->ringbuf != ringbuf)

			continue;

		/* Would completion of this request free enough space? */

		space = __intel_ring_space(target->postfix, ringbuf->tail,

					   ringbuf->size);

		if (space >= bytes)

			break;

	}

	if (WARN_ON(&target->list == &ring->request_list))

		return -ENOSPC;

	ret = i915_wait_request(target);

	if (ret)

		return ret;

	ringbuf->space = space;

	return 0;

}

/*

 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload

 * @request: Request to advance the logical ringbuffer of.

 *

 * The tail is updated in our logical ringbuffer struct, not in the actual context. What

 * really happens during submission is that the context and current tail will be placed

 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that

 * point, the tail *inside* the context is updated and the ELSP written to.

 */

static int

intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)

{

	struct intel_ringbuffer *ringbuf = request->ringbuf;

	struct drm_i915_private *dev_priv = request->i915;

	struct intel_engine_cs *engine = request->ring;

	intel_logical_ring_advance(ringbuf);

	request->tail = ringbuf->tail;

	/*

	 * Here we add two extra NOOPs as padding to avoid

	 * lite restore of a context with HEAD==TAIL.

	 *

	 * Caller must reserve WA_TAIL_DWORDS for us!

	 */

	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_emit(ringbuf, MI_NOOP);

	intel_logical_ring_advance(ringbuf);

	if (intel_ring_stopped(engine))

		return 0;

	if (engine->last_context != request->ctx) {

		if (engine->last_context)

			intel_lr_context_unpin(engine->last_context, engine);

		if (request->ctx != request->i915->kernel_context) {

			intel_lr_context_pin(request->ctx, engine);

			engine->last_context = request->ctx;

		} else {

			engine->last_context = NULL;

		}

	}

	if (dev_priv->guc.execbuf_client)

		i915_guc_submit(dev_priv->guc.execbuf_client, request);

	else

		execlists_context_queue(request);

	return 0;

}

static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)

{

	uint32_t __iomem *virt;

	int rem = ringbuf->size - ringbuf->tail;

	virt = ringbuf->virtual_start + ringbuf->tail;

	rem /= 4;

	while (rem--)

		iowrite32(MI_NOOP, virt++);

	ringbuf->tail = 0;

	intel_ring_update_space(ringbuf);

}

static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)

{

	struct intel_ringbuffer *ringbuf = req->ringbuf;

	int remain_usable = ringbuf->effective_size - ringbuf->tail;

	int remain_actual = ringbuf->size - ringbuf->tail;

	int ret, total_bytes, wait_bytes = 0;

	bool need_wrap = false;

	if (ringbuf->reserved_in_use)

		total_bytes = bytes;

	else

		total_bytes = bytes + ringbuf->reserved_size;

	if (unlikely(bytes > remain_usable)) {

		/*

		 * Not enough space for the basic request. So need to flush

		 * out the remainder and then wait for base + reserved.

		 */

		wait_bytes = remain_actual + total_bytes;

		need_wrap = true;

	} else {

		if (unlikely(total_bytes > remain_usable)) {

			/*

			 * The base request will fit but the reserved space

			 * falls off the end. So don't need an immediate wrap

			 * and only need to effectively wait for the reserved

			 * size space from the start of ringbuffer.

			 */

			wait_bytes = remain_actual + ringbuf->reserved_size;

		} else if (total_bytes > ringbuf->space) {

			/* No wrapping required, just waiting. */

			wait_bytes = total_bytes;

		}

	}

	if (wait_bytes) {

		ret = logical_ring_wait_for_space(req, wait_bytes);

		if (unlikely(ret))

			return ret;

		if (need_wrap)

			__wrap_ring_buffer(ringbuf);

	}

	return 0;

}

/**

 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands

 *

 * @req: The request to start some new work for

 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.

 *

 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to

 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that

 * and also preallocates a request (every workload submission is still mediated through

 * requests, same as it did with legacy ringbuffer submission).

 *

 * Return: non-zero if the ringbuffer is not ready to be written to.

 */

int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)

{

	struct drm_i915_private *dev_priv;

	int ret;

	WARN_ON(req == NULL);

	dev_priv = req->ring->dev->dev_private;

	ret = i915_gem_check_wedge(&dev_priv->gpu_error,

				   dev_priv->mm.interruptible);

	if (ret)

		return ret;

	ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));

	if (ret)

		return ret;

	req->ringbuf->space -= num_dwords * sizeof(uint32_t);

	return 0;

}

int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)

{

	/*

	 * The first call merely notes the reserve request and is common for

	 * all back ends. The subsequent localised _begin() call actually

	 * ensures that the reservation is available. Without the begin, if

	 * the request creator immediately submitted the request without

	 * adding any commands to it then there might not actually be

	 * sufficient room for the submission commands.

	 */

	intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);

	return intel_logical_ring_begin(request, 0);

}

/**

 * execlists_submission() - submit a batchbuffer for execution, Execlists style

 * @dev: DRM device.

 * @file: DRM file.

 * @ring: Engine Command Streamer to submit to.

 * @ctx: Context to employ for this submission.

 * @args: execbuffer call arguments.

 * @vmas: list of vmas.

 * @batch_obj: the batchbuffer to submit.

 * @exec_start: batchbuffer start virtual address pointer.

 * @dispatch_flags: translated execbuffer call flags.

 *

 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts

 * away the submission details of the execbuffer ioctl call.

 *

 * Return: non-zero if the submission fails.

 */

int intel_execlists_submission(struct i915_execbuffer_params *params,

			       struct drm_i915_gem_execbuffer2 *args,

			       struct list_head *vmas)

{

	struct drm_device       *dev = params->dev;

	struct intel_engine_cs  *ring = params->ring;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;

	u64 exec_start;

	int instp_mode;

	u32 instp_mask;

	int ret;

	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;

	instp_mask = I915_EXEC_CONSTANTS_MASK;

	switch (instp_mode) {

	case I915_EXEC_CONSTANTS_REL_GENERAL:

	case I915_EXEC_CONSTANTS_ABSOLUTE:

	case I915_EXEC_CONSTANTS_REL_SURFACE:

		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {

			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");

			return -EINVAL;

		}

		if (instp_mode != dev_priv->relative_constants_mode) {

			if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {

				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");

				return -EINVAL;

			}

			/* The HW changed the meaning on this bit on gen6 */

			instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;

		}

		break;

	default:

		DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);

		return -EINVAL;

	}

	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {

		DRM_DEBUG("sol reset is gen7 only\n");

		return -EINVAL;

	}

	ret = execlists_move_to_gpu(params->request, vmas);

	if (ret)

		return ret;

	if (ring == &dev_priv->ring[RCS] &&

	    instp_mode != dev_priv->relative_constants_mode) {

		ret = intel_logical_ring_begin(params->request, 4);

		if (ret)

			return ret;

		intel_logical_ring_emit(ringbuf, MI_NOOP);

		intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));

		intel_logical_ring_emit_reg(ringbuf, INSTPM);

		intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);

		intel_logical_ring_advance(ringbuf);

		dev_priv->relative_constants_mode = instp_mode;

	}

	exec_start = params->batch_obj_vm_offset +

		     args->batch_start_offset;

	ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);

	if (ret)

		return ret;

	trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);

	i915_gem_execbuffer_move_to_active(vmas, params->request);

	i915_gem_execbuffer_retire_commands(params);

	return 0;

}

void intel_execlists_retire_requests(struct intel_engine_cs *ring)

{

	struct drm_i915_gem_request *req, *tmp;

	struct list_head retired_list;

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));

	if (list_empty(&ring->execlist_retired_req_list))

		return;

	INIT_LIST_HEAD(&retired_list);

	spin_lock_irq(&ring->execlist_lock);

	list_replace_init(&ring->execlist_retired_req_list, &retired_list);

	spin_unlock_irq(&ring->execlist_lock);

	list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {

		struct intel_context *ctx = req->ctx;

		struct drm_i915_gem_object *ctx_obj =

				ctx->engine[ring->id].state;

		if (ctx_obj && (ctx != req->i915->kernel_context))

			intel_lr_context_unpin(ctx, ring);

		list_del(&req->execlist_link);

		i915_gem_request_unreference(req);

	}

}

void intel_logical_ring_stop(struct intel_engine_cs *ring)

{

	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	int ret;

	if (!intel_ring_initialized(ring))

		return;

	ret = intel_ring_idle(ring);

	if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))

		DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",

			  ring->name, ret);

	/* TODO: Is this correct with Execlists enabled? */

	I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));

	if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {

		DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);

		return;

	}

	I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));

}

int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)

{

	struct intel_engine_cs *ring = req->ring;

	int ret;

	if (!ring->gpu_caches_dirty)

		return 0;

	ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);

	if (ret)

		return ret;

	ring->gpu_caches_dirty = false;

	return 0;

}

static int intel_lr_context_do_pin(struct intel_context *ctx,

				   struct intel_engine_cs *ring)

{

	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;

	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;

	struct page *lrc_state_page;

	uint32_t *lrc_reg_state;

	int ret;

	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));

	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN,

			PIN_OFFSET_BIAS | GUC_WOPCM_TOP);

	if (ret)

		return ret;

	lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);