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Rev | Author | Line No. | Line |
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3243 | Serge | 1 | /* |
2 | * Copyright (c) 2006 Dave Airlie |
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3 | * Copyright © 2006-2008,2010 Intel Corporation |
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4 | * Jesse Barnes |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice (including the next |
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14 | * paragraph) shall be included in all copies or substantial portions of the |
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15 | * Software. |
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16 | * |
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17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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23 | * DEALINGS IN THE SOFTWARE. |
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24 | * |
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25 | * Authors: |
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26 | * Eric Anholt |
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27 | * Chris Wilson |
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28 | */ |
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29 | #include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | #include "intel_drv.h" |
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34 | #include |
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35 | #include "i915_drv.h" |
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36 | |||
6084 | serge | 37 | struct gmbus_pin { |
3243 | Serge | 38 | const char *name; |
6937 | serge | 39 | i915_reg_t reg; |
3243 | Serge | 40 | }; |
41 | |||
6084 | serge | 42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { |
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44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, |
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45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, |
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46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, |
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47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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3243 | Serge | 50 | }; |
51 | |||
6084 | serge | 52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, |
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54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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57 | }; |
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58 | |||
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
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60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, |
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61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, |
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62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, |
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63 | }; |
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64 | |||
65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
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6937 | serge | 66 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, |
67 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, |
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68 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, |
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6084 | serge | 69 | }; |
70 | |||
71 | /* pin is expected to be valid */ |
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72 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, |
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73 | unsigned int pin) |
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74 | { |
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75 | if (IS_BROXTON(dev_priv)) |
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76 | return &gmbus_pins_bxt[pin]; |
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6937 | serge | 77 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
6084 | serge | 78 | return &gmbus_pins_skl[pin]; |
79 | else if (IS_BROADWELL(dev_priv)) |
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80 | return &gmbus_pins_bdw[pin]; |
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81 | else |
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82 | return &gmbus_pins[pin]; |
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83 | } |
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84 | |||
85 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
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86 | unsigned int pin) |
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87 | { |
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88 | unsigned int size; |
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89 | |||
90 | if (IS_BROXTON(dev_priv)) |
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91 | size = ARRAY_SIZE(gmbus_pins_bxt); |
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6937 | serge | 92 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
6084 | serge | 93 | size = ARRAY_SIZE(gmbus_pins_skl); |
94 | else if (IS_BROADWELL(dev_priv)) |
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95 | size = ARRAY_SIZE(gmbus_pins_bdw); |
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96 | else |
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97 | size = ARRAY_SIZE(gmbus_pins); |
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98 | |||
6937 | serge | 99 | return pin < size && |
100 | i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); |
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6084 | serge | 101 | } |
102 | |||
3243 | Serge | 103 | /* Intel GPIO access functions */ |
104 | |||
105 | #define I2C_RISEFALL_TIME 10 |
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106 | |||
107 | static inline struct intel_gmbus * |
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108 | to_intel_gmbus(struct i2c_adapter *i2c) |
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109 | { |
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110 | return container_of(i2c, struct intel_gmbus, adapter); |
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111 | } |
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112 | |||
113 | void |
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114 | intel_i2c_reset(struct drm_device *dev) |
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115 | { |
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116 | struct drm_i915_private *dev_priv = dev->dev_private; |
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4560 | Serge | 117 | |
6084 | serge | 118 | I915_WRITE(GMBUS0, 0); |
119 | I915_WRITE(GMBUS4, 0); |
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3243 | Serge | 120 | } |
121 | |||
122 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) |
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123 | { |
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124 | u32 val; |
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125 | |||
126 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ |
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127 | if (!IS_PINEVIEW(dev_priv->dev)) |
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128 | return; |
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129 | |||
130 | val = I915_READ(DSPCLK_GATE_D); |
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131 | if (enable) |
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132 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
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133 | else |
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134 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
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135 | I915_WRITE(DSPCLK_GATE_D, val); |
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136 | } |
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137 | |||
138 | static u32 get_reserved(struct intel_gmbus *bus) |
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139 | { |
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140 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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141 | struct drm_device *dev = dev_priv->dev; |
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142 | u32 reserved = 0; |
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143 | |||
144 | /* On most chips, these bits must be preserved in software. */ |
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145 | if (!IS_I830(dev) && !IS_845G(dev)) |
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146 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
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147 | (GPIO_DATA_PULLUP_DISABLE | |
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148 | GPIO_CLOCK_PULLUP_DISABLE); |
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149 | |||
150 | return reserved; |
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151 | } |
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152 | |||
153 | static int get_clock(void *data) |
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154 | { |
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155 | struct intel_gmbus *bus = data; |
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156 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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157 | u32 reserved = get_reserved(bus); |
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158 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); |
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159 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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160 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; |
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161 | } |
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162 | |||
163 | static int get_data(void *data) |
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164 | { |
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165 | struct intel_gmbus *bus = data; |
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166 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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167 | u32 reserved = get_reserved(bus); |
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168 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); |
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169 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); |
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170 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; |
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171 | } |
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172 | |||
173 | static void set_clock(void *data, int state_high) |
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174 | { |
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175 | struct intel_gmbus *bus = data; |
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176 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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177 | u32 reserved = get_reserved(bus); |
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178 | u32 clock_bits; |
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179 | |||
180 | if (state_high) |
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181 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; |
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182 | else |
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183 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | |
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184 | GPIO_CLOCK_VAL_MASK; |
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185 | |||
186 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
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187 | POSTING_READ(bus->gpio_reg); |
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188 | } |
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189 | |||
190 | static void set_data(void *data, int state_high) |
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191 | { |
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192 | struct intel_gmbus *bus = data; |
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193 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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194 | u32 reserved = get_reserved(bus); |
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195 | u32 data_bits; |
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196 | |||
197 | if (state_high) |
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198 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; |
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199 | else |
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200 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | |
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201 | GPIO_DATA_VAL_MASK; |
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202 | |||
203 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
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204 | POSTING_READ(bus->gpio_reg); |
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205 | } |
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206 | |||
207 | static int |
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208 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) |
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209 | { |
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210 | struct intel_gmbus *bus = container_of(adapter, |
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211 | struct intel_gmbus, |
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212 | adapter); |
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213 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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214 | |||
215 | intel_i2c_reset(dev_priv->dev); |
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216 | intel_i2c_quirk_set(dev_priv, true); |
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217 | set_data(bus, 1); |
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218 | set_clock(bus, 1); |
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219 | udelay(I2C_RISEFALL_TIME); |
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220 | return 0; |
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221 | } |
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222 | |||
223 | static void |
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224 | intel_gpio_post_xfer(struct i2c_adapter *adapter) |
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225 | { |
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226 | struct intel_gmbus *bus = container_of(adapter, |
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227 | struct intel_gmbus, |
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228 | adapter); |
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229 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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230 | |||
231 | set_data(bus, 1); |
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232 | set_clock(bus, 1); |
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233 | intel_i2c_quirk_set(dev_priv, false); |
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234 | } |
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235 | |||
236 | static void |
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6084 | serge | 237 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
3243 | Serge | 238 | { |
239 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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240 | struct i2c_algo_bit_data *algo; |
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241 | |||
242 | algo = &bus->bit_algo; |
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243 | |||
6937 | serge | 244 | bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + |
245 | i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); |
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3243 | Serge | 246 | bus->adapter.algo_data = algo; |
247 | algo->setsda = set_data; |
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248 | algo->setscl = set_clock; |
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249 | algo->getsda = get_data; |
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250 | algo->getscl = get_clock; |
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251 | algo->pre_xfer = intel_gpio_pre_xfer; |
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252 | algo->post_xfer = intel_gpio_post_xfer; |
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253 | algo->udelay = I2C_RISEFALL_TIME; |
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254 | algo->timeout = usecs_to_jiffies(2200); |
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255 | algo->data = bus; |
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256 | } |
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257 | |||
258 | static int |
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3480 | Serge | 259 | gmbus_wait_hw_status(struct drm_i915_private *dev_priv, |
260 | u32 gmbus2_status, |
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261 | u32 gmbus4_irq_en) |
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262 | { |
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263 | int i; |
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264 | u32 gmbus2 = 0; |
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265 | DEFINE_WAIT(wait); |
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266 | |||
267 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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268 | gmbus4_irq_en = 0; |
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269 | |||
270 | /* Important: The hw handles only the first bit, so set only one! Since |
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271 | * we also need to check for NAKs besides the hw ready/idle signal, we |
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272 | * need to wake up periodically and check that ourselves. */ |
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6084 | serge | 273 | I915_WRITE(GMBUS4, gmbus4_irq_en); |
3480 | Serge | 274 | |
3746 | Serge | 275 | for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
3480 | Serge | 276 | prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
277 | TASK_UNINTERRUPTIBLE); |
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278 | |||
6084 | serge | 279 | gmbus2 = I915_READ_NOTRACE(GMBUS2); |
3480 | Serge | 280 | if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) |
281 | break; |
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282 | |||
283 | schedule_timeout(1); |
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284 | } |
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285 | finish_wait(&dev_priv->gmbus_wait_queue, &wait); |
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286 | |||
6084 | serge | 287 | I915_WRITE(GMBUS4, 0); |
3480 | Serge | 288 | |
289 | if (gmbus2 & GMBUS_SATOER) |
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290 | return -ENXIO; |
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291 | if (gmbus2 & gmbus2_status) |
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292 | return 0; |
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293 | return -ETIMEDOUT; |
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294 | } |
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295 | |||
296 | static int |
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297 | gmbus_wait_idle(struct drm_i915_private *dev_priv) |
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298 | { |
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299 | int ret; |
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300 | |||
6084 | serge | 301 | #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0) |
3480 | Serge | 302 | |
303 | if (!HAS_GMBUS_IRQ(dev_priv->dev)) |
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304 | return wait_for(C, 10); |
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305 | |||
306 | /* Important: The hw handles only the first bit, so set only one! */ |
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6084 | serge | 307 | I915_WRITE(GMBUS4, GMBUS_IDLE_EN); |
3480 | Serge | 308 | |
3746 | Serge | 309 | ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
310 | msecs_to_jiffies_timeout(10)); |
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3480 | Serge | 311 | |
6084 | serge | 312 | I915_WRITE(GMBUS4, 0); |
3480 | Serge | 313 | |
314 | if (ret) |
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315 | return 0; |
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316 | else |
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317 | return -ETIMEDOUT; |
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318 | #undef C |
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319 | } |
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320 | |||
321 | static int |
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6084 | serge | 322 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
323 | unsigned short addr, u8 *buf, unsigned int len, |
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324 | u32 gmbus1_index) |
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3243 | Serge | 325 | { |
6084 | serge | 326 | I915_WRITE(GMBUS1, |
3243 | Serge | 327 | gmbus1_index | |
328 | GMBUS_CYCLE_WAIT | |
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329 | (len << GMBUS_BYTE_COUNT_SHIFT) | |
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6084 | serge | 330 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | |
3243 | Serge | 331 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); |
332 | while (len) { |
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333 | int ret; |
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334 | u32 val, loop = 0; |
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335 | |||
3480 | Serge | 336 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
337 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 338 | if (ret) |
3480 | Serge | 339 | return ret; |
3243 | Serge | 340 | |
6084 | serge | 341 | val = I915_READ(GMBUS3); |
3243 | Serge | 342 | do { |
343 | *buf++ = val & 0xff; |
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344 | val >>= 8; |
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345 | } while (--len && ++loop < 4); |
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346 | } |
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347 | |||
348 | return 0; |
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349 | } |
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350 | |||
351 | static int |
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6084 | serge | 352 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
353 | u32 gmbus1_index) |
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3243 | Serge | 354 | { |
355 | u8 *buf = msg->buf; |
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6084 | serge | 356 | unsigned int rx_size = msg->len; |
357 | unsigned int len; |
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358 | int ret; |
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359 | |||
360 | do { |
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361 | len = min(rx_size, GMBUS_BYTE_COUNT_MAX); |
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362 | |||
363 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, |
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364 | buf, len, gmbus1_index); |
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365 | if (ret) |
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366 | return ret; |
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367 | |||
368 | rx_size -= len; |
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369 | buf += len; |
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370 | } while (rx_size != 0); |
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371 | |||
372 | return 0; |
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373 | } |
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374 | |||
375 | static int |
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376 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, |
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377 | unsigned short addr, u8 *buf, unsigned int len) |
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378 | { |
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379 | unsigned int chunk_size = len; |
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3243 | Serge | 380 | u32 val, loop; |
381 | |||
382 | val = loop = 0; |
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383 | while (len && loop < 4) { |
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384 | val |= *buf++ << (8 * loop++); |
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385 | len -= 1; |
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386 | } |
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387 | |||
6084 | serge | 388 | I915_WRITE(GMBUS3, val); |
389 | I915_WRITE(GMBUS1, |
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3243 | Serge | 390 | GMBUS_CYCLE_WAIT | |
6084 | serge | 391 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | |
392 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | |
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3243 | Serge | 393 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); |
394 | while (len) { |
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395 | int ret; |
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396 | |||
397 | val = loop = 0; |
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398 | do { |
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399 | val |= *buf++ << (8 * loop); |
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400 | } while (--len && ++loop < 4); |
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401 | |||
6084 | serge | 402 | I915_WRITE(GMBUS3, val); |
3243 | Serge | 403 | |
3480 | Serge | 404 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, |
405 | GMBUS_HW_RDY_EN); |
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3243 | Serge | 406 | if (ret) |
3480 | Serge | 407 | return ret; |
3243 | Serge | 408 | } |
6084 | serge | 409 | |
3243 | Serge | 410 | return 0; |
411 | } |
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412 | |||
6084 | serge | 413 | static int |
414 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) |
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415 | { |
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416 | u8 *buf = msg->buf; |
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417 | unsigned int tx_size = msg->len; |
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418 | unsigned int len; |
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419 | int ret; |
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420 | |||
421 | do { |
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422 | len = min(tx_size, GMBUS_BYTE_COUNT_MAX); |
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423 | |||
424 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); |
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425 | if (ret) |
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426 | return ret; |
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427 | |||
428 | buf += len; |
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429 | tx_size -= len; |
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430 | } while (tx_size != 0); |
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431 | |||
432 | return 0; |
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433 | } |
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434 | |||
3243 | Serge | 435 | /* |
436 | * The gmbus controller can combine a 1 or 2 byte write with a read that |
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437 | * immediately follows it by using an "INDEX" cycle. |
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438 | */ |
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439 | static bool |
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440 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) |
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441 | { |
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442 | return (i + 1 < num && |
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443 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && |
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444 | (msgs[i + 1].flags & I2C_M_RD)); |
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445 | } |
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446 | |||
447 | static int |
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448 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) |
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449 | { |
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450 | u32 gmbus1_index = 0; |
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451 | u32 gmbus5 = 0; |
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452 | int ret; |
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453 | |||
454 | if (msgs[0].len == 2) |
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455 | gmbus5 = GMBUS_2BYTE_INDEX_EN | |
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456 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); |
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457 | if (msgs[0].len == 1) |
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458 | gmbus1_index = GMBUS_CYCLE_INDEX | |
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459 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); |
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460 | |||
461 | /* GMBUS5 holds 16-bit index */ |
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462 | if (gmbus5) |
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6084 | serge | 463 | I915_WRITE(GMBUS5, gmbus5); |
3243 | Serge | 464 | |
465 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); |
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466 | |||
467 | /* Clear GMBUS5 after each index transfer */ |
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468 | if (gmbus5) |
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6084 | serge | 469 | I915_WRITE(GMBUS5, 0); |
3243 | Serge | 470 | |
471 | return ret; |
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472 | } |
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473 | |||
474 | static int |
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6937 | serge | 475 | do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) |
3243 | Serge | 476 | { |
477 | struct intel_gmbus *bus = container_of(adapter, |
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478 | struct intel_gmbus, |
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479 | adapter); |
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480 | struct drm_i915_private *dev_priv = bus->dev_priv; |
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6084 | serge | 481 | int i = 0, inc, try = 0; |
3243 | Serge | 482 | int ret = 0; |
483 | |||
6084 | serge | 484 | retry: |
485 | I915_WRITE(GMBUS0, bus->reg0); |
||
3243 | Serge | 486 | |
6084 | serge | 487 | for (; i < num; i += inc) { |
488 | inc = 1; |
||
3243 | Serge | 489 | if (gmbus_is_index_read(msgs, i, num)) { |
490 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); |
||
6084 | serge | 491 | inc = 2; /* an index read is two msgs */ |
3243 | Serge | 492 | } else if (msgs[i].flags & I2C_M_RD) { |
493 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); |
||
494 | } else { |
||
495 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
||
496 | } |
||
497 | |||
6937 | serge | 498 | if (!ret) |
499 | ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, |
||
500 | GMBUS_HW_WAIT_EN); |
||
3243 | Serge | 501 | if (ret == -ETIMEDOUT) |
502 | goto timeout; |
||
6937 | serge | 503 | else if (ret) |
3243 | Serge | 504 | goto clear_err; |
505 | } |
||
506 | |||
507 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
||
508 | * a STOP on the very first cycle. To simplify the code we |
||
509 | * unconditionally generate the STOP condition with an additional gmbus |
||
510 | * cycle. */ |
||
6084 | serge | 511 | I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
3243 | Serge | 512 | |
513 | /* Mark the GMBUS interface as disabled after waiting for idle. |
||
514 | * We will re-enable it at the start of the next xfer, |
||
515 | * till then let it sleep. |
||
516 | */ |
||
3480 | Serge | 517 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 518 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
519 | adapter->name); |
||
520 | ret = -ETIMEDOUT; |
||
521 | } |
||
6084 | serge | 522 | I915_WRITE(GMBUS0, 0); |
3243 | Serge | 523 | ret = ret ?: i; |
524 | goto out; |
||
525 | |||
526 | clear_err: |
||
527 | /* |
||
528 | * Wait for bus to IDLE before clearing NAK. |
||
529 | * If we clear the NAK while bus is still active, then it will stay |
||
530 | * active and the next transaction may fail. |
||
531 | * |
||
532 | * If no ACK is received during the address phase of a transaction, the |
||
533 | * adapter must report -ENXIO. It is not clear what to return if no ACK |
||
534 | * is received at other times. But we have to be careful to not return |
||
535 | * spurious -ENXIO because that will prevent i2c and drm edid functions |
||
536 | * from retrying. So return -ENXIO only when gmbus properly quiescents - |
||
537 | * timing out seems to happen when there _is_ a ddc chip present, but |
||
538 | * it's slow responding and only answers on the 2nd retry. |
||
539 | */ |
||
540 | ret = -ENXIO; |
||
3480 | Serge | 541 | if (gmbus_wait_idle(dev_priv)) { |
3243 | Serge | 542 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
543 | adapter->name); |
||
544 | ret = -ETIMEDOUT; |
||
545 | } |
||
546 | |||
547 | /* Toggle the Software Clear Interrupt bit. This has the effect |
||
548 | * of resetting the GMBUS controller and so clearing the |
||
549 | * BUS_ERROR raised by the slave's NAK. |
||
550 | */ |
||
6084 | serge | 551 | I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT); |
552 | I915_WRITE(GMBUS1, 0); |
||
553 | I915_WRITE(GMBUS0, 0); |
||
3243 | Serge | 554 | |
555 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
||
556 | adapter->name, msgs[i].addr, |
||
557 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); |
||
558 | |||
6084 | serge | 559 | /* |
560 | * Passive adapters sometimes NAK the first probe. Retry the first |
||
561 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm |
||
562 | * has retries internally. See also the retry loop in |
||
563 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. |
||
564 | */ |
||
565 | if (ret == -ENXIO && i == 0 && try++ == 0) { |
||
566 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", |
||
567 | adapter->name); |
||
568 | goto retry; |
||
569 | } |
||
570 | |||
3243 | Serge | 571 | goto out; |
572 | |||
573 | timeout: |
||
574 | DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
||
575 | bus->adapter.name, bus->reg0 & 0xff); |
||
6084 | serge | 576 | I915_WRITE(GMBUS0, 0); |
3243 | Serge | 577 | |
6937 | serge | 578 | /* |
579 | * Hardware may not support GMBUS over these pins? Try GPIO bitbanging |
||
580 | * instead. Use EAGAIN to have i2c core retry. |
||
581 | */ |
||
3243 | Serge | 582 | bus->force_bit = 1; |
6937 | serge | 583 | ret = -EAGAIN; |
584 | |||
585 | out: |
||
586 | return ret; |
||
587 | } |
||
588 | |||
589 | static int |
||
590 | gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) |
||
591 | { |
||
592 | struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, |
||
593 | adapter); |
||
594 | struct drm_i915_private *dev_priv = bus->dev_priv; |
||
595 | int ret; |
||
596 | |||
597 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
||
598 | mutex_lock(&dev_priv->gmbus_mutex); |
||
599 | |||
600 | if (bus->force_bit) |
||
3243 | Serge | 601 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
6937 | serge | 602 | else |
603 | ret = do_gmbus_xfer(adapter, msgs, num); |
||
3243 | Serge | 604 | |
605 | mutex_unlock(&dev_priv->gmbus_mutex); |
||
6084 | serge | 606 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
607 | |||
3243 | Serge | 608 | return ret; |
609 | } |
||
610 | |||
611 | static u32 gmbus_func(struct i2c_adapter *adapter) |
||
612 | { |
||
613 | return i2c_bit_algo.functionality(adapter) & |
||
614 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
||
615 | /* I2C_FUNC_10BIT_ADDR | */ |
||
616 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | |
||
617 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); |
||
618 | } |
||
619 | |||
620 | static const struct i2c_algorithm gmbus_algorithm = { |
||
621 | .master_xfer = gmbus_xfer, |
||
622 | .functionality = gmbus_func |
||
623 | }; |
||
624 | |||
625 | /** |
||
626 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
||
627 | * @dev: DRM device |
||
628 | */ |
||
629 | int intel_setup_gmbus(struct drm_device *dev) |
||
630 | { |
||
631 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 632 | struct intel_gmbus *bus; |
633 | unsigned int pin; |
||
634 | int ret; |
||
3243 | Serge | 635 | |
3746 | Serge | 636 | if (HAS_PCH_NOP(dev)) |
637 | return 0; |
||
6937 | serge | 638 | |
639 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
||
3480 | Serge | 640 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
6937 | serge | 641 | else if (!HAS_GMCH_DISPLAY(dev_priv)) |
642 | dev_priv->gpio_mmio_base = |
||
643 | i915_mmio_reg_offset(PCH_GPIOA) - |
||
644 | i915_mmio_reg_offset(GPIOA); |
||
3243 | Serge | 645 | |
646 | mutex_init(&dev_priv->gmbus_mutex); |
||
3480 | Serge | 647 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
3243 | Serge | 648 | |
6084 | serge | 649 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
650 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
||
651 | continue; |
||
3243 | Serge | 652 | |
6084 | serge | 653 | bus = &dev_priv->gmbus[pin]; |
654 | |||
3243 | Serge | 655 | bus->adapter.owner = THIS_MODULE; |
656 | bus->adapter.class = I2C_CLASS_DDC; |
||
657 | snprintf(bus->adapter.name, |
||
658 | sizeof(bus->adapter.name), |
||
659 | "i915 gmbus %s", |
||
6084 | serge | 660 | get_gmbus_pin(dev_priv, pin)->name); |
3243 | Serge | 661 | |
662 | bus->adapter.dev.parent = &dev->pdev->dev; |
||
663 | bus->dev_priv = dev_priv; |
||
664 | |||
665 | bus->adapter.algo = &gmbus_algorithm; |
||
666 | |||
6937 | serge | 667 | /* |
668 | * We wish to retry with bit banging |
||
669 | * after a timed out GMBUS attempt. |
||
670 | */ |
||
671 | bus->adapter.retries = 1; |
||
672 | |||
3243 | Serge | 673 | /* By default use a conservative clock rate */ |
6084 | serge | 674 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
3243 | Serge | 675 | |
676 | /* gmbus seems to be broken on i830 */ |
||
677 | if (IS_I830(dev)) |
||
678 | bus->force_bit = 1; |
||
679 | |||
6084 | serge | 680 | intel_gpio_setup(bus, pin); |
3243 | Serge | 681 | |
682 | ret = i2c_add_adapter(&bus->adapter); |
||
683 | if (ret) |
||
684 | goto err; |
||
685 | } |
||
686 | |||
687 | intel_i2c_reset(dev_priv->dev); |
||
688 | |||
689 | return 0; |
||
690 | |||
691 | err: |
||
6320 | serge | 692 | while (pin--) { |
6084 | serge | 693 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
694 | continue; |
||
695 | |||
696 | bus = &dev_priv->gmbus[pin]; |
||
3243 | Serge | 697 | i2c_del_adapter(&bus->adapter); |
698 | } |
||
699 | return ret; |
||
700 | } |
||
701 | |||
702 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
||
6084 | serge | 703 | unsigned int pin) |
3243 | Serge | 704 | { |
6084 | serge | 705 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
706 | return NULL; |
||
707 | |||
708 | return &dev_priv->gmbus[pin].adapter; |
||
3243 | Serge | 709 | } |
710 | |||
711 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
||
712 | { |
||
713 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
714 | |||
715 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
||
716 | } |
||
717 | |||
718 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) |
||
719 | { |
||
720 | struct intel_gmbus *bus = to_intel_gmbus(adapter); |
||
721 | |||
722 | bus->force_bit += force_bit ? 1 : -1; |
||
723 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", |
||
724 | force_bit ? "en" : "dis", adapter->name, |
||
725 | bus->force_bit); |
||
726 | } |
||
727 | |||
728 | void intel_teardown_gmbus(struct drm_device *dev) |
||
729 | { |
||
730 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
6084 | serge | 731 | struct intel_gmbus *bus; |
732 | unsigned int pin; |
||
3243 | Serge | 733 | |
6084 | serge | 734 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
735 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
||
736 | continue; |
||
737 | |||
738 | bus = &dev_priv->gmbus[pin]; |
||
3243 | Serge | 739 | i2c_del_adapter(&bus->adapter); |
740 | } |
||
741 | }>><>>>><>><>=>>>><>><>><>><>>>><>><>>> |